Ordering number : EN 51134465 MOS IC LC89972M PAL CCD Delay Line Overview Package Dimensions The LC89972M is a CCD delay line for PAL television systems. It incorporates a comb filter for chrominance signal and a 1H delay line for luminance signal. unit: mm 3045B-MFP24 [LC89972M] Structure * NMOS + CCD Functions * Two CCD shift registers (for chrominance and luminance signals) * CCD drive circuits * CCD stage count switching circuit * CCD signal adder * Auto-bias circuit * Sync tip clamping circuit (luminance signal) * Center-bias circuit (chrominance signal) * Sample-and-hold circuit * PLL 3 x frequency multiplier * 3 fsc clock output circuit * RD voltage generator SANYO: MFP24 Features * 5 V single-voltage power supply * Built-in PLL 3 x frequency multiplier circuit allows 3 fsc operation from an fsc (4.43 MHz) input. * Control pin switchable to handle PAL/GBI and 4.43 MHz NTSC systems. * Built-in chrominance signal crosstalk exclusion comb filter features high-precision comb characteristics in an adjustment-free circuit. * Built-in peripheral circuits allow applications to be constructed with a minimum number of external components. * Positive-phase signal input/positive-phase signal output (luminance signal) Specifications Absolute Maximum Ratings at Ta = 25C Parameter Maximum supply voltage Allowable power dissipation Symbol VDD max Pd max Conditions Ratings -0.3 to +6.0 600 Unit V mW Operating temperature Topr -10 to +70 C Storage temperature Tstg -55 to +150 C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 72595TH (OT) No. 5113-1/8 LC89972M Allowable Operating Ranges at Ta = 25C Parameter Symbol Conditions min typ max Unit Supply voltage VDD 4.75 5.00 5.25 V Clock input amplitude VCLK 300 500 1000 mVp-p Clock frequency FCLK -- 4.43361875 -- Clock signal input amplitude VIN-C -- 350 500 mVp-p Luminance signal input amplitude VIN-Y -- 400 572 mVp-p Sine wave MHz Electrical Characteristics at Ta = 25C, VDD = 5.0 V, FCLK = 4.43361875 MHz, VCLK = 500 mVp-p Parameter Supply current Symbol Switch states SW1 SW2 SW3 IDD-1 a a b IDD-2 b a b Conditions min typ max Unit 40 50 60 mA 2.0 2.4 2.8 V 1.2 1.6 2.0 V 3 -2 0 +2 dB 4 -- -40 -35 dB 5 -0.3 0.0 +0.3 dB -- 10 50 mVrms -- 0.8 1.5 mVrms 7 -- 0.5 2.0 mVrms 8 200 350 500 9 -- 245 -- ns 1 Chrominance System Characteristics (with no Y-IN input) Pin voltage (input) Pin voltage (output) Voltage gain Comb depth Linearity Clock leakage (3 fsc) Clock leakage (fsc) Noise Output impedance 0 H delay time VINC-1 a a b VINC-2 b a b VOUTC-1 a a b VOUTC-2 b a b GVC-1 a a b GVC-2 b a b CD-1 a a b CD-2 b a b LNC-1 a a b LNC-2 b a b LCK3C-1 a a b LCK3C-2 b a b LCK1C-1 a a b LCK1C-2 b a b NC-1 a a b NC-2 b a b ZOC-1 a a a, b ZOC-2 b a a, b TDC-1 a a b TDC-2 b a b 2 6 No. 5113-2/8 LC89972M Continued from preceding page. Parameter Switch states Symbol SW1 SW2 SW3 Conditions min typ max Unit Luminance System Characteristics (with no C-IN1 or C-IN2 input) Pin voltage (input) Pin voltage (output) Voltage gain Frequency response Differential gain Differential phase Linearity Clock leakage (3 fsc) Clock leakage (fsc) Noise Output impedance Delay time VINY-1 a a b VINY-2 b a b VOUTY-1 a a b VOUTY-2 b a b GVY-1 a a b GVY-2 b a b GFY-1 a b b GFY-2 b b b DGY-1 a a b DGY-2 b a b DPY-1 a a b DPY-2 b a b LSY-1 a a b LSY-2 b a b LCK3Y-1 a a b LCK3Y-2 b a b LCK1Y-1 a a b LCK1Y-2 b a b NY-1 a a b NY-2 b a b ZOY-1 a a c, b ZOY-2 b a c, b TDY-1 a a b TDY-2 b a b 1.7 2.1 2.5 V 0.8 1.2 1.6 V 11 -2 0 +2 dB 12 -2 0 +2 dB 0 5 7 % 0 5 7 deg 37 40 43 % -- 10 50 mVrms -- 0.8 1.5 mVrms 16 -- 0.5 2.0 mVrms 17 250 400 550 -- 63.92 -- -- 63.47 -- 10 13 14 15 18 s Test Conditions 1. Supply current with no signal input 2. C-OUT voltage (center bias voltage) with no signal input. 3. Measure the C-OUT output with 350 mVp-p sine wave signals input to C-IN1 and C-IN2. GVC = 20 log C-OUT output [mVp-p] [dB] 350 [mVp-p] Test frequencies GVC-1 4.429662 MHz (PAL/GBI) GVC-2 4.425694 MHz (4.43 NTSC) 4. Measure the comb depth from the C-OUT output with a 350 mVp-p sine wave signal of frequency fa input to C-IN1 and C-IN2 and with a frequency of fb input. CD = 20 log C-OUT output with fb input [mVp-p] [dB] C-OUT output with fa input [mVp-p] Test frequencies CD-1 CD-2 fa 4.429662 MHz 4.425694 MHz fb 4.425756 MHz (PAL/GBI) 4.417819 MHz (4.43 NTSC) No. 5113-3/8 LC89972M 5. Measure the C-OUT output with a 200 mVp-p sine wave signal input to C-IN1 and C-IN2 and with 500 mVp-p sine wave signal input and calculate the difference in the gains. LNC = 20 log Output for a 500 mVp-p input [mVp-p] 500 [mVp-p] Output for a 200 mVp-p input [mVp-p] 200 [mVp-p] [dB] Test frequencies LNC-1 4.429662 MHz (PAL/GBI) LNC-2 4.425694 MHz (4.43 NTSC) 6. Measure the 3 fsc (13.3 MHz) and fsc (4.43 MHz) components in the C-OUT output with no input. 7. Measure the noise in the C-OUT output with no input. Measure the noise with a noise meter set up with a 200 kHz high-pass filter and a 5 MHz low-pass filter. 8. Let V1 be the C-OUT output with a 350 mVp-p sine wave input to C-IN1 and C-IN2 and SW3 set to a, and let V2 be the C-OUT output with SW3 set to b. ZOC = V2 [mVp-p] - V1 [mVp-p] x 500 [] V1 [mVp-p] Test frequencies ZOC-1 4.429662 MHz (PAL/GBI) ZOC-2 4.425694 MHz (4.43 NTSC) 9. The C-OUT output delay time with respect to inputs to C-IN1. (the CCD 2.5 bit delay) 10. Y-OUT voltage (clamp voltage) with no signal input. 11. Measure the Y-OUT output with a 200 kHz 400 mVp-p sine wave input to Y-IN. GVY = 20 log Y-OUT output [mVp-p] [dB] 400 [mVp-p] 12. Measure the Y-OUT output with a 200 kHz 200 mVp-p sine wave input to Y-IN and with a 3.3 MHz 200 mVp-p sine wave input. GFY = 20 log Y-OUT output with a 3.3 MHz input [mVp-p] [dB] Y-OUT output with a 200 kHz input [mVp-p] Note that Vbias should be adjusted so that the circuit is biased to the clamp level plus 250 mV. No. 5113-4/8 LC89972M 13. Input a five-level step waveform (see the figure below) to Y-IN and measure the differential gain and differential phase in the Y-OUT output with a vector scope. 14. Input a five-level step waveform (see the figure below) to Y-IN and measure the luminance level (Y) and the sync level (S) in the Y-OUT output. LS = S [mV] x 100 [%] Y [mV] 15. Measure the 3 fsc (13.3 MHz) and fsc (4.43 MHz) components in the Y-OUT output with no input. 16. Measure the noise in the Y-OUT output with no input. Measure the noise with a noise meter set up with a 200 kHz high-pass filter, a 5 MHz low-pass filter and a 4.43 MHz trap filter. 17. Let V1 be the Y-OUT output with a 200 kHz 400 mVp-p sine wave input and SW3 set to c, and let V2 be the C-OUT output with SW3 set to b. ZOY = V2 [mVp-p] - V1 [mVp-p] x 500 [] V1 [mVp-p] 18. The Y-OUT delay time with respect to Y-IN No. 5113-5/8 LC89972M Block Diagram Control Pin Function Mode (representative example) Chrominance signal delay (CCD bits) Luminance signal delay (CCD bits) Low PAL/GBI 2 H (1705) + 0 H (2.5) 1 H (849.5) High 4.43 NTSC 1 H (847) + 0 H (2.5) 1 H (843.5) CONT Switching Voltage Levels Symbol min typ max Low Low/high VL -0.3 0.0 +0.5 Unit V High VH 2.0 5.0 6.0 V Note: Since the control pin has a built-in pull-down resistor, the pin will be set to the low state if left open. No. 5113-6/8 LC89972M VCO OUT Pin Function This pin outputs the 3 fsc clock generated by the PLL 3 x frequency multiplier circuit. Test Circuit No. 5113-7/8 LC89972M Test Circuit No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of July, 1995. Specifications and information herein are subject to change without notice. PS No. 5113-8/8