LC89972m - Sanyo Semiconductor - Datasheet.Directory

Ordering number : EN 51134465

72595TH (OT) No. 5113-1/8

Overview

The LC89972M is a CCD delay line for PAL television

systems. It incorporates a comb filter for chrominance signal

and a 1H delay line for luminance signal.

Structure

• NMOS + CCD

Functions

• Two CCD shift registers (for chrominance and

luminance signals)

• CCD drive circuits

• CCD stage count switching circuit

• CCD signal adder

• Auto-bias circuit

• Sync tip clamping circuit (luminance signal)

• Center-bias circuit (chrominance signal)

• Sample-and-hold circuit

• PLL 3 ×frequency multiplier

• 3 fsc clock output circuit

• RD voltage generator

Features

• 5 V single-voltage power supply

• Built-in PLL 3 ×frequency multiplier circuit allows

3 fsc operation from an fsc (4.43 MHz) input.

• Control pin switchable to handle PAL/GBI and

4.43 MHz NTSC systems.

• Built-in chrominance signal crosstalk exclusion comb

filter features high-precision comb characteristics in an

adjustment-free circuit.

• Built-in peripheral circuits allow applications to be

constructed with a minimum number of external

components.

• Positive-phase signal input/positive-phase signal output

(luminance signal)

Specifications

Absolute Maximum Ratings at Ta = 25°C

Package Dimensions

unit: mm

3045B-MFP24

SANYO: MFP24

[LC89972M]

LC89972M

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

PAL CCD Delay Line

MOS IC

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage VDD max –0.3 to +6.0 V

Allowable power dissipation Pd max 600 mW

Operating temperature Topr –10 to +70 °C

Storage temperature Tstg –55 to +150 °C

Allowable Operating Ranges at Ta = 25°C

Electrical Characteristics at Ta = 25°C, VDD = 5.0 V, FCLK = 4.43361875 MHz, VCLK = 500 mVp-p

No. 5113-2/8

LC89972M

Parameter Symbol Conditions min typ max Unit

Supply voltage VDD 4.75 5.00 5.25 V

Clock input amplitude VCLK 300 500 1000 mVp-p

Clock frequency FCLK Sine wave — 4.43361875 — MHz

Clock signal input amplitude VIN-C — 350 500 mVp-p

Luminance signal input amplitude VIN-Y — 400 572 mVp-p

Parameter Symbol Switch states Conditions min typ max Unit

SW1 SW2 SW3

Supply current IDD-1 a a b 140 50 60 mA

IDD-2 b a b

Chrominance System Characteristics (with no Y-IN input)

Pin voltage (input) VINC-1 a a b 2.0 2.4 2.8 V

VINC-2 b a b 2

Pin voltage (output) VOUTC-1 a a b 1.2 1.6 2.0 V

VOUTC-2 b a b

Voltage gain GVC-1 a a b 3–2 0 +2 dB

GVC-2 b a b

Comb depth CD-1 a a b 4 — –40 –35 dB

CD-2 b a b

Linearity LNC-1 a a b 5 –0.3 0.0 +0.3 dB

LNC-2 b a b

Clock leakage (3 fsc) LCK3C-1 a a b —10 50 mVrms

LCK3C-2 b a b 6

Clock leakage (fsc) LCK1C-1 a a b — 0.8 1.5 mVrms

LCK1C-2 b a b

Noise NC-1 a a b 7 — 0.5 2.0 mVrms

NC-2 b a b

Output impedance ZOC-1 a a a, b 8 200 350 500 Ω

ZOC-2 b a a, b

0 H delay time TDC-1 a a b 9 — 245 — ns

TDC-2 b a b

Continued from preceding page.

Test Conditions

1. Supply current with no signal input

2. C-OUT voltage (center bias voltage) with no signal input.

3. Measure the C-OUT output with 350 mVp-p sine wave signals input to C-IN1 and C-IN2.

GVC = 20 log [dB]

Test frequencies

GVC-1 4.429662 MHz (PAL/GBI)

GVC-2 4.425694 MHz (4.43 NTSC)

4. Measure the comb depth from the C-OUT output with a 350 mVp-p sine wave signal of frequency fa input to C-IN1

and C-IN2 and with a frequency of fb input.

CD= 20 log [dB]

Test frequencies fa fb

CD-1 4.429662 MHz 4.425756 MHz (PAL/GBI)

CD-2 4.425694 MHz 4.417819 MHz (4.43 NTSC)

C-OUT output with fb input [mVp-p]

C-OUT output with fa input [mVp-p]

C-OUT output [mVp-p]

350 [mVp-p]

No. 5113-3/8

LC89972M

Parameter Symbol Switch states Conditions min typ max Unit

SW1 SW2 SW3

Luminance System Characteristics (with no C-IN1 or C-IN2 input)

Pin voltage (input) VINY-1 a a b 1.7 2.1 2.5 V

VINY-2 b a b 10

Pin voltage (output) VOUTY-1 a a b 0.8 1.2 1.6 V

VOUTY-2 b a b

Voltage gain GVY-1 a a b 11 –2 0 +2 dB

GVY-2 b a b

Frequency response GFY-1 a b b 12 –2 0 +2 dB

GFY-2 b b b

Differential gain DGY-1 a a b 0 5 7 %

DGY-2 b a b 13

Differential phase DPY-1 a a b 0 5 7 deg

DPY-2 b a b

Linearity LSY-1 a a b 14 37 40 43 %

LSY-2 b a b

Clock leakage (3 fsc) LCK3Y-1 a a b —10 50 mVrms

LCK3Y-2 b a b 15

Clock leakage (fsc) LCK1Y-1 a a b — 0.8 1.5 mVrms

LCK1Y-2 b a b

Noise NY-1 a a b 16 — 0.5 2.0 mVrms

NY-2 b a b

Output impedance ZOY-1 a a c, b 17 250 400 550 Ω

ZOY-2 b a c, b

Delay time TDY-1 a a b 18 —63.92 — µs

TDY-2 b a b — 63.47 —

5. Measure the C-OUT output with a 200 mVp-p sine wave signal input to C-IN1 and C-IN2 and with 500 mVp-p sine

wave signal input and calculate the difference in the gains.

LNC = 20 log [dB]

Test frequencies

LNC-1 4.429662 MHz (PAL/GBI)

LNC-2 4.425694 MHz (4.43 NTSC)

6. Measure the 3 fsc (13.3 MHz) and fsc (4.43 MHz) components in the C-OUT output with no input.

7. Measure the noise in the C-OUT output with no input.

Measure the noise with a noise meter set up with a 200 kHz high-pass filter and a 5 MHz low-pass filter.

8. Let V1 be the C-OUT output with a 350 mVp-p sine wave input to C-IN1 and C-IN2 and SW3 set to a, and let V2 be

the C-OUT output with SW3 set to b.

ZOC = ×500 [Ω]

Test frequencies

ZOC-1 4.429662 MHz (PAL/GBI)

ZOC-2 4.425694 MHz (4.43 NTSC)

9. The C-OUT output delay time with respect to inputs to C-IN1. (the CCD 2.5 bit delay)

10. Y-OUT voltage (clamp voltage) with no signal input.

11. Measure the Y-OUT output with a 200 kHz 400 mVp-p sine wave input to Y-IN.

GVY = 20 log [dB]

12. Measure the Y-OUT output with a 200 kHz 200 mVp-p sine wave input to Y-IN and with a 3.3 MHz 200 mVp-p

sine wave input.

GFY = 20 log [dB]

Note that Vbias should be adjusted so that the circuit is biased to the clamp level plus 250 mV.

Y-OUT output with a 3.3 MHz input [mVp-p]

Y-OUT output with a 200 kHz input [mVp-p]

Y-OUT output [mVp-p]

400 [mVp-p]

V2 [mVp-p] – V1 [mVp-p]

V1 [mVp-p]

Output for a 200 mVp-p input [mVp-p]

200 [mVp-p]

Output for a 500 mVp-p input [mVp-p]

500 [mVp-p]

No. 5113-4/8

LC89972M

13. Input a five-level step waveform (see the figure below) to Y-IN and measure the differential gain and differential

phase in the Y-OUT output with a vector scope.

14. Input a five-level step waveform (see the figure below) to Y-IN and measure the luminance level (Y) and the sync

level (S) in the Y-OUT output.

LS= ×100 [%]

15. Measure the 3 fsc (13.3 MHz) and fsc (4.43 MHz) components in the Y-OUT output with no input.

16. Measure the noise in the Y-OUT output with no input.

Measure the noise with a noise meter set up with a 200 kHz high-pass filter, a 5 MHz low-pass filter and a 4.43 MHz

trap filter.

17. Let V1 be the Y-OUT output with a 200 kHz 400 mVp-p sine wave input and SW3 set to c, and let V2 be the C-OUT

output with SW3 set to b.

ZOY = ×500 [Ω]

18. The Y-OUT delay time with respect to Y-IN

V2 [mVp-p] – V1 [mVp-p]

V1 [mVp-p]

S [mV]

Y [mV]

No. 5113-5/8

LC89972M

Block Diagram

Control Pin Function

Switching Voltage Levels

Note: Since the control pin has a built-in pull-down resistor, the pin will be set to the low state if left open.

No. 5113-6/8

LC89972M

CONT Mode (representative example) Chrominance signal delay Luminance signal delay

(CCD bits) (CCD bits)

Low PAL/GBI 2 H (1705) + 0 H (2.5) 1 H (849.5)

High 4.43 NTSC 1 H (847) + 0 H (2.5) 1 H (843.5)

Low/high Symbol min typ max Unit

Low VL–0.3 0.0 +0.5 V

High VH2.0 5.0 6.0 V

VCO OUT Pin Function

This pin outputs the 3 fsc clock generated by the PLL 3 ×frequency multiplier circuit.

Test Circuit

No. 5113-7/8

LC89972M

Test Circuit

PS No. 5113-8/8

LC89972M

This catalog provides information as of July, 1995. Specifications and information herein are subject to change

without notice.

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