@ T2L FAST input and outputs @ Delays stable and precise @ 8-pin SIP package (.400 high) @ Available in delays from 25 to 400ns @ 20% taps each isolated and with 10 T@L fan-out capacity @ Fast rise time on all outputs design notes The "SIP Series" Logic Delay Modules developed by Engineered Components Company have been designed to provide precise tapped delays with required driving and pick-off circuitry contained in an 8&-pin SIP package compatible with FAST TL circuits. These logic delay modules are of hybrid construction utilizing the proven technologies of active integrated circuitry and of passive networks utilizing capacitive, inductive and resistive elements. The MTBF on these modules, when calculated per MIL-HDBK-217 for a 50C ground fixed environment, is in excess of 3 million hours. Module design includes compensation for propagation delays and incorpo- rates internal termination at the output; no additional external components are needed to obtain the desired delay. The SPFLOM-TTLis offered in 25 delays from 25ns to 400ns with 2 TL COMPATIBLE SIP LOGIC DELAY MODULE each module incorporating taps at 20% increments of total delay. Delay tolerances are maintained as shown inthe accompanying part number table, when tested underthe "Test Conditions" shown. Delay time is measured at the +1.5V level on the leading edge. Rise time for all modules is 4ns maximum when measured from 0.75 to 2.4V. Temperature coefficient of delay is approximately +500 ppm/ C over the operating temperature range of 0 to +70C. These modules accept either logic "1" or logic "0" inputs and reproduce the logic at the selected output tap without inversion, The delay modules are intended primarily for use with positive going pulses and are calibrated to the tolerances shown in the table on rising edge delay; where best accuracy is desired in applications using falling edge timing, it is recommended that a special unit be calibrated forthe specific application. Each module has the capability of driving up to 20 T@L loads with a maximum of 10 loads on any one tap. These "SIP Series" modules are packaged in an-pin SIP housing, molded of flame-proof Diallyl Phthalate per MIL-M-14, Type SDG-F, and are fully encapsulated in epoxy resin. Flat metal leads meet the solderability requirements of MIL-STD-202, Method 208. Marking consists of manufacturer's name, logo (EC), part num- ber, terminal identification and date code of manufacture. Allmarking is applied by silk screen process using white epoxy paint in accor- dance with MIL-STD-130, ta meet the permanency of identification required by MIL-STD-202, Method 215. engineered components company 3580 SACRAMENTO DRIVE @ P.O. BOX 8121, SAN LUIS OBISPO, CA 93403-8121 (805) 544-3800 @ OUTSIDE CALIFORNIA (800) 235-4144 @ FAX (805) 544-8091 BLOCK DIAGRAM IS SHOWN BELOW OPERATING SPECIFICATIONS rr SE _= = _ = * Vec supply voltage: ee ed eigen gar So 4.75 to 5.25 pc x x | Vee supply current: | | | Constant "Oia ofsiidek a wns . se 40mA typical | Coneiarit Wy ac eee eae eo Wma typical INPUT be DELAY LINE WITH | Logie 1 Input: I DRIVER T*L PICKOFF Voltage .-6 Oso taeier. . 2V min.; Vec max. | Currant. sis sees ween ee BY = 20UA max, 5.5V = 1mA max. | Logic 0 Input: x | Voltage eee ee ee seen ee = BY Max. l _ |= _ | Currant =: ++ "' nani a a mld mag S -.6mA max. Logic 1 Vollage cut: ........ we. 27 min. Logic O Voltage out: .... eee ... 5 max. 1 2 3 4 5 6 7 8 Operating temperature range: ...... 0 to 70C Vee IN 20% 40% 60% 80% OUTGROUND Storage temperature: ..........- -55 to +125C. + Delays increase or decrease approximately 2% for a respective increase or decrease of 5% in supply voltage. MECHANICAL DETAIL IS SHOWN BELOW PART NUMBER TABLE @ DELAYS AND TOLERANCES [in ns} Part Number Tap 1 Tap 2 Tap 3 Tap 4 Output ee SPFLOM-TTL-25 | 5+1 | 10+1 | 1541 | 2041 | 2521 SPFLOM-TTL-30 | 6r1 | 1221 | 1841 | 24t1 | a041 VINI 234 65 SPFLDM-T1L-35 | 741 | 1441 | 2te1 | 28415] 35415 SPFLOM-TTL-40 | 6+1 | 1641 | 2421.5] 2241.5| 4021.5 SPFLOM-TTL-45 | 921 | 1841 | 2741.5] 3641.5] 4522 SPFLDM-TTL-50 |10+1 | 2041 | 90+1.5| 402 | s0+2 SPFLOM-TTL-85 | 1141 | 2+1 | ag~15| 4442 | 5522 180 t SPFLDM-TIL-60 | 12+1 | 2441 | 36415] 48+2 | 60+2 400 7? engineered SPFLDOM-TIL-65 | 1341 | 26415| 39415] 52+2 | 65425 components co. SPFLOM-TTL-70 | i4+1 | 2841.5] 4222 5642 70+ 2.5 oo ee ee 9434 SPFLOM-TTL-75 | 15+1 | 3041.5] 4542 6+25) 7542.5 - ns SPFLDM-TTL-80 | 1621 | 2241.5] 4822 | 64+25] 8023 | | | | | | 130 + .030 SPFLDM-TTL-65 | 1741 | 3441.5] 5122 | 68425] 85+3 SPFLDM-TTL-90 | 18+1 | 36415] 54+2 | 72425] 923 rll 018 ae | SPFLDM-TTL-95 | 1941 | 98215] 57+2 | 76425] 9623 SPFLDM-TTL-100| 2041 | 4021.5) S042 8+93 | 100+ SPFLDM-TTL-125| 25+ 1 | SO+2 7542.5/100+3 | 12544 100 ee = SPFLDM-TTL-150| 90+1.5] 0+2 | 9023 |120+4 | 15045 o10- 050 TYP. SPFLDM-TTL-175| 352 1.5] 7042.5] 105+4 | 14025 |175+5 y tines saree te SPFLDM-TTL-200| 40+ 1.5] 80+2.5/120+4 |160=5 |200+6 7 SPFLDM-TTL-225] 45+2 | 923 [13544 |180+6 | 22527 SPFLDOM-TTL-250] 5022 |100+9 | 15044.5/20046 |250+8 SPFLDM-TIL-300| 60+2 [12044 |180+5 |240+7 | 30029 SPFLDM-TTL:-350 | 70+2 [140445)/210+7 | 28049 | 350211 TEST CONDITIONS SPFLOM-TTL-400] 80+3 [160+5 | 24027 | 220410 | 400212 1. All measurements are made at 25C. 2. Vee supply voltage is maintained at 5.0V DC, 3. Allunits are tested using a FAST T*L taggle-type positive input @ All modules can be operated with a minimum input pulse width of 40% of full delay and pulse period approaching square wave, since delay accuracies may be somewhat degraded, it is suggested that pulse and one FAST TL load at the output being tested. the module be evaluated under the intended specific operating @4. Input pulse width used is 5 to 10ns longer than full delay of conditions. Special modules can be readily manufactured to im- module under test; spacing between pulses (falling edge ta prove accuracies andor provide customer specified random delay rising edge) is three times the pulse width used, times for specific applications, Catalog No. C/os2294