LTC2640ACTS8-LM12#TRMPBF - Linear Technology

LTC2640

2640fb

BLOCK DIAGRAM

FEATURES

APPLICATIONS

DESCRIPTION

Single 12-/10-/8-Bit SPI

VOUT DACs with

10ppm/°C Reference

The LTC

2640 is a family of 12-, 10-, and 8-bit voltage-

output DACs with an integrated, high-accuracy, low-drift

reference in an 8-lead TSOT-23 package. It has a rail-to-rail

output buffer that is guaranteed monotonic.

The LTC2640-L has a full-scale output of 2.5V, and operates

from a single 2.7V to 5.5V supply. The LTC2640-H has a

full-scale output of 4.096V, and operates from a 4.5V to

5.5V supply. A 10ppm/°C reference output is available at

the REF pin.

Each DAC can also operate in External Reference mode,

in which a voltage supplied to the REF pin sets the full-

scale output.

The LTC2640 DACs use a SPI/MICROWIRE™ compatible

3-wire serial interface which operates at clock rates up

to 50MHz.

The LTC2640 incorporates a power-on reset circuit. Op-

tions are available for Reset to Zero-Scale or Reset to

Mid-Scale after power-up.

Integral Nonlinearity (LTC2640A-LZ12)

n Integrated Precision Reference

2.5V Full-Scale 10ppm/°C (LTC2640-L)

4.096V Full-Scale 10ppm/°C (LTC2640-H)

n Maximum INL Error: 1LSB (LTC2640A-12)

n Bidirectional Reference: Input or 10ppm/°C Output

n Low Noise (0.7mVpp, 0.1Hz to 200kHz)

n Guaranteed Monotonic Over Temperature

n 2.7V to 5.5V Supply Range (LTC2640-L)

n Low Power Operation: 180μA at 3V

n Power Down to 1.8μA Maximum (C and I Grades)

n Asynchronous DAC Clear Pin (LTC2640-Z)

n Power-On Reset to Zero or Mid-Scale options

n Double-Buffered Data Latches

n Guaranteed Operation from –40°C to 125°C (H-Grade)

n 8-Lead TSOT-23 (ThinSOT™) Package

n Mobile Communications

n Process Control and Industrial Automation

n Automatic Test Equipment

n Portable Equipment

n Automotive

n Optical Networking

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents including 5396245, 5859606, 6891433,

6937178 and 7414561.

(LTC2640-Z)

DAC

RESISTOR

DIVIDER

INTERNAL

REFERENCE

INPUT

24-BIT

SHIFT

DAC VOUT

SWITCH

CONTROL

DECODE LOGIC

CS/LD

VCC REF

GND

CLR

DACREF

2640 TA01

SCK

SDI

CODE

INL (LSB)

0.5

4095

2640 TA01b

–0.5

–1.0 1024 2048 3072

1.0 VCC = 3V

VFS = 2.5V

LTC2640

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ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VCC) ................................... –0.3V to 6V

CLR, CS/LD, REF_SEL, SCK, SDI ................. –0.3V to 6V

VOUT, REF ......................... –0.3V to Min(VCC + 0.3V, 6V)

Operating Temperature Range

LTC2640C ................................................ 0°C to 70°C

LTC2640I.............................................. –40°C to 85°C

LTC2640H (Note 3) ............................ –40°C to 125°C

(Notes 1, 2)

CS/LD 1

SCK 2

SDI 3

GND 4

8CLR

7 VOUT

6 REF

5 VCC

TOP VIEW

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

TJMAX = 150°C (NOTE 6), θJA = 195°C/W

CS/LD 1

SCK 2

SDI 3

GND 4

8 REF_SEL

7 VOUT

6 REF

5 VCC

TOP VIEW

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

TJMAX = 150°C (NOTE 6), θJA = 195°C/W

PIN CONFIGURATION

Maximum Junction Temperature........................... 150°C

Storage Temperature Range ...................–65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

LTC2640-Z LTC2640-M

LTC2640

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LTC2640 A C TS8 –L M 12 #TRM PBF

LEAD FREE DESIGNATOR

TAPE AND REEL

TR = 2,500-Piece Tape and Reel

TRM = 500-Piece Tape and Reel

RESOLUTION

12 = 12-Bit

10 = 10-Bit

8 = 8-Bit

POWER-ON RESET

M = Reset to Mid-Scale

Z = Reset to Zero-Scale

FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE

L = 2.5V

H = 4.096V

PACKAGE TYPE

TS8 = 8-Lead Plastic TSOT-23

TEMPERATURE GRADE

C = Commercial Temperature Range (0°C to 70°C)

I = Industrial Temperature Range (–40°C to 85°C)

H = Automotive Temperature Range (–40°C to 125°C)

ELECTRICAL GRADE (OPTIONAL)

A = ±1LSB Maximum INL (12-Bit)

PRODUCT PART NUMBER

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

ORDER INFORMATION

LTC2640

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PRODUCT SELECTION GUIDE

PART NUMBER PART MARKING*

VFS WITH INTERNAL

REFERENCE

POWER-ON RESET

TO CODE PIN 8 RESOLUTION VCC MAXIMUM INL

LTC2640A-LM12

LTC2640A-LZ12

LTC2640A-HM12

LTC2640A-HZ12

LTDH V

LTDH W

LTDH X

LTDH Y

2.5V • (4095/4096)

4.096V • (4095/4096)

Mid-Scale

Zero

Mid-Scale

Zero

REF_SEL

CLR

REF_SEL

CLR

12-Bit

2.7V – 5.5V

4.5V – 5.5V

±1LSB

LTC2640-LM12

LTC2640-LM10

LTC2640-LM8

LTDH V

LTDH Z

LTDJ F

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Mid-Scale

REF_SEL

12-Bit

10-Bit

8-Bit

2.7V – 5.5V

±2.5LSB

±1LSB

±0.5LSB

LTC2640-LZ12

LTC2640-LZ10

LTC2640-LZ8

LTDH W

LTDJ B

LTDJ G

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Zero

CLR

12-Bit

10-Bit

8-Bit

2.7V – 5.5V

±2.5LSB

±1LSB

±0.5LSB

LTC2640-HM12

LTC2640-HM10

LTC2640-HM8

LTDH X

LTDJ C

LTDJ H

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

Mid-Scale

REF_SEL

12-Bit

10-Bit

8-Bit

4.5V – 5.5V

±2.5LSB

±1LSB

±0.5LSB

LTC2640-HZ12

LTC2640-HZ10

LTC2640-HZ8

LTDH Y

LTDJ D

LTDJ J

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

Zero

CLR

12-Bit

10-Bit

8-Bit

4.5V – 5.5V

±2.5LSB

±1LSB

±0.5LSB

*The temperature grade is identiﬁ ed by a label on the shipping container.

LTC2640

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ELECTRICAL CHARACTERISTICS

LTC2640-8 LTC2640-10 LTC2640-12 LTC2640A-12

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

DC Performance

Resolution l8 10 12 12 Bits

Monotonicity VCC = 3V, Internal Ref. (Note 4) l8 10 12 12 Bits

DNL Differential

Nonlinearity

VCC = 3V, Internal Ref. (Note 4) l±0.5 ±0.5 ±1 ±1 LSB

INL Integral

Nonlinearity

VCC = 3V, Internal Ref. (Note 4) l±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 ±0.5 ±1 LSB

ZSE Zero-Scale Error VCC = 3V, Internal Ref.,

Code = 0

l0.5 5 0.5 5 0.5 5 0.5 5 mV

VOS Offset Error VCC = 3V, Internal Ref. (Note 5) l±0.5 ±5 ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV

VOSTC VOS Temperature

Coefﬁ cient

VCC = 3V, Internal Ref. (Note 5) ±10 ±10 ±10 ±10 μV/°C

FSE Full-Scale Error VCC = 3V, Internal Ref. (Note 11) l±0.08 ±0.4 ±0.08 ±0.4 ±0.08 ±0.4 ±0.08 ±0.4 %FSR

VFSTC Full-Scale Voltage

Temperature

Coefﬁ cient

VCC = 3V, Internal Ref. (Note 10)

C-Grade

I-Grade

H-Grade

±10

ppm/°C

Load Regulation Internal Ref., Mid-Scale,

VCC = 3V ±10%,

–5mA ≤ IOUT ≤ 5mA,

VCC = 5V ±10%,

–10mA ≤ IOUT ≤ 10mA

0.009

0.016

0.035

0.064

0.14

0.256

0.14

0.256

LSB/mA

ROUT DC Output

Impedance

Internal Ref., Mid-Scale,

VCC = 3V ±10%,

–5mA ≤ IOUT ≤ 5mA,

VCC = 5V ±10%,

–10mA ≤ IOUT ≤ 10mA

0.09

0.156

0.09

0.156

0.09

0.156

0.09

0.156

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2640-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2640A-LM12/-LZ12 (VFS = 2.5V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT DAC Output Span External Reference

Internal Reference

0 to VREF

0 to 2.5

PSR Power Supply Rejection VCC = 3V ±10% or 5V ±10% –80 dB

ISC Short-Circuit Output Current (Note 6)

Sinking

Sourcing

VFS = VCC = 5.5V

Zero-Scale; VOUT shorted to VCC

Full-Scale; VOUT shorted to GND

–28

–48

Power Supply

VCC Positive Supply Voltage For Speciﬁ ed Performance l2.7 5.5 V

ICC Supply Current (Note 7) VCC = 3V, VREF = 2.5V, External Reference

VCC = 3V, Internal Reference

VCC = 5V, VREF = 2.5V, External Reference

VCC = 5V, Internal Reference

150

180

160

190

200

240

210

260

μA

ISD Supply Current in Power-Down Mode

(Note 7)

VCC = 5V, C-Grade, I-Grade

VCC = 5V, H-Grade

0.6

1.8

μA

LTC2640

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ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2640-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2640A-LM12/-LZ12 (VFS = 2.5V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Reference Input

Input Voltage Range l0V

CC V

Resistance l160 190 220 kΩ

Capacitance 7.5 pF

IREF Reference Current, Power-Down Mode DAC Powered Down l0.005 0.1 μA

Reference Output

Output Voltage l1.240 1.250 1.260 V

Reference Temperature Coefﬁ cient ±10 ppm/°C

Output Impedance 0.5 kΩ

Capacitive Load Driving 10 μF

Short-Circuit Current VCC = 5.5V; REF Shorted to GND 2.5 mA

Digital I/O

VIH Digital Input High Voltage VCC = 3.6V to 5.5V

VCC = 2.7V to 3.6V

2.4

VIL Digital Input Low Voltage VCC = 4.5V to 5.5V

VCC = 2.7V to 4.5V

0.8

0.6

ILK Digital Input Leakage VIN = GND to VCC l±1 μA

CIN Digital Input Capacitance (Note 8) l2.5 pF

AC Performance

tSSettling Time VCC = 3V (Note 9)

±0.39% (±1LSB at 8-Bits)

±0.098% (±1LSB at 10-Bits)

±0.024% (±1LSB at 12-Bits)

3.2

3.8

4.1

μs

Voltage Output Slew Rate 1 V/μs

Capacitance Load Driving 500 pF

Glitch Impulse At Mid-Scale Transition 2.1 nV•s

Multiplying Bandwidth External Reference 300 kHz

enOutput Voltage Noise Density At f = 1kHz, External Reference

At f = 10kHz, External Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

140

130

160

150

nV√Hz

Output Voltage Noise 0.1Hz to 10Hz, External Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, External Reference

0.1Hz to 200kHz, Internal Reference,

CREF = 0.33μF

650

670

μVP-P

LTC2640

2640fb

TIMING CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 8).

LTC2640-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2640A-LM12/-LZ12 (VFS = 2.5V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t1SDI Valid to SCK Setup l4ns

t2SDI Valid to SCK Hold l4ns

t3SCK High Time l9ns

t4SCK Low Time l9ns

t5CS/LD Pulse Width l10 ns

t6LSB SCK High to CS/LD High l7ns

t7CS/LD Low to SCK High l7ns

t9CLR Pulse Width l20 ns

t10 CS/LD High to SCK Pos. Edge l7ns

SCK Frequency 50% Duty Cycle l50 MHz

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (VFS = 4.096V)

LTC2640-8 LTC2640-10 LTC2640-12 LTC2640A-12

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

DC Performance

Resolution l8 10 12 12 Bits

Monotonicity VCC = 5V, Internal Ref. (Note 4) l8 10 12 12 Bits

DNL Differential

Nonlinearity

VCC = 5V, Internal Ref. (Note 4) l±0.5 ±0.5 ±1 ±1 LSB

INL Integral

Nonlinearity

VCC = 5V, Internal Ref. (Note 4) l±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 ±0.5 ±1 LSB

ZSE Zero-Scale Error VCC = 5V, Internal Ref.,

Code = 0

l0.5 5 0.5 5 0.5 5 0.5 5 mV

VOS Offset Error VCC = 5V, Internal Ref. (Note 5) l±0.5 ±5 ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV

VOSTC VOS Temperature

Coefﬁ cient

VCC = 5V, Internal Ref. (Note 5) ±10 ±10 ±10 ±10 μV/°C

FSE Full-Scale Error VCC = 5V, Internal Ref. (Note 11) l±0.08 ±0.4 ±0.08 ±0.4 ±0.08 ±0.4 ±0.08 ±0.4 %FSR

VFSTC Full-Scale Voltage

Temperature

Coefﬁ cient

VCC = 5V, Internal Ref. (Note 10)

C-Grade

I-Grade

H-Grade

±10

ppm/°C

Load Regulation VCC = 5V ±10%,

Internal Ref. Mid-Scale,

–10mA ≤ IOUT ≤ 10mA

l0.006 0.01 0.022 0.04 0.09 0.16 0.09 0.16 LSB/mA

ROUT DC Output

Impedance

VCC = 5V ±10%,

Internal Ref. Mid-Scale,

–10mA ≤ IOUT ≤ 10mA

l0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 Ω

LTC2640

2640fb

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (VFS = 4.096V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT DAC Output Span External Reference

Internal Reference

0 to VREF

0 to 4.096

PSR Power Supply Rejection VCC = 5V ±10% –80 dB

ISC Short-Circuit Output Current (Note 6)

Sinking

Sourcing

VFS = VCC = 5.5V

Zero-Scale; VOUT shorted to VCC

Full-Scale; VOUT shorted to GND

–28

–48

Power Supply

VCC Positive Supply Voltage For Speciﬁ ed Performance l4.5 5.5 V

ICC Supply Current (Note 7) VCC = 5V, VREF = 4.096V, External Reference

VCC = 5V, Internal Reference

160

200

220

270

μA

ISD Supply Current in Power-Down Mode

(Note 7)

VCC = 5V, C-Grade, I-Grade

VCC = 5V, H-Grade

0.6

1.8

μA

Reference Input

Input Voltage Range l0V

CC V

Resistance l160 190 220 kΩ

Capacitance 7.5 pF

IREF Reference Current, Power-Down Mode DAC Powered Down l0.005 0.1 μA

Reference Output

Output Voltage l2.032 2.048 2.064 V

Reference Temperature Coefﬁ cient ±10 ppm/°C

Output Impedance 0.5 kΩ

Capacitive Load Driving 10 μF

Short-Circuit Current VCC = 5.5V; REF Shorted to GND 4.3 mA

Digital I/O

VIH Digital Input High Voltage l2.4 V

VIL Digital Input Low Voltage l0.8 V

ILK Digital Input Leakage VIN = GND to VCC l±1 μA

CIN Digital Input Capacitance (Note 8) l2.5 pF

AC Performance

tSSettling Time VCC = 5V (Note 9)

±0.39% (±1LSB at 8 Bits)

±0.098% (±1LSB at 10 Bits)

±0.024% (±1LSB at 12 Bits)

3.7

4.2

4.6

μs

Voltage Output Slew Rate 1 V/μs

Capacitance Load Driving 500 pF

Glitch Impulse At Mid-Scale Transition 3.0 nV•s

Multiplying Bandwidth External Reference 300 kHz

LTC2640

2640fb

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (VFS = 4.096V)

TIMING CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 8).

LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (VFS = 4.096V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t1SDI Valid to SCK Setup l4ns

t2SDI Valid to SCK Hold l4ns

t3SCK High Time l9ns

t4SCK Low Time l9ns

t5CS/LD Pulse Width l10 ns

t6LSB SCK High to CS/LD High l7ns

t7CS/LD Low to SCK High l7ns

t9CLR Pulse Width l20 ns

t10 CS/LD High to SCK Pos. Edge l7ns

SCK Frequency 50% Duty Cycle l50 MHz

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltages are with respect to GND.

Note 3: High temperatures degrade operating lifetimes. Operating lifetime

is derated at temperatures greater than 105°C.

Note 4: Linearity and monotonicity are deﬁ ned from code kL to code

2N – 1, where N is the resolution and kL is given by kL = 0.016 • (2N/ VFS),

rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26

and linearity is deﬁ ned from code 26 to code 4,095. For VFS = 4.096V

and N = 12, kL = 16 and linearity is deﬁ ned from code 16 to code 4,095.

Note 5: Inferred from measurement at code 16 (LTC2640-12), code 4

(LTC2640-10) or code 1 (LTC2640-8), and at full-scale.

Note 6: This IC includes current limiting that is intended to protect the

device during momentary overload conditions. Junction temperature can

exceed the rated maximum during current limiting. Continuous operation

above the speciﬁ ed maximum operating junction temperature may impair

device reliability.

Note 7: Digital inputs at 0V or VCC.

Note 8: Guaranteed by design and not production tested.

Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale

and 3/4 scale to 1/4 scale. Load is 2k in parallel with 100pF to GND.

Note 10: Temperature coefﬁ cient is calculated by dividing the maximum

change in output voltage by the speciﬁ ed temperature range.

Note 11: Full-scale error is determined using the reference voltage

measured at the REF pin.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

enOutput Voltage Noise Density At f = 1kHz, External Reference

At f = 10kHz, External Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

140

130

210

200

nV√Hz

Output Voltage Noise 0.1Hz to 10Hz, External Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, External Reference

0.1Hz to 200kHz, Internal Reference,

CREF = 0.33μF

650

670

μVP-P

LTC2640

2640fb

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

INL vs Temperature DNL vs Temperature

Full-Scale Output Voltage

vs Temperature

Settling to ±1LSB

LTC2640-L12 (Internal Reference, VFS = 2.5V)

CODE

INL (LSB)

0.5

4095

2640 G01

–0.5

–1.0 1024 2048 3072

1.0 VCC = 3V

CODE

DNL (LSB)

0.5

4095

2640 G02

–0.5

–1.0 1024

VCC = 3V

2048 3072

1.0

Reference Output Voltage

vs Temperature

TEMPERATURE (°C)

–50 –25 25 75 125

VREF (V)

1.250

1.255

150

2640 G03

1.245

1.240 050 100

1.260

VCC = 3V

TEMPERATURE (°C)

–50 –25 25 75 125

INL (LSB)

0.5

150

2640 G04

–0.5

–1.0 050 100

1.0

VCC = 3V

INL (POS)

INL (NEG)

TEMPERATURE (°C)

–50 –25 25 75 125

DNL (LSB)

0.5

150

2640 G05

–0.5

–1.0 050 100

1.0

VCC = 3V

DNL (POS)

DNL (NEG)

TEMPERATURE (°C)

–50 –25 25 75 125

FS OUTPUT VOLTAGE (V)

2.50

2.51

150

2640 G06

2.49

2.48 050 100

2.52

VCC = 3V

2μs/DIV

2640 G07

VOUT

1LSB/DIV

1/4 SCALE TO 3/4 SCALE STEP

VCC = 3V, VFS = 2.5V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

CS/LD

2V/DIV

3.6μs

2μs/DIV

2640 G08

VOUT

1LSB/DIV

3/4 SCALE TO 1/4 SCALE STEP

VCC = 3V, VFS = 2.5V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

CS/LD

2V/DIV

4.1μs

TA = 25°C, unless otherwise noted.

LTC2640

2640fb

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

INL vs Temperature DNL vs Temperature

Full-Scale Output Voltage

vs Temperature

Settling to ±1LSB

LTC2640-H12 (Internal Reference, VFS = 4.096V)

CODE

INL (LSB)

0.5

4095

2640 G09

–0.5

–1.0 1024 2048 3072

1.0 VCC = 5V

CODE

DNL (LSB)

0.5

4095

2640 G10

–0.5

–1.0 1024 2048 3072

1.0 VCC = 5V

Reference Output Voltage

vs Temperature

TEMPERATURE (°C)

–50 –25 25 75 125

VREF (V)

2.048

2.058

150

2640 G11

2.038

2.028 050 100

2.068

VCC = 5V

TEMPERATURE (°C)

–50 –25 25 75 125

INL (LSB)

0.5

150

2640 G12

–0.5

–1.0 050 100

1.0

VCC = 5V

INL (POS)

INL (NEG)

TEMPERATURE (°C)

–50 –25 25 75 125

DNL (LSB)

0.5

150

2640 G13

–0.5

–1.0 050 100

1.0

VCC = 5V

DNL (POS)

DNL (NEG)

TEMPERATURE (°C)

–50 –25 25 75 125

FS OUTPUT VOLTAGE (V)

4.095

4.105

150

2640 G14

4.085

4.075 050 100

4.115

VCC = 5V

2μs/DIV

2640 G15

VOUT

1LSB/DIV

1/4 SCALE TO 3/4 SCALE STEP

VCC = 5V, VFS = 4.095V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

CS/LD

5V/DIV

3.9μs

2μs/DIV

2640 G16

VOUT

1LSB/DIV

CS/LD

5V/DIV

4.6μs

3/4 SCALE TO 1/4 SCALE STEP

VCC = 5V, VFS = 4.095V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

TA = 25°C, unless otherwise noted.

LTC2640

2640fb

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2640-10

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

Load Regulation Current Limiting Offset Error vs Temperature

LTC2640-8

LTC2640

CODE

INL (LSB)

0.5

1023

2640 G17

–0.5

–1.0 256 512 768

1.0 VCC = 5V

VFS = 4.096V

INTERNAL REF.

CODE

DNL (LSB)

0.5

1023

2640 G18

–0.5

–1.0 256 512 768

1.0 VCC = 5V

VFS = 4.096V

INTERNAL REF.

CODE

INL (LSB)

0.5

255

2640 G19

–0.5

–1.0 64 128 192

1.0 VCC = 3V

VFS = 2.5V

INTERNAL REF.

CODE

DNL (LSB)

0.25

255

2640 G20

–0.25

–0.50 64 128 192

0.50 VCC = 3V

VFS = 2.5V

INTERNAL REF.

IOUT (mA)

–30 –20 –10 0 10 20 30

ΔVOUT (mV)

2630 G21

–6

–4

–2

–8

–10

INTERNAL REF.

CODE = MIDSCALE

VCC = 5V (LTC2640-H)

VCC = 5V (LTC2640-L)

VCC = 3V (LTC2640-L)

IOUT (mA)

–30 –20 –10 0 10 20 30

$VOUT (V)

–0.05

0.05

0.10

0.15

2630 G22

–0.20

–0.15

–0.10

0.20

INTERNAL REF.

CODE = MIDSCALE

VCC = 5V (LTC2640-H)

VCC = 5V (LTC2640-L)

VCC = 3V (LTC2640-L)

TEMPERATURE (°C)

–50 –25 0 25 50 75 100 125 150

OFFSET ERROR (mV)

2640 G23

–1

–2

–3

TA = 25°C, unless otherwise noted.

LTC2640

2640fb

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2640

Large-Signal Response

Mid-Scale-Glitch Impulse Power-On Reset Glitch

Headroom at Rails

vs Output Current

Exiting Power-Down to Mid-Scale Supply Current vs Logic Voltage Hardware CLR

2μs/DIV

VOUT

0.5V/DIV

2640 G26

VFS = VCC = 5V

1/4 SCALE TO 3/4 SCALE

2μs/DIV

LTC2640-H12, VCC = 5V:

3.0nV-s TYP

LTC2640-L12, VCC = 3V:

2.1nV-s TYP

VOUT

5mV/DIV

2640 G27

CS/LD

5V/DIV

200μs/DIV

VCC

2V/DIV

2640 G28

LTC2640-L

VOUT

2mV/DIV

ZERO-SCALE

IOUT (mA)

012345678910

VOUT (V)

2.5

2.0

3.5

3.0

4.0

2640 G29

1.5

1.0

0.5

5.0

4.5 5V SOURCING

3V (LTC2640-L) SOURCING

3V (LTC2640-L) SINKING

5V SINKING

4μs/DIV

2640 G30

LTC2640-H

CS/LD

2V/DIV

VOUT

0.5V/DIV

LOGIC VOLTAGE (V)

ICC (mA)

1.4

1.2

0.8

0.4

1.0

0.6

0.2

0.0 42

2640 G31

531

VCC = 5V

VCC = 3V

(LTC2640-L)

SWEEP SCK, SDI, CS/LD

AND CLR BETWEEN

0V AND VCC

1μs/DIV

2640 G32

LTC2640-LZ

VOUT

1V/DIV

CLR

5V/DIV

Gain Error vs VCC Gain Error vs Temperature

VCC (V)

2.5 3 3.5 4 4.5 5 5.5

GAIN ERROR (%FSR)

0.1

0.2

0.3

2640 G24

0.0

–0.3

–0.2

–0.1

–0.4

0.4 EXTERNAL REF.

VREF = 2.5V

TEMPERATURE (°C)

–50 –25 0 25 50 75 100 125 150

GAIN ERROR (%FSR)

0.1

0.2

0.3

2640 G25

0.0

–0.3

–0.2

–0.1

–0.4

0.4 EXTERNAL REF.

VREF = 2.5V

TA = 25°C, unless otherwise noted.

LTC2640

2640fb

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2640

Multiplying Bandwidth Noise Voltage vs Frequency 0.1Hz to 10Hz Voltage Noise

PIN FUNCTIONS

CS/LD (Pin 1): Serial Interface Chip Select/Load Input.

When CS/LD is low, SCK is enabled for shifting data on

SDI into the register. When CS/LD is taken high, SCK

is disabled and the speciﬁ ed command (see Table 1) is

executed.

SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL

compatible.

SDI (Pin 3): Serial Interface Data Input. Data on SDI is

clocked into the DAC on the rising edge of SCK. The LTC2640

accepts input word lengths of either 24- or 32-bits.

GND (Pin 4): Ground.

VCC (Pin 5): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V

(LTC2640-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2640-H). Bypass

to GND with a 0.1μF capacitor.

REF (Pin 6): Reference Voltage Input or Output. When

External Reference mode is selected, REF is an input

(0V ≤ VREF ≤ VCC) where the voltage supplied sets the

full-scale voltage. When Internal Reference is selected,

the 10ppm/°C 1.25V (LTC2640-L) or 2.048V (LTC2640-H)

internal reference is available at the pin. This output may

be bypassed to GND with up to 10μF (0.33μF is recom-

mended), and must be buffered when driving external DC

load current.

VOUT (Pin 7): DAC Analog Voltage Output.

CLR (Pin 8, LTC2640-Z): Asynchronous Clear Input. A

logic low at this level-triggered input clears all registers

and causes the DAC voltage output to reset to Zero. CMOS

and TTL compatible.

REF_SEL (Pin 8, LTC2640-M): Selects default Reference

at power-up. Tie to VCC to select the Internal Reference,

or GND to select an External Reference. After power-up,

the logic state at this pin is ignored and the reference may

be changed only by software command.

FREQUENCY (Hz)

100

NOISE VOLTAGE (nV/√Hz)

200

300

2640 G34

100

01k 10k 100k

500

400

INTERNAL REF.

CODE = MIDSCALE

LTC2640-H

(VCC = 5V)

LTC2640-L

(VCC = 4V)

1s/DIV

10μV/DIV

2640 G35

LTC2640-L, VCC = 4V

INTERNAL REF.

CODE = MIDSCALE

FREQUENCY (Hz)

–2

–6

–8

–14

–4

–12

–10

–16

–18 100k

2640 G33

1000k10k

VCC = 5V

VREF(DC) = 2V

VREF(AC) = 0.2VP-P

CODE = FULL SCALE

TA = 25°C, unless otherwise noted.

LTC2640

2640fb

BLOCK DIAGRAMS

2640 BD

DAC

RESISTOR

DIVIDER

INTERNAL

REFERENCE

INPUT

24-BIT

SHIFT

DAC VOUT

SWITCH

CONTROL

DECODE LOGIC

CS/LD

VCC REF

GNDCLR

DACREF

SCK

SDI

DAC

RESISTOR

DIVIDER

INTERNAL

REFERENCE

INPUT

24-BIT

SHIFT

DAC VOUT

REF_SEL

SWITCH

CONTROL

DECODE LOGIC

CS/LD

VCC REF

GND

DACREF

SCK

SDI

LTC2640-Z

LTC2640-M

LTC2640

2640fb

TIMING DIAGRAM

Figure 1. Serial Interface Timing

SDI

CS/LD

SCK

t10

t5t7

t3t4

1232324

2640 F01

LTC2640

2640fb

The LTC2640 is a family of single voltage-output DACs

in 8-lead ThinSOT packages. Each DAC can operate rail-

to-rail using an external reference, or with its full-scale

voltage set by an integrated reference. 12 combinations

of accuracy (12-, 10-, and 8-bit), power-on reset value

(zero or mid-scale), and full-scale voltage (2.5V or 4.096V)

are available. The LTC2640 is controlled using a 3-wire

SPI/MICROWIRE compatible interface.

Power-On Reset

The LTC2640-HZ/LTC2640-LZ clear the output to zero-scale

when power is ﬁ rst applied, making system initialization

consistent and repeatable.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2640

contains circuitry to reduce the power-on glitch: the

analog output typically rises less than 5mV above zero-

scale during power on if the power supply is ramped

to 5V in 1ms or more. In general, the glitch amplitude

decreases as the power supply ramp time is increased.

See “Power-On Reset Glitch” in the Typical Performance

Characteristics section.

The LTC2640-HM/LTC2640-LM provide an alternative

reset, setting the output to mid-scale when power is ﬁ rst

applied.

Default reference mode selection is described in the Refer-

ence Modes section.

Power Supply Sequencing

The voltage at REF (Pin 6) should be kept within the range

–0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Rat-

ings). Particular care should be taken to observe these

limits during power supply turn-on and turn-off sequences,

when the voltage at VCC (Pin 5) is in transition.

Transfer Function

The digital-to-analog transfer function is:

VOUT(IDEAL) =k









VREF

where k is the decimal equivalent of the binary DAC input

code, N is the resolution, and VREF is either 2.5V (LTC2640-

LM/LTC2640-LZ) or 4.096V (LTC2640-HM/LTC2640-HZ)

when in Internal Reference mode, and the voltage at REF

(Pin 6) when in External Reference mode.

OPERATION

Figure 2. Command and Data Input Format

2640 F02

COMMAND 4 DON'T-CARE BITS

MSB

LSB

DATA (12 BITS + 4 DON'T-CARE BITS)

C2 C1 C0 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

COMMAND 4 DON'T-CARE BITS DATA (10 BITS + 6 DON'T-CARE BITS)

C2 C1 C0 X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXXXXX

COMMAND

INPUT WORD (LTC2640-12)

INPUT WORD (LTC2640-10)

INPUT WORD (LTC2640-8)

4 DON'T-CARE BITS DATA (8 BITS + 8 DON'T-CARE BITS)

C2 C1 C0 X X X X D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXX

LTC2640

2640fb

OPERATION

Serial Interface

The CS/LD input is level triggered. When this input is

taken low, it acts as a chip-select signal, enabling the SDI

and SCK buffers and the input shift register. Data (SDI

input) is transferred at the next 24 rising SCK edges.

The 4-bit command, C3-C0, is loaded ﬁ rst, followed by

4 don’t-cares bits, and ﬁ nally the 16-bit data word. The

data word comprises the 12-, 10- or 8-bit input code,

ordered MSB-to-LSB, followed by 4, 6 or 8 don’t-cares

bits (LTC2640-12, LTC2640-10 and LTC2640-8 respectively;

see Figure 2). Data can only be transferred to the device

when the CS/LD signal is low, beginning on the ﬁ rst rising

edge of SCK. SCK may be high or low at the falling edge

of CS/LD. The rising edge of CS/LD ends the data transfer

and causes the device to execute the command speciﬁ ed

in the 24-bit input sequence. The complete sequence is

shown in Figure 3a.

The command (C3-C0) assignments are shown in Table 1.

The ﬁ rst three commands in the table consist of write and

update operations. A Write operation loads a 16-bit data

word from the 24-bit shift register into the input register.

In an Update operation, the input register is copied to the

DAC register and converted to an analog voltage at the

DAC output. Write to and Update combines the ﬁ rst two

commands. The Update operation also powers up the

DAC if it had been in power-down mode. The data path

and registers are shown in the Block Diagram.

Table 1. Command Codes

COMMAND*

C3 C2 C1 C0

0 0 0 0 Write to Input Register

0 0 0 1 Update (Power-Up) DAC Register

0 0 1 1 Write to and Update (Power-Up) DAC Register

0 1 0 0 Power Down

0 1 1 0 Select Internal Reference

0 1 1 1 Select External Reference

*Command codes not shown are reserved and should not be used

While the minimum input sequence is 24-bits, it may

optionally be extended to 32-bits to accommodate micro-

processors that have a minimum word width of 16-bits

(2-bytes). To use the 32-bit width, 8 don’t-cares bits are

transferred to the device ﬁ rst, followed by the 24-bit sequence

described. Figure 3b shows the 32-bit sequence.

The 16-bit data word is ignored for all commands that do

not include a Write operation.

Reference Modes

For applications where an accurate external reference is

not available, the LTC2640 has a user-selectable, integrated

reference. The LTC2640-LM/LTC2640-LZ provide a full-

scale output of 2.5V. The LTC2640-HM/LTC2640-HZ provide

a full-scale output of 4.096V. The internal reference can be

useful in applications where the supply voltage is poorly

regulated. Internal Reference mode can be selected by using

command 0110, and is the power-on default for LTC2640-

HZ/LTC2640-LZ, as well as for LTC2640-HM/LTC2640-LM

when REF_SEL is tied high.

The 10ppm/°C, 1.25V (LTC2640-LM/LTC2640-LZ) or

2.048V (LTC2640-HM/LTC2640-HZ) internal reference

is available at the REF pin. Adding bypass capacitance

to the REF pin will improve noise performance; 0.33μF

is recommended, and up to 10μF can be driven without

oscillation. This output must be buffered when driving an

external DC load current.

Alternatively, the DAC can operate in External Reference

mode using command 0111. In this mode, an input voltage

supplied externally to the REF pin provides the reference

(0V ≤ VREF ≤ VCC) and the supply current is reduced.

External Reference mode is the power-on default for

LTC2640-HM/LTC2640-LM when REF_SEL is tied low.

The reference mode of LTC2640-HZ/LTC2640-LZ can be

changed only by software command. The same is true for

LTC2640-HM/LTC2640-LM after power-on, after which the

logic state on REF_SEL is ignored.

LTC2640

2640fb

OPERATION

Power-Down Mode

For power-constrained applications, the LTC2640’s power-

down mode can be used to reduce the supply current

whenever the DAC output is not needed. When in power-

down, the buffer ampliﬁ er, bias circuit, and reference

circuit are disabled and draw essentially zero current. The

DAC output is put into a HIGH-impedance state, and the

output pin is passively pulled to ground through a 200k

resistor. Input and DAC register contents are not disturbed

during power-down.

The DAC can be put into power-down mode by using

command 0100. The supply current is reduced to 1.8μA

maximum (C and I grades) and the REF pin becomes HIGH

impedance (typically > 1GΩ).

Normal operation resumes after executing any command

that includes a DAC update, as shown in Table 1. The

DAC is powered up and its voltage output is updated.

Normal settling is delayed while the bias, reference, and

ampliﬁ er circuits are re-enabled. When the REF pin output

is bypassed to GND with 1nF or less, the power-up delay

time is 20μs for settling to 12-bits. This delay increases

to 200μs for 0.33μF, and 10ms for 10μF.

Voltage Output

The LTC2640’s integrated rail-to-rail ampliﬁ er has guar-

anteed load regulation when sourcing or sinking up to

10mA at 5V, and 5mA at 3V.

Load regulation is a measure of the ampliﬁ er’s ability to

maintain the rated voltage accuracy over a wide range of

load current. The measured change in output voltage per

change in forced load current is expressed in LSB/mA.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change in

units from LSB/mA to ohms. The ampliﬁ er’s DC output

impedance is 0.1Ω when driving a load well away from

the rails.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by

the 50Ω typical channel resistance of the output devices

(e.g., when sinking 1mA, the minimum output voltage is

50Ω • 1mA, or 50mV). See the graph “Headroom at Rails

vs. Output Current” in the Typical Performance Charac-

teristics section.

The ampliﬁ er is stable driving capacitive loads of up to

500pF.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is limited

to voltages within the supply range.

Since the analog output of the DAC cannot go below ground,

it may limit the lowest codes, as shown in Figure 4b.

Similarly, limiting can occur near full-scale when the REF

pin is tied to VCC. If VREF = VCC and the DAC full-scale error

(FSE) is positive, the output for the highest codes limits

at VCC, as shown in Figure 4c. No full-scale limiting can

occur if VREF is less than VCC – FSE.

Offset and linearity are deﬁ ned and tested over the region

of the DAC transfer function where no output limiting can

occur.

Board Layout

The PC board should have separate areas for the analog and

digital sections of the circuit. A single, solid ground plane

should be used, with analog and digital signals carefully

routed over separate areas of the plane. This keeps digital

signals away from sensitive analog signals and minimizes

the interaction between digital ground currents and the

analog section of the ground plane. The resistance from

the LTC2640 GND pin to the ground plane should be as

low as possible. Resistance here will add directly to the

effective DC output impedance of the device (typically

0.1Ω). Note that the LTC2640 is no more susceptible to

LTC2640

2640fb

OPERATION

this effect than any other parts of this type; on the con-

trary, it allows layout-based performance improvements

to shine rather than limiting attainable performance with

excessive internal resistance.

Another technique for minimizing errors is to use a sepa-

rate power ground return trace on another board layer.

The trace should run between the point where the power

supply is connected to the board and the DAC ground pin.

Thus the DAC ground pin becomes the common point for

analog ground, digital ground, and power ground. When

the LTC2640 is sinking large currents, this current ﬂ ows

out the ground pin and directly to the power ground trace

without affecting the analog ground plane voltage.

It is sometimes necessary to interrupt the ground plane

to conﬁ ne digital ground currents to the digital portion of

the plane. When doing this, make the gap in the plane only

as long as it needs to be to serve its purpose and ensure

that no traces cross over the gap.

LTC2640

2640fb

OPERATION

Figure 3a. LTC2640-12 24-Bit Load Sequence (Minimum Input Word).

LTC2640-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Cares Bits;

LTC2640-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Cares Bits

Figure 3b. LTC2640-12 32-Bit Load Sequence

LTC2640-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Cares Bits;

LTC2640-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Cares Bits

12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24

C2 C1 C0 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X XC3

CS/LD

SCK

SDI

COMMAND WORD 4 DON’T-CARE BITS DATA WORD

24-BIT INPUT WORD

2640 F03a

12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

C2 C1 C0 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X XC3XXXXXXXX

CS/LD

SCK

SDI

COMMAND WORD DATA WORD

8 DON’T-CARE BITS 4 DON’T-CARE BITS

2640 F03b

32-BIT INPUT WORD

LTC2640

2640fb

OPERATION

Figure 4. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12-Bits)

(a) Overall Transfer Function

(b) Effect of Negative Offset for Codes Near Zero

2640 F04

INPUT CODE

(b)

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

0V 2,0480 4,095

INPUT CODE

OUTPUT

VOLTAGE

(a)

VREF = VCC

(c)

INPUT CODE

OUTPUT

VOLTAGE

POSITIVE

FSE

LTC2640

2640fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

TS8 Package

8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637)

1.50 – 1.75

(NOTE 4)

2.80 BSC

0.22 – 0.36

8 PLCS (NOTE 3)

DATUM ‘A’

0.09 – 0.20

(NOTE 3) TS8 TSOT-23 0802

2.90 BSC

(NOTE 4)

0.65 BSC

1.95 BSC

0.80 – 0.90

1.00 MAX 0.01 – 0.10

0.20 BSC

0.30 – 0.50 REF

PIN ONE ID

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

3.85 MAX

0.52

MAX

0.65

REF

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

1.4 MIN

2.62 REF

1.22 REF

LTC2640

2640fb

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 1108 REV B • PRINTED IN USA

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SDI

SCK

CS/LD

0.1μF

VOUT = ±5V

VCC REF

VOUT

SERIAL

BUS LTC2640A

-LM12

2640 TA03

–

LTC2054

GND

REF_SEL

–10V

10V

LT1991

VEE

VCC

OUT

REF

0.1μF