IDT7024S25PF8 - Integrated Device Technology

1

OCTOBER 2008

DSC 2740/13

IDT7024S/LHIGH-SPEED

4K x 16 DUAL-PORT

STATIC RAM

◆◆

◆IDT7024 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

◆◆

◆M/S = H for BUSY output flag on Master

M/S = L for BUSY input on Slave

◆◆

◆Interrupt Flag

◆◆

◆On-chip port arbitration logic

◆◆

◆Full on-chip hardware support of semaphore signaling

between ports

◆◆

◆Fully asynchronous operation from either port

◆◆

◆Battery backup operation—2V data retention

◆◆

◆TTL-compatible, single 5V (±10%) power supply

◆◆

◆Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin

Quad Flatpack

◆◆

◆Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆◆

◆Green parts availble, see ordering information

Functional Block Diagram

Features

◆◆

◆True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

◆◆

◆High-speed access

– Military: 20/25/35/55/70ns (max.)

– Industrial: 55ns (max.)

– Commercial: 15/17/20/25/35/55ns (max.)

◆◆

◆Low-power operation

– IDT7024S

Active: 750mW (typ.)

Standby: 5mW (typ.)

– IDT7024L

Active: 750mW (typ.)

Standby: 1mW (typ.)

◆◆

◆Separate upper-byte and lower-byte control for multiplexed

bus compatibility

I/O

Control

Address

Decoder MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

Address

Decoder

I/O

Control

R/W

L

BUSY

L

A

11L

A

0L

2740 drw 01

UB

L

LB

L

CE

L

OE

L

I/O

8L

-I/O

15L

I/O

0L

-I/O

7L

CE

L

OE

L

R/W

L

SEM

L

INT

L

M/S

R/W

R

BUSY

R

UB

R

LB

R

CE

R

OE

R

I/O

8R

-I/O

15R

I/O

0R

-I/O

7R

A

11R

A

0R

R/W

R

SEM

R

INT

R

CE

R

OE

R

(2)

(1,2) (1,2)

(2)

12 12

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

2

Description

The IDT7024 is a high-speed 4Kx 16 Dual-Port Static RAM. The

IDT7024 is designed to be used as a stand-alone 64K-bit Dual-Port RAM

or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or more

word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach

in 32-bit or wider memory system applications results in full-speed, error-

free operation without the need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for

reads or writes to any location in memory. An automatic power down

feature controlled by chip enable (CE) permits the on-chip circuitry of each

Pin Configurations(1,2,3)

NOTES:

1. All VCC pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.

F84-2 package body is approximately 1.17 in x 1.17 in x .11 in.

PN100-1 package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

port to enter a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these

devices typically operate on only 750mW of power. Low-power (L)

versions offer battery backup data retention capability with typical power

consumption of 500µW from a 2V battery.

The IDT7024 is packaged in a ceramic 84-pin PGA, an 84-pin Flatpack

and PLCC, and a 100-pin TQFP. Military grade product is manufactured

in compliance with the latest revision of MIL-PRF-38535 QML, making it

ideally suited to military temperature applications demanding the highest

level of performance and reliability.

2740 drw 02

14

15

16

17

18

19

20

INDEX

21

22

23

24

11109876543218483

33 34 35 36 37 38 39 40 41 42 43 44 45

V

CC

GND

I/O

8L

A

7L

13

12

25

26

27

28

29

30

31

32 46 47 48 49 50 51 52 53

72

71

70

69

68

67

66

65

64

63

62

73

74

61

60

59

58

57

56

55

54

82 81 80 79 78 77 76 75

GND

BUSY

L

GND

IDT7024J or F

J84-1

(4)

F84-2

(4)

84-Pin PLCC / Flatpack

Top View

(5)

INT

L

M/S

INT

R

I/O

9L

I/O

10L

I/O

11L

I/O

12L

I/O

13L

I/O

14L

I/O

15L

I/O

0R

I/O

1R

I/O

2R

V

CC

I/O

3R

I/O

4R

I/O

5R

I/O

6R

I/O

7R

I/O

8R

A

6L

A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

BUSY

R

A

0R

A

2R

A

3R

A

4R

A

5R

A

6R

A

1R

I/O

7L

I/O

6L

I/O

5L

I/O

4L

I/O

3L

I/O

2L

V

CC

R/W

L

SEM

L

CE

L

UB

L

LB

L

N/C

A

11L

GND

I/O

1L

I/O

0L

A

10L

A

9L

A

8L

OE

L

I/O

9R

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

GND

I/O

15R

GND

N/C

A

11R

A

10R

A

9R

A

8R

A

7R

OE

R

R/W

R

SEM

R

CE

R

UB

R

LB

R

,

11/06/01

Index

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

IDT7024PF

PN100-1(4)

100-Pin TQFP

Top View(5)

N/C

I/O

10L

I/O

11L

I/O

12L

I/O

13L

GND

I/O

14L

I/O

15L

V

CC

GND

I/O

0R

I/O

1R

I/O

2R

I/O

3R

V

CC

I/O

4R

I/O

5R

I/O

6R

N/C

2740 drw 03

N/C

A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

INT

L

GND

M/S

BUSY

R

INT

R

A

0R

N/C

BUSY

L

A

1R

A

2R

A

3R

A

4R

I/O

9L

I/O

8L

I/O

7L

I/O

6L

I/O

5L

I/O

4L

I/O

3L

I/O

2L

GND

I/O

1L

I/O

0L

OE

L

V

CC

R/W

L

SEM

L

CE

L

UB

L

LB

L

N/C

A

11L

A

10L

A

9L

A

8L

A

7L

A

6L

I/O

7R

I/O

8R

I/O

9R

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

GND

I/O

15R

OE

R

R/W

R

SEM

R

CE

R

UB

R

LB

R

GND

N/C

A

11R

A

10R

A

9R

A

8R

A

7R

A

6R

A

5R

,

11/06/01

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

3

Pin Names Maximum Operating Temperature

and Supply Voltage(1)

NOTES:

1. All VCC pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. Package body is approximately 1.12 in x 1.12 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

Pin Configurations(1,2,3) (con't.)

NOTES:

1. This is the parameter TA. This is the "instant on" case temperature.

2740 drw 04

I/O

7L

63 61 60 58 55 54 51 48 46 45

66

67

69

72

75

76

79

81

82

83

125

7

8

11

10

12

14 17 20

23

26

28 29

32 31

33 35

38

41

43

IDT7024G

G84-3(4)

84-Pin PGA

Top View(5)

ABCDEFGHJKL

42

59 56 49 50 40

25

27

30

36

34

37

39

84 3 4 6 9 15 13 16 18

22 24

19 21

68

71

70

77

80

UB

R

CE

R

GND

11

10

09

08

07

06

05

04

03

02

01

64

65

62

57 53 52

47 44

73

74

78

GND GND

R/W

R

OE

R

LB

R

GNDGND SEM

R

N/C

UB

L

CE

L

R/W

L

OE

L

GND

SEM

L

V

CC

LB

L

INT

R

BUSY

R

BUSY

L

M/S

INT

L

A

11L

N/C

I

ndex

I/O

5L

I/O

4L

I/O

2L

I/O

0L

I/O

10L

I/O

8L

I/O

6L

I/O

3L

I/O

1L

I/O

11L

I/O

9L

I/O

13L

I/O

12L

I/O

15L

I/O

14L

I/O

0R

A

9L

A

10L

A

8L

A

7L

A

5L

A

6L

A

4L

A

3L

A

2L

A

0L

A

1L

A

0R

A

2R

A

1R

A

5R

A

3R

A

6R

A

4R

A

9R

A

7R

A

8R

A

10R

A

11R

I/O

1R

I/O

2R

V

CC

I/O

3R

I/O

4R

I/O

5R

I/O

7R

I/O

6R

I/O

9R

I/O

8R

I/O

11R

I/O

10R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

V

CC

11/06/01

Left Port Right Port Names

CE

L

CE

R

Chip Enab le

R/W

L

R/W

R

Re ad /Write Enab le

OE

L

OE

R

Output Enab le

A

0L

- A

11L

A

0R

- A

11R

Address

I/O

0L

- I/ O

15L

I/O

0R

- I/O

15R

Data Inp ut/ Outp ut

SEM

L

SEM

R

Semaphore Enable

UB

L

UB

R

Upp er Byte Select

LB

L

LB

R

Lower Byte Select

INT

L

INT

R

Inte r rupt Fl ag

BUSY

L

BUSY

R

Busy Flag

M/SMaster or Slave Select

V

CC

Power

GND Ground

2740 tbl 01

Grade Ambient

Temperature GND Vcc

Military -55

O

C to +125

O

C0V5.0V

+

10%

Commercial 0

O

C to +70

O

C0V5.0V

+

10%

Industrial -40

O

C to +85

O

C0V5.0V

+

10%

2740 tbl 02

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

4

T ruth Table I: Non-Contention Read/Write Control

Recommended DC Operating

Conditions

T ruth Table II: Semaphore Read/Write Control(1)

Absolute Maximum Ratings(1)

NOTE:

1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0 - I/O15).

These eight semaphores are addressed by A0 - A2.

NOTE:

1. A0L — A11L ≠ A0R — A11R

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above

those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

2. VTERM must not exceed Vcc +10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period over VTERM > Vcc + 10%.

NOTES:

1. VIL > -1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 10%.

Inputs(1) Outputs

Mode

CE R/WOE UB LB SEM I/O

8-15

I/O

0-7

HXXXXHHigh-ZHigh-ZDeselcted: Power-Down

X X X H H H High-Z High-Z Both Bytes Deselected

LLXLHHDATA

IN

Hi g h-Z Wri te to Up p e r By te Onl y

LLXHLHHigh-ZDATA

IN

Write to Lo wer Byte Only

LLXLLHDATA

IN

DATA

IN

Wr i te to Both B y te s

LHLLHHDATA

OUT

High-Z Re ad Uppe r Byte Only

LHLHLHHigh-ZDATA

OUT

Re ad Lo wer Byte Only

LHLLLHDATA

OUT

DATA

OUT

Read Both Bytes

X X H X X X High-Z High-Z Outputs Disabled

2 740 t b l 03

Inputs

(1)

Outputs

Mode

CE

(2)

R/WOE UB LB SEM I/O

8-15

I/O

0-7

HHLXXLDATA

OUT

DATA

OUT

Read Semaphore Flag Data Out

XHLHHLDATA

OUT

DATA

OUT

Read Semaphore Flag Data Out

H↑XXXLDATA

IN

DATA

IN

Write I/O

0

into Semaphore Flag

X↑XHHLDATA

IN

DATA

IN

Write I/O

0

into Semaphore Flag

LXXLXL

____ ____

No t Allo we d

LXXXLL

____ ____

No t Allo we d

2740 tbl 04

Symbol Rating Commercial

& Industrial Military Unit

V

TERM

(2)

Te rminal Vo ltag e

with Re s pe c t

to GND

-0.5 to +7.0 -0.5 to +7.0 V

T

BIAS

Temperature

Under B i as -55 to +125 -65 to +135

o

C

T

STG

Storage

Temperature -65 to +150 -65 to +150

o

C

I

OUT

DC O utp u t

Current 50 50 mA

2740 tbl 05

Symbol Parameter Min. Typ. Max. Unit

V

CC

Sup ply Vo ltag e 4.5 5.0 5.5 V

GND Ground 0 0 0 V

V

IH

Input Hig h Vol tag e 2.2

____

6.0

(2)

V

IL

Input Lo w Vo ltag e -0.5

(1)

____

0.8 V

2740 tbl 06

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

5

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)

NOTES:

1. This parameter are determined by device characterization, but is not

production tested.

2. 3dV references the interpolated capacitance when the input and

output signals switch from 0V to 3V or from 3V to 0V.

Capacitance (TA = +25°C, f = 1.0MHz)(1)

NOTES:

1. 'X' in part number indicates power rating (S or L)

2. VCC = 5V, TA = +25°C, and are not production tested. ICC DC = 120mA (TYP.)

3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

NOTE:

1. At Vcc < 2.0V input leakages are undefined.

DC Electrical Characteristics Over the Operating

T emperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)

Symbol Parameter Conditions

(2)

Max. Unit

C

IN

Inp ut Cap ac itanc e V

IN

= 3dV 9 pF

C

OUT

Outp ut Capacitance V

OUT

= 3dV 10 pF

2740 tbl 07

Symbol Parameter Test Conditions

7024S 7024L

UnitMin. Max. Min. Max.

|I

LI

| Input Leakage Current

(1)

V

CC

= 5.5V, V

IN

= 0V to V

CC

___

10

___

5µA

|I

LO

| Outp ut Le ak age Curre nt CE = V

IH

, V

OUT

= 0V to V

CC

___

10

___

5µA

V

OL

Outp ut Lo w Vo ltag e I

OL

= +4mA

___

0.4

___

0.4 V

V

OH

Output Hig h Voltage I

OH

= -4mA 2.4

___

2.4

___

V

2740 t bl 0 8

7024X15

Com'l Only 7024X17

Com'l Only 7024X20

Com'l, Ind

& Mil itary

7024X25

Com'l &

Military

S ym bol Parameter Test Condi tion Versio n Typ.

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Unit

I

CC

Dy nam i c O p e ra ting

Current

(Both Po rts Ac ti ve)

CE = V

IL

,

Outputs Disabled

SEM = V

IH

f = f

MAX

(3)

COM'L S

L170

170 310

260 170

170 310

260 160

160 290

240 155

155 265

220 mA

MIL &

IND S

L____

____

____ 160

160 370

320 155

155 340

280

I

SB1

Standb y Curre nt

(Both Po rts - TTL

Le v e l Inp u ts)

CE

R

= CE

L

= V

IH

SEM

R

= SEM

L

= V

IH

f = f

MAX

(3)

COM'L S

L20

20 60

50 20

20 60

50 20

20 60

50 16

16 60

50 mA

MIL &

IND S

L____

____

____ 20

20 90

70 16

16 80

65

I

SB2

Standb y Curre nt

(One P o rt - TTL

Le v e l Inp u ts)

CE

"A"

= V

IL

and CE

"B"

= V

IH

(5)

A c ti v e P o rt O utpu ts Di s abl e d ,

f=f

MAX

(3)

SEM

R

= SEM

L

= V

IH

COM'L S

L105

105 190

160 105

105 190

160 95

95 180

150 90

90 170

140 mA

MIL &

IND S

L____

____

____ 95

95 240

210 90

90 215

180

I

SB3

Full Stand by Curre nt

(Both Po rt s -

CM OS Le v e l Inp ut s)

Bo th Ports CE

L

and

CE

R

> V

CC

- 0.2V,

V

IN

> V

CC

- 0. 2V o r

V

IN

< 0. 2V , f = 0

(4)

SEM

R

= SEM

L

>

V

CC

- 0.2V

COM'L S

L1.0

0.2 15

51.0

0.2 15

51.0

0.2 15

51.0

0.2 15

5mA

MIL &

IND S

L____

____

____ 1.0

0.2 30

10 1.0

0.2 30

10

I

SB4

Full Stand by Curre nt

(One P o rt -

CM OS Le v e l Inp ut s)

CE

"A"

< 0. 2V and

CE

"B"

> V

CC

- 0.2V

(5)

SEM

R

= SEM

L

> V

CC

- 0.2V

V

IN

> V

CC

- 0. 2V o r V

IN

< 0.2V

A c ti v e P o rt O utpu ts Di s abl e d ,

f = f

MAX

(3)

COM'L S

L100

100 170

140 100

100 170

140 90

90 155

130 85

85 145

120 mA

MIL &

IND S

L____

____

____ 90

90 225

200 85

85 200

170

2 740 tb l 09a

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

6

DC Electrical Characteristics Over the Operating

T emperature and Supply Voltage Range(1) (con’t.) (VCC = 5.0V ± 10%)

Data Retention Characteristics Over All Temperature Ranges

(L V ersion Only) (VLC = 0.2V, VHC = VCC - 0.2V)(4)

NOTES:

1. 'X' in part number indicates power rating (S or L)

2. VCC = 5V, TA = +25°C, and are not production tested.

3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

NOTES:

1. TA = +25°C, VCC = 2V, and are by device characterization but are not production tested.

2. tRC = Read Cycle Time

3. This parameter is guaranteed but not tested.

4.At Vcc < 2.0V, input leakages are not defined.

7024X35

Com 'l &

Military

7024X55

Com'l, Ind

& Military

7024X70

Military Only

Symbol Parameter Test Condition Version Typ.

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Uni

t

ICC Dynamic Ope rating

Current

(Bo th Po rts Active )

CE = VIL,

Outputs Disabled

SEM = VIH

f = fMAX

(3)

COM'L S

L150

150 250

210 150

150 250

210 ____

____

____ mA

MIL &

IND S

L150

150 300

250 150

150 300

250 140

140 300

250

ISB1 Standby Current

(Bo th Po rts - TTL

Le ve l Inputs )

CE

R = CEL = VIH

SEMR = SEML = VIH

f = fMAX

(3)

COM'L S

L13

13 60

50 13

13 60

50 ____

____

____ mA

MIL &

IND S

L13

13 80

65 13

13 80

65 10

10 80

65

ISB2 Standby Current

(One Po rt - TTL

Le ve l Inputs )

CE

"A" = VIL and CE"B" = VIH

(5)

Active Port Outputs Disabled,

f=fMAX

(3)

SEMR = SEML = VIH

COM'L S

L85

85 155

130 95

95 155

130 ____

____

____ mA

MIL &

IND S

L85

85 190

160 95

95 190

160 80

80 190

160

ISB3 Full S tand by Current

(Bo th Po rts -

CMOS Le ve l Inp uts)

Both Po rts CE

L and

CE

R > VCC - 0. 2V,

VIN > VCC - 0.2V o r

VIN < 0.2V , f = 0

(4)

SEMR = SEML > VCC - 0.2V

COM'L S

L1.0

0.2 15

51.0

0.2 15

5____

____

____ mA

MIL &

IND S

L1.0

0.2 30

10 1.0

0.2 30

10 1.0

0.2 30

10

ISB4 Full S tand b y Current

(One P o rt -

CMOS Le ve l Inp uts)

CE

"A" < 0.2V and

CE

"B" > VCC - 0.2V

(5)

SEMR = SEML > VCC - 0.2V

VIN > VCC - 0.2V o r VIN < 0.2V

Active Port Outputs Disabled,

f = fMAX

(3)

COM'L S

L80

80 135

110 80

80 135

110 ____

____

____ mA

MIL &

IND S

L80

80 175

150 80

80 175

150 75

75 175

150

2740 tbl 09b

Symbol Parameter Test Condi tion Min. Typ.

(1)

Max. Unit

V

DR

V

CC

fo r Data Rete ntio n V

CC

= 2V 2.0

___ ___

V

I

CCDR

Data Retention Curre nt CE > V

HC

V

IN

> V

HC

or < V

LC

MIL. & IND.

___

100 4000 µA

COM'L.

___

100 1500

t

CDR

(3)

Chip Des e l ec t to Data Re te ntio n Time SEM > V

HC

0

___ ___

ns

t

R

(3)

Op e ratio n Re c ov e ry Time t

RC

(2)

___ ___

ns

2740 tbl 10

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

7

Data Retention Waveform

AC Test Conditions

Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

*Including scope and Jig

Figure 1. AC Output Test Load

D

A

T

A

R

E

T

E

N

T

I

O

N

M

O

D

E

V

CC

CE

2740 drw 05

4.5V

t

CDR

t

R

V

IH

V

DR

V

IH

4.5V

V

DR

2V

≥

2740 drw 06

1250Ω

30pF

775Ω

5

V

DATA

OUT

BUSY

INT

1250Ω

5pF*

775Ω

5V

DATA

OUT

,

Inp ut Pul se Le v e ls

Inp ut Ris e /Fall Time s

Inp ut Timi ng Refe re nc e Le ve l s

Outp ut Refe re nc e Le ve ls

Outp ut Lo ad

GND to 3. 0V

5ns

1.5V

Fi g ure s 1 and 2

2740 tbl 11

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

8

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = VIL, UB or LB = VIL, and SEM =VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM =VIL.

4. 'X' in part number indicates power rating (S or L).

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(4)

7024X15

Com'l Only 7024X17

Com 'l Only 7024X20

Com'l, Ind

& Military

7024X25

Com'l &

Military

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.

READ CYCLE

t

RC

Re ad Cyc le Time 15

____

17

____

20

____

25

____

ns

t

AA

Address Access Time

____

15

____

17

____

20

____

25 ns

t

ACE

Chip Enable Access Time

(3)

____

15

____

17

____

20

____

25 ns

t

ABE

Byte Enable Access Time

(3)

____

15

____

17

____

20

____

25 ns

t

AOE

Output Enable Ac ce ss Time

____

10

____

10

____

12

____

13 ns

t

OH

Output Hold from A ddre ss Change 3

____

3

____

3

____

3

____

ns

t

LZ

Output Low-Z Time

(1,2)

3

____

3

____

3

____

3

____

ns

t

HZ

Outp ut Hig h-Z Time

(1,2)

____

10

____

10

____

12

____

15 ns

t

PU

Chip E nab l e to Po we r Up Tim e

(1,2)

0

____

0

____

0

____

0

____

ns

t

PD

C hip Dis ab le to Po wer Do wn Time

(1,2)

____

15

____

17

____

20

____

25 ns

t

SOP

Semaphore Flag Update Pulse (OE or SEM)10

____

10

____

10

____

10

____

ns

t

SAA

Semaphore Address Access

(3)

____

15

____

17

____

20

____

25 ns

2740 tbl 12a

7024X35

Com'l &

Military

7024X55

Com 'l, I nd

& Military

7024X70

Military Only

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.

READ CYCLE

t

RC

Read Cycle Time 35

____

55

____

70

____

ns

t

AA

Address Access Time

____

35

____

55

____

70 ns

t

ACE

Chip Enable Access Time

(3)

____

35

____

55

____

70 ns

t

ABE

Byte Enable Acce ss Time

(3)

____

35

____

55

____

70 ns

t

AOE

Outp ut Enab le Ac ce ss Time

____

20

____

30

____

35 ns

t

OH

Output Hold from Ad d ress Chang e 3

____

3

____

3

____

ns

t

LZ

Outp ut Low-Z Time

(1,2)

3

____

3

____

3

____

ns

t

HZ

Output High-Z Time

(1,2)

____

15

____

25

____

30 ns

t

PU

Chip Enab le to Power Up Time

(1,2)

0

____

0

____

0

____

ns

t

PD

Chip Dis ab le to Powe r Do wn Time

(1,2)

____

35

____

50

____

50 ns

t

SOP

Semaphore Flag Update Pulse (OE or SEM)15

____

15

____

15

____

ns

t

SAA

Semaphore Address Access

(3)

____

35

____

55

____

70 ns

2740 tbl 12b

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

9

NOTES:

1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.

2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.

3. tBDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has

no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

Waveform of Read Cycles(5)

t

RC

R/W

CE

ADDR

t

AA

OE

UB,LB

2740 drw 07

(4)

t

ACE

(4)

t

AOE

(4)

t

ABE

(4)

(1)

t

LZ

t

OH

(2)

t

HZ

(3,4)

t

BDD

DATA

OUT

BUSY

OUT

VALID DATA

(4)

CE

2740 drw 08

t

PU

I

CC

I

SB

t

PD

,

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

10

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage(5)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.

Either condition must be valid for the entire tEW time.

4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH

and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW.

5. 'X' in part number indicates power rating (S or L).

Symbol Parameter

7024X15

Com'l Only 7024X17

Com'l Only 7024X20

Com 'l, I nd

& Military

7024X25

Com'l &

Military

UnitMin. Max. Min. Max. Min. Max. Min. Max.

WRITE CYCLE

t

WC

Write Cycle Time 15

____

17

____

20

____

25

____

ns

t

EW

Chip Enable to End-of-Write

(3)

12

____

12

____

15

____

20

____

ns

t

AW

Address Valid to End-of-Write 12

____

12

____

15

____

20

____

ns

t

AS

Address Set-up Time

(3)

0

____

0

____

0

____

0

____

ns

t

WP

Write Pulse Width 12

____

12

____

15

____

20

____

ns

t

WR

Write Recovery Time 0

____

0

____

0

____

0

____

ns

t

DW

Data Vali d to En d -of-Wri te 10

____

10

____

15

____

15

____

ns

t

HZ

Output High-Z Time

(1,2)

____

10

____

10

____

12

____

15 ns

t

DH

Data Hold Time

(4)

0

____

0

____

0

____

0

____

ns

t

WZ

Write Enab le to Output in High-Z

(1,2)

____

10

____

10

____

12

____

15 ns

t

OW

Outp ut A cti ve fro m End -o f-Wri te

(1,2,4)

0

____

0

____

0

____

0

____

ns

t

SWRD

SEM Flag Write to Read Time 5

____

5

____

5

____

5

____

ns

t

SPS

SEM Flag Contention Window 5

____

5

____

5

____

5

____

ns

2 740 tb l 13 a

Symbol Parameter

7024X35

Com 'l &

Military

7024X55

Com 'l, I nd

& Military

7024X70

Military Only

UnitMin. Max. Min. Max. Min. Max.

WRITE CYCLE

t

WC

Write Cycle Time 35

____

55

____

70

____

ns

t

EW

Chip Enable to End-of-Write

(3)

30

____

45

____

50

____

ns

t

AW

Address Valid to End-of-Write 30

____

45

____

50

____

ns

t

AS

Address Set-up Time

(3)

0

____

0

____

0

____

ns

t

WP

Write Pulse Width 25

____

40

____

50

____

ns

t

WR

Write Recovery Time 0

____

0

____

0

____

ns

t

DW

Data Vali d to En d -of-Wri te 15

____

30

____

40

____

ns

t

HZ

Output High-Z Time

(1,2)

____

15

____

25

____

30 ns

t

DH

Data Hold Time

(4)

0

____

0

____

0

____

ns

t

WZ

Write Enab le to Output in High-Z

(1,2)

____

15

____

25

____

30 ns

t

OW

Outp ut A cti ve fro m End -o f-Wri te

(1,2,4)

0

____

0

____

0

____

ns

t

SWRD

SEM Flag Write to Read Time 5

____

5

____

5

____

ns

t

SPS

SEM Flag Contention Window 5

____

5

____

5

____

ns

2740 tbl 13b

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

11

Timing Wa v eform of Write Cyc le No. 1, R/W Controlled Timing(1,5,8)

Timing Wa vef orm of Write Cyc le No. 2, CE, UB, LB Controlled Timing(1,5)

NOTES:

1. R/W or CE or UB & LB = VIH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a UB or LB = VIL and a CE = VIL and a R/W = VIL for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH = VIL to the end-of-write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE, R/W, UB, or LB.

7. This parameter is guaranted by device characterization, but is not production tested. Transition is measured 0mV steady state with the Output Test Load

(Figure 2).

8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP for (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified tWP .

9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. tEW must be

met for either condition.

R/W

t

WC

t

HZ

t

AW

t

WR

t

AS

t

WP

DATA

OUT

(2)

t

WZ

t

DW

t

DH

t

OW

OE

ADDRESS

DATA

IN

(6)

(4) (4)

(7)

UB or LB

2740 drw 09

(9)

CE or SEM

(9)

(7)

(3)

2740 drw 10

t

WC

t

AS

t

WR

t

DW

t

DH

ADDRESS

DATA

IN

R/W

t

AW

t

EW

UB or LB

(3)

(2)

(6)

CE or SEM

(9)

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

12

Timing Wa veform of Semaphore Read after Write Timing, Either Side(1)

NOTES:

1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).

2. “DATAOUT VALID” represents all I/O's (I/O0-I/O15) equal to the semaphore value.

NOTES:

1. D0R = D0L = VIL, CER = CEL = VIH, or both UB & LB = VIH, semaphore flag is released from both sides (reads as ones from both sides) at cycle start.

2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/WA or SEMA going HIGH to R/WB or SEMB going HIGH.

4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.

Timing Waveform of Semaphore Write Contention(1,3,4)

SEM

2740 drw 11

t

AW

t

EW

t

SOP

I/O

0

VALID ADDRESS

t

SAA

R/W

t

WR

t

OH

t

ACE

VALID ADDRESS

DATA

IN

VALID DATA

OUT

t

DW

t

WP

t

DH

t

AS

t

SWRD

t

AOE

Read CycleWrite Cycle

A

0

-A

2

OE

VALID

(2)

SEM

"A"

2740 drw 12

t

SPS

MATCH

R/W

"A"

MATCH

A

0"A"

-A

2"A"

SIDE "A"

(2)

SEM

"B"

R/W

"B"

A

0"B"

-A

2"B"

SIDE

(2)

"B"

,

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

13

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write Port-to-Port Read and BUSY (M/S = VIH)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port 'B' during contention with port 'A'.

5. To ensure that a write cycle is completed on port 'B' after contention with port 'A'.

6. 'X' in part number indicates power rating (S or L).

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(6)

7024X15

Com'l Only 7024X17

Com'l Only 7024X20

Com'l, Ind

& Military

7024X25

Co m 'l &

Military

Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit

BUSY TI MING (M/S = V

IH

)

t

BAA

BUSY Access Time from Address Match

____

15

____

17

____

20

____

20 ns

t

BDA

BUSY Disable Time from Address Not Match

____

15

____

17

____

20

____

20 ns

t

BAC

BUSY A ccess Time from Chip Enable Low

____

15

____

17

____

20

____

20 ns

t

BDC

BUSY Disable Time from Chip Enable High

____

15

____

17

____

17

____

17 ns

t

APS

Arbitration Priority Set-up Time

(2)

5

____

5

____

5

____

5

____

ns

t

BDD

BUSY Disable to Valid Data

(3)

____

18

____

18

____

30

____

30 ns

t

WH

Write Hold Afte r BUSY

(5)

12

____

13

____

15

____

17

____

ns

BUSY INPUT TIMING (M/S = V

IH

)

t

WB

BUSY Inp ut to Wri te

(4)

0

____

0

____

0

____

0

____

ns

t

WH

Write Hold Afte r BUSY

(5)

12

____

13

____

15

____

17

____

ns

PORT -TO-PORT DE LAY TI MING

t

WDD

Write Pulse to Data Delay

(1)

____

30

____

30

____

45

____

50 ns

t

DDD

Write Data Valid to Read Data De lay

(1)

____

25

____

25

____

35

____

35 ns

2 740 tb l 14 a

7024X35

Com 'l &

Military

7024X55

Com'l, Ind

& Military

7024X70

Military Only

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

BUSY TIMING (M/S = V

IH

)

t

BAA

BUSY Access Time from Address Match

____

20

____

45

____

45 ns

t

BDA

BUSY Disable Time from Address Not Match

____

20

____

40

____

40 ns

t

BAC

BUSY A ccess Time from Chip Enable Low

____

20

____

40

____

40 ns

t

BDC

BUSY Disable Time from Chip Enable High

____

20

____

35

____

35 ns

t

APS

Arbitration Priority Set-up Time

(2)

5

____

5

____

5

____

ns

t

BDD

BUSY Disable to Valid Data

(3)

____

35

____

40

____

45 ns

t

WH

Write Hold Afte r BUSY

(5)

25

____

25

____

25

____

ns

BUSY INPUT TIMING (M/S = V

IH

)

t

WB

BUSY Inp ut to Write

(4)

0

____

0

____

0

____

ns

t

WH

Write Hold Afte r BUSY

(5)

25

____

25

____

25

____

ns

PORT -TO-PORT DE LAY TI MING

t

WDD

Write Pulse to Data Delay

(1)

____

60

____

80

____

95 ns

t

DDD

Write Data Valid to Read Data De lay

(1)

____

45

____

65

____

80 ns

2740 tbl 14b

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

14

2740 drw 13

t

DW

t

APS

ADDR

"A"

t

WC

DATA

OUT "B"

MATCH

t

WP

R/W

"A"

DATA

IN "A"

ADDR

"B"

t

DH

VALID

(1)

MATCH

BUSY

"B"

t

BDA

VALID

t

BDD

t

DDD

(3)

t

WDD

t

BAA

Timing Waveform of Write with Port-to-Port Read and BUSY(2,4,5) (M/S = VIH)

Timing Waveform of Write with BUSY

NOTES:

1. tWH must be met for both BUSY input (slave) and output (master).

2. BUSY is asserted on port "B" Blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB is only for the 'Slave' Version.

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).

2. CEL = CER = VIL.

3. OE = VIL for the reading port.

4. If M/S = VIL (slave) then BUSY is an input BUSY"A" = VIL and BUSY"B" = don't care, for this example.

5. All timing is the same for both left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

2740 drw 14

R/W

"A"

BUSY

"B"

t

WP

t

WB

R/W

"B"

t

WH

(1)

(2)

(3)

,

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

15

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(1)

Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing(1) (M/S = VIH)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

NOTES:

1. 'X' in part number indicates power rating (S or L).

2740 drw 15

ADDR

"A"

and

"B"

ADDRESSES MATCH

CE

"A"

CE

"B"

BUSY

"B"

t

APS

t

BAC

t

BDC

(2)

2740 drw 16

ADDR

"A"

ADDRESS "N"

ADDR

"B"

BUSY

"B"

t

APS

t

BAA

t

BDA

(2)

MATCHING ADDRESS "N"

7024X15

Com'l Only 7024X17

Com'l Only 7024X20

Com'l , Ind

& Military

7024X25

Co m 'l &

Military

Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit

INTERRUP T TI MI NG

t

AS

Address Set-up Time 0

____

0

____

0

____

0

____

ns

t

WR

Write Recovery Time 0

____

0

____

0

____

0

____

ns

t

INS

Inte rrup t S e t Tim e

____

15

____

15

____

20

____

20 ns

t

INR

Inte rrup t Re s e t Tim e

____

15

____

15

____

20

____

20 ns

2 740 tb l 15 a

7024X35

Co m 'l &

Military

7024X55

Com'l, Ind

& Military

7024X70

Military Only

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

INTERRUP T TI MI NG

t

AS

Address Set-up Time 0

____

0

____

0

____

ns

t

WR

Write Recovery Time 0

____

0

____

0

____

ns

t

INS

Inte rrup t S e t Tim e

____

25

____

40

____

50 ns

t

INR

Inte rrup t Re s e t Tim e

____

25

____

40

____

50 ns

2740 tbl 15b

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

16

Truth T able III — Interrupt Flag(1,4)

Wa v eform of Interrupt Timing(1)

NOTES:

1. Assumes BUSYL = BUSYR = VIH.

2. If BUSYL = VIL, then no change.

3. If BUSYR = VIL, then no change.

4. INTR and INTL must be initialized at power-up.

2740 drw 17

ADDR

"A"

INTERRUPT SET ADDRESS

CE

"A"

R/W

"A"

t

AS

t

WC

t

WR

(3) (4)

t

INS

(3)

INT

"B"

(2)

2740 drw 18

ADDR"B" INTERRUPT CLEAR ADDRESS

CE"B"

OE"B"

tAS

tRC

(3)

tINR(3)

INT"B"

(2)

Left P or t Ri ght Po rt

FunctionR/W

L

CE

L

OE

L

A

11L

-A

0L

INT

L

R/W

R

CE

R

OE

R

A

11R

-A

0R

INT

R

L LXFFFXXXX X L

(2)

S e t Ri g h t INT

R

Fl ag

XXX X XXL L FFF H

(3)

Re s et Ri g ht INT

R

Flag

XXX X L

(3)

LLXFFE XSet Left INT

L

Flag

XLLFFE H

(2)

X X X X X Reset Left INT

L

Flag

2740 tbl 16

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2 . See Interrupt Truth Table III.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

17

T ruth T able IV —

Address BUSY Arbritration

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7024 are

push pull, not open drain outputs. On slaves, the BUSY asserted input internally inhibits write.

2 . "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSYR outputs are driving LOW regardless of actual logic level on the pin.

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024.

2. There are eight semaphore flags written to via I/O0 and read from all the I/O's. These eight semaphores are addressed by A0-A2.

3. CE = VIH, SEM = VIL, to access the Semaphores. Refer to the Semaphore Read/Write Control Truth Table.

Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)

Functional Description

The IDT7024 provides two ports with separate control, address and

I/O pins that permit independent access for reads or writes to any location

in memory. The IDT7024 has an automatic power down feature controlled

by CE. The CE controls on-chip power down circuitry that permits the

respective port to go into a standby mode when not selected (CE = VIH).

When a port is enabled, access to the entire memory array is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail box

or message center) is assigned to each port. The left port interrupt flag

(INTL) is asserted when the right port writes to memory location FFE

(HEX), where a write is defined as the CE = R/W = VIL per the Truth Table

III. The left port clears the interrupt by access address location FFE access

when CER = OER = VIL, R/W is a "don't care". Likewise, the right port

interrupt flag (INTR) is asserted when the left port writes to memory location

FFF (HEX) and to clear the interrupt flag (INTR), the right port must access

the memory location FFF. The message (16 bits) at FFE or FFF is user-

defined, since it is an addressable SRAM location. If the interrupt function

Inputs Outputs

Function

CE

L

CE

R

A

0L

-A

11L

A

0R

-A

11R

BUSY

L

(1)

BUSY

R

(1)

X X NO MATCH H H No rmal

H X MATCH H H Normal

X H MATCH H H Normal

L L MATCH (2) (2) Write Inhib it

(3)

2 740 tbl 17

Functions D

0

- D

15

Left D

0

- D

15

Ri gh t S tatus

No Action 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Rig ht Po rt Write s "0" to S em aphore 0 1 No chang e . Rig ht sid e has no write acce ss to se map ho re

Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token

Left P ort Write s "0" to Se map ho re 1 0 No chang e . Le ft po rt has no write acc e ss to s emap hore

Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token

Left P ort Write s "1" to Se map ho re 1 1 Se map hore fre e

Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token

Right Port Writes "1" to Semaphore 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Left P ort Write s "1" to Se map ho re 1 1 Se map hore fre e

2740 t bl 18

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

18

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT7024 RAMs.

is not used, address locations FFE and FFF are not used as mail boxes,

but as part of the random access memory. Refer to Truth Table III for the

interrupt operation.

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM

have accessed the same location at the same time. It also allows one of the

two accesses to proceed and signals the other side that the RAM is “busy”.

The BUSY pin can then be used to stall the access until the operation on

the other side is completed. If a write operation has been attempted from

the side that receives a BUSY indication, the write signal is gated internally

to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applications.

In some cases it may be useful to logically OR the BUSY outputs together

and use any BUSY indication as an interrupt source to flag the event of

an illegal or illogical operation. If the write inhibit function of BUSY logic is

not desirable, the BUSY logic can be disabled by placing the part in slave

mode with the M/S pin. Once in slave mode the BUSY pin operates solely

as a write inhibit input pin. Normal operation can be programmed by tying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT 7024 SRAM in master mode, are push-

pull type outputs and do not require pull up resistors to operate. If these

RAMs are being expanded in depth, then the BUSY indication for the

resulting array requires the use of an external AND gate.

Width Expansion with BUSY Logic

Master/Slave Arrays

When expanding an IDT7024 RAM array in width while using BUSY

logic, one master part is used to decide which side of the RAM array will

receive a BUSY indication, and to output that indication. Any number of

slaves to be addressed in the same address range as the master, use

the BUSY signal as a write inhibit signal. Thus on the IDT7024 RAM the

BUSY pin is an output if the part is used as a master (M/S pin = VIH), and

the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown

in Figure 3.

If two or more master parts were used when expanding in width, a split

decision could result with one master indicating BUSY on one side of the

array and another master indicating BUSY on one other side of the array.

This would inhibit the write operations from one port for part of a word and

inhibit the write operations from the other port for the other part of the word.

The BUSY arbitration, on a master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In

a master/slave array, both address and chip enable must be valid long

enough for a BUSY flag to be output from the master before the actual write

pulse can be initiated with either the R/W signal or the byte enables. Failure

to observe this timing can result in a glitched internal write inhibit signal and

corrupted data in the slave.

Semaphores

The IDT7024 is an extremely fast Dual-Port 4K x 16 CMOS Static RAM

with an additional 8 address locations dedicated to binary semaphore flags.

These flags allow either processor on the left or right side of the Dual-Port

RAM to claim a privilege over the other processor for functions defined by

the system designer’s software. As an example, the semaphore can be

used by one processor to inhibit the other from accessing a portion of the

Dual-Port RAM or any other shared resource.

The Dual-Port RAM features a fast access time, and both ports are

completely independent of each other. This means that the activity on the

left port in no way slows the access time of the right port. Both ports are

identical in function to standard CMOS Static RAM and can be read from,

or written to, at the same time with the only possible conflict arising from the

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphore location. Semaphores are protected against such ambiguous

situations and may be used by the system program to avoid any conflicts

in the non-semaphore portion of the Dual-Port RAM. These devices have

an automatic power-down feature controlled by CE, the Dual-Port RAM

enable, and SEM, the semaphore enable. The CE and SEM pins control

on-chip power down circuitry that permits the respective port to go into

standby mode when not selected. This is the condition which is shown in

Truth Table I where CE and SEM = VIH.

Systems which can best use the IDT7024 contain multiple processors

or controllers and are typically very high-speed systems which are

software controlled or software intensive. These systems can benefit from

a performance increase offered by the IDT7024's hardware semaphores,

which provide a lockout mechanism without requiring complex program-

ming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in varying

configurations. The IDT7024 does not use its semaphore flags to control

any resources through hardware, thus allowing the system designer total

flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred

in either processor. This can prove to be a major advantage in very

high-speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are independent

of the Dual-Port RAM. These latches can be used to pass a flag, or token,

from one port to the other to indicate that a shared resource is in use. The

semaphores provide a hardware assist for a use assignment method

called “Token Passing Allocation.” In this method, the state of a semaphore

latch is used as a token indicating that shared resource is in use. If the left

processor wants to use this resource, it requests the token by setting the

latch. This processor then verifies its success in setting the latch by reading

2740 drw 19

MASTER

Dual Port

RAM

BUSY (L) BUSY (R)

CE

MASTER

Dual Port

RAM

BUSY (L) BUSY (R)

CE

SLAVE

Dual Port

RAM

BUSY (L) BUSY (R)

CE

SLAVE

Dual Port

RAM

BUSY (L) BUSY (R)

CE

BUSY (L) BUSY (R)

DECODER

,

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

19

it. If it was successful, it proceeds to assume control over the shared

resource. If it was not successful in setting the latch, it determines that the

right side processor has set the latch first, has the token and is using the

shared resource. The left processor can then either repeatedly request

that semaphore’s status or remove its request for that semaphore to perform

another task and occasionally attempt again to gain control of the token via

the set and test sequence. Once the right side has relinquished the token,

the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by writing

a zero into a semaphore latch and is released when the same side writes

a one to that latch.

The eight semaphore flags reside within the IDT7024 in a separate

memory space from the Dual-Port RAM. This address space is accessed

by placing a LOW input on the SEM pin (which acts as a chip select for the

semaphore flags) and using the other control pins (Address, OE, and

R/W) as they would be used in accessing a standard Static RAM. Each

of the flags has a unique address which can be accessed by either side

through address pins A0 – A2. When accessing the semaphores, none of

the other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If a low level

is written into an unused semaphore location, that flag will be set to a zero

on that side and a one on the other side (see Truth Table III). That

semaphore can now only be modified by the side showing the zero. When

a one is written into the same location from the same side, the flag will be

set to a one for both sides (unless a semaphore request from the other side

is pending) and then can be written to by both sides. The fact that the side

which is able to write a zero into a semaphore subsequently locks out writes

from the other side is what makes semaphore flags useful in interprocessor

communications. (A thorough discussion on the use of this feature follows

shortly.) A zero written into the same location from the other side will be

stored in the semaphore request latch for that side until the semaphore is

freed by the first side.

When a semaphore flag is read, its value is spread into all data bits so

that a flag that is a one reads as a one in all data bits and a flag containing

a zero reads as all zeros. The read value is latched into one side’s output

register when that side's semaphore select (SEM) and output enable (OE)

signals go active. This serves to disallow the semaphore from changing

state in the middle of a read cycle due to a write cycle from the other side.

Because of this latch, a repeated read of a semaphore in a test loop must

cause either signal (SEM or OE) to go inactive or the output will never

change.

A sequence WRITE/READ must be used by the semaphore in order

to guarantee that no system level contention will occur. A processor

requests access to shared resources by attempting to write a zero into a

semaphore location. If the semaphore is already in use, the semaphore

request latch will contain a zero, yet the semaphore flag will appear as one,

a fact which the processor will verify by the subsequent read (see Truth

Table III). As an example, assume a processor writes a zero to the left port

at a free semaphore location. On a subsequent read, the processor will

verify that it has written successfully to that location and will assume control

over the resource in question. Meanwhile, if a processor on the right side

attempts to write a zero to the same semaphore flag it will fail, as will be

verified by the fact that a one will be read from that semaphore on the right

side during subsequent read. Had a sequence of READ/WRITE been

used instead, system contention problems could have occurred during the

gap between the read and write cycles.

It is important to note that a failed semaphore request must be followed

by either repeated reads or by writing a one into the same location. The

reason for this is easily understood by looking at the simple logic diagram

of the semaphore flag in Figure 4. Two semaphore request latches feed

into a semaphore flag. Whichever latch is first to present a zero to the

semaphore flag will force its side of the semaphore flag LOW and the other

side HIGH. This condition will continue until a one is written to the same

semaphore request latch. Should the other side’s semaphore request latch

have been written to a zero in the meantime, the semaphore flag will flip

over to the other side as soon as a one is written into the first side’s request

latch. The second side’s flag will now stay LOW until its semaphore request

latch is written to a one. From this it is easy to understand that, if a semaphore

is requested and the processor which requested it no longer needs the

resource, the entire system can hang up until a one is written into that

semaphore request latch.

The critical case of semaphore timing is when both sides request

a single token by attempting to write a zero into it at the same time.

The semaphore logic is specially designed to resolve this problem.

If simultaneous requests are made, the logic guarantees that only one

side receives the token. If one side is earlier than the other in making the

request, the first side to make the request will receive the token. If both

requests arrive at the same time, the assignment will be arbitrarily made

to one port or the other.

One caution that should be noted when using semaphores is that

semaphores alone do not guarantee that access to a resource is secure.

As with any powerful programming technique, if semaphores are misused

or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be handled

via the initialization program at power-up. Since any semaphore request

flag which contains a zero must be reset to a one, all semaphores on both

sides should have a one written into them at initialization from both sides

to assure that they will be free when needed.

Using Semaphores—Some Examples

Perhaps the simplest application of semaphores is their application as

resource markers for the IDT7024’s Dual-Port RAM. Say the 4K x 16 RAM

was to be divided into two 2K x 16 blocks which were to be dedicated at

any one time to servicing either the left or right port. Semaphore 0 could

be used to indicate the side which would control the lower section of

memory, and Semaphore 1 could be defined as the indicator for the upper

section of memory.

To take a resource, in this example the lower 2K of Dual-Port RAM,

the processor on the left port could write and then read a zero in to

Semaphore 0. If this task were successfully completed (a zero was read

back rather than a one), the left processor would assume control of the

lower 2K. Meanwhile the right processor was attempting to gain control of

the resource after the left processor, it would read back a one in response

to the zero it had attempted to write into Semaphore 0. At this point, the

software could choose to try and gain control of the second 2K section by

writing, then reading a zero into Semaphore 1. If it succeeded in gaining

control, it would lock out the left side.

Once the left side was finished with its task, it would write a one to

Semaphore 0 and may then try to gain access to Semaphore 1. If

Semaphore 1 was still occupied by the right side, the left side could undo

its semaphore request and perform other tasks until it was able to write, then

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

20

read a zero into Semaphore 1. If the right processor performs a similar task

with Semaphore 0, this protocol would allow the two processors to swap

2K blocks of Dual-Port RAM with each other.

The blocks do not have to be any particular size and can even be

variable, depending upon the complexity of the software using the

semaphore flags. All eight semaphores could be used to divide the Dual-

Port RAM or other shared resources into eight parts. Semaphores can

even be assigned different meanings on different sides rather than being

given a common meaning as was shown in the example above.

Semaphores are a useful form of arbitration in systems like disk

interfaces where the CPU must be locked out of a section of memory during

a transfer and the I/O device cannot tolerate any wait states. With the use

of semaphores, once the two devices has determined which memory area

was “off-limits” to the CPU, both the CPU and the I/O devices could access

their assigned portions of memory continuously without any wait states.

D

2740 drw 20

0DQ

WRITE D

0

D

Q

WRITE

SEMAPHORE

REQUEST FLIP FLOP SEMAPHORE

REQUEST FLIP FLOP

L

P

O

R

T

RPORT

SEMAPHORE

READ SEMAPHORE

READ

,

Figure 4. IDT7024 Semaphore Logic

Semaphores are also useful in applications where no memory “WAIT”

state is available on one or both sides. Once a semaphore handshake has

been performed, both processors can access their assigned RAM

segments at full speed.

Another application is in the area of complex data structures. In this

case, block arbitration is very important. For this application one processor

may be responsible for building and updating a data structure. The other

processor then reads and interprets that data structure. If the interpreting

processor reads an incomplete data structure, a major error condition may

exist. Therefore, some sort of arbitration must be used between the two

different processors. The building processor arbitrates for the block, locks

it and then is able to go in and update the data structure. When the update

is completed, the data structure block is released. This allows the

interpreting processor to come back and read the complete data structure,

thereby guaranteeing a consistent data structure.

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

21

Ordering Information

NOTE:

1. Industrial temperature range is available on selected PLCC packages in standard power. For other speeds, packages and powers contact your sales office.

2. Green parts available. For specific speeds, packages and powers contact your local sales office.

2740 drw 21

A

Power

999

Speed

A

Package

A

Process/

Temperature

Range

Blank

I

(1)

B

Commercial (0°Cto+70°C)

Industrial (-40°Cto+85°C)

Military (-55°C to +125°C)

Compliant to MIL-PRF-38535 QML

PF

G

J

F

100-pin TQFP (PN100-1)

84-pin PGA (G84-3)

84-pin PLCC (J84-1)

84-pin Flatpack (F84-2)

15

17

20

25

35

55

70

Commercial Only

Commercial, Industrial & Military

Commercial & Military

Commercial, Industrial & Military

Military Only

S

LStandard Power

Low Power

XXXXX

Device

Type

64K (4K x 16) Dual-Port RAM7024

Speed in

nanoseconds

A

G

(2)

Green

Datasheet Document History

1/13/99: Initiated datasheet document history

Converted to new format

Cosmetic and typographical corrections

Pages 2 and 3 Added additional notes to pin configurations

6/4/99: Changed drawing format

Page 1 Corrected DSC number

4/4/00: Replaced IDT logo

Page 6 Corrected typo in Data Retention chart

Changed ±500mV to 0mV in notes

5/19/00: Page 3 Clarified TA parameter

Page 4 Increased storage temperature parameter

Pages 5 and 6 DC Electrical parameters–changed wording from "open" to "disabled"

Datasheet Document History continued on page 22

6.42

IDT7024S/L

High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

22

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-824-2775 DualPortHelp@idt.com

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Datasheet Document History (continued)

9/12/01: Page 2 & 3 Added date revision for pin configurations

Page 5 Added Industrial temp to the column heading for 20ns to DC Electrical Characteristics

Pages 8,10,13&15 Added Industrial temp to the column headings for 20ns to AC Electrical Characteristics

Pages 3,5,6,8,10,13&15 Removed Industrial temp note from all tables footnotes

Page 21 Added Industrial to 20ns ordering information

07/25/05: Page 1 Added green availability to features

Page 21 Added green indicator to ordering information

Page 1 & 21 Replaced old IDT ® logo with the new IDTTM logo

Page 21 Updated address and phone contact information

10/29/08: Page 21 Removed "IDT" from orderable part number