PWM+PFC Combi IC
TDA 16888 / TDA 16888G
High Performance Power
Combi Controller
Never stop thinking.
Power Conversion
Datasheet, V2.0, 28 Feb 2000
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TDA 16888/ TDA 16888G
Revision History:2000-02-28 Datasheet
Previous Version:
Page Subjects (major changes since last revision)
Edition 2000-02-28
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be endangered.
P-DIP-20-5
P-DSO-20-1 /-6 /-7
High Performance Power Combi Controller TDA 16888
Version 2.0 3 28 Feb 2000
1 Overview
1.1 Features
PFC Section
– IEC 1000-3 compliant
– Additional operation mode as auxiliary power supply
– Fast, soft switching totem pole gate drive (1 A)
– Dual loop control (average current and voltage
sensing)
– Leading edge triggered pulse width modulation
– Peak current limitation
– Topologies of PFC preconverter are boost or flyback
– Continuous/discontinuous mode possible
– 94% maximum d uty cy cle
PWM Section
– Improved current mode control
– Fast, soft switching totem pole gate drive (1 A)
– Soft-start management
– Trailing edge triggered pulse width modulation
– Topologies of PWM converter are feed forward or flyback
– 50% maximum duty cycle to prevent transformer saturation
–fPWM =fPFC
▼ New type
Type Ordering Code Package
▼TDA 16888 Q67000-A9284-X201-K5 P-DIP-20-5
▼TDA 16888 G Q67000-A9310-A702 P-DSO-20-1
TDA 16888
Version 2.0 4 28 Feb 2000
Special Features
– High power factor
– Typical 50 µA start-up supply current
– Low quiescent current (15 mA)
– Undervoltage lockout with internal stand-by operation
– Internally synchronized fixed operating frequency ranging from 15 kHz to 200 kHz
– External synchronization possible
– Shutd own of bot h outputs externally triggera ble
– Peak current limitation
– Overvoltage protection
– Average current sensing by noise filtering
1.2 General Remarks
The TDA 16888 comprises the complete control for power factor controlled switched
mode powe r supplies. With its PFC and PWM section being internally synchronized, it
applies for off-line converters with input voltages ranging from 90 V to 270 V.
While the p referred topolo gies of the PFC p reconverter are boost or f lyback, the PWM
section can be designed as forward or flyback converter. In order to achieve minimal line
current gaps the maximum duty cycle of the PFC is about 94%. The maximum duty cycle
of the PWM, however, is limited to 50% to prevent transformer saturation.
TDA 16888
Version 2.0 5 28 Feb 2000
Figure 1 Pin Configuration (top view)
PFC CL
GND
PFC OUT
SYNC
PWM SS
PWM IN
V
ROSC
PFC VC
PFC VS
AUX VS
REF
PWM RMP
201
192
183
174
165
156
147
138
129
AEP02461
PFC CC
PFC CS
PWM OUT PWM CS
PFC IAC
1110
GND S
CC
V
PFC FB
AEP02486
11
12
13
14
15
16
17
18
19
20
10
9
8
7
6
5
4
3
2
1
V
CC
GND S
PFC IAC
PWM OUT
PFC CS
PFC CC
REF
V
PFC OUT
GND
PFC CL
PFC FB
PWM CS
PWM RMP
AUX VS
PFC VS
PFC VC
ROSC
PWM IN
PWM SS
SYNC
P-DSO-20-1P-DIP-20-5
TDA 16888
Version 2.0 6 28 Feb 2000
1.3 Pin Definitions and Functions
Pin No. Symbol Function
1 PFC IAC AC line voltage sensing input
2VREF 7.5 V reference
3 PFC CC PFC current loop compensation
4 PFC CS PFC current sense
5 GND S Ground sensing input
6 PFC CL Sensing input for PFC current limitation
7 GND Ground
8 PFC OUT PFC driver ou tput
9VCC Supply voltage
10 PWM OUT PWM driver output
11 PWM CS PWM current sense
12 SYNC Oscillator synchronization input
13 PWM SS PWM soft-start
14 PWM IN PWM output voltage sensing input
15 PWM RMP PWM voltage ramp
16 ROSC Oscillator frequency set-up
17 PFC FB PFC voltage loop feedback
18 PFC VC PFC voltage loop compensation
19 PFC VS PFC output voltage sensing input
20 AUX VS Auxiliary power supply voltage sense
TDA 16888
Version 2.0 7 28 Feb 2000
1.4 Block Diagram
Figure 2
AEB02357
5 V
_
+
1.2 V
D1 D2
5 V
D3 D4
&
5.5 V 1 V
4 V
&
6 V
5.5 V
&&
0.4 V
C10
10 k
1.5 V
Osc
0.45 V
1
6 V
7.4 V
Undervoltage Lockout
11 V-14 V
Power Management
7.5 V (Output Disable)
Voltage Reference
Z3
17.5 V
PWM
Bias
Control
OTA3
OTA1
R
S
R
S
17
PFC
18 4 VS
20
AUX S5
GND CC
3
PFC VS
19
PFC CL
6
PFC
9OUT
PFC
V
2SYNC
12 ROSC
16 PWM
13
SS IN
PWM
14
RMP
PWM
15
CS
PWM
11 GND
7
OUT
PWM
FB VC
PFC PFC
CSIAC
PFC
1 8
10
REF
CC
V
R
2
10 k
Ω
OP1
1
M
M
2
3
M
Q
M
OP2 C1
OTA2
C4
C2
C6
C3
1 V
FF1
Z1
V
S
V
S
S
V
_
<
30
µ
A
C5
0.4 V
1
C9
OP3
5
Ω
R
1
V
1
R
3
100 k
Ω
V
S
Z2
FF2
C7
C8
Ι
1
1 V
_
+
_
+
_
+
_
+
_
+
_
+
+
_
_
+
+
_
_
+
_
+
_
+
_
+
+
_
TDA 16888
Version 2.0 8 28 Feb 2000
2 Functional Description
Power Supply
The TDA 16888 is protecte d against overvolt ages typica lly above 17.5 V by an internal
Zener diode Z3 at pin 9 (VCC) and against electrostatic discharging at any pin by special
ESD circuitry.
By means of its power management the TDA 16888 will switch from internal stand-by,
which is characterized by negligible current consumption, to operation mode as soon as
a supply voltage threshold of 14 V at pin 9 (VCC) is exceeded. To avoid uncontrolled
ringing at switch-over an undervoltage lockout is implemented, which will cause the
power man agement to switch from operation m ode to in ternal stand -by as so on as the
supply voltage falls below a threshold of 11 V. Therefore, even if the supply voltage will
fall below 14 V, operation mode will be maintained as long as the supply voltage is well
above 11 V.
As soon a s the supply vo ltage has stabil ized, wh ich is d etermined by the TDA 1 6888’s
power management and its soft-start feature at pin 13 (PWM SS), the PWM section will
be enabled by means of its internal bias control.
Protection Circuitry
Both PFC and PWM section are equipped with a fast overvoltage protection (C6)
sensing at pin 19 (PFC VS), which when being activated will immediately shut down both
gate drives. In addition to improve the PFC section’s load regulation it uses a fast but soft
overvoltage protection (OTA2) prior to the one described above, which when being
activated will cause a well controlled throttling of the multiplier output QM.
In case an undervoltage of the PFC output voltage is detected at pin 19 (PFC VS) by
comparator C4 the gate drive of the PWM section will be shut do wn in order to reduce
the load current and to increase the PFC output voltage. This undervoltage shutdown
has to be prior to the undervoltage lockout of the internal power management and
therefore has to be bound to a threshold voltage at pin 9 (VCC) well above 11 V.
In order to prevent the external circuitry from destruction the PFC output PFC OUT
(pin 8) will immediately be switched off by comparator C2, if the voltage at pin 19
(PFC VS) drops to ground caused by a broken wire. In a similar way measures are taken
to handle a broken wire at any other pin in order to ensure a safe operation of the IC and
its adjoining circuitry.
If necessa ry both outputs, PFC OUT (p in 8) and PWM OUT (pin 10), can be shutdown
on external requ est. This is acc omplished by shorting the ex ternal reference voltage at
pin 2 (VREF) to ground. To protect th e external reference, it is equipp ed with a foldback
charact eristic, wh ich will cut d own the output c urrent when VREF (pin 2) is sh orted (see
Figure 4).
TDA 16888
Version 2.0 9 28 Feb 2000
Both PFC and PWM section are equipped with a peak current limitation, which is realized
by the comparators C3 and C9 sensing at pin 6 (PFC CL) and pin 11 (PWM CS)
respectively. When being activated this current limitation will immediately shut down the
respective gate drive PFC OUT (pin 8) or PWM OUT (pin 10).
Finally each pin is protected against electrostatic discharge.
Oscillator/Synchronization
The PFC and PWM clock signals as well as the PFC voltage ramp are synchronized by
the internal oscillator (see Figure 18). The oscillator’s frequency is set by an external
resistor connected to pin 16 (ROSC) and ground (see Figure 5). The corresponding
capacitor, however, is integrated to guarantee a low current consumption and a high
resistance against electromagnetic interferences. In order to ensure superior precision
of the clock frequency, the clock signal CLK OSC is derived from a triangular instead of
a saw-tooth signal. Furthermore to provide a clock reference CLK OUT with exactly 50%
duty cycle, the frequency of the oscillator’s clock signal CLK OSC is halved by a D-latch
before being fed into the PFC and PWM section respectively (see Figure 18).
The ramp signal of the PFC section VPFC RMP is composed of a slowly falling and a
steeply rising edge. This ramp has been reversed in contrast to the common practice, in
order to simultaneously allow for current measurement at pin 5 (GND S) and for external
compensation of OP2 by means of pin 5 (GND S) and pin 3 (PFC CC).
The oscillator can be synchronized with an external clock signal supplied at pin 12
(SYNC). However, since the oscillator’s frequency is halved before being fed into the
PFC and PWM section, a synchronization frequency being twice the operating frequency
is recommended. As long as the synchronization signal is H the oscillator’s triangular
signal VOSC is interrupted and its clock signal CLK OSC is H (see Figure 19 and
Figure 20). However, as soon as the external clock changes from H to L the oscillator is
released. Correspondingly, by means of an external clock signal supplied at pin 12
(SYNC) the oscillator frequency fOSC set by an external resistor at pin 16 (ROSC) can be
varied on prin ciple only wi thin the rang e from 0.66 fOSC to 2 fOSC. If the o scilla tor has to
be synchroni zed over a wider freq uency ran ge, a synch roni zation by mean s of the sink
current at pin 16 (ROSC) has to be preferred to a synchronization by means of pin 12
(SYNC). Anyhow, please note, that pin 12 (SYNC) is not meant to permanently
shutdown both PFC and PWM sec tion. It can be us ed to halt the oscil lator freezi ng the
prevailing state of both drivers but does not allow to automatically shut them down. A
shutdown can be achieved by shorting pin 2 (VREF) to ground, instead.
Finally, In order to reduce the overall current consumption under low load conditions, the
oscillator frequency itself is halved as long as the voltage at pin 13 (PWM SS) is less
than 0.4 V (disabled PWM section).
TDA 16888
Version 2.0 10 28 Feb 2000
PFC Section
At normal operation the PFC section operates with dual loop control. An inner loop,
which includes OP2, C1, FF1 and the PFC’s driver, controls the shape of the line current
by average current control enabling either continuous or discontinuous operation. By the
outer loop, which is supported by OP1, the multiplier, OP2, C1, FF1 and the PFC's driver,
the PFC output voltage is controlled. Furthermore there is a third control loop composed
of OTA1, OP2, C1, FF1 and the PFC’s driver, which allows the PFC section to be
operated as an auxiliary power supply even when the PWM section is disabled. With
disabled PWM section, however, the PFC section is operated with half of its nominal
operating frequency in order to reduce the overall current consumption.
Based on a pulse-width-mo dula tion, which i s l ead ing edge trigge re d with respect to the
internal clock reference CLK OUT and which is trailing edge modulated according to the
PFC ramp signal VPFC RMP and the output voltage of OP2 VPFC CC (see Figure 18), the
PFC section is designed for a maxi mum duty cycle of ca. 94% to achieve mini mal line
current gaps.
PWM Section
The PWM section is equipped with improved curren t mode cont rol containing effective
slope compensation as well as enhanced spike suppression in contrast to the commonly
used leading edge current blanking. This is achieved by the chain of operational amplifier
OP3, voltage source V1 and the 1st order low pass filter composed of R1 and an external
capacitor, which is connected to pin 15 (PWM RMP). For crosstalk suppression between
PFC and PWM section a signal-to-noise ratio comparable to voltage mode controlled
PWM’s is set by operational amplifier OP3 performing a fivefold amplification of the PWM
load current, which is sensed by an external shunt resistor. In order to simultaneously
perform effective slope compensation and to suppress leading spikes, which are due to
parasiti c capacitan ces being dis charged when ever the power tran sistor is swi tched on,
the resulting signal is subsequent ly increased by the constant voltage of V1 and finally
fed into the 1st order low pass filter. The peak ramp voltage, that in this way can be
reached, amounts to ca. 6.5 V. By combination of voltage source V1 and the following
low pass f ilter a basic ramp (step response ) with a leading notch is created, whic h will
fully compensate a leading spike (see Figure 12) provided, the external capacitor at
pin 15 (PWM RMP) and the external current sensing shunt resistor are scaled properly.
TDA 16888
Version 2.0 11 28 Feb 2000
The pulse-width-modulation of the PWM section is trailing edge modulated according to
the PWM ramp signal VPWM RMP at pin 15 (PWM RMP ) and the input volt age VPWM IN at
pin 14 (PWM IN) (see Figure 18). In contrast to the PFC section, however, the pulse-
width-modulation of the PWM section is trailing edge triggered with respect to the
internal clock reference CLK OUT in order to avoid undesirable electromagnetic
interference o f both sections. M oreover the maximu m duty cycle of th e PWM is limited
to 50% to prevent transformer saturation.
By means of the above mentioned improved current mode control a stable pulse-width-
modulation from maximum loa d dow n to no load is achi eve d. Fin ally , in ca se of no load
conditions the PWM section may as well be disabled by shorting pin 13 (PWM SS) to
ground.
TDA 16888
Version 2.0 12 28 Feb 2000
3 Functional Block Description
Gate Drive
Both PFC and PWM section use fast totem pole gate drives at pin 8 (PFC OUT) and
pin 10 (PWM OUT) respectively, which are designed to avoid cross conduction currents
and which are equipped with Zener diodes (Z1, Z2) in order to improve the control of the
attached power transistors as well as to protect them against undesirable gate
overvoltages. At voltages below the undervoltage lockout threshold these gate drives are
active low. In order to keep the switching losses of the involved power diodes low and to
minimize electromagnetic emissions, both gate drives are optimized for soft switching
operation. This is achieved by a novel slope control of the rising edge at each driver’s
output (see Figure 13).
Oscillator
The TDA 16888’s clock signals as well as the PFC voltage ramp are provided by the
internal os cillator. The oscill ator’s freque ncy is se t by an ex ternal resist or connecte d to
pin 16 (ROSC) and ground (see Figure 5). The corresponding capacitor, however, is
integrated to guarantee a low current consumption and a high resistance against
electromagnetic interferences. In order to ensure superior precision of the clock
frequency, the clock signal CLK OSC is derived from the minima and maxima of a
triangular instead of a saw-tooth signal (see Figure 18). Furthermore, to provide a clock
reference CLK OUT wi th exactly 50% duty cycle, the frequ ency of the osc illator’s clo ck
signal CLK OSC is halved by a D-latch before being fed into the PFC and PWM section
respectively.
The ramp signal of the PFC section VPFC RMP is composed of a slowly falling and a
steeply rising edge, the latter of which is triggered by the rising edge of the clock
reference C LK O UT. This ramp h as been reverse d in co ntrast to the co mmon p racti ce,
in order to simultaneously allow for current measurement at pin 5 (GND S) and for
external compensation of OP2 by means of pin 5 (GND S) and pin 3 (PFC CC). The
slope of the falling edge, which in conjunction with the output of OP2 controls the pulse-
width-modulation of the PFC output signal VPFC OUT, is derived from the current set by the
external resistor at p in 16 (RO SC). In this way a con stant ampli tude of the ramp signal
(ca. 4.5 V) is ensured. In contrast, the slope of the rising edge, which marks the minimum
blanking interval and therefore limits the maximum duty cycle ton,max of the PFC output
signal, is determined by an internal current source.
In contrast to the PFC section the ramp signal of the PWM section is trailing edge
triggered with respect to the internal clock reference CLK OUT to avoid undesirable
electromagnetic interference of both sections. Moreover, the maximum duty cycle of the
PWM is limited by the rising edge of the clock reference CLK OUT to 50% to prevent
transformer saturation.
TDA 16888
Version 2.0 13 28 Feb 2000
The oscillator can be synchronized with an external clock signal supplied at pin 12
(SYNC). As long as this clock signal is H the oscillator’s triangular signal VOSC is
interrupted and its clock signal CLK OSC is H (see Figure 19 and Figure 20). However,
as soon as the external clock changes from H to L the oscillator is released.
Correspondingly, by means of an external clock signal supplied at pin 12 (SYNC) the
oscillator freq uency fOSC set by a n external res istor a t pin 1 6 (ROSC) can be varied on
principle only within the range from 0.66 fOSC to 2 fOSC. Please note, that the slope of the
falling edge of the PFC ramp is not influenced by the synchronization frequency. Instead
the lower voltage peak is modulated. Consequently, on the one hand at high
synchronization frequencies fSYNC >fOSC the amplitude of the ramp signal and
correspondingly its signal-to-noise ratio is decreased (see Figure 19). On the other hand
at low synchronization frequencies fSYNC <fOSC the lower voltage peak is clamped to the
minimum ramp voltage (typ. 1.1 V), that at least can be achieved (see Figure 20), which
may cause undefined PFC du ty cycles a s the voltage VPFC CC at pin 3 (PFC CC) drops
below this threshold. However, if the oscillator has to be synchronized over a wide
frequency ran ge, a sync hronizat ion by mean s of the sin k current a t pi n 16 (ROS C) has
to be preferred to a synchronization by means of pin 12 (SYNC).
In order to reduce the overall current consumption under low load conditions, the
oscillator frequency itself is halved as long as the voltage at pin 13 (PWM SS) is less
than 0.4 V (disabled PWM section).
Multiplier
The multipl ier serves t o provide t he cont rolled current IQM by combination of the shape
of the sinusoidal input current IM1 derived from the voltage at pin 1 (PFC IAC) by means
of the 10 kΩ resistor R2, the magnitude of the PFC output voltage VM2 given at pin 18
(PFC VC) and the possibility for soft overvoltage protection VM3 (see Chapter
Protection Circuitry). By means of this current the required power factor as well as the
magnitude o f the PFC ou tput voltag e is ensured . To achiev e an exce llent performa nce
over a wide ra nge of out put power and inpu t voltage, the input voltag e VM2 is ampli fied
by an exponential function before being fed into the multiplier (see Figure 8).
Voltage Amplifier OP1
Being part of the outer l oop the error ampli fier OP1 controls the magnitude o f the PFC
output volt age by comparis on of the PFC ou tput voltage me asured at pi n 17 (PFC F B)
with an internal reference voltage. The latter is fixed to 5 V in order to achieve immunity
from external no ise. To allow fo r individual fe edback the ou tput of OP1 is con nected to
pin 18 (PFC VC).
TDA 16888
Version 2.0 14 28 Feb 2000
Current Amplifier OP2
Being part of the inner loop the error amplifier OP2 controls the shape of the line current
by comparison of the controlled current IQM with the measured average line current. This
is achieved by setting the pulse width of the PFC gate drive in conjunction with the
comparator C1. In order to limit the voltage range supplied at pin 4 (PFC CS) and at pin 5
(GND S), clamping diodes D1, D2 and D3 are connected with these pins and ground. To
allow for individual feedback the output of OP2 is connected to pin 3 (PFC CC).
Ramp Amplifier OP3
For crosstalk suppression between PFC and PWM section a signal-to-noise ratio
comparable to voltage mode controlled PWMs is set by operational amplifier OP3
performing a fivefold amplification of the PWM load current, which is sensed by an
external shunt resistor. In order to suppress leading spikes, which are due to parasitic
capacitances being discharged whenever the power transistor is switched on, the
resulting signal is subsequently increased by the constant volta ge of V1 and finally fed
into a 1st order low pass filter. By combination of voltage source V1 and the following low
pass filter a step response with a leading notch is created, which will fully compensate a
leading spike (see Figure 12) provided, the external capacitor at pin 15 (PWM RMP)
and the external current sensing shunt resistor are scaled properly.
Operational Transconductance Amplifier OTA1
The TDA 16888’s auxiliary power supply mode is controlled by the fast operational
transconductance amplifier OTA1. When under low load or no load conditions a voltage
below 5 V is sensed at pin 20 (AUX VS), it will start to superimpose its output on the
output QM of the multiplier and in this way will replace the error amplifier OP1 and the
multiplier. At normal operation, however, when the voltage at pin 20 (AUX VS) is well
above 5 V, this operational transconductance amplifier is disabled.
Operational Transconductance Amplifier OTA2
By means of the operational transconductance amplifier OTA2 sensing at pin 19
(PFC VS) a fast but soft overvoltage protection of the PFC output voltage is achieved,
which when being activated (VPFC VS > 5.5 V) will cause a well controlled throttling of the
multiplier output QM (see Figure 9).
Operational Transconductance Amplifier OTA3
In order to achieve offset compensation of error amplifier OP2 under low load conditions,
that will not suffice to start OTA1, the operational transconductance amplifier OTA3 is
introduced. It will start operation as soon as these conditions are reached, i.e. the voltage
at pin 18 (PFC VC) falls below 1.2 V .
TDA 16888
Version 2.0 15 28 Feb 2000
Comparator C1
The comparator C1 serves to adjust the duty cycle of the PFC gate drive. This is
achieved by comp arison of the output voltage of O P2 give n at pin 3 (PFC CC ) and the
voltage ramp of the oscillator.
Comparator C2
The comparator C2 serves to prevent the external circuitry from destruction by
immediately switching the PFC output PFC OUT (pin 8) off, if the voltage at pin 19
(PFC VS) drops below 1 V due to a broken wire.
Comparator C3
By means of this extremely fast comparator sensing at pin 6 (PFC CL) peak current
limitation is realized. When being activated (VPFC CL < 1 V) it will immediately shut down
the gate drive of the PFC section (pin 8, PFC OUT). In order to protect C3 against
undervoltag es at pin 6 (PFC CL) due t o large inrush c urrents, this pi n is equippe d with
an additional clamping diode D4.
Comparator C4
This comparator along with the TDA 16888’s power management serves to reset the
PWM section’s soft start at pin 13 (PWM SS). C4 becomes active as soon as an
undervoltage (VPFC VS < 4 V) of the PFC output voltage is sensed at pin 19 (PFC VS).
Comparator C5
Based on the status of the PWM section’s soft start at pin 13 (PWM SS), the comparator
C5 controls the bias of the entire PWM section. In this way the PWM section is switched
off giving a very low quiescent current, until its soft start is released.
Comparator C6
Overvoltage protection of the PWM section’s input voltage sensed at pin 19 (PFC VS) is
realized by comparator C6, which when being activated will immediately shut down both
gate drives PFC OUT (pin 8) and PWM OUT (pin 10).
Comparator C7
This comparator sensing at pin 13 (PWM SS) and at pin 15 (PWM RMP) controls the
pulse width modulation of the PWM section during the soft start. This is done right after
the PWM section is biased by comparator C5.
TDA 16888
Version 2.0 16 28 Feb 2000
Comparator C8
The control of the pulse width modulation of the PWM section is taken over by
comparator C8 as soon as the so ft start is fi nished. This is achieve d by comparison of
the PWM output voltage at pin 14 (PWM IN) and the PWM voltage ramp at pin 15
(PWM RMP).
Comparator C9
By means of this extremely fast comparator sensing at pin 11 (PWM CS) peak current
limitation is realized. When being activated ( VPWM CS > 1 V) it will immediately shut down
the gate drive of the PWM section (PWM OUT).
Comparator C10
By means of the threshold of 0.4 V the comparator C10 allows the PWM duty cycle to be
continuously controlled from 0 to 50%. As long as the ramp voltage at pin 15
(PWM RMP) is below this threshold the gate drive of the PWM section (pin 10,
PWM OUT) is turned off.
TDA 16888
Version 2.0 17 28 Feb 2000
4 Electrical Characteristics
4.1 Absolute Maximum Ratings
TA = – 25 to 85 °C
Parameter# Symbol Limit Values Unit Remarks
min. max.
VCC supply voltage VS–0.3 VZ3 VVZ3 = Zener voltage of Z3
Zener current of Z3 IZ3 –50mA–
VREF voltage VVREF – 0.3 8 V VVREF <VS
ROSC voltage VROSC – 0.3 8 V VROSC <VS
SYNC voltage VSYNC – 0.3 8 V –
PFC FB voltage VPFC FB – 0.3 8 V –
PFC IAC voltage VPFC IAC – 0.3 15 V –
AUX VS voltage VAUX VS – 0.3 8 V –
PFC VS vol tage VPFC VS – 0.3 8 V |IPFC VS|<1mA
PFC CL voltage VPFC CL – 1 3 V |IPFC CL|<1mA
PWM SS voltage VPWM SS – 0.3 8 V VPWM SS <VVREF
PWM IN voltage VPWM IN – 0.3 8 V –
PWM RMP voltage VPWM RMP – 0.3 8 V VPWM RMP <VVREF
PWM CS voltage VPWM CS – 0.3 3 V –
PFC VC voltage VPFC VC – 0.3 8 V –
PFC VC current IPFC VC – 20 20 mA –
PFC CS current IPFC CS – 5 5 mA –
GND S current IGND S – 5 5 mA –
PFC CC voltage VPFC CC – 0.3 8 V –
PFC CC current IPFC CC – 20 20 mA –
PFC/PW M OUT DC
current IOUT – 100 100 mA –
PFC/PWM OUT peak
clamping current IOUT – 200 mA VOUT =High
PFC/PWM OUT peak
clamping current IOUT –500 – mA VOUT = Low
Junction temperature TJ– 40 150 °C–
TDA 16888
Version 2.0 18 28 Feb 2000
Note: Absolute maximum ratings are defined as ratings, which when being exceeded
may l ead to des truction of the integrate d circ uit . To avoid dest ruction m ake sure,
that fo r any pi n excep t for pins PFC OUT and PWM OUT the curren ts cause d by
transient processes stay well below 100 mA. For the same reason make sure, that
any capacitor that will be connected to pin 9 (
VCC
) is discharged before
assembling the application circuit. In order to characterize the gate driver’s output
performance Figure 14, Figure 15, Figure 16 and Figure 17 are provided,
instead of referring just to a single parameter like the maximum gate charge or the
maximum output energy.
Note: Within the operating range the IC operates as described in the functional
description. In order to characterize the gate driver’s output performance
Figure 14, Figure 15, Figure 16 and Figure 17 are provided, instead of referring
just to a single parameter like the ma ximum gate charge o r the maximu m output
energy.
Storage temperature TS– 65 150 °C–
Thermal resistance RthJA – 60 K/W P-DIP-20-5
Thermal resistance RthJA – 70 K/W P-DSO-20-1
4.2 Operating Range
Parameter Symbol Limit Values Unit Remarks
min. max.
VCC supply voltage VS0VZ3 VVZ3 = Zener voltage of Z3
Zener current IZ3 0 50 mA Limited by TJ,max
PFC/PWM OUT curren t IOUT –1 1.5 A –
PFC IAC input current IPFC IAC 01mA–
PFC/PWM frequency fOUT 15 200 kHz –
Junction temperature TJ– 25 125 °C–
4.1 Absolute Maximum Ratings (cont’d)
TA = – 25 to 85 °C
Parameter# Symbol Limit Values Unit Remarks
min. max.
TDA 16888
Version 2.0 19 28 Feb 2000
4.3 Characteristics
Note: The electrical characteristics involve the spread of values guaranteed within the
specified supply voltage and ambient temperature range
TA
from – 25
°
C to 85
°
C
Typical values represent the median values, which are related to production
processes. If not otherwise stated, a supply voltage of
VS
= 15 V is assumed.
Supply Section
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Zener voltage1)
1) See Figure 3
VZ3 16.0 17.5 19.0 V IZ3 =30mA
Zener current IZ3 ––500
µAVS≤15.5 V2)
2) Design c haracteristics (not m eant for production t es t ing)
Quiescent supply
current IS––12mAVPWM SS =0V
RROSC =51k
Ω
CL=0V
PFC enabled
PWM disabled
––15mA
VPWM SS =6V
RROSC =51k
Ω
CL=0F
PFC enabled
PWM enabled
Supply current IS––40mAVPWM SS =6V
RROSC =51k
Ω
CL=4.7nF
PFC enabled
PWM enabled
TDA 16888
Version 2.0 20 28 Feb 2000
Undervoltage Lockout
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Power up,
rising voltage
threshold1)
VS,UP 13.0 14.0 14.5 V –
Power down,
falling voltage
threshold1)
VS,DWN 10.5 11.0 11.5 V –
Power up,
threshold current IS,UP –23100
µAVS=VS,UP –0.1V
VPFC CL <0.3V
2)
Stand-by mode
1) See Figure 3
2) To ensure t he v olt age fallback of pin PF C CL is disabled .
Internal Voltage Reference
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Trimmed reference
voltage VREF 4.9 5.0 5.1 V Measured at
pin PFC VC
Li ne regul ation ∆VREF ––40mV
∆VS=3V
TDA 16888
Version 2.0 21 28 Feb 2000
External Voltage Reference
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Buffered output voltage VVREF 7.2 7.5 7.8 V –3mA≤IVREF ≤0
Li ne regul ation ∆VVREF ––50mV
∆VS=3V
Load regulation ∆VVREF 040100mV
∆IVREF =2mA
Ma ximum output
current1) IVREF –10–6–4mAVVREF =6.5V
Short circuit current1) IVREF ––2–mAVVREF =0V
Shutdown hysteresis,
rising voltage threshold VVREF –6.6–V–
Shutdown hysteresis,
falling voltage threshold VVREF –6.2–V–
Shutdown delay td,VREF –500–nsVVREF =5V
2)3)
VPFC OUT =3V
2)3)
VPWM OUT =3V
2)3)
1) See Figure 4
2) Design c haracteristics (not m eant for production t es t ing)
3) Transient reference v alue
Oscillator
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
PFC/PWM frequency1)
1) See Figure 5
fOUT50 43 50 57 kHz RROSC = 110 kΩ
PFC/PWM frequency1) fOUT100 87 100 113 kHz RROSC =51kΩ
PFC/PWM frequency,
line regulation ∆fOUT ––1%∆VS=3V
RROSC =51kΩ
Maximum ramp vol tage VPFC RMP 5.0 5.4 5.6 V –
Minimum ramp voltage VPFC RMP 0.8 1.1 1.4 V –
SYNC, low level voltage VSYNC ––0.4V–
SYNC, high level voltage VSYNC 3.5 – VVREF V–
SYNC, input current ISYNC ––20µAVSYNC <0.4V
– – 150 µAVSYNC =3.5V
TDA 16888
Version 2.0 22 28 Feb 2000
PFC Section
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Max duty cycle1)
1) See Figure 6
Don,PFC 91 94 98 % VPFC OUT =2V
3)
RROSC =51k
Ω
CL=4.7nF
Multiplier throttling
(OTA2), threshold
voltage2)
2) See Figure 9
VPFC VS 5.2 5.5 5.8 V 0.9 IPFC CS
IPFC IAC =100µA
VPFC VC =6V
OTA1 disabled
Overvoltage protection
(C6), rising voltage
threshold
VPFC VS 5.8 6 6.2 V –
Overvoltage protection
(C6), falling voltage
threshold
VPFC VS 5.3 5.5 5.7 V –
Overvoltage protection
(C6), turn-off delay td,OV –2–µsVPFC VS =6.5V
3)4)
VPFC OUT =3V
3)4)
3) Transient reference v alue
4) Design c haracteristics (not m eant for production t es t ing)
Broken wire detection
(C 2), threshold voltage VPFC VS 0.93 1 1.07 V –
Voltage sense, input
current IPFC VS 0.2 0.45 0.7 µAVPFC VS =1V
Current limitation (C3),
threshold voltage VPFC CL 0.93 1 1.07 V –
Current limitation (C3),
input current IPFC CL 1–10µAVPFC CL =1V
Current limitation (C3,
D4), clamping voltage VPFC CL – 0.9 – – 0.1 V IPFC CL =–500µA
Current limitation (C3),
turn-off delay td,CL 30 – 150 ns VPFC CL =0.75V
3)
VPFC OUT =3V
3)
CL=4.7nF
TDA 16888
Version 2.0 23 28 Feb 2000
Multiplier
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Input current IPFC IAC 0–1mA–
Input voltage VPFC VC 0–6.7V–
Exponential function,
threshold voltage VPFC VC –1.1–V1)2)
Maximum output current IPFC CS – 320 – 420 – 550 µA OTA1 disabled
Output current 3) IPFC CS – – 100 – 500 nA IPFC IAC =0A
VPFC VC =2V
OTA1 disabled
–– 1.2–µAIPFC IAC =25µA
VPFC VC =2V
OTA1 disabled
–– 10–µAIPFC IAC =25µA
VPFC VC =4V
OTA1 disabled
–– 40–µAIPFC IAC =100µA
VPFC VC = 4 V
OTA1 disabled
–– 150–µAIPFC IAC =400µA
VPFC VC =4V
OTA1 disabled
–– 170–µAIPFC IAC =100µA
VPFC VC =6V
OTA1 disabled
1) Design c haracteristics (not m eant for production t es t ing)
2) For input voltages below this threshold the multiplier output current remains constant. For input voltages above
this threshold the outp ut rise s exponentially (s ee Figure 8).
3) See Figure 7
TDA 16888
Version 2.0 24 28 Feb 2000
Operational Transconductance Amplifier (OTA1)
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Auxiliary power supply,
threshold voltage1) VAUX VS 4.8 5.0 5.2 V IPFC CS =–1µA
Multiplier disabled
Input current IAUX VS ––15
µAVAUX VS >5.2V
–20 – – µAVAUX VS <4.8V
Output current IPFC CS –0–µAVAUX VS >5.2V
1)
–– 30–µAVAUX VS <4.8V
1) For input voltages below this threshold the output current is linearly increasing until at ca. 4.8 V the maximum
output cu rrent is reached.
Operational Transconductance Amplifier (OTA3)
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Offset com pen sati on,
threshold voltage VPFC VC 1.1 1.2 – V –
Input current IPFC VC – 1 – – µA1)
1) Design c haracteristics (not m eant for production t es t ing)
Output current IGND S –0–µAVPFC VC >1.2V
––10–µAVPFC VC <1.1V
TDA 16888
Version 2.0 25 28 Feb 2000
Voltage Amplifier (OP1)
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Offset vol tage VOff –4–4mV
1)
Input current IPFC FB –1 – 1 µAVPFC FB =4V
Open loop gain APFC VC –85–dB
2)
Input voltage range VPFC FB 0–6V–
Voltage sense,
threshold voltage VPFC FB 4.95 5.1V –
Output, maximum
voltage VPFC VC 6.3 – VVREF VIPFC VC =–500µA
Output, minimum
voltage VPFC VC 0.5– 1.1V IPFC VC = 500 µA
Output, short circuit
source curren t IPFC VC ––10–mAVPFC VC =0V
VPFC FB =4.9V
Output, short circuit sink
current IPFC VC –10–mAVPFC VC =6.4V
VPFC FB =5.1V
1) Guarant eed by wafer test
2) Design c haracteristics (not m eant for production t es t ing)
TDA 16888
Version 2.0 26 28 Feb 2000
Current Amplifier (OP2)
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Offset vol tage VOff –5 –1 3 mV –
Input current IPFC CS
IGND S
– 500 – 500 nA –
Open loop gain APFC CC – 110 – dB –
Gain bandwidth product fT–2.5–MHz
1)
Phase margin ϕ–60–°1)
Common mode voltage
range VCMVR – 0.2 – 0.5 V 1)
Clamped input voltage,
upper threshold
(D2, D3)
VPFC CS
VGND S
0.4 – 1.0 V IPFC CS =500µA
IGND S =500µA
Multiplier, OTA1
and OTA3 disabled
Clamped input voltage,
lower threshold (D1) VPFC CS –0.9 – –0.1 V IPFC CS = – 500 µA
Multiplier and OTA1
disabled
Output, maximum
voltage VPFC CC 6.3 – VVREF VIPFC CC =– 500µA
Output, minimum
voltage VPFC CC 0.5 – 1.1 V IPFC CC =500µA
Output, short circuit
source curren t IPFC CC ––10–mAVPFC CC =0V
VPFC CS =0V
VGND S =0.5V
Output, short circuit sink
current IPFC CC –10–mAVPFC CC =6.5V
VPFC CS =0.5V
VGND S =0V
1) Design c haracteristics (not m eant for production t es t ing)
TDA 16888
Version 2.0 27 28 Feb 2000
PWM Section
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Undervoltage protection (C4),
threshold voltage VPFC VS 3.8 4.0 4.2 V –
Bias control (C5),
rising voltage threshold VBC,Th –0.45–V–
Bias control (C5),
falling voltage threshold VBC,Th –0.4–V–
Softstart (I1),
charging current II1 20 30 40 µA–
Softstart, maximum voltage VPWM SS –6.7–V–
Input voltage VPWM IN 0.4 – 7.4 V –
PWM IN – GND resistance R375 100 150 kΩ–
Ramp (OP3), voltage gain AOP3 –5–V/V–
Ramp (C10), pulse start
threshold voltage VRMP 0.36 0.4 0.5 V –
Ramp, maximum voltage VRMP –6.5–V–
Ramp (V1), voltage offset VV1 –1.5–V–
Ramp (R1),
output impedance ZRMP –10–k
Ω–
Ma ximum duty cycle Don,PWM 41 – 50 % VPWM OUT =2V
1)
RROSC =51kΩ
CL=4.7nF
Current sense (C9),
voltage threshold VCS,Th 0.9 1.0 1.1 V –
Current sense (C9),
overload turn-off delay td,CS 30 – 250 ns VPWM CS =1.25V
1)
VPWM OUT =3V
1)
CL=4.7nF
1) Transient reference v alue
TDA 16888
Version 2.0 28 28 Feb 2000
Note: If not otherwise stated the figures shown in this section represent typical
performance characteristics.
Gate Drive (PWM and PFC Section)
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Output, minimum voltage VOUT ––1.2VV
S=5V
IOUT =5mA
––1.5V
VS=5V
IOUT =20mA
–0.8–V
IOUT =0A
–1.62.0V
IOUT =50mA
–0.2 0.2 – V IOUT = – 50 mA
Output, maximum voltage VOUT 10 11 12 V VS=16V
tH=10µs
CL=4.7nF
10.0 10.5 – V VS=12V
tH=10µs
CL=4.7nF
8.8 – – V VS=VS,DWN +0.2V
tH=10µs
CL=4.7nF
Rise ti me1) tr–150–nsVOUT =2V…8V
2)
CL=4.7nF
–100–ns
VOUT =3V…6V
2)
CL=4.7nF
Fall time tf–30–nsVOUT =9V…3V
2)
CL=4.7nF
–40–ns
VOUT =9V…2V
2)
CL=4.7nF
Output current, rising edge3) IOUT –1 – – A CL=4.7nF
4)
Output current, falling edge3) IOUT ––1.5ACL=4.7nF
4)
1) See Figure 13
2) Transient reference v alue
3) The gate driv er’s output perf ormance is charac t eriz ed in Figure 14, Figure 15, Figure 16 and Figure 17.
4) Design c haracteristics (not m eant for production t es t ing)
TDA 16888
Version 2.0 29 28 Feb 2000
Figure 3 Undervoltage Lockout Hysteresis and Zener Diode Overvoltage
Protection
Figure 4 Foldback Characteristic of Pin 2 (VREF)
AED02462
V
VCC
VCC
Ι
S, UP
Ι
S
Ι
V
S, DWN
V
S, UP Z3
V
AED02463
0
0
V
VREF
VREF
Ι
12345678
-1
-2
-3
-4
-5
-6
mA
-8
-7
V
TDA 16888
Version 2.0 30 28 Feb 2000
Figure 5 PFC/PWM Frequency
Figure 6 Maximum PFC Duty Cycle
AED02464
R
OSC
OUT
f
kΩ
10
10
100
100
kHz
400
500
AED02465
0
80
R
OSC
on, PFC, max
D
100 200 300 400
85
90
95
100
%
kΩ
TDA 16888
Version 2.0 31 28 Feb 2000
Figure 7 Multiplier Linearity
Figure 8 Multiplier Dynamic
AED02466
0
0
Ι
PFC IAC
PFC CCS
Ι
0.2 0.4 0.6 0.8 1
100
200
300
400
500
µ
A
mA
2 V
3 V
4 V5 V6 V
= 7 V
V
PFC VC
0
0
V
PFC VC
PFC CCS
Ι
100
200
300
400
500
µ
A
123 4 5 6 7V
PFC IAC
Ι
µ
A= 800 A400
µ
A200
µ
A100
µ
A50
µ
A25
µ
AED02356
TDA 16888
Version 2.0 32 28 Feb 2000
Figure 9 Multiplier Throttling by OTA2
Figure 10 Open Loop Gain and Phase Characteristic of Voltage Amplifier OP1
5.0
0
V
PFC VS
PFC CCS
Ι
100
200
300
400
500
µ
A
PFC IAC
Ι
µ
A> 300
A250
µ
A200
µ
A150
µ
A100
µ
A50
µ
AED02467
5.25 5.5 5.75 6.0V
= 6 V
V
PFC VC
010
-2
PFC VC
A
Frequency
20
40
60
80
100
10
-1
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
AED02468
Hz -150
-120
-90
-60
-30
0
PFC VC
A
φ
φ
dB deg
TDA 16888
Version 2.0 33 28 Feb 2000
Figure 11 Open Loop Gain and Phase Characteristic of Current Amplifier OP2
Figure 12 PWM Ramp Composition Scheme
010
-2
PFC CC
A
Frequency
10
-1
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
AED02469
Hz -180
PFC CC
A
φ
φ
deg
dB
20 -150
40 -120
60 -90
80 -60
100 -30
120 0
AED02470
0
0
Time
PWM RMP
V
0
T/2 T
1
V
V
1
2
V
3
1
V
4
1
V
1
V
/2
1
PWM CS
V
V
PWMCS
= 0
TDA 16888
Version 2.0 34 28 Feb 2000
Figure 13 Rising Edge of Driver Output
Figure 14 Power Dissipation of Single Gate Driver at fOUT =15kHz
AED02471
0
0
Time
PFC OUT
V
0.1 0.2 0.3 0.4
2
4
6
8
10
12
V
µ
s
AED02542
0
0
D
P
10 20 30 40 50nF
50
100
150
mW
C
L
R
L
= 0
Ω
R
L
= 1
Ω
R
L
= 2
Ω
R
L
= 5
Ω
R
L
= 10
Ω
= 15 kHz
f
OUT
= 0.194 W
P
D0
TDA 16888
Version 2.0 35 28 Feb 2000
Figure 15 Power Dissipation of Single Gate Driver at fOUT =50kHz
Figure 16 Power Dissipation of Single Gate Driver at fOUT = 100 kHz
AED02543
0
0
D
P
10 20 30 40 50nF
mW
C
L
R
L
= 0
Ω
R
L
= 1
Ω
R
L
= 2
Ω
R
L
= 5
Ω
R
L
= 10
Ω
= 50 kHz
f
OUT
= 0.197 W
P
D0
100
200
300
400
500
AED02544
0
0
D
P
10 20 30 40 50nF
mW
C
L
R
L
= 0
Ω
R
L
= 1
Ω
R
L
= 2
Ω
R
L
= 5
Ω
R
L
= 10
Ω
= 100 kHz
f
OUT
= 0.201 W
P
D0
0.2
0.4
0.6
0.8
1
TDA 16888
Version 2.0 36 28 Feb 2000
Figure 17 Power Dissipation of Single Gate Driver at fOUT = 200 kHz
AED02545
0
0
D
P
10 20 30 40 50nF
0.5
1.0
1.5
mW
C
L
R
L
= 0
Ω
R
L
= 1
Ω
R
L
= 2
Ω
R
L
= 5
Ω
R
L
= 10
Ω
= 200 kHz
f
OUT
= 0.212 W
P
D0
TDA 16888
Version 2.0 37 28 Feb 2000
Figure 18 Timing Diagram without Synchronization
AET02546
OSC
V
CLK OSC
PFC RMP
V
PFC OUT
V
PWM RMP
V
PWM OUT
V
CLK OUT
Time
on, max
t
on, max
t
V
PWM IN
BC, Th
V
V
PFC CC
TDA 16888
Version 2.0 38 28 Feb 2000
Figure 19 Timing Diagram with Synchronization (fSYNC > fOSC)
AET02547
OSC
V
CLK OSC
PFC RMP
V
PFC OUT
V
PWM RMP
V
PWM OUT
V
CLK OUT
Time
on, max
t
on, max
t
V
BC, Th
PWM IN
V
V
PFC CC
SYNC
V
TDA 16888
Version 2.0 39 28 Feb 2000
Figure 20 Timing Diagram with Synchronization (fSYNC < fOSC)
AET02548
OSC
V
CLK OSC
PFC RMP
V
PFC OUT
V
PWM RMP
V
PWM OUT
V
CLK OUT
Time
on, max
t
on, max
t
BC, Th
V
V
PWM IN
PFC CC
V
SYNC
V
TDA 16888
Version 2.0 40 28 Feb 2000
5 Package Outlines
P-DIP-20-5
(Plastic Dual In-line Package)
GPD05587
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm
TDA 16888
Version 2.0 41 28 Feb 2000
110
1120
Index Marking
1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side
GPS05094
2.65 max
0.1
0.2
-0.1
2.45
-0.2
+0.15
0.35
1.27
2)
0.2 24x
-0.2
7.6
1)
0.35 x 45˚
0.23
8˚ max
+0.09
+0.8
±0.3
10.3
0.4
12.8
-0.21)
P-DSO-20-1
(Plastic Dual Small Outline)
GPS 05094
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm
SMD = Surface Mounted Device
Qualität hat für uns eine umfassende
Bedeutung. Wir wollen allen Ihren
Ansprüchen in der bestmöglichen
Weise gerecht werden. Es geht uns also
nicht nur um die Produktqualität –
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gleichermaßen der Lieferqualität und
Logistik, dem Service und Support
sowie allen sonstigen Beratungs- und
Betreuungsleistungen.
Dazu gehört eine bestimmte
Geisteshaltung unserer Mitarbeiter.
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gegenüber Kollegen, Lieferanten und
Ihnen, unserem Kunden. Unsere
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Unternehmensweit orientieren wir uns
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Geben Sie uns die Chance, hohe
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For us it means living up to each and
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possible way. So we are not only
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direct our efforts equally at quality of
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Part of this is the very special attitude of
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deed, to wards co-workers, suppliers
and you, our customer. Our guideline is
“do everything with zero defects”, in an
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beyond your immediate workplace, and
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Throughout the corporation we also
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Processes (top ), greater speed on our
part to give you that decisive
competitive edge.
Give us the chance to prove the best of
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Total Quality Management
Published by Infineon Technologies AG
