18-Mb (512K x 36/1M x 18) Flow-through
SRAM with NoBL™ Architecture
CY7C1371CV25
CY7C1373CV25
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-05236 Rev. *B Revised February 26, 2004
Features
•No Bus Latency (NoBL) architecture eliminates
dead cycles between write and read cycles.
• Can support up to 133-MHz bus operations with zero
wait states
• Data is transferred on every clock
•Pin compatible and functionally equivalent to ZBT
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• Single 2.5V power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
• Clock Enable to enable clock and suspend operation
• Synchronous self-timed writes
• Offered in JEDEC-standard 100 TQFP, 119-Ball BGA and
165-Ball fBGA packages
• Three chip enables for simple depth expansion
Functional Description[1]
The CY7C1371CV25 is a 2.5V, 512K x 36/ 1M x 18
Synchronous Flow-through Burst SRAM designed specifically
to support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The CY7C1371CV25 is
equipped with the advanced No Bus Latency (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data through the
SRAM, especially in systems that require frequent Write-Read
transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Selection Guide
133 MHz 117 MHz 100 MHz Unit
Maximum Access Time 6.5 7.5 8.5 ns
Maximum Operating Current 210 190 175 mA
Maximum CMOS Standby Current 70 70 70 mA
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 2 of 31
1
2
C
MODE
BW
A
BW
B
WE
CE1
CE2
CE3
OE READ LOGIC
DQs
DQP
A
DQP
B
DQP
C
DQP
D
MEMORY
ARRAY
E
INPUT
REGISTER
BW
C
BW
D
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0 Q1
Q0
A0
A1
ADV/LD
CE ADV/LD
C
C
LK
C
EN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
SE
ZZ SLEEP
CONTROL
Logic Block Diagram – CY7C1371CV25 (512K x 36)
C
MODE
BW
A
BW
B
WE
CE1
CE2
CE3
OE READ LOGIC
DQs
DQP
A
DQP
B
MEMORY
ARRAY
E
INPUT
REGISTER
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0 Q1
Q0
A0
A1
ADV/LD
CE ADV/LD
C
C
LK
C
EN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
SE
ZZ
SLEEP
CONTROL
Logic Block Diagram – CY7C1373CV25 (1M x 18)
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 3 of 31
Pin Configurations
100-lead TQFP
A
A
A
A
A1
A0
NC / 288M
NC / 144M
V
SS
V
DD
NC / 36M
A
A
A
A
A
A
DQP
B
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
DQP
A
DQP
C
DQ
C
DQ
C
V
DDQ
V
SS
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
DQ
D
DQ
D
DQP
D
A
A
CE
1
CE
2
BW
D
BW
C
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
ADV/LD
ZZ
MODE
NC / 72M
CY7C1371CV25
BYTE A
BYTE B
BYTE D
BYTE C
A
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 4 of 31
Pin Configurations (continued)
100-lead TQFP
A
A
A
A
A1
A0
NC / 288M
NC / 144M
V
SS
V
DD
NC / 36M
A
A
A
A
A
A
A
NC
NC
V
DDQ
V
SS
NC
DQP
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
NC
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
NC
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQP
B
NC
V
SS
V
DDQ
NC
NC
NC
A
A
CE
1
CE
2
NC
NC
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
ADV/LD
ZZ
MODE
NC / 72M
CY7C1373CV25
BYTE A
BYTE B
A
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 5 of 31
Pin Configurations (continued)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC
DQPC
DQC
DQD
DQC
DQD
AA AAV
DDQ
CE2A
DQC
VDDQ
DQC
VDDQ
VDDQ
VDDQ
DQD
DQD
NC
NC
VDDQ
VDD
CLK
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
TDOTCKTDITMS
NC / 36MNC / 72M
NC
VDDQ
VDDQ
VDDQ
AAA
A
CE3
AA
A
AA
A
A0
A1
DQA
DQC
DQA
DQA
DQA
DQB
DQB
DQB
DQB
DQB
DQB
DQB
DQA
DQA
DQA
DQA
DQB
VDD
DQC
DQC
DQC
VDD
DQD
DQD
DQD
DQD
ADV/LD
NC
CE1
OE
A
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS DQPA
MODE
DQPD
DQPB
BWB
BWC
NC VDD NC
BWA
NC
CEN
BWD
ZZ
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC
NCDQB
DQB
DQB
DQB
AA AAV
DDQ
CE2A
NC
VDDQ
NC
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC / 72M
VDDQ
VDD
CLK
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
TDOTCKTDITMS
AA
NC
VDDQ
VDDQ
VDDQ
A NC / 36M A
A
CE3
AA
A
AA
A
A0
A1
DQA
DQB
NC
NC
DQA
NC
DQA
DQA
NC
NC
DQA
NC
DQA
NC
DQA
NC
DQA
VDD
NC
DQB
NC
VDD
DQB
NC
DQB
NC
ADV/LD
NC
CE1
OE
A
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS NC
MODE
DQPB
DQPA
VSS
BWB
NC VDD NC
BWA
NC
CEN
VSS
ZZ
CY7C1373CV25 (1M x 18)
CY7C1371CV25 (512K x 36)
119-ball BGA (3 Chip Enables with JTAG)
A
A
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 6 of 31
Pin Configurations (continued)
165-ball fBGA (3 Chip Enable with JTAG)
CY7C1371CV25 (512K x 36)
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC / 288M
NC
DQP
C
DQ
C
DQP
D
NC
DQ
D
CE
1
BW
B
CE3
BW
C
CEN
ACE2
DQ
C
DQ
D
DQ
D
MODE
NC
DQ
C
DQ
C
DQ
D
DQ
D
DQ
D
NC / 36M
NC / 72M
V
DDQ
BW
D
BW
A
CLK WE
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
V
DD
V
SS
V
DD
V
SS
V
SS
V
DDQ
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
SS
NC
TCK
V
SS
TDI
A
A
DQ
C
V
SS
DQ
C
V
SS
DQ
C
DQ
C
NC
V
SS
V
SS
V
SS
V
SS
NC
V
SS
A1
DQ
D
DQ
D
NC
NC
V
DDQ
V
SS
TMS
891011
NC
A
A
ADV/LD
NC
OE
ANC / 144M
V
SS
V
DDQ
NC DQP
B
V
DDQ
V
DD
DQ
B
DQ
B
DQ
B
NC
DQ
B
NC
DQ
A
DQ
A
V
DD
V
DDQ
V
DD
V
DDQ
DQ
B
V
DD
NC
V
DD
DQ
A
V
DD
V
DDQ
DQ
A
V
DDQ
V
DD
V
DD
V
DDQ
V
DD
V
DDQ
DQ
A
V
DDQ
AA
V
SS
A
A
A
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQP
A
DQ
A
A
V
DDQ
A
A0
A
V
SS
NC
CY7C1373CV25 (1M x 18)
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC / 288M
NC
NC
NC
DQP
B
NC
DQ
B
CE
1
NC
CE3
BW
B
CEN
ACE2
NC
DQ
B
DQ
B
MODE
NC
DQ
B
DQ
B
NC
NC
NC
NC / 36M
NC / 72M
V
DDQ
NC BW
A
CLK WE
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
V
DD
V
SS
V
DD
V
SS
V
SS
V
DDQ
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
SS
NC
TCK
V
SS
TDI
A
A
DQ
B
V
SS
NC V
SS
DQ
B
NC
NC
V
SS
V
SS
V
SS
V
SS
NC
V
SS
A1
DQ
B
NC
NC
NC
V
DDQ
V
SS
TMS
891011
NC
A
A
ADV/LD
A
OE
ANC / 144M
V
SS
V
DDQ
NC DQP
A
V
DDQ
V
DD
NC
DQ
A
DQ
A
NC
NC
NC
DQ
A
NC
V
DD
V
DDQ
V
DD
V
DDQ
DQ
A
V
DD
NC
V
DD
NCV
DD
V
DDQ
DQ
A
V
DDQ
V
DD
V
DD
V
DDQ
V
DD
V
DDQ
NC
V
DDQ
AA
V
SS
A
A
A
DQ
A
NC
NC
ZZ
DQ
A
NC
NC
DQ
A
A
V
DDQ
A
A0
A
V
SS
NC
A
A
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 7 of 31
CY7C1371CV25–Pin Definitions
Name TQFP BGA fBGA I/O Description
A0, A1 , A 37,36,32,33,
34,35,44,45,
46,47,48,49,
50,81,82,83,
84,99,100
P4,N4,A2,
C2,R2,A3,
B3,C3,T3,
A4,G4,T4,
A5,B5,C5,
T5,A6,C6,
R6
R6,P6,A2,
A9,A10,B2,
B9,B10,P3,
P4,P8,P9,
P10,R3,R4,
R8,R9,R10,
R11
Input-
Synchronous
Address Inputs used to select one of the 512K
address locations. Sampled at the rising edge of the
CLK. A[1:0] are fed to the two-bit burst counter.
BWA,BWB
BWC,BWD
93,94,95,96 L5,G5,G3,
L3
B5,A5,A4,
B4
Input-
Synchronous Byte Write Inputs, active LOW. Qualified with WE to
conduct writes to the SRAM. Sampled on the rising edge
of CLK.
WE 88 H4 B7 Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a write sequence.
ADV/LD 85 B4 A8 Input-
Synchronous
Advance/Load Input. Used to advance the on-chip
address counter or load a new address. When HIGH (and
CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into
the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
CLK 89 K4 B6 Input-
Clock
Clock Input. Used to capture all synchronous inputs to
the device. CLK is qualified with CEN. CLK is only recog-
nized if CEN is active LOW.
CE1
98 E4 A3 Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE2, and CE3 to
select/deselect the device.
CE297 B2 B3 Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising
edge of CLK. Used in conjunction with CE1 and CE3 to
select/deselect the device.
CE392 B6 A6 Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE1 and CE2 to
select/deselect the device.
OE 86 F4 B8 Input-
Asynchronous
Output Enable, asynchronous input, active LOW.
Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW,
the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as
input data pins. OE is masked during the data portion of
a write sequence, during the first clock when emerging
from a deselected state, when the device has been
deselected.
CEN 87 M4 A7 Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW
the Clock signal is recognized by the SRAM. When
deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can
be used to extend the previous cycle when required.
ZZ 64 T7 H11 Input-
Asynchronous
ZZ “sleep” Input. This active HIGH input places the
device in a non-time critical “sleep” condition with data
integrity preserved. During normal operation, this pin can
be connected to Vss or left floating.
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 8 of 31
DQs52,53,56,57,
58,59,62,63,
68,69,72,73,
74,75,78,79,
2,3,6,7,8,9,
12,13,18,19,
22,23,24,25,
28,29
K6,L6,M6,
N6,K7,L7,
N7,P7,E6,
F6,G6,H6,
D7,E7,G7,
H7,D1,E1,
G1,H1,E2,
F2,G2,H2,
K1,L1,N1,
P1,K2,L2,
M2,N2
M11,L11,
K11,J11,
J10,K10,
L10,M10,
D10,E10,
F10,G10,
D11,E11,
F11,G11,
D1,E1,F1,
G1,D2,E2,
F2,G2,J1,
K1,L1,M1,
J2,K2,L2
M2,
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge
of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented
during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs. When HIGH,
DQs and DQP[A:D] are placed in a three-state
condition.The outputs are automatically three-stated
during the data portion of a write sequence, during the first
clock when emerging from a deselected state, and when
the device is deselected, regardless of the state of OE.
DQP[A:D] 51,80,1,30 P6,D6,D2,
P2
N11,C11,C1,
N1
I/O-
Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these
signals are identical to DQs. During write sequences,
DQP[A:D] is controlled by BW[A:D] correspondingly.
MODE 31 R3 R1 Input Strap Pin Mode Input. Selects the burst order of the device. When
tied to Gnd selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst sequence.
VDD 15,41,65,91 J2,C4,J4,
R4,J6
D4,D8,E4,
E8,F4,F8,
G4,G8,H2,
H4,H8,J4,
J8,K4,K8,
L4,L8,M4,
M8
Power Supply Power supply inputs to the core of the device.
VDDQ 4,11,20,27,
54,61,70,77
A1,F1,J1,
M1,U1,
A7,F7,J7,
M7,U7
C3,C9,D3,
D9,E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
I/O Power
Supply
Power supply for the I/O circuitry.
VSS 5,10,17,21,
26,40,55,60,
67,71,76,90
D3,E3,F3,
H3,K3,
M3,N3,
P3,D5,E5,
F5,H5,K5,
M5,N5,P5
C4,C5,C6,
C7,C8,D5,
D6,D7,E5,
E6,E7,F5,
F6,F7,G5,
G6,G7,H5,
H6,H7,J5,
J6,J7,K5,K6,
K7,L5,L6,L7,
M5,M6,M7,
N4,N8
Ground Ground for the device.
TDO – U5 P7 JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the
negative edge of TCK. If the JTAG feature is not being
utilized, this pin should be left unconnected. This pin is not
available on TQFP packages.
TDI – U3 P5 JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising
edge of TCK. If the JTAG feature is not being utilized, this
pin can be left floating or connected to VDD through a pull
up resistor. This pin is not available on TQFP packages.
CY7C1371CV25–Pin Definitions(continued)
Name TQFP BGA fBGA I/O Description
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 9 of 31
TMS – U2 R5 JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising
edge of TCK. If the JTAG feature is not being utilized, this
pin can be disconnected or connected to VDD. This pin is
not available on TQFP packages.
TCK – U4 R7 JTAG
-Clock
Clock input to the JTAG circuitry. If the JTAG feature is
not being utilized, this pin must be connected to VSS. This
pin is not available on TQFP packages.
NC 16,38,39,42,
43,66,14
B1,C1,R1,
T1,T2,J3,
D4,L4,J5,
R5,T6,U6,
B7,C7,R7
A1,A11,B1,
B11,C2,C10,
H1,H3,H9,H
10,N2,N5,
N6,N7,
N10,P1,P2,
P11,R2
–No Connects. Not internally connected to the die. 18M,
36M, 72M, 144M and 288M are address expansion pins
and are not internally connected to the die.
CY7C1371CV25–Pin Definitions(continued)
Name TQFP BGA fBGA I/O Description
CY7C1373CV25–Pin Definitions
Name TQFP BGA fBGA I/O Description
A0, A1 , A 37,36,32,33,
34,35,44,45,
46,47,48,49,
50,80,81,82,
83,84,99,
100
P4,N4,A2,
C2,R2,T2,
A3,B3,C3,
T3,A4,
A5,B5,C5,
T5,A6,C6,
R6,T6
R6,P6,A2,
A9,A10,A11,
B2,B9,B10,
P3,P4,P8,
P9,P10,R3,
R4,R8,R9,
R10,R11
Input-
Synchronous
Address Inputs used to select one of the 1M address
locations. Sampled at the rising edge of the CLK. A[1:0]
are fed to the two-bit burst counter.
BWA,BWB93,94 G3,L5 B5,A4 Input-
Synchronous Byte Write Select Inputs, active LOW. Qualified with WE
to conduct writes to the SRAM. Sampled on the rising
edge of CLK.
WE 88 H4 B7 Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a write sequence.
ADV/LD 85 B4 A8 Input-
Synchronous
Advance/Load Input. Used to advance the on-chip
address counter or load a new address. When HIGH (and
CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into
the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
CLK 89 K4 B6 Input-
Clock
Clock Input. Used to capture all synchronous inputs to
the device. CLK is qualified with CEN. CLK is only recog-
nized if CEN is active LOW.
CE1
98 E4 A3 Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE2, and CE3 to
select/deselect the device.
CE297 B2 B3 Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising
edge of CLK. Used in conjunction with CE1 and CE3 to
select/deselect the device.
CE3 92 B6 A6 Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE1 and CE2 to
select/deselect the device.
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 10 of 31
OE 86 F4 B8 Input-
Asynchronous
Output Enable, asynchronous input, active LOW.
Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW,
the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as
input data pins. OE is masked during the data portion of a
write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.
CEN 87 M4 A7 Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW
the Clock signal is recognized by the SRAM. When
deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can
be used to extend the previous cycle when required.
ZZ 64 T7 H11 Input-
Asynchronous
ZZ “sleep” Input, active HIGH. When asserted HIGH
places the device in a non-time-critical “sleep” condition
with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal
pull-down.
DQs58,59,62,63,
68,69,72,73,
8,9,12,13,
18,19,22,23
P7,K7,G7,
E7,F6,H6,
L6,N6,D1,
H1,L1,N1,
E2,G2,K2,
M2
J10,K10,
L10,M10,
D11,E11,
F11,G11,J1,
K1,L1,M1,
D2,E2,F2,
G2
I/O-
Synchronous
Bidirectional Data I/O Lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge of
CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented
during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs. When HIGH,
DQs and DQP[A:B] are placed in a three-state
condition.The outputs are automatically three-stated
during the data portion of a write sequence, during the first
clock when emerging from a deselected state, and when
the device is deselected, regardless of the state of OE.
DQP[A:B] 74,24 D6,P2 C11,N1 I/O-
Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these
signals are identical to DQs. During write sequences,
DQP[A:B] is controlled by BW[A:B] correspondingly.
MODE 31 R3 R1 Input Strap Pin Mode Input. Selects the burst order of the device. When
tied to Gnd selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst sequence.
VDD 15,41,65,91 C4,J2,J4,
J6,R4
D4,D8,E4,
E8,F4,F8,
G4,G8,H2,
H4,H8,J4,
J8,K4,K8,
L4,L8,M4,
M8
Power Supply Power supply inputs to the core of the device.
VDDQ 4,11,20,27,
54,61,70,77
A1,A7,F1,
F7,J1,J7,
M1,M7,U1
,U7
C3,C9,D3,
D9,E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
I/O Power
Supply
Power supply for the I/O circuitry.
CY7C1373CV25–Pin Definitions(continued)
Name TQFP BGA fBGA I/O Description
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 11 of 31
Functional Overview
The CY7C1371CV25 is a synchronous flow-through burst
SRAM designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (tCDV) is 6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BWX can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
VSS 5,10,17,21,
26,40,55,60,
67,71,76,90
D3,D5,E3,
E5,F3,F5,
G5,H3,
H5,K3,K5,
L3,M3,
M5,N3,
N5,P3,P5
C4,C5,C6,
C7,C8,D5,
D6,D7,E5,
E6,E7,F5,
F6,F7,G5,
G6,G7,H5,
H6,H7,J5,
J6,J7,K5,K6,
K7,L5,L6,L7,
M5,M6,M7,
N4,N8
Ground Ground for the device.
TDO – U5 P7 JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the
negative edge of TCK. If the JTAG feature is not being
utilized, this pin should be left unconnected. This pin is not
available on TQFP packages.
TDI – U3 P5 JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising
edge of TCK. If the JTAG feature is not being utilized, this
pin can be left floating or connected to VDD through a pull
up resistor. This pin is not available on TQFP packages.
TMS – U2 R5 JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising
edge of TCK. If the JTAG feature is not being utilized, this
pin can be disconnected or connected to VDD. This pin is
not available on TQFP packages.
TCK – U4 R7 JTAG
-Clock
Clock input to the JTAG circuitry. If the JTAG feature is
not being utilized, this pin must be connected to VSS. This
pin is not available on TQFP packages.
NC 1,2,3,6,7,16,
25,28,29,30,
38,39,42,43,
51,52,53,56,
57,66,75,78,
79,95,96,14
B1,B7,C1,
C7,D2,D4,
D7,E1,E6,
H2,F2,G1,
G6,
H7,J3,J5,
K1,K6,L4,
L2,L7,M6,
N2,N7,L7,
P1,P6,R1,
R5,R7,T1,
T4,U6
A1,A5,B1,
B4,B11,
C1,C2,C10,
D1,D10,E1,
E10,F1,F10,
G1,G10,H1,
H3,H9,H10,
J2,J11,K2,
K11,L2,L11,
M2,M11,N2,
N5,N6,N7,
N10,N11,P1,
P2,P11,R2
–No Connects. Not internally connected to the die. 18M,
36M, 72M, 144M and 288M are address expansion pins
and are not internally connected to the die.
CY7C1373CV25–Pin Definitions(continued)
Name TQFP BGA fBGA I/O Description
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 12 of 31
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.
Burst Read Accesses
The CY7C1371CV25 has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enable inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically three-stated regardless of the state of the OE
input signal. This allows the external logic to present the data
on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX
(or a subset for byte write operations, see truth table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BWX signals. The CY7C1371CV25 provides byte write
capability that is described in the truth table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write opera-
tions.
Because the CY7C1371CV25 is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE) can be deasserted HIGH
before presenting data to the DQs and DQPX inputs. Doing so
will three-state the output drivers. As a safety precaution, DQs
and DQPX are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1371CV25 has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four Write operations without reasserting the address
inputs. ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct
BWX inputs must be driven in each cycle of the burst write, in
order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this
“sleep”mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive for
the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 13 of 31
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
IDDZZ Snooze mode standby current ZZ > VDD – 0.2V 60 mA
tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns
tZZI ZZ active to snooze current This parameter is sampled 2tCYC ns
tRZZI ZZ Inactive to exit snooze current This parameter is sampled 0 ns
Truth Table[ 2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used CE1CE2CE3ZZ ADV/LD WE BWXOE CEN CLK DQ
Deselect Cycle None H X X L L X X X L L->H three-state
Deselect Cycle None X X H L L X X X L L->H three-state
Deselect Cycle None X L X L L X X X L L->H three-state
Contine Deselect Cycle None X X X L H X X X L L->H three-state
READ Cycle (Begin Burst) External L H L L L H X L L L->H Data Out (Q)
READ Cycle (Contine Burst) Next X X X L H X X L L L->H Data Out (Q)
NOP/DUMMY READ (Begin Burst) External L H L L L H X H L L->H three-state
DUMMY READ (Continue Burst) Next X X X L H X X H L L->H three-state
WRITE Cycle (Begin Burst) External L H L L L L L X L L->H Data In (D)
WRITE Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D)
NOP/WRITE ABORT (Begin Burst) None L H L L L L H X L L->H three-state
WRITE ABORT (Continue Burst) Next X X X L H X H X L L->H three-state
IGNORE CLOCK EDGE(Stall) Current X X X L X X X X H L->H –
SNOOZE MODE None X X X H X X X X X X three-state
Partial Truth Table for Read/Write[2, 3]
Function (CY7C1371CV25) WE BWABWBBWCBWD
Read H X X X X
Write No bytes written L H H H H
Write Byte A – ( DQA and DQPA )LLHHH
Write Byte B – ( DQB and DQPB )LHLHH
Write Byte C – ( DQC and DQPC )LHHLH
Write Byte D – ( DQD and DQPD )LHHHL
Write All Bytes L L L L L
Notes:
2. X=”Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BWX, and WE. See truth table for Read/Write.
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = three-state when
OE is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 14 of 31
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1371CV25 incorporates a serial boundary scan test
access port (TAP). This port operates in accordance with IEEE
Standard 1149.1-1990 but does not have the set of functions
required for full 1149.1 compliance. These functions from the
IEEE specification are excluded because their inclusion
places an added delay in the critical speed path of the SRAM.
Note that the TAP controller functions in a manner that does
not conflict with the operation of other devices using 1149.1
fully compliant TAPs. The TAP operates using
JEDEC-standard 2.5V I/O logic levels.
The CY7C1371CV25 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID
register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
TAP Controller State Diagram
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
Partial Truth Table for Read/Write[2, 3]
Function (CY7C1373CV25) WE BWABWB
Read H X X
Write - No bytes written L H H
Write Byte A – ( DQA and DQPA )LHH
Write Byte B – ( DQB and DQPB )LHH
Write All Bytes L L L
TEST-LOGIC
RESET
RUN-TEST/
IDLE SELECT
DR-SCAN SELECT
IR-SCAN
CAPTURE-DR
SHIFT-DR
CAPTURE-IR
SHIFT-IR
EXIT1-DR
PAUSE-DR
EXIT1-IR
PAUSE-IR
EXIT2-DR
UPDATE-DR
EXIT2-IR
UPDATE-IR
1
1
1
0
1 1
0 0
1 1
1
0
0
0
0 0
0
0
0 0
1
0
1
1
0
1
0
1
1
1
1 0
Bypass Register
0
Instruction Register
012
Identification Register
012293031 ...
Boundary Scan Register
012..x ...
S
election
Circuitr
y
Selection
Circuitry
TCK
T
MS TAP CONTROLLER
TDI TD
O
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 15 of 31
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The SRAM has a 75-bit-long
register.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD; rather, it performs a capture of the I/O ring when
these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 16 of 31
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (tCS plus tCH).
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
TAP AC Switching Characteristics Over the operating Range[9, 10]
Parameter Description Min. Max. Unit
Clock
tTCYC TCK Clock Cycle Time 100 ns
tTF TCK Clock Frequency 10 MHz
tTH TCK Clock HIGH time 40 ns
tTL TCK Clock LOW time 40 ns
Output Times
tTDOV TCK Clock LOW to TDO Valid 20 ns
tTDOX TCK Clock LOW to TDO Invalid 0 ns
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise 10 ns
tTDIS TDI Set-up to TCK Clock Rise 10 ns
tCS Capture Set-up to TCK Rise 10
Hold Times
tTMSH TMS hold after TCK Clock Rise 10 ns
tTDIH TDI Hold after Clock Rise 10 ns
tCH Capture Hold after Clock Rise 10 ns
Notes:
9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1ns
tTL
Test Clock
(TCK)
123456
T
est Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE UNDEFINED
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 17 of 31
2.5V TAP AC Test Conditions
Input pulse levels ........................................ VSS to 2.5V
Input rise and fall time...................................................... 1ns
Input timing reference levels .........................................1.25V
Output reference levels.................................................1.25V
Test load termination supply voltage.............................1.25V
2.5V TAP AC Output Load Equivalent
T
DO
1.25V
20p
F
Z = 50Ω
O
50Ω
TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; Vdd = 2.5V ±0.165V unless
otherwise noted)[11]
Parameter Description Description Min. Max. Unit
VOH1 Output HIGH Voltage IOH = –1.0 mA 2.0 V
VOH2 Output HIGH Voltage IOH = –100 µA 2.1 V
VOL1 Output LOW Voltage IOL = 1.0 mA 0.4 V
VOL2 Output LOW Voltage IOL = 100 µA 0.2 V
VIH Input HIGH Voltage 1.7 VDD + 0.3 V
VIL Input LOW Voltage –0.3 0.7 V
IXInput Load Current GND < VIN < VDDQ –5 5 µA
Identification Register Definitions
Instruction Field
CY7C1371CV25
(512Kx36)
CY7C1373CV25
(1Mx18) Description
Revision Number (31:29) 010 010 Describes the version number
Device Depth (28:24) 01011 01011 Reserved for Internal Use
Device Width (23:18) 001001 001001 Defines memory type and architecture
Cypress Device ID (17:12) 100101 010101 Defines width and density
Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor
ID Register Presence Indicator (0) 11
Indicates the presence of an ID register
Scan Register Sizes
Register Name Bit Size (x36) Bit Size (x18)
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary Scan Order 70 51
Identification Codes
Instruction Code Description
EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operations.
SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
Note:
11. All voltages referenced to VSS (GND).
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 18 of 31
SAMPLE/PR
ELOAD
100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is
therefore not 1149.1-compliant.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
119-Ball BGA Boundary Scan Order
CY7C1371CV25 (512K x 36) CY7C1373CV25(1M x 18)
Bit# Ball ID Bit# Ball ID Bit# Ball ID Bit# Ball ID
1K4 36 P4 1 K4 36 P4
2 H4 37 N4 2 H4 37 N4
3M438 R6 3 M438 R6
4F439 T5 4 F439 T5
5B440 T3 5 B440 T3
6A441 R2 6 A441 R2
7G442 R3 7 G442 R3
8 C6 43 P2 8 C6 43 Not Bonded (Preset
to 0)
9 A6 44 P1 9 A6 44 Not Bonded (Preset
to 0)
10 D6 45 N2 10 T6 45 Not Bonded (Preset
to 0)
11 D7 46 L2 11 Not Bonded
(Preset to 0)
46 Not Bonded (Preset
to 0)
12 E6 47 K1 12 Not Bonded
(Preset to 0)
47 P2
13 G6 48 N1 13 Not Bonded
(Preset to 0)
48 N1
14 H7 49 M2 14 D6 49 M2
15 E7 50 L1 15 E7 50 L1
16 F6 51 K2 16 F6 51 K2
17 G7 52 NC 17 G7 52 NC
18 H6 53 H1 18 H6 53 H1
19 T7 54 G2 19 T7 54 G2
20 K7 55 E2 20 K7 55 E2
21 L6 56 D1 21 L6 56 D1
22 N6 57 H2 22 N6 57 Not Bonded (Preset
to 0)
23 P7 58 G1 23 P7 58 Not Bonded (Preset
to 0)
24 K6 59 F2 24 Not Bonded
(Preset to 0)
59 Not Bonded (Preset
to 0)
25 L7 60 E1 25 Not Bonded
(Preset to 0)
60 Not Bonded (Preset
to 0)
26 M6 61 D2 26 Not Bonded
(Preset to 0)
61 Not Bonded (Preset
to 0)
Identification Codes(continued)
Instruction Code Description
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 19 of 31
27 N7 62 A5 27 Not Bonded
(Preset to 0)
62 A5
28 P6 63 A3 28 Not Bonded
(Preset to 0)
63 A3
29 B5 64 E4 29 B5 64 E4
30 B3 65 B2 30 B3 65 B2
31 C5 66 L3 31 C5 66 Not Bonded (Preset
to 0)
32 C3 67 G3 32 C3 67 G3
33 C2 68 G5 33 C2 68 Not Bonded (Preset
to 0)
34 A2 69 L5 34 A2 69 L5
35 T4 70 B6 35 T2 70 B6
165-Ball fBGA Boundary Scan Order
CY7C1371CV25 (512K x 36) CY7C1373CV25 (1M x 18)
Bit# Ball ID Bit# Ball ID Bit# Ball ID Bit# Ball ID
1B636 R6 1 B636R6
2 B7 37 P6 2 B7 37 P6
3A738 R4 3 A738R4
4B839 R3 4 B839R3
5 A8 40 P4 5 A8 40 P4
6 B9 41 P3 6 B9 41 P3
7A942 R1 7 A942R1
8 B10 43 N1 8 B10 43 Not Bonded
(Preset to 0)
9 A10 44 L2 9 A10 44 Not Bonded
(Preset to 0)
10 C11 45 K2 10 A11 45 Not Bonded
(Preset to 0)
11 E10 46 J2 11 Not Bonded
(Preset to 0)
46 Not Bonded
(Preset to 0)
12 F10 47 M2 12 Not Bonded
(Preset to 0)
47 N1
13 G10 48 M1 13 Not Bonded
(Preset to 0)
48 M1
14 D10 49 L1 14 Not Bonded
(Preset to 0)
49 L1
15 D11 50 K1 15 D11 50 K1
16 E11 51 J1 16 E11 51 J1
17 F11 52 Internal 17 F11 52 Internal
18 G11 53 G2 18 G11 53 G2
19 H11 54 F2 19 H11 54 F2
20 J10 55 E2 20 J10 55 E2
21 K10 56 D2 21 K10 56 D2
22 L10 57 G1 22 L10 57 Not Bonded
(Preset to 0)
119-Ball BGA Boundary Scan Order
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 20 of 31
23 M10 58 F1 23 M10 58 Not Bonded
(Preset to 0)
24 J11 59 E1 24 Not Bonded
(Preset to 0)
59 Not Bonded
(Preset to 0)
25 K11 60 D1 25 Not Bonded
(Preset to 0)
60 Not Bonded
(Preset to 0)
26 L11 61 C1 26 Not Bonded
(Preset to 0)
61 Not Bonded
(Preset to 0)
27 M11 62 A2 27 Not Bonded
(Preset to 0)
62 A2
28 N11 63 B2 28 Not Bonded
(Preset to 0)
63 B2
29 R11 64 A3 29 R11 64 A3
30 R10 65 B3 30 R10 65 B3
31 R9 66 B4 31 R9 66 Not Bonded
(Preset to 0)
32 R8 67 A4 32 R8 67 Not Bonded
(Preset to 0)
33 P10 68 A5 33 P10 68 A4
34 P9 69 B5 34 P9 69 B5
35 P8 70 A6 35 P8 70 A6
165-Ball fBGA Boundary Scan Order
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 21 of 31
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
DC Voltage Applied to Outputs
in three-state ....................................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Ambient
Temperature VDD VDDQ
Commercial 0°C to +70°C 2.5V + 5% 2.5V – 5%
to VDD
Industrial –40°C to +85°C
Electrical Characteristics Over the Operating Range [12, 13]
Parameter Description Test Conditions Min. Max. Unit
VDD Power Supply Voltage 2.375 2.625 V
VDDQ I/O Supply Voltage VDDQ = 2.5V 2.375 2.625 V
VOH Output HIGH Voltage VDDQ = 2.5V, VDD = Min., IOH =-1.0ma 2.0 V
VOL Output LOW Voltage VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA 0.4 V
VIH Input HIGH Voltage[12] VDDQ = 2.5V 1.7 VDD + 0.3V V
VIL Input LOW Voltage[12] VDDQ = 2.5V –0.3 0.7 V
IXInput Load GND ≤ VI ≤ VDDQ –5 5 µA
Input Current of MODE –30 30 µA
IOZ Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled –5 5 µA
IDD VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz 210 mA
8.5-ns cycle, 117 MHz 190 mA
10-ns cycle, 100 MHz 175 mA
ISB1 Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX, inputs switching
7.5-ns cycle, 133 MHz 120 mA
8.5-ns cycle, 117 MHz 110 mA
10-ns cycle, 100 MHz 100 mA
ISB2 Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max, Device Deselected,
VIN ≤ 0.3V or VIN > VDD – 0.3V,
f = 0, inputs static
All speeds 70 mA
ISB3 Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max, Device Deselected, or
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
f = fMAX, inputs switching
7.5-ns cycle, 133 MHz 105 mA
8.5-ns cycle, 117 MHz 100 mA
10-ns cycle, 100 MHz 95 mA
ISB4 Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VDD - 0.3V or VIN ≤ 0.3V
, f =
0, inputs static
All Speeds 80 mA
Notes:
12. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2).
13. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 22 of 31
Thermal Resistance[14]
Parameter Description Test Conditions
TQFP
Package
BGA
Package
fBGA
Package Unit
ΘJA Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
test methods and procedures
for measuring thermal
impedence, per EIA/JESD51.
31 45 46 °C/W
ΘJC Thermal Resistance
(Junction to Case)
673°C/W
Capacitance[14]
Parameter Description Test Conditions
TQFP
Package
BGA
Package
fBGA
Package Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 2.5V.
VDDQ = 2.5V
589pF
CCLK Clock Input Capacitance 5 8 9 pF
CI/O Input/Output Capacitance 5 8 9 pF
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range [19, 20]
Parameter Description
133 MHz 117 MHz 100 MHz
UnitMin. Max. Min. Max. Min. Max.
tPOWER‘ ‘111ms
Clock
tCYC Clock Cycle Time 7.5 8.5 10 ns
tCH Clock HIGH 2.1 2.3 2.5 ns
tCL Clock LOW 2.1 2.3 2.5 ns
Output Times
tCDV Data Output Valid After CLK Rise 6.5 7.5 8.5 ns
tDOH Data Output Hold After CLK Rise 2.0 2.0 2.0 ns
tCLZ Clock to Low-Z[16, 17, 18] 2.0 2.0 2.0 ns
tCHZ Clock to High-Z[16, 17, 18] 4.0 4.0 5.0 ns
tOEV OE LOW to Output Valid 3.2 3.4 3.8 ns
tOELZ OE LOW to Output Low-Z[16, 17, 18] 00 0ns
tOEHZ OE HIGH to Output High-Z[16, 17, 18] 4.0 4.0 5.0 ns
Notes:
14. Tested initially and after any design or process change that may affect these parameters
15. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD( minimum) initially, before a read or write operation
can be initiated.
16. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
17. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
18. This parameter is sampled and not 100% tested.
19. Timing reference level is 1.5V when VDDQ = 2.5V and is 1.25V when VDDQ = 2.5V.
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
OUTPUT
R = 1667Ω
R =1538Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50Ω
Z0= 50Ω
VL= 1.25V
2.5V ALL INPUT PULSES
VDD
GND
90%
10%
90%
10%
≤1ns ≤1ns
(c)
2.5V I/O Test Load
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 23 of 31
Set-up Times
tAS Address Set-up Before CLK Rise 1.5 1.5 1.5 ns
tALS ADV/LD Set-up Before CLK Rise 1.5 1.5 1.5 ns
tWES WE, BWX Set-up Before CLK Rise 1.5 1.5 1.5 ns
tCENS CEN Set-up Before CLK Rise 1.5 1.5 1.5 ns
tDS Data Input Set-up Before CLK Rise 1.5 1.5 1.5 ns
tCES Chip Enable Set-Up Before CLK Rise 1.5 1.5 1.5 ns
Hold Times
tAH Address Hold After CLK Rise 0.5 0.5 0.5 ns
tALH ADV/LD Hold After CLK Rise 0.5 0.5 0.5 ns
tWEH WE, BWX Hold After CLK Rise 0.5 0.5 0.5 ns
tCENH CEN Hold After CLK Rise 0.5 0.5 0.5 ns
tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 ns
tCEH Chip Enable Hold After CLK Rise 0.5 0.5 0.5 ns
Switching Characteristics Over the Operating Range(continued)[19, 20]
Parameter Description
133 MHz 117 MHz 100 MHz
UnitMin. Max. Min. Max. Min. Max.
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 24 of 31
Switching Waveforms
Read/Write Waveforms[21, 22, 23]
3
WRITE
D(A1)
123456789
CLK
t
CYC
tCL
tCH
10
CE
tCEH
tCES
WE
CEN
tCENH
tCENS
BWX
ADV/LD
tAH
tAS
ADDRESS A1 A2 A3 A4 A5 A6 A7
tDH
tDS
DQ
C
OMMAND
tCLZ
D(A1) D(A2) Q(A4)Q(A3)
D(A2+1)
tDOH tCHZ
tCDV
WRITE
D(A2) BURST
WRITE
D(A2+1)
READ
Q(A3) READ
Q(A4) BURST
READ
Q(A4+1)
WRITE
D(A5) READ
Q(A6) WRITE
D(A7) DESELECT
OE
tOEV
tOELZ
tOEHZ
DON’T CARE UNDEFINED
D(A5)
tDOH
Q(A4+1)
D(A7)Q(A6)
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 25 of 31
NOP, STALL AND DESELECT Cycles[21, 22, 24]
Notes:
21. For this waveform ZZ is tied low.
22. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
23. Order of the Burst sequence is determined by the status of the MODE (0= Linear, 1= Interleaved). Burst operations are optional.
24. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
25. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
26. DQs are in high-Z when exiting ZZ sleep mode.
Switching Waveforms(continued)
WRITE
D(A1)
123456789
CLK
tCYC
tCL
tCH
10
CE
tCEH
tCES
WE
CEN
tCENH
tCENS
BWX
ADV/LD
tAH
tAS
ADDRESS A1 A2 A3 A4 A5 A6 A7
tDH
tDS
DQ
C
OMMAND
tCLZ
D(A1) D(A2) Q(A4)Q(A3)
D(A2+1)
tDOH tCHZ
tCDV
WRITE
D(A2) BURST
WRITE
D(A2+1)
READ
Q(A3) READ
Q(A4) BURST
READ
Q(A4+1)
WRITE
D(A5) READ
Q(A6) WRITE
D(A7) DESELECT
OE
tOEV
tOELZ
tOEHZ
DON’T CARE UNDEFINED
D(A5)
tDOH
Q(A4+1)
D(A7)Q(A6)
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 26 of 31
Switching Waveforms(continued)
tZZ
ISUPPLY
CLK
ZZ
tZZREC
A
LL INPUTS
(except ZZ)
DON’T CARE
IDDZZ
tZZI
tRZZI
Outputs (Q) High-Z
DESELECT or READ Only
Z Mode Timing
,
Ordering Information
Speed
(MHz) Ordering Code
Package
Name Part and Package Type
Operating
Range
133 CY7C1371CV25-133AC
CY7C1373CV25-133AC
A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
CY7C1371CV25-133AI
CY7C1373CV25-133AI
A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
CY7C1371CV25-133BGC BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Commercial
CY7C1373CV25-133BGC
CY7C1371CV25-133BGI BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Industrial
CY7C1373CV25-133BGI
CY7C1371CV25-133BZC BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
Commercial
CY7C1373CV25-133BZC
CY7C1371CV25-133BZI BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
Industrial
CY7C1373CV25-133BZI
117 CY7C1371CV25-117AC
CY7C1373CV25-117AC
A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
CY7C1371CV25-117AI
CY7C1373CV25-117AI
A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
CY7C1371CV25-117BGC BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Commercial
CY7C1373CV25-117BGC
CY7C1371CV25-117BGI BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Industrial
CY7C1373CV25-117BGI
CY7C1371CV25-117BZC BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
Commercial
CY7C1373CV25-117BZC
CY7C1371CV25-117BZI BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
Industrial
CY7C1373CV25-117BZI
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 27 of 31
100 CY7C1371CV25-100AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
3 Chip Enables
Commercial
CY7C1373CV25-100AC
CY7C1371CV25-100AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)
3 Chip Enables
Industrial
CY7C1373CV25-100AI
CY7C1371CV25-100BGC BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Commercial
CY7C1373CV25-100BGC
CY7C1371CV25-100BG BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Industrial
ICY7C1373C-100BGI
CY7C1371CV25-100BZC BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2 mm)
3 Chip Enables and JTAG
Commercial
CY7C1373CV25-100BGC
CY7C1371CV25-100BZI BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2 mm)
3 Chip Enables and JTAG
Industrial
CY7C1373CV25-100BGI
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.
Ordering Information
Speed
(MHz) Ordering Code
Package
Name Part and Package Type
Operating
Range
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 28 of 31
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
DIMENSIONS ARE IN MILLIMETERS.
0.30±0.08
0.65
20.00±0.10
22.00±0.20
1.40±0.05
12°±1°
1.60 MAX.
0.05 MIN.
0.60±0.15
0° MIN.
0.25
0°-7°
(8X)
STAND-OFF
R 0.08 MIN.
TYP.
0.20 MAX.
0.15 MAX.
0.20 MAX.
R0.08MIN.
0.20 MAX.
14.00±0.10
16.00±0.20
0.10
SEE DETAIL A
DETAIL A
1
100
30
31 50
51
80
81
GAUGE PLANE
1.00 REF.
0.20 MIN.
SEATING PLANE
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 29 of 31
Package Diagrams (continued)
51-85115-*B
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 30 of 31
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
CY7C1371CV25
CY7C1373CV25
Document #: 38-05236 Rev. *B Page 31 of 31
Document History Page
Document Title: CY7C1371CV25/CY7C1373CV25 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
with NoBL™ Architecture
Document Number: 38-05236
REV. ECN NO. Issue Date
Orig. of
Change Description of Change
** 116276 08/05/02 SKX New Data Sheet
*A 121539 11/21/02 DSG Updated package diagram 51-85115 (BG119) to rev. *B
*B 206100 see ECN RKF Final Data Sheet