Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. E
11/10/08
IS24C01B IS24C02B
IS24C01B/02B
2-WIRE (I2C)
1K-bit/2K-bit
SERIAL EEPROM
2 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/10/08
IS24C01B IS24C02B
TABLE OF CONTENTS
Features ……………………………………………………….…………….................3
Description ………………………………………………...……………….................3
Functional Block Diagram ……………………………………………….................4
Pin Configuration & Description ………………………………………..................5
Device Operations …..…………………………………………………….................6
Absolute Maximum Ratings ……………………………………………..................14
DC Characteristics ………………………………………………………...................14
AC Characteristics ………………………………………………………...................15
Ordering Information ……………………………………………………...................16
Packaging Information ….………………………………………………...................17
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev. E
11/10/08
IS24C01B IS24C02B
1K-bit/2K-bit
2-WIRE SERIAL CMOS EEPROM
DESCRIPTION
The IS24C01B and IS24C02B are EEPROM de-
vices that use the industrial standard 2-wire, I2C,
interface for communications. The IS24C01B and
IS24C02B contain a memory array of 1K-bits (128
x 8) and 2K-bits (256 x 8), respectively. Each de-
vice is organized into 8 byte pages for page write
mode.
This EEPROM operates in a wide voltage range of
1.8V to 5.5V to be compatible with most applica-
tion voltages. ISSI designed this device family to
be a practical, low-power 2-wire EEPROM solution.
The devices are offered in lead-free, RoHS, halo-
gen free or Green. The available package types are
8-pin SOIC, TSSOP, PDIP, DFN, and CSP.
The IS24C01B/02B maintains compatibility with
the popular 2-wire bus protocol, so it is easy to
use in applications implementing this bus type.
The simple bus consists of the Serial Clock wire
(SCL) and the Serial Data wire (SDA). Using the
bus, a Master device such as a microcontroller is
usually connected to one or more Slave devices
such as this device. The bit stream over the SDA
line includes a series of bytes, which identifies a
particular Slave device, an instruction, an address
within that Slave device, and a series of data, if ap-
propriate. The IS24C01B/02B has a
Write Protect pin (WP) to allow blocking of any
write instruction transmitted over the bus.
FEATURES
• Two-WireSerialInterface,I2CTM compatible
– Bi-directional data transfer protocol
• WideVoltageOperation
– Vcc = 1.8V to 5.5V
• 400KHz(2.5V)and1MHz(5.0V)compatibility
• LowPower
– Standby Current: 1 µA or less (1.8V)
– Read Current: 2 mA or less (5.0V)
– Write Current: 3 mA or less (5.0V)
• HardwareDataProtection
– Write Protect Pin
• SequentialReadFeature
• FilteredInputsforNoiseSuppression
• Selftimewritecyclewithautoclear
5 ms max. @ 2.5V
• MemoryOrganization:
– IS24C01B: 128x8 (1K bits)
– IS24C02B: 256x8 (2K bits)
• 8-BytePageWriteBuffer
• HighReliability
– Endurance: 1,000,000 Cycles
– Data Retention: 100 Years
• Industrialtemperaturegrade
• Packages:SOIC/SOP,TSSOP,PDIP,DFN,and
CSP
Copyright © 2008 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specication and its products at any time without
notice. ISSI products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equip-
ment, aerospace systems, or for other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best
performance and optimization on the functionality and etc. ISSI assumes no liability arising out of the application or use of any information, products or services described
herein. Customers are advised to obtain the latest version of this device specication before relying on any published information and prior placing orders for products.
4 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/10/08
IS24C01B IS24C02B
>
CONTROL
LOGIC
X
DECODER
SLAVE ADDRESS
REGISTER &
COMPARATOR
WORD ADDRESS
COUNTER
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
EEPROM
ARRAY
Y
DECODER
DATA
REGISTER
Clock
DI/O
ACK
8
5
6
7
4
GND
WP
SCL
SDA
Vcc
nMOS
1
2
3
A2
A1
A0
FUNCTIONAL BLOCK DIAGRAM
Integrated Silicon Solution, Inc. — www.issi.com 5
Rev. E
11/10/08
IS24C01B IS24C02B
SCL
This input clock pin is used to synchronize the data transfer
to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wire-Or'ed with other open drain or
open collector outputs. The SDA bus requires a pullup resistor
to Vcc.
PIN CONFIGURATION
8-Pin SOIC, TSSOP, PDIP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
PIN DESCRIPTIONS
A0-A2 Address Inputs
SDA Serial Address/Data I/O
SCL Serial Clock Input
WP Write Protect Input
Vcc Power Supply
GND Ground
A0, A1, A2
The A0, A1 and A2 are the device address inputs. The
IS24C01B/02B uses the A0, A1, and A2 for hardware addressing
and a total of 8 devices may be used on a single bus system.
When the A0, A1, or A2 inputs are left floating, the input
internally defaults to zero.
WP
WP is the Write Protect pin. If the WP pin is tied to Vc c on
the EEPROM, the entire array becomes Write Protected
(Read only). When WP is tied to GND or left floating normal
read/write operations are allowed to the device.
8-pad DFN
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
(Top View)
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/10/08
IS24C01B IS24C02B
DEVICE OPERATION
IS24C01B/02B features serial communication and
supports a bi-directional 2-wire bus transmission protocol
called I2CTM.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and
the receiving devices as receivers. The bus is controlled
by Master device that generates the SCL, controls the bus
access, and generates the Stop and Start conditions. The
IS24C01B/02B is the Slave device on the bus.
The Bus Protocol:
– Data transfer may be initiated only when the bus is not
busy
– During a data transfer, the SDA line must remain stable
whenever the SCL line is high. Any changes in the SDA
line while the SCL line is high will be interpreted as a
Start or Stop condition.
The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of
the High period of the clock signal. The data on the SDA
line may be changed during the Low period of the clock
signal. There is one clock pulse per bit of data. Each data
transfer is initiated with a Start condition and terminated
with a Stop condition.
Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when
SCL is High. The EEPROM monitors the SDA and SCL
lines and will not respond until the Start condition is met.
Stop Condition
The Stop condition is defined as a Low to High transition
of SDA when SCL is High. All operations must end with
a Stop condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is
requiredtogenerateanACK. TheAcknowledgingdevice
pulls down the SDA line.
Reset
The IS24C01B/02B contains a reset function in case the
2-wire bus transmission is accidentally interrupted (eg. a
power loss), or needs to be terminated mid-stream. The
reset is caused when the Master device creates a Start
condition. To do this, it may be necessary for the Master
device to monitor the SDA line while cycling the SCL up
to nine times. (For each clock signal transition to High,
the Master checks for a High level on SDA.)
Standby Mode
Power consumption is reduced in standby mode. The
IS24C01B/02B will enter standby mode: a) At Power-up,
and remain in it until SCL or SDA toggles; b) Following the
Stop signal if a no write operation is initiated; or c) Following
any internal write operation.
Integrated Silicon Solution, Inc. — www.issi.com 7
Rev. E
11/10/08
IS24C01B IS24C02B
Page Write
The IS24C01B/02B is capable of 8-byte Page-Write
operation. A Page-Write is initiated in the same manner as
a Byte Write, but instead of terminating the internal Write
cycle after the first data word is transferred, the Master
device can transmit up to 7 more bytes. After the receipt of
each data word, the EEPROM responds immediately with
an ACK on SDA line, and the three lower order data word
address bits are internally incremented by one, while the
higher order bits of the data word address remain constant.
If a byte address is incremented from the last byte of a
page, it returns to the first byte of that page. If the Master
device should transmit more than 8 bytes prior to issuing
the Stop condition, the address counter will “roll over,” and
the previously written data will be overwritten. Once all 8
bytes are received and the Stop condition has been sent by
the Master, the internal programming cycle begins. At this
point, all received data is written to the IS24C01B/02B in a
single Write cycle. All inputs are disabled until completion
of the internal Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage
of the typical Write cycle time. Once the Stop condition
is issued to indicate the end of the host's Write operation,
the IS24C01B/02B initiates the internal Write cycle. ACK
polling can be initiated immediately. This involves issuing
the Start condition followed by the Slave address for a
Write operation. If the EEPROM is still busy with the Write
operation, no ACK will be returned. If the IS24C01B/02B
has completed the Write operation, an ACK will be returned
and the host can then proceed with the next Read or Write
operation.
WRITE OPERATION
Byte Write
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends the byte address that is to be
written into the address pointer of the IS24C01B/02B. After
receiving another ACK from the Slave, the Master device
transmits the data byte to be written into the address
memory location. The IS24C01B/02B acknowledges
once more and the Master generates the Stop condition,
at which time the device begins its internal programming
cycle. While this internal cycle is in progress, the device
willnotrespondtoanyrequestfromtheMasterdevice.
DEVICE ADDRESSING
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particularSlavedevicesitisrequesting.TheSlavedevice
(Fig. 5) address is 8 bits.
The four most significant bits of the Slave device address
are fixed as 1010 for the IS24C01B/02B.
The next three bits of the Slave address are specific for
each of the EEPROM. The bit values enable access to
multiple memory blocks or multiple devices.
The IS24C01B/02B uses the three bits A0, A1, and A2 in
a comparison with the hard-wired input values on the A0,
A1, and A2 pins. Up to eight units may share the 2-wire
bus.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master transmits the Start condition and Slave
address byte (Fig. 5), the appropriate 2-wire Slave (eg.
IS24C02B) will respond with ACK on the SDA line. The
Slave will pull down the SDA on the ninth clock cycle,
signaling that it received the eight bits of data. The selected
EEPROM then prepares for a Read or Write operation by
monitoring the bus.
8 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/10/08
IS24C01B IS24C02B
READ OPERATION
Read operations are initiated in the same manner as
Write operations, except that the (R/W) bit of the Slave
address is set to “1”. There are three Read operation
options: current address read, random address read and
sequentialread.
Current Address Read
The IS24C01B/02B contains an internal address counter
which maintains the address of the last byte accessed,
incremented by one. For example, if the previous operation
is either a Read or Write operation addressed to the
address location n, the internal address counter would
increment to address location n+1. When the EEPROM
receives the Slave Addressing Byte with a Read operation
(R/W bit set to “1”), it will respond an ACK and transmit the
8-bit data byte stored at address location n+1. The Master
should not acknowledge the transfer but should generate
a Stop condition so the IS24C01B/02B discontinues
transmission. If 'n' is the last byte of the memory, the
data from location '0' will be transmitted. (Refer to Figure
8. Current Address Read Diagram.)
Random Address Read
Selective Read operations allow the Master device to select
at random any memory location for a Read operation. The
Master device first performs a 'dummy' Write operation by
sending the Start condition, Slave address and byte address
of the location it wishes to read. After the IS24C01B/02B
acknowledges the byte address, the Master device resends
the Start condition and the Slave address, this time with
the R/W bit set to one. The EEPROM then responds
withitsACKandsendsthedatarequested. TheMaster
device does not send an ACK but will generate a Stop
condition. (Refer to Figure 9. Random Address Read
Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
IS24C01B/02Bsendstheinitialbytesequence,theMaster
devicenowrespondswithanACK,indicatingitrequires
additional data from the IS24C01B/02B. The EEPROM
continues to output data for each ACK received. The
MasterdeviceterminatesthesequentialReadoperation
by pulling SDA High (no ACK) indicating the last data word
to be read, followed by a Stop condition.
Thedataoutputissequential,withthedatafromaddress
n followed by the data from address n+1,n+2 ... etc. The
address counter increments by one automatically, allowing
the entire memory contents to be serially read during
sequentialRead operation. Whenthememory address
boundary of 127 or 255 (depending on the device) is
reached, the address counter “rolls over” to address 0,
and the device continues to output data. (Refer to Figure
10.SequentialReadDiagram).
Integrated Silicon Solution, Inc. — www.issi.com 9
Rev. E
11/10/08
IS24C01B IS24C02B
STOP
Condition
SCL
SDA
START
Condition
FIGURE 3. START AND STOP CONDITIONS
SCL
SDA
Master
Transmitter/
Receiver
IS24Cxx
Vcc
FIGURE 1. TYPICAL SYSTEM BUS CONFIGURATION
tAA
Data Output
from
Transmitter
SCL from
Master
Data Output
from
Receiver
189
ACK
tAA
FIGURE 2. OUTPUT ACKNOWLEDGE
10 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/10/08
IS24C01B IS24C02B
FIGURE 5. SLAVE ADDRESS
FIGURE 4. DATA VALIDITY PROTOCOL
SCL
SDA
Data Stable Data Stable
Data Change
FIGURE 6. BYTE WRITE
SDA
Bus
Activity
S
T
A
R
T
M
S
B
L
S
B
M
S
B
W
R
I
T
E
S
T
O
P
R/W
A
C
K
A
C
K
A
C
K
Data
Device
Address Byte Address
*
7BIT 4 3 1256 0
R/W
A0A1A2
0101
* = Don't care bit for IS24C01B
Integrated Silicon Solution, Inc. — www.issi.com 11
Rev. E
11/10/08
IS24C01B IS24C02B
FIGURE 9. RANDOM ADDRESS READ
SDA
Bus
Activity
A
C
K
A
C
K
A
C
K
Data n
Byte
Address (n)
Device
Address
DUMMY WRITE
Device
Address
S
T
A
R
T
W
R
I
T
E
R
E
A
D
S
T
A
R
T
S
T
O
P
M
S
B
L
S
B
N
O
A
C
K
R/W
*
FIGURE 7. PAGE WRITE
SDA
Bus
Activity
S
T
A
R
T
M
S
B
L
S
B
W
R
I
T
E
A
C
K
A
C
K
A
C
K
A
C
K
Data (n+1) Data (n)
Byte Address (n)
Device
Address
S
T
O
P
A
C
K
Data (n+7)
R/W
*
FIGURE 8. CURRENT ADDRESS READ
SDA
Bus
Activity
S
T
A
R
T
M
S
B
L
S
B
N
O
A
C
K
R
E
A
D
S
T
O
P
A
C
K
Data
Device
Address
R/W
* = Don't care bit for IS24C01B
* = Don't care bit for IS24C01B
12 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/10/08
IS24C01B IS24C02B
FIGURE 10. SEQUENTIAL READ
S
T
O
P
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data Byte n+XData Byte n+1Data Byte n Data Byte n+2
R/W
SDA
Bus
Activity
Device
Address
R
E
A
D
Integrated Silicon Solution, Inc. — www.issi.com 13
Rev. E
11/10/08
IS24C01B IS24C02B
AC WAVEFORMS
Figure 11. Bus Timing
t
SU:STA
t
F
t
HIGH
t
LOW
t
R
t
SU:STO
t
BUF
t
DH
t
AA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
IN
SDA
OUT
t
SU:WP
t
HD:WP
WP
8th BIT ACK
WORD n
STOP
Condition
START
Condition
tWR
SCL
SDA
Figure 12. Write Cycle Timing
14 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/10/08
IS24C01B IS24C02B
DC ELECTRICAL CHARACTERISTICS
Industrial (Ta = -40oC to +85oC)
Symbol Parameter Test Conditions Min. Max. Unit
Vo l 1 Output Low Voltage Vc c = 1.8V, Io l = 0.15 mA — 0.2 V
Vo l 2 Output Low Voltage Vc c = 2.5V, Io l = 3 mA — 0.4 V
VI h Input High Voltage Vc c x 0.7 Vc c + 0.5 V
VI l Input Low Voltage –1.0 Vc c x 0.3 V
Il I Input Leakage Current VI n = Vc c max. — 3 µA
Il o Output Leakage Current — 3 µA
Notes: VI l min and VI h max are reference only and are not tested.
POWER SUPPLY CHARACTERISTICS
Industrial (Ta = -40oC to +85oC)
Symbol Parameter Test Conditions Min. Max. Unit
Ic c 1 Operating Current Read at 400 KHz (Vcc = 5V) — 2.0 mA
Ic c 2 Operating Current Write at 400 KHz (Vcc = 5V) — 3.0 mA
Is b 1 Standby Current Vcc = 1.8V — 1 µA
Is b 2 Standby Current Vcc = 2.5V — 2 µA
Is b 3 Standby Current Vcc = 5.0V — 6 µA
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
Vs Supply Voltage –0.5 to +6.5 V
Vp Voltage on Any Pin –0.5 to Vcc + 0.5 V
Tb I a s Temperature Under Bias –55 to +125 °C
Ts T g Storage Temperature –65 to +150 °C
Io u T Output Current 5 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause per-
manent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
cI n Input Capacitance VI n = 0V 6 pF
co u T Output Capacitance Vo u T = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
a = 25°c, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. — www.issi.com 15
Rev. E
11/10/08
IS24C01B IS24C02B
AC ELECTRICAL CHARACTERISTICS
Industrial (Ta = -40oC to +85oC)
1.8V ≤ Vcc < 2.5V
2.5V ≤ Vcc < 4.5V
4.5V ≤ Vcc ≤ 5.5V
(1)
Symbol Parameter
(2)
Min. Max. Min. Max. Min. Max. Unit
fs c l SCLClockFrequency 0 100 0 400 0 1000 KHz
T
Noise Suppression Time
(1)
— 100 — 50 — 50 ns
tl o w
Clock Low Period 4.7 — 1.2 — 0.6 — µs
th I g h Clock High Period 4 — 0.6 — 0.4 — µs
tb u f
Bus Free Time Before New Transmission
(1)
4.7 — 1.2 — 0.5 — µs
ts u :s T a Start Condition Setup Time 4 — 0.6 — 0.25 — µs
ts u :s T o Stop Condition Setup Time 4 — 0.6 — 0.25 — µs
th d :s T a
Start Condition Hold Time 4 — 0.6 — 0.25 — µs
th d :s T o
Stop Condition Hold Time 4 — 0.6 — 0.25 — µs
ts u :d a T
Data In Setup Time 100 — 100 — 100 — ns
th d :d a T
Data In Hold Time 0 — 0 — 0 — ns
ts u :w p WP pin Setup Time 4 — 0.6 — 0.6 — µs
th d :w p WP pin Hold Time 4.7 — 1.2 — 1.2 — µs
td h
Data Out Hold Time 100 — 50 — 50 — ns
(SCL Low to SDA Data Out Change)
ta a
Clock to Output 100 3500 50 900 50 400 ns
(SCL Low to SDA Data Out Valid)
tr
SCL and SDA Rise Time
(1)
— 1000 — 300 — 300 ns
tf
SCL and SDA Fall Time
(1)
— 300 — 300 — 100 ns
tw r
Write Cycle Time — 10 — 5 — 5 ms
Note:
1. This parameter is characterized but not 100% tested.
2. The timing is referenced to half Vcc level.
16 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/10/08
IS24C01B IS24C02B
ORDERING INFORMATION
Industrial Range*: –40°C to +85°C
Voltage Range Part Number* Package Type* (8-pin)
1.8V to 5.5V IS24C01B-2GLI 150-mil SOIC (JEDEC)
IS24C01B-2ZLI 3 x 4.4 mm TSSOP
IS24C01B-2PLI 300-mil PDIP
IS24C01B-2CLI CSP
1.8V to 5.5V IS24C02B-2GLI 150-mil SOIC (JEDEC)
IS24C02B-2ZLI 3 x 4.4 mm TSSOP
IS24C02B-2PLI 300-mil PDIP
IS24C02B-2DLI-TR 2 x 3 mm DFN
IS24C02B-2CLI CSP
*
1. Contact ISSI Sales Representatives for availability and other information.
2. Most listed part numbers are packed in tube, except DFN. DFN is only offered in “-TR”.
3. For tape and reel, add “-TR” at the end of the P/N.
4. Refer to ISSI website for related declaration document on lead free, RoHS, halogen free, or Green, whichever is applicable.
5. ISSI offers Industrial grade for Commercial applications (0oC to +70oC).
Integrated Silicon Solution, Inc. — www.issi.com 17
Rev. E
11/10/08
IS24C01B IS24C02B
18 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/10/08
IS24C01B IS24C02B
Thin Shrink Small Outline TSSOP
Package Code: Z (8 pin, 14 pin)
Rev B 02/01/02
TSSOP (Z)
Ref. Std. JEDEC MO-153
No. Leads 8
Millimeters Inches
Symbol Min Max Min Max
A — 1.20 — 0.047
A1 0.05 0.15 0.002 0.006
A2 0.80 1.05 0.032 0.041
B 0.19 0.30 0.007 0.012
C 0.09 0.20 0.004 0.008
D 2.90 3.10 0.114 0.122
E1 4.30 4.50 0.169 0.177
E 6.40 BSC 0.252 BSC
e 0.65 BSC 0.026 BSC
L 0.45 0.75 0.018 0.030
α—8° —8°
TSSOP (Z)
Ref. Std. JEDEC MO-153
No. Leads 14
Millimeters Inches
Symbol Min Max Min Max
A — 1.20 — 0.047
A1 0.05 0.15 0.002 0.006
A2 0.80 1.05 0.031 0.041
B 0.19 0.30 0.007 0.012
C 0.09 0.20 0.0035 0.008
D 4.90 5.10 0.193 0.201
E1 4.30 4.50 0.170 0.177
E 6.40 BSC 0.252 BSC
e 0.65 BSC 0.026 BSC
L 0.45 0.75 0.0177 0.0295
α—8° — 8°
D
B
e
E1
A2
E
C
A
A1 L
α
1
N
N/2
Integrated Silicon Solution, Inc. — www.issi.com 19
Rev. E
11/10/08
IS24C01B IS24C02B
300-mil Plastic DIP
Package Code: N,P
A
D
1
B
N
SEATING PLANE
C
A1
eA
L
e
B1S
E1
E
S
FOR
32-PIN ONLY B2
MILLIMETERS INCHES
Sym. Min. Max. Min. Max.
N0.
Leads 8
A
3.68
4.57
0.145
0.180
A1
0.38
—
0.015
—
B
0.36
0.56
0.014
0.022
B1
1.14
1.52
0.045
0.060
B2
0.81
1.17
0.032
0.046
C
0.20
0.33
0.008
0.013
D
9.12 9.53 0.359 0.375
E
7.62 8.26 0.300 0.325
E1 6.20 6.60 0.244 0.260
eA8.13 9.65 0.320 0.380
e 2.54 BSC 0.100 BSC
L 3.18 —0.125 —
S 0.64 0.762 0.025 0.030
Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and
should
be measured from the bottom of the package
.
4. Formed leads shall be planar with respect to one another within 0.004
inches at the seating plane.
20 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/10/08
IS24C01B IS24C02B
Dual Flat No-Lead
Package Code: D (8-pad)
A2
A2
b
(8X)
(8X)
A1
A3
A3
D
E
A
L (8X)
L (8X)
e (6X)
e (6X)
1.50 REF.
1.50 REF.
D2
D2
E2
Pad 1 ID
Pad 1 index area
tie bars
(3)
Notes:
1. Refer to JEDEC Drawing MO-229.
2. This is the metallized terminal and
is measured between 0.18 mm
and 0.30 mm from the terminal tip.
The terminal may have a straight
end instead of rounded.
3. Package may have exposed tie
bars, ending flush with package
edge.
DFN
MILLIMETERS
Sym. Min. Nom. Max.
N0.
Pad 8
D 2.00 BSC
E 3.00 BSC
D2 1.50 — 1.75
E2 1.60 — 1.90
A 0.70 0.75 0.80
A1 0.0 0.02 0.05
A2 — — 0.75
A3 0.20 REF
L 0.30 0.40 0.50
e 0.50 BSC
b 0.18 0.25 0.30
