HD64F2623FA20J - Renesas Electronics

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please

confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to

additional and different information to be disclose d by Renesa s Electronics such as that disclosed through our website.

2. Renesas Electronics does not assum e any liability for inf ringement of patents, co pyrights, or other int ellectual property rights

of third parties by or arising from the use of Renesas Elec tronics products or technical information described in this document.

No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights

of Renesas Electronics or others.

3. You should not alter, m odify, copy, or otherw ise misappropriate an y Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of

semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,

and information in the design of your equipment. Renesas Electronics assumes no responsi bility for any losse s incurred by

you or third parties arising from the use of these circuits, software, or information.

5. When exporting the products or technol ogy described in this document, you should comply with the applicable export control

laws and regulations and follow the procedures required by such law s and regulations. You should not use Renesas

Electronics products or the technology described in this docum ent for any purpose rela ting to military applications or use by

the military, including but not limited to the developm ent of weapons of ma ss destruction. Renesas Electronics products and

technology may not be used for or incor porated into any products or system s whose manufac ture, use, or sale is prohibited

under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in prepa ring the information included in this document, but Renesas Electronics

does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages

incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and

“Specific”. The recom mended applicatio ns for each Renesas Electronics prod uct depends on the produc t’s quality grade, as

indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular

application. You may not use any Renesas Elec tronics product for any application cate gorized as “Spec ific” without the prior

written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any applic ation for

which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way

liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an

application categorized as “Specific” or for which the product is not intende d where you have failed to obtain the prior written

consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise

expressly specified in a Renesas Electronics data sheets or data books, etc.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

equipment; home electronic appli ances; mac hine tools; personal electronic equipm ent; and industrial robots.

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-

crime systems; safety equipment; and medical equipment not specifically designed for life support.

“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or

systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare

intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,

especially with respect to the m aximum rating , opera ting supply voltag e range, movement power voltage ra nge, heat radiation

characteristics, installation and other product characteristic s. Re nesas Electronics shall have no liabil ity for malfunctions or

damages arising out of the use of Re nesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliabili ty of its products, semiconductor products have

specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,

Renesas Electronics products are not subject to radiation res istance design. Pleas e be sure to implement saf ety measures to

guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a

Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire

control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because

the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system

manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental

compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable

laws and regulations that regulate the inclusion or use of controlled substa nces, including without lim itation, the EU R oHS

Directive. Renesas Electronics assum es no liability for damage s or losses occurring as a result of your noncom pliance with

applicable laws and regulatio ns.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas

Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions re garding the information conta ined in this

document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-

owned subsidiaries.

(Note 2) “Re nesas Electronics produc t(s)” means any product develope d or manufactured by or for Re nesas Electronics.

H8S/2600 Series,

H8S/2000 Series

Software Manual

User’s Manual

Rev.4.00 2006.02

Renesas 16-Bit Single-Chip

Microcomputer

H8S Family

Rev. 4.00 Feb 24, 2006 page ii of xiv

1. These materials are intended as a reference to assist our customers in the selection of the Renesas

Technology Corp. product best suited to the customer's application; they do not convey any license

under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or

a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-

party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or

circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and

algorithms represents information on products at the time of publication of these materials, and are

subject to change by Renesas Technology Corp. without notice due to product improvements or

other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or

an authorized Renesas Technology Corp. product distributor for the latest product information

before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising

from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corp. by various means,

including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,

diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total

system before making a final decision on the applicability of the information and products. Renesas

Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the

information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or

system that is used under circumstances in which human life is potentially at stake. Please contact

Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when

considering the use of a product contained herein for any specific purposes, such as apparatus or

systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in

whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must

be exported under a license from the Japanese government and cannot be imported into a country

other than the approved destination.

Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the

country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products

contained therein.

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and

more reliable, but there is always the possibility that trouble may occur with them. Trouble with

semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate

measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or

(iii) prevention against any malfunction or mishap.

Keep safety first in your circuit designs!

Notes regarding these materials

Rev. 4.00 Feb 24, 2006 page iii of xiv

Preface

The H8S/2600 Series and the H8S/2000 Series are built around an H8S/2000 CPU core.

The H8S/2600 and H8S/2000 CPUs have the same internal 32-bit architecture. Both CPUs

execute basic instructions in one state, have sixteen 16-bit registers, and have a concise, optimized

instruction set. They can address a 16-Mbyte linear address space.Programs coded in the high-

level language C can be compiled to high-sp eed executable code.

For easy migration, the instruction set is upward-compatible with the H8/300H, H8/300, and

H8/300L Series at the object-code level.

The H8S/2600 CPU is upward-compatible with the H8S/2000 CPU at the object-code level, and

supports sum of products instructions.

This manual gives details of the H8S/2600 and H8S/2000 instructions and can be sued with all

microcontrollers in the H8S/2600 Series and the H8S/2000 Series.

For hard war e details, r ef e r to the r e levant microcontroller hard war e manuals.

Rev. 4.00 Feb 24, 2006 page iv of xiv

Rev. 4.00 Feb 24, 2006 page v of xiv

Main Revisions for This Edition

Item Page Revisions (See Manual for Details)

1.1.1 Features 2 Note * added

— Maximum clock frequency: 20 MHz*

Note: * The maximum operating frequency and instruction

execution time differ depending on the product.

2.2.22 CLRMAC

Operand Format and

Number of States

Required for Execution

90 Further explanation added to note

The number of states may differ depending on the prod uct.

For details, refer to the hardware manual of the product in

question.

2.2.24 DAA

Description 94 Table amended

C Flag

before

Adjustment

Upper 4 Bits

before

Adjustment

H Flag

before

Adjustment

Lower 4 Bits

before

Adjustment

Value

Added

(Hexadecimal)

C Flag

after

Adjustment

0 A to F 1 0 to 3 66 1

10 to 2 0 0 to 9 60 1

10 to 2 0 A to F 66 1

10 to 3 1 0 to 3 6 6 1

2.2.37 LDMAC

Operand Format and

Number of States

Required for Execution

130

2.2.42 (1) MULXS (B)

Operand Format and

Number of States

Required for Execution

151

Further explanation added to note

The number of states may differ depending on the prod uct.

For details, refer to the hardware manual of the product in

question.

2.2.42 (2) MULXS (W)

Operand Format and

Number of States

Required for Execution

152

2.2.43 (1) MULXU (B)

Operand Format and

Number of States

Required for Execution

153

2.2.43 (2) MULXU (W)

Operand Format and

Number of States

Required for Execution

154

Rev. 4.00 Feb 24, 2006 page vi of xiv

Item Page Revisions (See Manual for Details)

2.2.64 STMAC

Operand Format and

Number of States

Required for Execution

232 Table amended

Instruction Format

1st byte 2nd byte 3rd byte 4th byte

0220erd

0230erd

Further explanation added to note

The number of states may differ depending on the prod uct.

For details, refer to the hardware manual of the product in

question.

2.3 Instruction Set

Table 2.1 Instruction

Set

250,

251,

260,

262

Note 7 amended and note 10 added

Mnemonic

DAS DAS Rd 1

MULXU MULXU.B Rs,Rd 3 (12*7)

MULXU.W Rs,ERd 4 (20*7)

*4 *10

MULXS MULXS.B Rs,Rd 4 (13*7)

MULXS.W Rs,ERd 5 (21*7)

No. of

States*

Normal

Advanced

*5 *10

Mnemonic

MAC*

MAC @ERn+,@ERm+ 4

CLRMAC

CLRMAC 2*

LDMAC*

LDMAC ERs,MACH 2*

LDMAC ERs,MACL 2*

STMAC*

STMAC MACH,ERd 1*

STMAC MACL,ERd 1*

No. of

States*

Normal

Advanced

Mnemonic

No. of

States*

Normal

Advanced

TRAPA TRAPA #x:2 7[9] 8[9]

RTE RTE 5[9]

*7*7

Notes: 7. Values in parentheses ( ) are for the H8S/2000

CPU. Values in square brackets [ ] apply to interrupt control

modes 2 and 3.

10. The number of states may differ depending on the product.

For details, refer to the hardware manual of the product in

question.

Rev. 4.00 Feb 24, 2006 page vii of xiv

Item Page Revisions (See Manual for Details)

Note 6 added

Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

CLRMAC*

CLRMAC 1 1 *

2.6 Number of States

Required for Instruction

Execution

Table 2.5 Number of

Cycles in Instruction

Execution

283,

285,

286,

288

Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

LDMAC*5LDMAC E Rs,MACH 1 *3 *6

LDMAC ERs,MACL 1

1*3 *6

Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

MULXS MULXS.B Rs,Rd H8S/2600 2 *

H8S/2000 2 1

MULXS.W Rs,ERd H8S/2600 2 *

H8S/2000 2 9

MULXU MULXU.B Rs,Rd H8S/2600 1 *

H8S/2000 1 1

MULXU.W Rs,ERd H8S/2600 1 *

H8S/2000 1

Instruction

Fetch

Branch

Address

Read Stack

Operation Byte Data

Access Word Data

Access Internal

Operation

Instruction Mnemonic I J K L M N

STMAC*

STMAC MACH,ERd 1 0*

STMAC MACL,ERd 1 0*

Notes: 6. The number of states may differ depending on the

product. For details, refer to the hardware manual of the

product in question.

2.7 Bus States During

Instruction Execution 290 :M deleted from legend

Table 2.6 Instruction

Execution Cycles 293 to

302 All instances of :M deleted from table

3.3.5 Usage Notes 312,

313 Newly added

Rev. 4.00 Feb 24, 2006 page viii of xiv

Rev. 4.00 Feb 24, 2006 page ix of xiv

Contents

Section 1 CPU...................................................................................................................... 1

1.1 Overview........................................................................................................................... 1

1.1.1 Features................................................................................................................ 1

1.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 2

1.1.3 Differences from H8/300 CPU ............................................................................ 3

1.1.4 Differences from H8/300H CPU.......................................................................... 4

1.2 CPU Operating Modes...................................................................................................... 5

1.3 Address Space................................................................................................................... 10

1.4 Register Configuration...................................................................................................... 11

1.4.1 Overview.............................................................................................................. 11

1.4.2 General Registers................................................................................................. 12

1.4.3 Control Registers ................................................................................................. 13

1.4.4 Initial Register Values.......................................................................................... 15

1.5 Data Formats..................................................................................................................... 16

1.5.1 General Register Data Formats............................................................................ 16

1.5.2 Memory Data Formats......................................................................................... 18

1.6 Instruction Set................................................................................................................... 19

1.6.1 Overview.............................................................................................................. 19

1.6.2 Instructions and Addressing Modes..................................................................... 20

1.6.3 Table of Instructions Classified by Function....................................................... 22

1.6.4 Basic Instruction Formats.................................................................................... 32

1.7 Addressing Modes and Effective Address Calculation..................................................... 33

Section 2 Instruction Descriptions.................................................................................. 41

2.1 Tables and Symbols.......................................................................................................... 41

2.1.1 Assembly-Language Format................................................................................ 42

2.1.2 Operation ............................................................................................................. 43

2.1.3 Condition Code.................................................................................................... 44

2.1.4 Instruction Format................................................................................................ 44

2.1.5 Register Specification.......................................................................................... 45

2.1.6 Bit Data Access in Bit Manipulation Instructions................................................ 46

2.2 Instruction Descriptions.................................................................................................... 47

2.2.1 (1) ADD (B).......................................................................................................... 48

2.2.1 (2) ADD (W)......................................................................................................... 49

2.2.1 (3) ADD (L).......................................................................................................... 50

2.2.2 ADDS.............................................................................................................. 51

2.2.3 ADDX............................................................................................................. 52

2.2.4 (1) AND (B).......................................................................................................... 53

Rev. 4.00 Feb 24, 2006 page x of xiv

2.2.4 (2) AND (W)......................................................................................................... 54

2.2.4 (3) AND (L).......................................................................................................... 55

2.2.5 (1) ANDC ............................................................................................................. 56

2.2.5 (2) ANDC ............................................................................................................. 57

2.2.6 BAND ............................................................................................................. 58

2.2.7 Bcc .................................................................................................................. 60

2.2.8 BCLR.............................................................................................................. 62

2.2.9 BIAND............................................................................................................ 64

2.2.10 BILD ............................................................................................................... 66

2.2.11 BIOR............................................................................................................... 68

2.2.12 BIST................................................................................................................ 70

2.2.13 BIXOR............................................................................................................ 72

2.2.14 BLD................................................................................................................. 74

2.2.15 BNOT.............................................................................................................. 76

2.2.16 BOR ................................................................................................................ 78

2.2.17 BSET............................................................................................................... 80

2.2.18 BSR................................................................................................................. 82

2.2.19 BST ................................................................................................................. 84

2.2.20 BTST............................................................................................................... 86

2.2.21 BXOR.............................................................................................................. 88

2.2.22 CLRMAC........................................................................................................ 90

2.2.23 (1) CMP (B).......................................................................................................... 91

2.2.23 (2) CMP (W)......................................................................................................... 92

2.2.23 (3) CMP (L).......................................................................................................... 93

2.2.24 DAA................................................................................................................ 94

2.2.25 DAS................................................................................................................. 96

2.2.26 (1) DEC (B) .......................................................................................................... 98

2.2.26 (2) DEC (W) ......................................................................................................... 99

2.2.26 (3) DEC (L)........................................................................................................... 100

2.2.27 (1) DIVXS (B)...................................................................................................... 101

2.2.27 (2) DIVXS (W)..................................................................................................... 103

2.2.28 (1) DIVXU (B) ..................................................................................................... 105

2.2.28 (2) DIVXU (W) .................................................................................................... 107

2.2.29 (1) EEPMOV (B).................................................................................................. 109

2.2.29 (2) EEPMOV (W)................................................................................................. 110

2.2.30 (1) EXTS (W) ....................................................................................................... 112

2.2.30 (2) EXTS (L)......................................................................................................... 113

2.2.31 (1) EXTU (W)....................................................................................................... 114

2.2.31 (2) EXTU (L)........................................................................................................ 115

2.2.32 (1) INC (B) ........................................................................................................... 116

2.2.32 (2) INC (W) .......................................................................................................... 117

Rev. 4.00 Feb 24, 2006 page xi of xiv

2.2.32 (3) INC (L)............................................................................................................ 118

2.2.33 JMP ................................................................................................................. 119

2.2.34 JSR.................................................................................................................. 120

2.2.35 (1) LDC (B) .......................................................................................................... 122

2.2.35 (2) LDC (B) .......................................................................................................... 123

2.2.35 (3) LDC (W) ......................................................................................................... 124

2.2.35 (4) LDC (W) ......................................................................................................... 126

2.2.36 LDM................................................................................................................ 128

2.2.37 LDMAC.......................................................................................................... 130

2.2.38 MAC................................................................................................................ 131

2.2.39 (1) MOV (B)......................................................................................................... 134

2.2.39 (2) MOV (W)........................................................................................................ 135

2.2.39 (3) MOV (L) ......................................................................................................... 136

2.2.39 (4) MOV (B)......................................................................................................... 137

2.2.39 (5) MOV (W)........................................................................................................ 139

2.2.39 (6) MOV (L) ......................................................................................................... 141

2.2.39 (7) MOV (B)......................................................................................................... 143

2.2.39 (8) MOV (W)........................................................................................................ 145

2.2.39 (9) MOV (L) ......................................................................................................... 147

2.2.40 MOVFPE ........................................................................................................ 149

2.2.41 MOVTPE........................................................................................................ 150

2.2.42 (1) MULXS (B) .................................................................................................... 151

2.2.42 (2) MULXS (W) ................................................................................................... 152

2.2.43 (1) MULXU (B).................................................................................................... 153

2.2.43 (2) MULXU (W)................................................................................................... 154

2.2.44 (1) NEG (B).......................................................................................................... 155

2.2.44 (2) NEG (W)......................................................................................................... 156

2.2.44 (3) NEG (L) .......................................................................................................... 157

2.2.45 NOP................................................................................................................. 158

2.2.46 (1) NOT (B).......................................................................................................... 159

2.2.46 (2) NOT (W)......................................................................................................... 160

2.2.46 (3) NOT (L) .......................................................................................................... 161

2.2.47 (1) OR (B)............................................................................................................. 162

2.2.47 (2) OR (W)............................................................................................................ 163

2.2.47 (3) OR (L)............................................................................................................. 164

2.2.48 (1) ORC ................................................................................................................ 165

2.2.48 (2) ORC ................................................................................................................ 166

2.2.49 (1) POP (W).......................................................................................................... 167

2.2.49 (2) POP (L) ........................................................................................................... 168

2.2.50 (1) PUSH (W)....................................................................................................... 169

2.2.50 (2) PUSH (L) ........................................................................................................ 170

Rev. 4.00 Feb 24, 2006 page xii of xiv

2.2.51 (1) ROTL (B)........................................................................................................ 171

2.2.51 (2) ROTL (B)........................................................................................................ 172

2.2.51 (3) ROTL (W)....................................................................................................... 173

2.2.51 (4) ROTL (W)....................................................................................................... 174

2.2.51 (5) ROTL (L)........................................................................................................ 175

2.2.51 (6) ROTL (L)........................................................................................................ 176

2.2.52 (1) ROTR (B)........................................................................................................ 177

2.2.52 (2) ROTR (B)........................................................................................................ 178

2.2.52 (3) ROTR (W)....................................................................................................... 179

2.2.52 (4) ROTR (W)....................................................................................................... 180

2.2.52 (5) ROTR (L)........................................................................................................ 181

2.2.52 (6) ROTR (L)........................................................................................................ 182

2.2.53 (1) ROTXL (B)..................................................................................................... 183

2.2.53 (2) ROTXL (B)..................................................................................................... 184

2.2.53 (3) ROTXL (W).................................................................................................... 185

2.2.53 (4) ROTXL (W).................................................................................................... 186

2.2.53 (5) ROTXL (L) ..................................................................................................... 187

2.2.53 (6) ROTXL (L) ..................................................................................................... 188

2.2.54 (1) ROTXR (B)..................................................................................................... 189

2.2.54 (2) ROTXR (B)..................................................................................................... 190

2.2.54 (3) ROTXR (W).................................................................................................... 191

2.2.54 (4) ROTXR (W).................................................................................................... 192

2.2.54 (5) ROTXR (L)..................................................................................................... 193

2.2.54 (6) ROTXR (L)..................................................................................................... 194

2.2.55 RTE................................................................................................................. 195

2.2.56 RTS ................................................................................................................. 197

2.2.57 (1) SHAL (B)........................................................................................................ 198

2.2.57 (2) SHAL (B)........................................................................................................ 199

2.2.57 (3) SHAL (W)....................................................................................................... 200

2.2.57 (4) SHAL (W)....................................................................................................... 201

2.2.57 (5) SHAL (L)........................................................................................................ 202

2.2.57 (6) SHAL (L)........................................................................................................ 203

2.2.58 (1) SHAR (B)........................................................................................................ 204

2.2.58 (2) SHAR (B)........................................................................................................ 205

2.2.58 (3) SHAR (W) ....................................................................................................... 206

2.2.58 (4) SHAR (W) ....................................................................................................... 207

2.2.58 (5) SHAR (L)........................................................................................................ 208

2.2.58 (6) SHAR (L)........................................................................................................ 209

2.2.59 (1) SHLL (B) ........................................................................................................ 210

2.2.59 (2) SHLL (B) ........................................................................................................ 211

2.2.59 (3) SHLL (W) ....................................................................................................... 212

Rev. 4.00 Feb 24, 2006 page xiii of xiv

2.2.59 (4) SHLL (W) ....................................................................................................... 213

2.2.59 (5) SHLL (L)......................................................................................................... 214

2.2.59 (6) SHLL (L)......................................................................................................... 215

2.2.60 (1) SHLR (B)........................................................................................................ 216

2.2.60 (2) SHLR (B)........................................................................................................ 217

2.2.60 (3) SHLR (W)....................................................................................................... 218

2.2.60 (4) SHLR (W)....................................................................................................... 219

2.2.60 (5) SHLR (L) ........................................................................................................ 220

2.2.60 (6) SHLR (L) ........................................................................................................ 221

2.2.61 SLEEP............................................................................................................. 222

2.2.62 (1) STC (B)........................................................................................................... 223

2.2.62 (2) STC (B)........................................................................................................... 224

2.2.62 (3) STC (W).......................................................................................................... 225

2.2.62 (4) STC (W).......................................................................................................... 227

2.2.63 STM ................................................................................................................ 229

2.2.64 STMAC........................................................................................................... 231

2.2.65 (1) SUB (B)........................................................................................................... 233

2.2.65 (2) SUB (W) ......................................................................................................... 235

2.2.65 (3) SUB (L)........................................................................................................... 236

2.2.66 SUBS............................................................................................................... 237

2.2.67 SUBX.............................................................................................................. 238

2.2.68 TAS................................................................................................................. 239

2.2.69 TRAPA............................................................................................................ 240

2.2.70 (1) XOR (B).......................................................................................................... 242

2.2.70 (2) XOR (W)......................................................................................................... 243

2.2.70 (3) XOR (L).......................................................................................................... 244

2.2.71 (1) XORC.............................................................................................................. 245

2.2.71 (2) XORC.............................................................................................................. 246

2.3 Instruction Set................................................................................................................... 247

2.4 Instruction Code................................................................................................................ 263

2.5 Operation Code Map......................................................................................................... 274

2.6 Number of States Required for Instruction Execution...................................................... 278

2.7 Bus States During Instruction Execution.......................................................................... 290

2.8 Condition Code Modification ........................................................................................... 304

Section 3 Processing States .............................................................................................. 309

3.1 Overview........................................................................................................................... 309

3.2 Reset State......................................................................................................................... 310

3.3 Exception-Handling State................................................................................................. 311

3.3.1 Types of Exception Handling and Their Priority................................................. 311

3.3.2 Reset Exception Handling.................................................................................... 312

Rev. 4.00 Feb 24, 2006 page xiv of xiv

3.3.3 Trace.................................................................................................................... 312

3.3.4 Interrupt Exception Handling and Trap Instruction Exception Handling............ 312

3.3.5 Usage Notes......................................................................................................... 312

3.4 Program Execution State................................................................................................... 314

3.5 Bus-Released State............................................................................................................ 315

3.6 Power-Down State ............................................................................................................ 315

3.6.1 Sleep Mode.......................................................................................................... 315

3.6.2 Software Standby Mode....................................................................................... 315

3.6.3 Hardware Standby Mode ..................................................................................... 316

Section 4 Basic Timing...................................................................................................... 317

4.1 Overview........................................................................................................................... 317

4.2 On-Chip Memory (ROM, RAM)...................................................................................... 317

4.3 On-Chip Supporting Module Access Timing.................................................................... 319

4.4 External Address Space Access Timing............................................................................ 320

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 1 of 322

REJ09B0139-0400

Section 1 CPU

1.1 Overview

The H8S/2600 CPU and the H8S/2000 CPU are high-speed central processing units with a

common an intern al 32-bit architecture. Each CPU is upward-compatible with the H8/300 and

H8/300H CPUs. The H8S/2600 CPU and H8S/2000 CPU have sixteen 16-bit general registers,

can address a 4- Gbyte linear addr ess sp ace, and are ideal for realtime control.

1.1.1 Features

The H8S/2600 CPU and H8S/2000 CPU have the following features.

• Upward-compatible with H8 /300 and H8/300H CPUs

 Can execute H8/300 and H8/300 H object programs

• General-register architecture

 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit

registers)

• Sixty-nine basic instructions (H8S/2000 CPU has sixty-five)

 8/16/32-b it ar ithmetic and logic in str uctions

 Multiply and divide instructio ns

 Powerful bit-manipulation instructions

 Multiply-and-accumulate instruction (H8S/2600 CPU only)

• Eight addressing modes

 Register direct [Rn]

 Register indirect [@ERn]

 Register indirect with displacement [@(d:16,ERn) or @( d:32,ERn)]

 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]

 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]

 Immediate [#xx:8, #xx: 16, or #xx: 3 2]

 Program-counter relative [@(d:8,PC) or @(d:16,PC)]

 Memory indirect [@@aa:8]

• 4-Gbyte address space

 Program: 16 Mbytes

 Data: 4 Gb ytes

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 2 of 322

REJ09B0139-0400

• High-speed operation

 All frequently-u sed instructions execute in one or two states

 Maximum clock frequency: 20 MHz*

 8/16/32-bit register-register add/subtract: 50 ns

 8 × 8-bit register-register multiply: 150 ns (H8S/2000 CPU: 600 ns)

 16 ÷ 8-bit register-register divide: 600 ns

 16 × 16-bit register-register multiply: 200 ns (H8S/2000 CPU: 1000 ns)

 32 ÷ 16-bit regis t er-regis t er divide: 1000 ns

• Two CPU operating modes

 Normal mode

 Advanced mode

• Power-down modes

 Transition to power-down state by SLEEP instruction

 CPU clock speed selection

Note: * The maximum operating frequency and instruction execution time differ depending on

the product.

1.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU

Differences between the H8S/2600 CPU and the H8S/2000 CPU are as follows.

• Register configuration

 The MAC register is supported only by the H8S/2600 CPU.

For details, see section 1.4, Register Configuration.

• Basic instructions

 The MAC, CLRMAC, LDMAC, and STMAC instructions are supported only by the

H8S/2600 CPU.

For details, see section 1.6, Instruction Set, and Section 2, Instruction Descriptions.

• Number of states required for execution

 The number of states required for execution of the MULXU and MULXS instructions.

For details, see section 2.6, Number of States Required for Execution.

In addition, there may be defferences in address spaces, EXR register fu nctions, power-down

states, and so on. For details, refer to th e relevant microcontroller hardware manual.

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 3 of 322

REJ09B0139-0400

1.1.3 Differences from H8/300 CPU

In comparison with the H8/300 CPU, the H8S/2600 CPU and H8S/2000 CPU have the following

enhancements.

• More general registers and control registers

 Eight 16-bit registers, one 8-bit and two 32-bit control registers have been added.

• Expanded address space

 Normal mode supports the same 64-kbyte address space as the H8/300 CPU.

 Advanced mode supports a maximum 4-Gbyte address space.

• Enhanced addressing

 The addressing modes have been enhanced to make effective use of the 4-Gbyte address

space.

• Enhanced instructions

 Addressing modes of bit-manipulation instructions have been enhanced.

 Signed multiply and divide in structions have be en added.

 A multiply-and-accumulate instruction has been added. (H8S/2600CPU only)

 Two-bit shift and rotate instructions have been added.

 Instructio ns for saving and restoring multiple registers have been added.

 A test and set instruction has been added.

• Higher speed

 Basic instructions execute twice as fast.

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 4 of 322

REJ09B0139-0400

1.1.4 Differences from H8/300H CPU

In comparison with the H8/300H CPU, the H8S/2600 CPU and H8S/2000 CPU have the following

enhancements.

• Additional control register

 One 8-bit and two 32-bit control registers have been added.

• Expanded address space

 Advanced mode supports a maximum 4-Gbyte data address space.

• Enhanced instructions

 Addressing modes of bit-manipulation instructions have been enhanced.

 A multiply-and-accumulate instruction has been added (H8S/2600 CPU only).

 Two-bit shift and rotate instructions have been added.

 Instructio ns for saving and r e storing multiple registers have be en added.

 A test and set instruction has been added.

• Higher speed

 Basic instructions execute twice as fast.

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 5 of 322

REJ09B0139-0400

1.2 CPU Operating Modes

Like the H8/300H CPU, the H8S/2600 CPU has two operating modes: normal and advanced.

Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum

4-Gbyte total address space, of which up to 16 Mbytes can be used for prog ram code and up to 4

Gbytes for data. The mode is selected with the mode pins of the microcontroller. For further

informatio n, re f er to th e relevant microcontroller hardware manual.

CPU operating modes

Normal mode

Advanced mode

Maximum 64 kbytes, program

and data areas combined

Maximum 16-Mbyte program

area and 4-Gbyte data area,

maximum 4 Gbytes for program

and data areas combined

Figure 1.1 CPU Operating Modes

(1) Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU.

Address Space: A maximum address space of 64 kbytes can be accessed, as in the H8/300 CPU.

Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as

the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain

any value, even when the corresponding general register (R0 to R7) is used as an address register.

If the general register is referenced in the register indirect addressing mode with pre-decrement

(@–Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the

correspo ndin g exten d ed register will be affected.

Instruction Set: All additional instr uctions and addressing mo des not found in the H8/300 CPU

can be used. Only the lo wer 16 bits of effective addresses (EA) are valid.

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 6 of 322

REJ09B0139-0400

Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area

starting at H'0000 is allocated to the exception vector table. One branch address is stored per

16 bits (figure 1.2). The exception vector table differs depending on the microcontroller. Refer to

the relevant microcontroller hardware manual for further information.

H'0000

H'0001

H'0002

H'0003

H'0004

H'0005

H'0006

H'0007

H'0008

H'0009

H'000A

H'000B

Power-on reset exception vector

Manual reset exception vector

Exception vector 1

Exception vector 2

Exception

vector table

(Reserved for system use)

Figure 1.2 Exception Vector Table (Normal Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses

an 8-bit absolute address included in th e instruction code to specify a memory operand that

contains a branch address. In normal mode the operand is a 16-bit word operand, providing a

16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF.

Note that this area is also used for th e exception vector table.

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 7 of 322

REJ09B0139-0400

Stack Structure: When the program counter (PC) is pushed onto the stack in a subrou tine call,

and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto

the stack in exception handling, they are stored as shown in figure 1.3. When EXR is invalid, it is

not pushed onto the stack. For details, see the relevant hardware manual.

(a) Subroutine Branch (b) Exception Handling

(16 bits) EXR*1

Reserved*1 *3

CCR

CCR*3

(16 bits)

SP SP

Notes: 1.

When EXR is not used it is not stored on the stack.

SP when EXR is not used.

Ignored on return.

(SP )

Figure 1.3 Stack Structure in Normal Mode

(2) Advanced Mode

In advanced mode the data address space is larger than for the H8/300H CPU.

Address Space: The 4-Gbyte maximum address space provides linear access to a maximum

16 Mbytes of program code and maximum 4 Gbytes of data.

Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as

the upper 16-bit segments of 32-bit registers or address registers.

Instruction Set: All instructions and addressing modes can be used.

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 8 of 322

REJ09B0139-0400

Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top

area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each

32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 1.4).

The exception vector table differs depend ing on the microcontroller. Refer to the relevant

microcontroller hardware manual for further information.

H'00000000

H'00000003

H'00000004

H'0000000B

H'0000000C

Exception vector table

Reserved

Power-on reset exception vector

(Reserved for system use)

Reserved

Exception vector 1

Reserved

Manual reset exception vector

H'00000010

H'00000008

H'00000007

Figure 1.4 Exception Vector Table (Advanced Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses

an 8-bit absolute address included in th e instruction code to specify a memory operand that

contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing

a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area th at is regarded as

H'00. Branch addresses can be stored in the top area from H'00000000 to H'000000FF. Note that

this area is also used for the exception vector table.

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 9 of 322

REJ09B0139-0400

Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a

subroutine call, and the PC, condition- co de register (CCR), and ex te nded control register (EXR)

are pushed onto the stack in exception handling, they are stored as shown in figure 1.5. When

EXR is invalid, it is not pushed onto the stack. For details, see the relevant hardware manual.

(a) Subroutine Branch (b) Exception Handling

(24 bits)

EXR*1

Reserved*1 *3

CCR

(24 bits)

SP SP

Notes: 1.

When EXR is not used it is not stored on the stack.

SP when EXR is not used.

Ignored on return.

(SP )

Reserved

Figure 1.5 Stack Structure in Advanced Mode

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 10 of 322

REJ09B0139-0400

1.3 Address Space

Figure 1.6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear

access to a maximum 64-kbyte address space in normal mode, and a maximum 4-Gbyte address

space in advanced mode. The address space differs depending on the operating mode. For details,

refer to th e releva nt microcontroller hardware m anu al.

(b) Advanced Mode

H'0000

H'FFFF

H'00000000

H'FFFFFFFF

H'00FFFFFF

(a) Normal Mode

Data area

Program area

Figure 1.6 Memory Map

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 11 of 322

REJ09B0139-0400

1.4 Register Configuration

1.4.1 Overview

The CPUs have the internal registers shown in figure 1.7. There are two types of registers: general

registers and control registers. The H8S/2000 CPU does not support the MAC register.

————

I2 I1 I0EXR 76543210

23 0

15 07 07 0

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

General Registers (Rn) and Extended Registers (En)

Control Registers (CR)

Legend: Stack pointer

Program counter

Extended control register

Trace bit

Interrupt mask bits

Condition-code register

Interrupt mask bit

User bit or interrupt mask bit

SP:

PC:

EXR:

I2 to I0:

CCR:

UI:

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7 (SP)

HUNZVCCCR 76543210

Sign extension

63 32

031

MAC MACL

Half-carry flag

User bit

Negative flag

Zero flag

Overflow flag

Carry flag

Multiply-accumulate register

MAC:

MACH

Figure 1.7 CPU Registers

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 12 of 322

REJ09B0139-0400

1.4.2 General Registers

The CPUs have eight 32-bit general registers. These general registers are all functionally alike and

can be used as both address registers and data registers. When a general register is used as a data

as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R

(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit

registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and

RL (R0L to R7L). These registers are functionally equivalent, prov iding a maximum sixteen 8-bit

registers.

Figure 1.8 illustrates the usage of the general registers. The usage of each register can be selected

independently.

• Address registers

• 32-bit registers • 16-bit registers • 8-bit registers

ER registers

(ER0 to ER7)

E registers (extended registers)

(E0 to E7)

R registers

(R0 to R7)

RH registers

(R0H to R7H)

RL registers

(R0L to R7L)

Figure 1.8 Usage of General Registers

General register ER7 has the function of stack pointer (SP) in addition to its general-register

function, and is used implicitly in exception handling and subroutine calls. Figure 1.9 shows the

stack.

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 13 of 322

REJ09B0139-0400

Free area

Stack area

SP (ER7)

Figure 1.9 Stack

1.4.3 Control Registers

The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),

8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC: H8S/2600

CPU only).

(1) Program Counter (PC)

This 24-b it coun ter indicates th e address of the next instruction the CPU will execute. Th e length

of all CPU instru ctions is 16 bits ( one word) or a multiple of 16 bits, so the least significant PC bit

is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0.

(2) Extended Control Register (EXR)

This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0).

Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed

in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is

executed.

Bits 6 to 3—Reserved: These bits are reserved, always read as 1.

Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate th e interrupt mask level (0 to

7). For details refer to the relevant microcontroller hardware manual.

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 14 of 322

REJ09B0139-0400

Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC

instruction s. All in ter r upts, including NMI , are disabled for three states after one of th ese

instructions is executed, except for STC.

(3) Condition-Code Register (CCR)

This 8-bit r egister contains internal CPU statu s information , including an interrupt ma sk bit (I ) and

half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted

regardless of the I bit setting.) The I bit is set to 1 by hardware at the start o f an exception-

handling sequence.

Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by sof twar e using the

LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask

bit. For details r e f er to the relevant microcontro ller hardware manual.

Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B

instruction is ex ecuted, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0

otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is ex ecuted, the H flag is

set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,

SUB.L, CMP.L, or NEG.L in struction is executed, th e H flag is set to 1 if there is a carry or

borrow at bit 27, and cleared to 0 otherwise.

Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and

XORC instru ctions.

Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data.

Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other

times.

Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to sto re the value shifted out of th e end bit

The carry flag is also used as a bit accumulator by bit manipulation instructions.

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 15 of 322

REJ09B0139-0400

Some instructions leave some or all of the flag bits unchanged. For the action of each instruction

on the flag bits, refer to the detailed descriptions of the instructions starting in section 2.2.1.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC

instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch

(Bcc) instructions.

(4) Multiply - A ccumulate Register (MAC)

The MAC register is supported only by the H8S/2600 CPU. This 64-bit register stores the results

of multip ly -and-accumulate operations. It consists of two 32-bit registers d enoted MACH and

MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension.

1.4.4 Initial Register Values

Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the

trace bit in EXR to 0, and sets the inter r upt mask bits in CCR and EXR to 1 . The other CCR bits

and the genera l r egisters ar e not initialized. In par ticular, the stack pointer (ER7 ) is not initialized.

The stack pointer should therefore be initialized by an MOV.L instruction executed immediately

after a reset.

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 16 of 322

REJ09B0139-0400

1.5 Data Formats

The CPUs can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data.

Bit-manipulation instructions op erate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte

operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-b it

BCD data.

1.5.1 General Register Data Formats

Figure 1.10 shows the data formats in general registers.

76543210 Don’t care

Don’t care 76543210

Don’t careUpper Lower

LSB

MSB LSB

Data Type Register Number Data Format

1-bit data

4-bit BCD data

Byte data

RnH

RnL

RnH

RnL

RnH

RnL

MSB

Don’t care Upper Lower

Don’t care

Don’t care 70

Figure 1.10 General Register Data Formats

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 17 of 322

REJ09B0139-0400

MSB LSB

Word data

LSB

MSB

En Rn

General register ER

General register E

General register R

General register RH

General register RL

Most significant bit

Least significant bit

Legend:

ERn:

En:

Rn:

RnH:

RnL:

MSB:

LSB:

MSB LSB

Longword data ERn

Figure 1.10 General Register Data Formats (cont)

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 18 of 322

REJ09B0139-0400

1.5.2 Memory Data Formats

Figure 1.11 shows the data formats in memory. The CPU can access word data and longwor d data

in memory, but word or longword data must begin at an even address. If an attempt is made to

access word or longword data at an odd address, no address error occurs bu t the least significant

bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to

instructio n fetches.

76543210

MSB LSB

MSB

LSB

MSB

LSB

Data Type Data Format

1-bit data

Byte data

Word data

Longword data

Address

Address L

Address 2M

Address 2M + 1

Address 2N

Address 2N + 1

Address 2N + 2

Address 2N + 3

Figure 1.11 Memory Data Formats

When the stack pointer (ER7) is used as an address register to access the stack, the operand size

should be word size or longword size.

Section 1 CPU

Rev. 4.00 Feb 24, 2006 page 19 of 322

REJ09B0139-0400

1.6 Instruction Set

1.6.1 Overview

The H8S/2600 CPU has 69types of instructions, while the H8S/2000 CPU has 65 types. The

instructions are classified by function as shown in table 1.1. For a detailed description of each

instruction, see section 2.2, Instruction Descriptions.

Table 1.1 Instruction Classification

Function Instructions Size Types

MOV BWL

POP*2, PUSH*2WL

LDM, STM L

Data transfer

MOVFPE, MOVTPE B

ADD, SUB, CMP, NEG BWL

ADDX, SUBX, DAA, DAS B

INC, DEC BWL

ADDS, SUBS L

MULXU, DIVXU, MULXS, DIVXS BW

EXTU, EXTS WL

TAS*4B

Arithmetic

operations

MAC, LDMAC, STMAC, CLRMAC*1— 4*1

Logic operations AND, OR, XOR, NOT BWL 4

Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8

Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

BIAND, BOR, BIOR, BXOR, BIXOR B14

Branch Bcc*3, JMP, BSR, JSR, RTS — 5

System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9

Block data transfer EEPMOV — 1

H8S/2600 CPU: Total 69 types H8S/2000 CPU: Total 65 types

Legend: B: Byte size

W: Word size

L: Longword size

Notes: 1. The MAC, LDMAC, STMAC, and CLRMAC instructions are supported only by the

H8S/2600 CPU.

2. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,

@–SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L

ERn, @–SP.

3. Bcc is the generic designation of a conditional branch instruction.

4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.