S9S08RNA32W1VLCR - NXP SEMICONDUCTORS

S9S08RN60

S9S08RN60 Series Data

Sheet

Supports: S9S08RN60, S9S08RN48

and S9S08RN32

Features

•8-Bit S08 central processor unit (CPU)

– Up to 20 MHz bus at 2.7 V to 5.5 V across

temperature range of -40 °C to 125 °C

– Supporting up to 40 interrupt/reset sources

– Supporting up to four-level nested interrupt

– On-chip memory

– Up to 60 KB flash read/program/erase over full

operating voltage and temperature

– Up to 256 byte EEPROM with ECC; 2-byte erase

sector; EEPROM program and erase while executing

code from flash

– Up to 4096 byte random-access memory (RAM)

– Flash and RAM access protection

•Power-saving modes

– One low-power stop mode; reduced power wait

mode

– Peripheral clock enable register can disable clocks to

unused modules, reducing currents; allows clocks to

remain enabled to specific peripherals in stop3 mode

•Clocks

– Oscillator (XOSC) - loop-controlled Pierce

oscillator; crystal or ceramic resonator

– Internal clock source (ICS) - containing a frequency-

locked-loop (FLL) controlled by internal or external

reference; precision trimming of internal reference

allowing 1% deviation across temperature range of 0

°C to 70 °C and -40 °C to 85 °C, 1.5% deviation

across temperature range of -40 °C to 105 °C, and

2% deviation across temperature range of -40 °C to

125 °C; up to 20 MHz

•System protection

– Watchdog with independent clock source

– Low-voltage detection with reset or interrupt;

selectable trip points

– Illegal opcode detection with reset

– Illegal address detection with reset

•Development support

– Single-wire background debug interface

– Breakpoint capability to allow three breakpoints

setting during in-circuit debugging

– On-chip in-circuit emulator (ICE) debug module

containing two comparators and nine trigger modes

•Peripherals

– ACMP - one analog comparator with both positive

and negative inputs; separately selectable interrupt

on rising and falling comparator output; filtering

– ADC - 16-channel, 12-bit resolution; 2.5 µs

conversion time; data buffers with optional

watermark; automatic compare function; internal

bandgap reference channel; operation in stop mode;

optional hardware trigger

– CRC - programmable cyclic redundancy check

module

– FTM - three flex timer modulators modules

including one 6-channel and two 2-channel ones;

16-bit counter; each channel can be configured for

input capture, output compare, edge- or center-

aligned PWM mode

– IIC - One inter-integrated circuit module; up to 400

kbps; multi-master operation; programmable slave

address; supporting broadcast mode and 10-bit

addressing

– MTIM - Two modulo timers with 8-bit prescaler and

overflow interrupt

– RTC - 16-bit real timer counter (RTC)

– SCI - three serial communication interface (SCI/

UART) modules optional 13-bit break; full duplex

non-return to zero (NRZ); LIN extension support

– SPI - one 8-bit and one 16-bit serial peripheral

interface (SPI) modules; full-duplex or single-wire

bidirectional; master or slave mode

– TSI - supporting up to 16 external electrodes;

configurable software or hardware scan trigger; fully

support freescale touch sensing software library;

capability to wake MCU from stop3 mode

Freescale Semiconductor Document Number: S9S08RN60

Data Sheet: Technical Data Rev. 1, 01/2014

Freescale reserves the right to change the detail specifications as may be

required to permit improvements in the design of its products.

•Input/Output

– Up to 55 GPIOs including one output-only pin

– Two 8-bit keyboard interrupt modules (KBI)

– Two true open-drain output pins

– Eight, ultra-high current sink pins supporting 20 mA source/sink current

•Package options

– 64-pin LQFP

– 48-pin LQFP

– 32-pin LQFP

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

2 Freescale Semiconductor, Inc.

Table of Contents

1 Ordering parts...........................................................................4

1.1 Determining valid orderable parts......................................4

2 Part identification......................................................................4

2.1 Description.........................................................................4

2.2 Format...............................................................................4

2.3 Fields.................................................................................4

2.4 Example............................................................................5

3Parameter Classification...........................................................5

4Ratings......................................................................................5

4.1 Thermal handling ratings...................................................5

4.2 Moisture handling ratings..................................................6

4.3 ESD handling ratings.........................................................6

4.4 Voltage and current operating ratings...............................6

5General.....................................................................................7

5.1 Nonswitching electrical specifications...............................7

5.1.1 DC characteristics.................................................7

5.1.2 Supply current characteristics...............................14

5.1.3 EMC performance.................................................15

5.2 Switching specifications.....................................................16

5.2.1 Control timing........................................................16

5.2.2 Debug trace timing specifications.........................17

5.2.3 FTM module timing...............................................17

5.3 Thermal specifications.......................................................18

5.3.1 Thermal characteristics.........................................18

6 Peripheral operating requirements and behaviors....................19

6.1 External oscillator (XOSC) and ICS characteristics...........20

6.2 NVM specifications............................................................21

6.3 Analog...............................................................................23

6.3.1 ADC characteristics...............................................23

6.3.2 Analog comparator (ACMP) electricals.................25

6.4 Communication interfaces.................................................26

6.4.1 SPI switching specifications..................................26

6.5 Human-machine interfaces (HMI)......................................29

6.5.1 TSI electrical specifications...................................29

7 Dimensions...............................................................................29

7.1 Obtaining package dimensions.........................................29

8 Pinout........................................................................................30

8.1 Signal multiplexing and pin assignments...........................30

8.2 Device pin assignment......................................................33

9 Revision history.........................................................................35

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 3

Ordering parts

1.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part

numbers for this device, go to www.freescale.com and perform a part number search for

the following device numbers: RN60, RN48 and RN32.

Part identification

2.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

2.2 Format

Part numbers for this device have the following format:

S 9 S08 RN AA F1 B CC

2.3 Fields

This table lists the possible values for each field in the part number (not all combinations

are valid):

Field Description Values

S Qualification status • S = fully qualified, general market flow

9 Memory • 9 = flash based

S08 Core • S08 = 8-bit CPU

RN Device family • RN

AA Approximate flash size in KB • 60 = 60 KB

• 48 = 48 KB

• 32 = 32 KB

F1 Fab and mask set identifier • W1

B Temperature range (°C) • M = –40 to 125

Table continues on the next page...

Ordering parts

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

4 Freescale Semiconductor, Inc.

Field Description Values

CC Package designator • LH = 64-pin LQFP

• LF = 48-pin LQFP

• LC = 32-pin LQFP

2.4 Example

This is an example part number:

S9S08RN60W1MLH

3 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods.

To give the customer a better understanding, the following classification is used and the

parameters are tagged accordingly in the tables where appropriate:

Table 1. Parameter Classifications

P Those parameters are guaranteed during production testing on each individual device.

C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size

across process variations.

T Those parameters are achieved by design characterization on a small sample size from typical devices under

typical conditions unless otherwise noted. All values shown in the typical column are within this category.

D Those parameters are derived mainly from simulations.

NOTE

The classification is shown in the column labeled “C” in the

parameter tables where appropriate.

Ratings

4.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes

TSTG Storage temperature –55 150 °C 1

TSDR Solder temperature, lead-free — 260 °C 2

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

Parameter Classification

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 5

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

4.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes

MSL Moisture sensitivity level — 3 — 1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

4.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes

VHBM Electrostatic discharge voltage, human body model -6000 +6000 V 1

VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2

ILAT Latch-up current at ambient temperature of 125°C -100 +100 mA

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

4.4 Voltage and current operating ratings

Absolute maximum ratings are stress ratings only, and functional operation at the

maxima is not guaranteed. Stress beyond the limits specified in below table may affect

device reliability or cause permanent damage to the device. For functional operating

conditions, refer to the remaining tables in this document.

This device contains circuitry protecting against damage due to high static voltage or

electrical fields; however, it is advised that normal precautions be taken to avoid

application of any voltages higher than maximum-rated voltages to this high-impedance

circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate

logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor

associated with the pin is enabled.

Symbol Description Min. Max. Unit

VDD Supply voltage –0.3 5.8 V

IDD Maximum current into VDD — 120 mA

Table continues on the next page...

Ratings

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

6 Freescale Semiconductor, Inc.

Symbol Description Min. Max. Unit

VDIO Digital input voltage (except RESET, EXTAL, XTAL, or true

open drain pin PTA2 and PTA3)

–0.3 VDD + 0.3 V

Digital input voltage (true open drain pin PTA2 and PTA3) -0.3 6 V

VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V

IDInstantaneous maximum current single pin limit (applies to all

port pins)

–25 25 mA

VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V

1. All digital I/O pins, except open-drain pin PTA2 and PTA3, are internally clamped to VSS and VDD. PTA2 and PTA3 is only

clamped to VSS.

General

Nonswitching electrical specifications

5.1.1 DC characteristics

This section includes information about power supply requirements and I/O pin

characteristics.

Table 2. DC characteristics

Symbol C Descriptions Min Typical1Max Unit

— — Operating voltage — 2.7 — 5.5 V

VOH C Output high

voltage

All I/O pins, standard-

drive strength

5 V, Iload =

-5 mA

VDD - 0.8 — — V

C 3 V, Iload =

-2.5 mA

VDD - 0.8 — — V

C High current drive

pins, high-drive

strength2, 2

5 V, Iload =

-20 mA

VDD - 0.8 — — V

C 3 V, Iload =

-10 mA

VDD - 0.8 — — V

IOHT D Output high

current

Max total IOH for all

ports

5 V — — -100 mA

3 V — — -50

VOL C Output low

voltage

All I/O pins, standard-

drive strength

5 V, Iload = 5

— — 0.8 V

C 3 V, Iload =

2.5 mA

— — 0.8 V

C High current drive

pins, high-drive

strength2

5 V, Iload

=20 mA

— — 0.8 V

C 3 V, Iload =

10 mA

— — 0.8 V

Table continues on the next page...

5.1

General

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 7

Table 2. DC characteristics (continued)

Symbol C Descriptions Min Typical1Max Unit

IOLT D Output low

current

Max total IOL for all

ports

5 V — — 100 mA

3 V — — 50

VIH P Input high

voltage

All digital inputs VDD>4.5V 0.70 × VDD — — V

C VDD>2.7V 0.75 × VDD — —

VIL P Input low

voltage

All digital inputs VDD>4.5V — — 0.30 × VDD V

C VDD>2.7V — — 0.35 × VDD

Vhys C Input

hysteresis

All digital inputs — 0.06 × VDD — — mV

|IIn| P Input leakage

current

All input only pins

(per pin)

VIN = VDD or

VSS

— 0.1 1 µA

|IOZ| P Hi-Z (off-

state) leakage

current

All input/output (per

pin)

VIN = VDD or

VSS

— 0.1 1 µA

|IOZTOT| C Total leakage

combined for

all inputs and

Hi-Z pins

All input only and I/O VIN = VDD or

VSS

— — 2 µA

RPU P Pullup

resistors

All digital inputs,

when enabled (all I/O

pins other than PTA2

and PTA3)

— 30.0 — 50.0 kΩ

RPU3P Pullup

resistors

PTA2 and PTA3 pin — 30.0 — 60.0 kΩ

IIC D DC injection

current4, 5, 6Single pin limit VIN < VSS,

VIN > VDD

-0.2 — 2 mA

Total MCU limit,

includes sum of all

stressed pins

-5 — 25

CIn C Input capacitance, all pins — — — 7 pF

VRAM C RAM retention voltage — 2.0 — — V

1. Typical values are measured at 25 °C. Characterized, not tested.

2. Only PTB4, PTB5 support ultra high current output.

3. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured

externally on the pin.

4. All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to VSS and VDD.

5. Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values for positive and negative clamp voltages, then use the large one.

6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current

conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could

result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than

maximum injection current when the MCU is not consuming power, such as no system clock is present, or clock rate is

very low (which would reduce overall power consumption).

Table 3. LVD and POR Specification

Symbol C Description Min Typ Max Unit

VPOR D POR re-arm voltage1, 21.5 1.75 2.0 V

Table continues on the next page...

Nonswitching electrical specifications

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

8 Freescale Semiconductor, Inc.

Table 3. LVD and POR Specification (continued)

Symbol C Description Min Typ Max Unit

VLVDH C Falling low-voltage detect

threshold - high range (LVDV

= 1)3

4.2 4.3 4.4 V

VLVW1H C Falling low-

voltage

warning

threshold -

high range

Level 1 falling

(LVWV = 00)

4.3 4.4 4.5 V

VLVW2H C Level 2 falling

(LVWV = 01)

4.5 4.5 4.6 V

VLVW3H C Level 3 falling

(LVWV = 10)

4.6 4.6 4.7 V

VLVW4H C Level 4 falling

(LVWV = 11)

4.7 4.7 4.8 V

VHYSH C High range low-voltage

detect/warning hysteresis

— 100 — mV

VLVDL C Falling low-voltage detect

threshold - low range (LVDV =

2.56 2.61 2.66 V

VLVDW1L C Falling low-

voltage

warning

threshold -

low range

Level 1 falling

(LVWV = 00)

2.62 2.7 2.78 V

VLVDW2L C Level 2 falling

(LVWV = 01)

2.72 2.8 2.88 V

VLVDW3L C Level 3 falling

(LVWV = 10)

2.82 2.9 2.98 V

VLVDW4L C Level 4 falling

(LVWV = 11)

2.92 3.0 3.08 V

VHYSDL C Low range low-voltage detect

hysteresis

— 40 — mV

VHYSWL C Low range low-voltage

warning hysteresis

— 80 — mV

VBG P Buffered bandgap output 41.14 1.16 1.18 V

1. Maximum is highest voltage that POR is guaranteed.

2. POR ramp time must be longer than 20us/V to get a stable startup.

3. Rising thresholds are falling threshold + hysteresis.

4. Voltage factory trimmed at VDD = 5.0 V, Temp = 125 °C

Nonswitching electrical specifications

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 9

0.1

0.2

0.3

0.4

0.5

0.6

0 1 2 3 4 5 6 7

V DD -V OH (V)

I OH (mA)

Typical I OH Vs. V DD -V OH (low drive

strength) (V DD = 5 V)

125°C

25°C

-40°

Figure 1. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 5 V)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0 1 2 3 4 5 6 7

V DD -V OH (V)

I OH (mA)

Typical I OH Vs. V DD -V OH (low drive

strength) (V DD = 3 V)

125°C

25°C

-40°C

Figure 2. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 3 V)

Nonswitching electrical specifications

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

10 Freescale Semiconductor, Inc.

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0 5 10 15 20 25 30

V DD -V OH (V)

I OH (mA)

Typical I OH Vs. V DD -V OH (high drive

strength) (V DD = 5 V)

125°C

25°C

-40°C

Figure 3. Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 5 V)

0.2

0.4

0.6

0.8

1.2

0 5 10 15 20 25 30

V DD -V OH (V)

I OH (mA)

Typical I OH Vs. V DD -V OH (high drive

strength) (V DD = 3 V)

125°C

25°C

-40°C

Figure 4. Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 3 V)

Nonswitching electrical specifications

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 11

0.1

0.2

0.3

0.4

0.5

0.6

0 1 2 3 4 5 6 7

VOL (V)

I OL (mA)

Typical I OL Vs. V OL (low drive strength) (V

DD = 5 V)

125°C

25°C

-40°

0.3

125°C

Figure 5. Typical IOL Vs. VOL (standard drive strength) (VDD = 5 V)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0 1 2 3 4 5 6 7

VOL (V)

I OL (mA)

Typical I OL Vs. V OL (low drive strength) (V

DD = 3 V)

125°C

25°C

-40°C

0.3

125°C

Figure 6. Typical IOL Vs. VOL (standard drive strength) (VDD = 3 V)

Nonswitching electrical specifications

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

12 Freescale Semiconductor, Inc.

0.1

0.2

0.3

0.4

0.5

0.6

0 5 10 15 20 25 30

VOL (V)

I OL (mA)

Typical I OL Vs. V OL (high drive strength) (V

DD = 5 V)

125°C

25°C

-40°C

Figure 7. Typical IOL Vs. VOL (high drive strength) (VDD = 5 V)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0 5 10 15 20 25 30

V OL (V)

I OL (mA)

Typical I OL Vs. V OL (high drive strength) (V

DD = 3 V)

125°C

25°C

-40°

Figure 8. Typical IOL Vs. VOL (high drive strength) (VDD = 3 V)

Nonswitching electrical specifications

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 13

5.1.2 Supply current characteristics

This section includes information about power supply current in various operating modes.

Table 4. Supply current characteristics

Num C Parameter Symbol Bus Freq VDD (V) Typical1Max Unit Temp

1 C Run supply current FEI

mode, all modules on; run

from flash

RIDD 20 MHz 5 12.6 — mA -40 to 125 °C

C 10 MHz 7.2 —

1 MHz 2.4 —

C 20 MHz 3 9.6 —

C 10 MHz 6.1 —

1 MHz 2.1 —

2 C Run supply current FEI

mode, all modules off &

gated; run from flash

RIDD 20 MHz 5 10.5 — mA -40 to 125 °C

C 10 MHz 6.2 —

1 MHz 2.3 —

C 20 MHz 3 7.4 —

C 10 MHz 5.0 —

1 MHz 2.0 —

3 P Run supply current FBE

mode, all modules on; run

from RAM

RIDD 20 MHz 5 12.1 14.8 mA -40 to 125 °C

C 10 MHz 6.5 —

1 MHz 1.8 —

P 20 MHz 3 9.1 11.8

C 10 MHz 5.5 —

1 MHz 1.5 —

4 P Run supply current FBE

mode, all modules off &

gated; run from RAM

RIDD 20 MHz 5 9.8 12.3 mA -40 to 125 °C

C 10 MHz 5.4 —

1 MHz 1.6 —

P 20 MHz 3 6.9 9.2

C 10 MHz 4.4 —

1 MHz 1.4 —

5 C Wait mode current FEI

mode, all modules on

WIDD 20 MHz 5 7.8 — mA -40 to 125 °C

C 10 MHz 4.5 —

1 MHz 1.3 —

C 20 MHz 3 5.1 —

10 MHz 3.5 —

1 MHz 1.2 —

6 C Stop3 mode supply

current no clocks active

(except 1 kHz LPO

clock)2, 3

S3IDD — 5 3.8 — µA -40 to 125 °C

C — 3 3 — -40 to 125 °C

Table continues on the next page...

Nonswitching electrical specifications

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

14 Freescale Semiconductor, Inc.

Table 4. Supply current characteristics (continued)

Num C Parameter Symbol Bus Freq VDD (V) Typical1Max Unit Temp

7 C ADC adder to stop3

ADLPC = 1

ADLSMP = 1

ADCO = 1

MODE = 10B

ADICLK = 11B

— — 5 44 — µA -40 to 125 °C

C 3 40 —

8 C TSI adder to stop34

PS = 010B

NSCN =0x0F

EXTCHRG = 0

REFCHRG = 0

DVOLT = 01B

— — 5 111 — µA -40 to 125 °C

C 3 110 —

9 C LVD adder to stop35— — 5 130 — µA -40 to 125 °C

C 3 125 —

1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.

2. RTC adder cause <1 µA IDD increase typically, RTC clock source is 1 kHz LPO clock.

3. ACMP adder cause <1 µA IDD increase typically.

4. The current varies with TSI configuration and capacity of touch electrode. Please refer to TSI electrical specifications.

5. LVD is periodically woken up from stop3 by 5% duty cycle. The period is equal to or less than 2 ms.

5.1.3 EMC performance

Electromagnetic compatibility (EMC) performance is highly dependant on the

environment in which the MCU resides. Board design and layout, circuit topology

choices, location and characteristics of external components as well as MCU software

operation all play a significant role in EMC performance. The system designer should

consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and

AN1259 for advice and guidance specifically targeted at optimizing EMC performance.

5.1.3.1 EMC radiated emissions operating behaviors

Nonswitching electrical specifications

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 15

Switching specifications

5.2.1 Control timing

Table 5. Control timing

Num C Rating Symbol Min Typical1Max Unit

1 P Bus frequency (tcyc = 1/fBus) fBus DC — 20 MHz

2 P Internal low power oscillator frequency fLPO 0.67 1.0 1.25 KHz

3 D External reset pulse width2, 2textrst 1.5 ×

tSelf_reset

— — ns

4 D Reset low drive trstdrv 34 × tcyc — — ns

5 D BKGD/MS setup time after issuing background

debug force reset to enter user or BDM modes

tMSSU 500 — — ns

6 D BKGD/MS hold time after issuing background

debug force reset to enter user or BDM modes3tMSH 100 — — ns

7 D Keyboard interrupt pulse

width

Asynchronous

path2tILIH 100 — — ns

D Synchronous path tIHIL 1.5 × tcyc — — ns

8 C Port rise and fall time -

Normal drive strength

(HDRVE_PTXx = 0) (load

= 50 pF)4, 4

— tRise — 10.2 — ns

C tFall — 9.5 — ns

C Port rise and fall time -

Extreme high drive

strength (HDRVE_PTXx =

1) (load = 50 pF)4

— tRise — 5.4 — ns

C tFall — 4.6 — ns

1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.

2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request.

3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of tMSH after

VDD rises above VLVD.

4. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 125 °C.











 

textrst

RESET PIN

Figure 9. Reset timing

tIHIL

KBIPx

tILIH

KBIPx

Figure 10. KBIPx timing

5.2

Switching specifications

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

16 Freescale Semiconductor, Inc.

5.2.2 Debug trace timing specifications

Table 6. Debug trace operating behaviors

Symbol Description Min. Max. Unit

tcyc Clock period Frequency dependent MHz

twl Low pulse width 2 — ns

twh High pulse width 2 — ns

trClock and data rise time — 3 ns

tfClock and data fall time — 3 ns

tsData setup 3 — ns

thData hold 2 — ns

Figure 11. TRACE_CLKOUT specifications

Ts Ts Th

TRACE_CLKOUT

TRACE_D[3:0]

Figure 12. Trace data specifications

5.2.3 FTM module timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the

fastest clock that can be used as the optional external source to the timer counter. These

synchronizers operate from the current bus rate clock.

Table 7. FTM input timing

No. C Function Symbol Min Max Unit

1 D External clock

frequency

fTCLK 0 fBus/4 Hz

Table continues on the next page...

Switching specifications

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 17

Table 7. FTM input timing (continued)

No. C Function Symbol Min Max Unit

2 D External clock

period

tTCLK 4 — tcyc

3 D External clock

high time

tclkh 1.5 — tcyc

4 D External clock

low time

tclkl 1.5 — tcyc

5 D Input capture

pulse width

tICPW 1.5 — tcyc











 

tTCLK

tclkh

tclkl

TCLK

Figure 13. Timer external clock











 

tICPW

FTMCHn

tICPW

FTMCHn

Figure 14. Timer input capture pulse

Thermal specifications

5.3.1 Thermal characteristics

This section provides information about operating temperature range, power dissipation,

and package thermal resistance. Power dissipation on I/O pins is usually small compared

to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-

determined rather than being controlled by the MCU design. To take PI/O into account in

power calculations, determine the difference between actual pin voltage and VSS or VDD

and multiply by the pin current for each I/O pin. Except in cases of unusually high pin

current (heavy loads), the difference between pin voltage and VSS or VDD will be very

small.

5.3

Thermal specifications

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

18 Freescale Semiconductor, Inc.

Table 8. Thermal characteristics

Rating Symbol Value Unit

Operating temperature range

(packaged)

TATL to TH -40 to 125 °C

Junction temperature range TJ-40 to 135 °C

Thermal resistance single-layer board

64-pin LQFP θJA 71 °C/W

48-pin LQFP θJA 81 °C/W

32-pin LQFP θJA 86 °C/W

Thermal resistance four-layer board

64-pin LQFP θJA 53 °C/W

48-pin LQFP θJA 57 °C/W

32-pin LQFP θJA 57 °C/W

The average chip-junction temperature (TJ) in °C can be obtained from:

TJ = TA + (PD × θJA)

Where:

TA = Ambient temperature, °C

θJA = Package thermal resistance, junction-to-ambient, °C/W

PD = Pint + PI/O

Pint = IDD × VDD, Watts - chip internal power

PI/O = Power dissipation on input and output pins - user determined

For most applications, PI/O << Pint and can be neglected. An approximate relationship

between PD and TJ (if PI/O is neglected) is:

PD = K ÷ (TJ + 273 °C)

Solving the equations above for K gives:

K = PD × (TA + 273 °C) + θJA × (PD)2

where K is a constant pertaining to the particular part. K can be determined by measuring

PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be

obtained by solving the above equations iteratively for any value of TA.

6 Peripheral operating requirements and behaviors

Peripheral operating requirements and behaviors

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 19

6.1 External oscillator (XOSC) and ICS characteristics

Table 9. XOSC and ICS specifications (temperature range = -40 to 125 °C ambient)

Num C Characteristic Symbol Min Typical1Max Unit

1 C Oscillator

crystal or

resonator

Low range (RANGE = 0) flo 32 — 40 kHz

C High range (RANGE = 1)

FEE or FBE mode2, 2fhi 4 — 20 MHz

C High range (RANGE = 1),

high gain (HGO = 1),

FBELP mode

fhi 4 — 20 MHz

C High range (RANGE = 1),

low power (HGO = 0),

FBELP mode

fhi 4 — 20 MHz

2 D Load capacitors C1, C2 See Note3

3 D Feedback

resistor

Low Frequency, Low-Power

Mode4, 4RF— — — MΩ

Low Frequency, High-Gain

Mode

— 10 — MΩ

High Frequency, Low-

Power Mode

— 1 — MΩ

High Frequency, High-Gain

Mode

— 1 — MΩ

4 D Series resistor -

Low Frequency

Low-Power Mode 4RS— — — kΩ

High-Gain Mode — 200 — kΩ

5 D Series resistor -

High Frequency

Low-Power Mode4RS— — — kΩ

D Series resistor -

High

Frequency,

High-Gain Mode

4 MHz — 0 — kΩ

D 8 MHz — 0 — kΩ

D 16 MHz — 0 — kΩ

6 C Crystal start-up

time Low range

= 39.0625 kHz

crystal; High

range = 20 MHz

crystal5, 5, 6

Low range, low power tCSTL — 1000 — ms

C Low range, high power — 800 — ms

C High range, low power tCSTH — 3 — ms

C High range, high power — 1.5 — ms

7 T Internal reference start-up time tIRST — 20 50 µs

8 D Square wave

input clock

frequency

FEE or FBE mode2fextal 0.03125 — 5 MHz

D FBELP mode 0 — 20 MHz

9 P Average internal reference frequency -

trimmed

fint_t — 39.0625 — kHz

10 P DCO output frequency range - trimmed fdco_t 16 — 20 MHz

Table continues on the next page...

Peripheral operating requirements and behaviors

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

20 Freescale Semiconductor, Inc.

Table 9. XOSC and ICS specifications (temperature range = -40 to 125 °C ambient)

(continued)

Num C Characteristic Symbol Min Typical1Max Unit

11 P Total deviation

of DCO output

from trimmed

frequency5

Over full voltage range and

temperature range of -40 to

125 °C

Δfdco_t — — ±2.0

C Over full voltage range and

temperature range of -40 to

105 °C

±1.5 %fdco

C Over fixed voltage and

temperature range of 0 to

70 °C

±1.0

12 C FLL acquisition time5, 7tAcquire — — 2 ms

13 C Long term jitter of DCO output clock

(averaged over 2 ms interval)8CJitter — 0.02 0.2 %fdco

1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.

2. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25

kHz to 39.0625 kHz.

3. See crystal or resonator manufacturer's recommendation.

4. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO =

5. This parameter is characterized and not tested on each device.

6. Proper PC board layout procedures must be followed to achieve specifications.

7. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed,

DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

8. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage

for a given interval.

XOSC

EXTAL XTAL

Crystal or Resonator

Figure 15. Typical crystal or resonator circuit

Peripheral operating requirements and behaviors

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 21

6.2 NVM specifications

This section provides details about program/erase times and program/erase endurance for

the flash and EEPROM memories.

Table 10. Flash characteristics

C Characteristic Symbol Min1Typical2Max3Unit4

D Supply voltage for program/erase -40 °C

to 125 °C

Vprog/erase 2.7 — 5.5 V

D Supply voltage for read operation VRead 2.7 — 5.5 V

D NVM Bus frequency fNVMBUS 1 — 25 MHz

D NVM Operating frequency fNVMOP 0.8 1 1.05 MHz

D Erase Verify All Blocks tVFYALL — — 17338 tcyc

D Erase Verify Flash Block tRD1BLK — — 16913 tcyc

D Erase Verify EEPROM Block tRD1BLK — — 810 tcyc

D Erase Verify Flash Section tRD1SEC — — 484 tcyc

D Erase Verify EEPROM Section tDRD1SEC — — 555 tcyc

D Read Once tRDONCE — — 450 tcyc

D Program Flash (2 word) tPGM2 0.12 0.12 0.29 ms

D Program Flash (4 word) tPGM4 0.20 0.21 0.46 ms

D Program Once tPGMONCE 0.20 0.21 0.21 ms

D Program EEPROM (1 Byte) tDPGM1 0.10 0.10 0.27 ms

D Program EEPROM (2 Byte) tDPGM2 0.17 0.18 0.43 ms

D Program EEPROM (3 Byte) tDPGM3 0.25 0.26 0.60 ms

D Program EEPROM (4 Byte) tDPGM4 0.32 0.33 0.77 ms

D Erase All Blocks tERSALL 96.01 100.78 101.49 ms

D Erase Flash Block tERSBLK 95.98 100.75 101.44 ms

D Erase Flash Sector tERSPG 19.10 20.05 20.08 ms

D Erase EEPROM Sector tDERSPG 4.81 5.05 20.57 ms

D Unsecure Flash tUNSECU 96.01 100.78 101.48 ms

D Verify Backdoor Access Key tVFYKEY — — 464 tcyc

D Set User Margin Level tMLOADU — — 407 tcyc

C FLASH Program/erase endurance TL to

TH = -40 °C to 125 °C

nFLPE 10 k 100 k — Cycles

C EEPROM Program/erase endurance TL

to TH = -40 °C to 125 °C

nFLPE 50 k 500 k — Cycles

C Data retention at an average junction

temperature of TJavg = 85°C after up to

10,000 program/erase cycles

tD_ret 15 100 — years

1. Minimum times are based on maximum fNVMOP and maximum fNVMBUS

2. Typical times are based on typical fNVMOP and maximum fNVMBUS

3. Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging

4. tcyc = 1 / fNVMBUS

Peripheral operating requirements and behaviors

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

22 Freescale Semiconductor, Inc.

Program and erase operations do not require any special power sources other than the

normal VDD supply. For more detailed information about program/erase operations, see

the Memory section.

6.3 Analog

6.3.1 ADC characteristics

Table 11. 5 V 12-bit ADC operating conditions

Characteri

stic

Conditions Symb Min Typ1Max Unit Comment

Supply

voltage

Absolute VDDA 2.7 — 5.5 V —

Delta to VDD (VDD-VDDAD)ΔVDDA -100 0 +100 mV

Ground

voltage

Delta to VSS (VSS-VSSA)2ΔVSSA -100 0 +100 mV

Input

voltage

VADIN VREFL — VREFH V

Input

capacitance

CADIN — 4.5 5.5 pF

Input

resistance

RADIN — 3 5 kΩ —

Analog

source

resistance

12-bit mode

• fADCK > 4 MHz

• fADCK < 4 MHz

RAS —

—

kΩ External to

MCU

10-bit mode

• fADCK > 4 MHz

• fADCK < 4 MHz

—

8-bit mode

(all valid fADCK)

— — 10

ADC

conversion

clock

frequency

High speed (ADLPC=0) fADCK 0.4 — 8.0 MHz —

Low power (ADLPC=1) 0.4 — 4.0

1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

2. DC potential difference.

Peripheral operating requirements and behaviors

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 23

ADC SAR

ENGINE

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

Pad

leakage

due to

input

protection

ZAS

R AS

C AS

v ADIN

v AS

z ADIN

R ADIN

INPUT PIN

C ADIN

Figure 16. ADC input impedance equivalency diagram

Table 12. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA)

Characteristic Conditions C Symb Min Typ1Max Unit

Supply current

ADLPC = 1

ADLSMP = 1

ADCO = 1

T IDDA — 133 — µA

Supply current

ADLPC = 1

ADLSMP = 0

ADCO = 1

T IDDA — 218 — µA

Supply current

ADLPC = 0

ADLSMP = 1

ADCO = 1

T IDDA — 327 — µA

Supply current

ADLPC = 0

ADLSMP = 0

ADCO = 1

T IDDAD — 582 990 µA

Supply current Stop, reset, module

off

T IDDA — 0.011 1 µA

Table continues on the next page...

Peripheral operating requirements and behaviors

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

24 Freescale Semiconductor, Inc.

Table 12. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)

Characteristic Conditions C Symb Min Typ1Max Unit

ADC asynchronous

clock source

High speed (ADLPC

= 0)

P fADACK 2 3.3 5 MHz

Low power (ADLPC

= 1)

1.25 2 3.3

Conversion time

(including sample

time)

Short sample

(ADLSMP = 0)

T tADC — 20 — ADCK

cycles

Long sample

(ADLSMP = 1)

— 40 —

Sample time Short sample

(ADLSMP = 0)

T tADS — 3.5 — ADCK

cycles

Long sample

(ADLSMP = 1)

— 23.5 —

Total unadjusted

Error2, 212-bit mode T ETUE — ±5.0 — LSB3, 3

10-bit mode P — ±1.5 ±2.0

8-bit mode P — ±0.7 ±1.0

Differential Non-

Linearity

12-bit mode T DNL — ±1.0 — LSB3

10-bit mode4, 4P — ±0.25 ±0.5

8-bit mode4P — ±0.15 ±0.25

Integral Non-Linearity 12-bit mode T INL — ±1.0 — LSB3

10-bit mode T — ±0.3 ±0.5

8-bit mode T — ±0.15 ±0.25

Zero-scale error5, 512-bit mode C EZS — ±2.0 — LSB3

10-bit mode P — ±0.25 ±1.0

8-bit mode P — ±0.65 ±1.0

Full-scale error612-bit mode T EFS — ±2.5 — LSB3

10-bit mode T — ±0.5 ±1.0

8-bit mode T — ±0.5 ±1.0

Quantization error ≤12 bit modes D EQ— — ±0.5 LSB3

Input leakage error7all modes D EIL IIn * RAS mV

Temp sensor slope -40°C– 25°C D m — 3.266 — mV/°C

25°C– 125°C — 3.638 —

Temp sensor voltage 25°C D VTEMP25 — 1.396 — V

1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

2. Includes quantization.

3. 1 LSB = (VREFH - VREFL)/2N

4. Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes

5. VADIN = VSSA

6. VADIN = VDDA

7. IIn = leakage current (refer to DC characteristics)

Peripheral operating requirements and behaviors

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 25

6.3.2 Analog comparator (ACMP) electricals

Table 13. Comparator electrical specifications

C Characteristic Symbol Min Typical Max Unit

D Supply voltage VDDA 2.7 — 5.5 V

T Supply current (Operation mode) IDDA — 10 20 µA

D Analog input voltage VAIN VSS - 0.3 — VDDA V

P Analog input offset voltage VAIO — — 40 mV

C Analog comparator hysteresis (HYST=0) VH— 15 20 mV

C Analog comparator hysteresis (HYST=1) VH— 20 30 mV

T Supply current (Off mode) IDDAOFF — 60 — nA

C Propagation Delay tD— 0.4 1 µs

6.4 Communication interfaces

6.4.1 SPI switching specifications

The serial peripheral interface (SPI) provides a synchronous serial bus with master and

slave operations. Many of the transfer attributes are programmable. The following tables

provide timing characteristics for classic SPI timing modes. Refer to the SPI chapter of

the chip's reference manual for information about the modified transfer formats used for

communicating with slower peripheral devices. All timing is shown with respect to 20%

VDD and 70% VDD, unless noted, and 100 pF load on all SPI pins. All timing assumes

slew rate control is disabled and high drive strength is enabled for SPI output pins.

Table 14. SPI master mode timing

Symbol Description Min. Max. Unit Comment

1 fop Frequency of operation fBus/2048 fBus/2 Hz fBus is the bus

clock

2 tSPSCK SPSCK period 2 x tBus 2048 x tBus ns tBus = 1/fBus

3 tLead Enable lead time 1/2 — tSPSCK —

4 tLag Enable lag time 1/2 — tSPSCK —

5 tWSPSCK Clock (SPSCK) high or low time tBus - 30 1024 x tBus ns —

6 tSU Data setup time (inputs) 15 — ns —

7 tHI Data hold time (inputs) 0 — ns —

8 tvData valid (after SPSCK edge) — 25 ns —

9 tHO Data hold time (outputs) 0 — ns —

Table continues on the next page...

Peripheral operating requirements and behaviors

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

26 Freescale Semiconductor, Inc.

Table 14. SPI master mode timing (continued)

Symbol Description Min. Max. Unit Comment

10 tRI Rise time input — tBus - 25 ns —

tFI Fall time input

11 tRO Rise time output — 25 ns —

tFO Fall time output

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

SS1

(OUTPUT)

6 7

MSB IN2

BIT 6 . . . 1

LSB IN

MSB OUT2LSB OUT

BIT 6 . . . 1

(CPOL 0)

(CPOL 1)

SPSCK

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

1. If configured as an output.

Figure 17. SPI master mode timing (CPHA=0)

<<CLASSIFICATION>>

<<NDA MESSAGE>>

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

6 7

MSB IN2

BIT 6 . . . 1

LSB IN

MASTER MSB OUT MASTER LSB OUT

BIT 6 . . . 1

10 11

PORT DATA

(CPOL 0)

(CPOL 1)

PORT DATA

SS1

(OUTPUT)

310 11 4

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

SPSCK

Figure 18. SPI master mode timing (CPHA=1)

Peripheral operating requirements and behaviors

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 27

Table 15. SPI slave mode timing

Symbol Description Min. Max. Unit Comment

1 fop Frequency of operation 0 fBus/4 Hz fBus is the bus clock as

defined in .

2 tSPSCK SPSCK period 4 x tBus — ns tBus = 1/fBus

3 tLead Enable lead time 1 — tBus —

4 tLag Enable lag time 1 — tBus —

5 tWSPSCK Clock (SPSCK) high or low time tBus - 30 — ns —

6 tSU Data setup time (inputs) 15 — ns —

7 tHI Data hold time (inputs) 25 — ns —

8 taSlave access time — tBus ns Time to data active from

high-impedance state

9 tdis Slave MISO disable time — tBus ns Hold time to high-

impedance state

10 tvData valid (after SPSCK edge) — 25 ns —

11 tHO Data hold time (outputs) 0 — ns —

12 tRI Rise time input — tBus - 25 ns —

tFI Fall time input

13 tRO Rise time output — 25 ns —

tFO Fall time output

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

(INPUT)

6 7

MSB IN

BIT 6 . . . 1

LSB IN

SLAVE MSB SLAVE LSB OUT

BIT 6 . . . 1

(CPOL 0)

(CPOL 1)

NOTE: Not defined

SEE

NOTE

see

note

SPSCK

Figure 19. SPI slave mode timing (CPHA = 0)

Peripheral operating requirements and behaviors

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

28 Freescale Semiconductor, Inc.

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

6 7

MSB IN

BIT 6 . . . 1

LSB IN

MSB OUT SLAVE LSB OUT

BIT 6 . . . 1

12 13

(CPOL 0)

(CPOL 1)

(INPUT)

312 13

NOTE: Not defined

SLAVE

see

note

SPSCK

Figure 20. SPI slave mode timing (CPHA=1)

6.5 Human-machine interfaces (HMI)

6.5.1 TSI electrical specifications

Table 16. TSI electrical specifications

Symbol Description Min. Type Max Unit

TSI_RUNF Fixed power consumption in run mode — 100 — µA

TSI_RUNV Variable power consumption in run mode

(depends on oscillator's current selection)

1.0 — 128 µA

TSI_EN Power consumption in enable mode — 100 — µA

TSI_DIS Power consumption in disable mode — 1.2 — µA

TSI_TEN TSI analog enable time — 66 — µs

TSI_CREF TSI reference capacitor — 1.0 — pF

TSI_DVOLT Voltage variation of VP & VM around nominal

values

-10 — 10 %

Dimensions

7.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

Dimensions

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 29

To find a package drawing, go to freescale.com and perform a keyword search for the

drawing’s document number:

If you want the drawing for this package Then use this document number

32-pin LQFP 98ASH70029A

48-pin LQFP 98ASH00962A

64-pin LQFP 98ASS23234W

Pinout

8.1 Signal multiplexing and pin assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control Module is responsible

for selecting which ALT functionality is available on each pin.

Table 17. Pin availability by package pin-count

Pin Number Lowest Priority <-- --> Highest

64-LQFP 48-LQFP 32-LQFP Port Pin Alt 1 Alt 2 Alt 3 Alt 4

1 1 1 PTD11, 1KBI1P1 FTM2CH3 MOSI1 —

2 2 2 PTD01KBI1P0 FTM2CH2 SPSCK1 —

3 — — PTH7 — — — —

4 — — PTH6 — — — —

5 3 — PTE7 — TCLK2 — —

6 4 — PTH2 — BUSOUT — —

7 5 3 — — — — VDD

8 6 4 — — — VDDA VREFH

9 7 5 — — — VSSA VREFL

10 8 6 — — — — VSS

11 9 7 PTB7 — SCL — EXTAL

12 10 8 PTB6 — SDA — XTAL

13 11 — — — — — VSS

14 — — PTH11— FTM2CH1 — —

15 — — PTH01— FTM2CH0 — —

16 12 — PTE6 — — — —

17 13 — PTE5 — — — —

18 14 9 PTB51FTM2CH5 SS0 — —

19 15 10 PTB41FTM2CH4 MISO0 — —

Table continues on the next page...

Pinout

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

30 Freescale Semiconductor, Inc.

Table 17. Pin availability by package pin-count (continued)

Pin Number Lowest Priority <-- --> Highest

64-LQFP 48-LQFP 32-LQFP Port Pin Alt 1 Alt 2 Alt 3 Alt 4

20 16 11 PTC3 FTM2CH3 — ADP11 —

21 17 12 PTC2 FTM2CH2 — ADP10 —

22 18 — PTD7 KBI1P7 TXD2 — —

23 19 — PTD6 KBI1P6 RXD2 — —

24 20 — PTD5 KBI1P5 — — —

25 21 13 PTC1 — FTM2CH1 ADP9 TSI7

26 22 14 PTC0 — FTM2CH0 ADP8 TSI6

27 — — PTF7 — — ADP15 —

28 — — PTF6 — — ADP14 —

29 — — PTF5 — — ADP13 —

30 — — PTF4 — — ADP12 —

31 23 15 PTB3 KBI0P7 MOSI0 ADP7 TSI5

32 24 16 PTB2 KBI0P6 SPSCK0 ADP6 TSI4

33 25 17 PTB1 KBI0P5 TXD0 ADP5 TSI3

34 26 18 PTB0 KBI0P4 RXD0 ADP4 TSI2

35 — — PTF3 — — — TSI15

36 — — PTF2 — — — TSI14

37 27 19 PTA7 FTM2FAULT2 — ADP3 TSI1

38 28 20 PTA6 FTM2FAULT1 — ADP2 TSI0

39 29 — PTE4 — — — —

40 30 — — — — — VSS

41 31 — — — — — VDD

42 — — PTF1 — — — TSI13

43 — — PTF0 — — — TSI12

44 32 — PTD4 KBI1P4 — — —

45 33 21 PTD3 KBI1P3 SS1 — TSI11

46 34 22 PTD2 KBI1P2 MISO1 — TSI10

47 35 23 PTA32, 2KBI0P3 TXD0 SCL —

48 36 24 PTA22KBI0P2 RXD0 SDA —

49 37 25 PTA1 KBI0P1 FTM0CH1 ACMP1 ADP1

50 38 26 PTA0 KBI0P0 FTM0CH0 ACMP0 ADP0

51 39 27 PTC7 — TxD1 — TSI9

52 40 28 PTC6 — RxD1 — TSI8

53 41 — PTE3 — SS0 — —

54 42 — PTE2 — MISO0 — —

55 — — PTG3 — — — —

56 — — PTG2 — — — —

57 — — PTG1 — — — —

Table continues on the next page...

Pinout

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 31

Table 17. Pin availability by package pin-count (continued)

Pin Number Lowest Priority <-- --> Highest

64-LQFP 48-LQFP 32-LQFP Port Pin Alt 1 Alt 2 Alt 3 Alt 4

58 — — PTG0 — — — —

59 43 — PTE11— MOSI0 — —

60 44 — PTE01— SPSCK0 TCLK1 —

61 45 29 PTC5 — FTM1CH1 — —

62 46 30 PTC4 — FTM1CH0 RTCO —

63 47 31 — — — — RESET

64 48 32 — — — BKGD MS

1. This is a high current drive pin when operated as output.

2. This is a true open-drain pin when operated as output.

Note

When an alternative function is first enabled, it is possible to

get a spurious edge to the module. User software must clear any

associated flags before interrupts are enabled. The table above

illustrates the priority if multiple modules are enabled. The

highest priority module will have control over the pin. Selecting

a higher priority pin function with a lower priority function

already enabled can cause spurious edges to the lower priority

module. Disable all modules that share a pin before enabling

another module.

Pinout

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

32 Freescale Semiconductor, Inc.

8.2 Device pin assignment

PTF0/TSI12

PTF2/TSI14

PTB1/KBI0P5/TxD0/ADP5/TSI3

PTB2/KBI0P6/SPSCK0/ADP6/TSI4

PTF6/ADP14

PTC3/FTM2CH3/ADP11

2. True open drain pins

PTE6

PTG3

PTF1/TSI13

PTF3/TSI15

PTB0/KBI0P4/RxD0/ADP4/TSI2

PTB3/KBI0P7/MOSI0/ADP7/TSI5

PTF4/ADP12

PTF5/ADP13

PTF7/ADP15

PTA7/FTM2FAULT2/ADP3/TSI1

PTA6/FTM2FAULT1/ADP2/TSI0

PTE4

VSS

VDD

PTD4/KBI1P4

PTD3/KBI1P3/SS1/TSI11

PTD2/KBI1P2/MISO1/TSI10

PTA3/KBI0P3/TxD0/SCL2

PTA2/KBI0P2/RxD0/SDA2

PTG0

PTG2

PTG1

PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1

PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0

PTC7/TxD1/TSI9

PTC6/RxD1/TSI8

PTE3/SS0

PTE2/MISO0

PTE1/MOSI01

PTE0/SPSCK0/TCLK11

PTC5/FTM1CH1

PTC4/FTM1CH0/RTCO

RESET

BKGD/MS

PTD1/KBI1P1/FTM2CH3/MOSI11

PTD0/KBI1P0/FTM2CH2/SPSCK11

PTH7

PTH6

PTE7/TCLK2

PTH2/BUSOUT

VDD

VDDA /VREFH

VSSA /VREFL

VSS

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

PTH1/FTM2CH11

PTH0/FTM2CH01

PTE5

PTB5/FTM2CH5/SS01

PTB4/FTM2CH4/MISO01

PTC2/FTM2CH2/ADP10

PTD7/KBI1P7/TxD2

PTD6/KBI1P6/RxD2

PTD5/KBI1P5

PTC1/FTM2CH1/ADP9/TSI7

PTC0/FTM2CH0/ADP8/TSI6

1. High source/sink current pins

Pins in bold are not available on less pin-count packages.

Figure 21. S9S08RN60 64-pin LQFP package

Pinout

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 33

PTB1/KBI0P5/TxD0/ADP5/TSI3

PTB2/KBI0P6/SPSCK0/ADP6/TSI4

PTC3/FTM2CH3/ADP11

2. True open drain pins

PTE6

PTB0/KBI0P4/RxD0/ADP4/TSI2

PTB3/KBI0P7/MOSI0/ADP7/TSI5

PTA7/FTM2FAULT2/ADP3/TSI1

PTA6/FTM2FAULT1/ADP2/TSI0

PTE4

VSS

VDD

PTD4/KBI1P4

PTD3/KBI1P3/SS1/TSI11

PTD2/KBI1P2/MISO1/TSI10

PTA3/KBI0P3/TxD0/SCL2

PTA2/KBI0P2/RxD0/SDA2

PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1

PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0

PTC7/TxD1/TSI9

PTC6/RxD1/TSI8

PTE3/SS0

PTE2/MISO0

PTE1/MOSI01

PTE0/SPSCK0/TCLK11

PTC5/FTM1CH1

PTC4/FTM1CH0/RTCO

RESET

BKGD/MS

PTD1/KBI1P1/FTM2CH3/MOSI11

PTD0/KBI1P0/FTM2CH2/SPSCK11

PTE7/TCLK2

PTH2/BUSOUT

VDD

VDDA /VREFH

VSSA /VREFL

VSS

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

PTE5

PTB5/FTM2CH5/SS01

PTB4/FTM2CH4/MISO01

PTC2/FTM2CH2/ADP10

PTD7/KBI1P7/TxD2

PTD6/KBI1P6/RxD2

PTD5/KBI1P5

PTC1/FTM2CH1/ADP9/TSI7

PTC0/FTM2CH0/ADP8/TSI6

1. High source/sink current pins

Pins in bold are not available on less pin-count packages.

Figure 22. S9S08RN60 48-pin LQFP package

Pinout

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

34 Freescale Semiconductor, Inc.

PTB1/KBI0P5/TxD0/ADP5/TSI3

PTB2/KBI0P6/SPSCK0/ADP6/TSI4

PTC3/FTM2CH3/ADP11

2. True open drain pins

PTB0/KBI0P4/RxD0/ADP4/TSI2

PTB3/KBI0P7/MOSI0/ADP7/TSI5

PTA7/FTM2FAULT2/ADP3/TSI1

PTA6/FTM2FAULT1/ADP2/TSI0

PTD3/KBI1P3/SS1/TSI11

PTD2/KBI1P2/MISO1/TSI10

PTA2/KBI0P2/RxD0/SDA2

PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1

PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0

PTC7/TxD1/TSI9

PTC6/RxD1/TSI8

PTC5/FTM1CH1

PTC4/FTM1CH0/RTCO

RESET

BKGD/MS

PTD1/KBI1P1/FTM2CH3/MOSI11

PTD0/KBI1P0/FTM2CH2/SPSCK11

VDD

VDDA /VREFH

VSSA /VREFL

VSS

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

PTB5/FTM2CH5/SS01

PTB4/FTM2CH4/MISO01

PTC2/FTM2CH2/ADP10

PTC1/FTM2CH1/ADP9/TSI7

PTC0/FTM2CH0/ADP8/TSI6

1. High source/sink current pins

PTA3/KBI0P3/TxD0/SCL2

Figure 23. S9S08RN60 32-pin LQFP package

9 Revision history

The following table provides a revision history for this document.

Table 18. Revision history

Rev. No. Date Substantial Changes

1 01/2014 Initial Release

Revision history

S9S08RN60 Series Data Sheet Data Sheet, Rev. 1, 01/2014.

Freescale Semiconductor, Inc. 35

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Document Number: S9S08RN60

Rev. 1, 01/2014

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