CAT24C256XI-G - ON Semiconductor L.L.C.

Characteristics subject to change without notice Doc. No. MD-1104, Rev. G

256-Kb I2C CMOS Serial EEPROM

CAT24C256

PIN CONFIGURATION FUNCTIONAL SYMBOL

FEATURES

■ Supports Standard and Fast I2C Protocol

■ 1.8V to 5.5V Supply Voltage Range

■ 64-Byte Page Write Buffer

■ Hardware Write Protection for entire memory

■ Schmitt Triggers and Noise Suppression Filters

on I2C Bus Inputs (SCL and SDA).

■ Low power CMOS technology

■ 1,000,000 program/erase cycles

■ 100 year data retention

■ Industrial temperature range

■ RoHS-compliant 8-pin PDIP, SOIC, TSSOP and

8-pad TDFN packages

PDIP (L)

SOIC (W, X)

TSSOP (Y)

TDFN (ZD2)

VCC

VSS

SCL

CAT24C256

A2, A1, A0

DEVICE DESCRIPTION

The CAT24C256 is a 256-Kb Serial CMOS EEPROM,

internally organized as 32,768 words of 8 bits each.

It features a 64-byte page write buffer and supports

both the Standard (100kHz) as well as Fast (400kHz)

I2C protocol.

Write operations can be inhibited by taking the WP pin

High (this protects the entire memory).

External address pins make it possible to address up to

eight CAT24C256 devices on the same bus.

VCC

SCL

SDA

VSS

For the location of Pin 1, please consult the

corresponding package drawing.

PIN FUNCTIONS

A0, A1, A2Device Address

SDA Serial Data

SCL Serial Clock

WP Write Protect

VCC Power Supply

VSS Ground * Catalyst carries the I2C protocol under a license from the Philips Corporation.

For Ordering Information details, see page 15.

CAT24C256

Characteristics subject to change without notice

ABSOLUTE MAXIMUM RATINGS(1)

Storage Temperature -65°C to +150°C

Voltage on Any Pin with Respect to Ground(2) -0.5 V to +6.5 V

RELIABILITY CHARACTERISTICS(3)

Symbol Parameter Min Units

NEND(4) Endurance 1,000,000 Program/ Erase Cycles

TDR Data Retention 100 Years

D.C. OPERATING CHARACTERISTICS

VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise speciﬁ ed.

Symbol Parameter Test Conditions Min Max Units

ICC Supply Current Read or Write at 400kHz 1 mA

ISB Standby Current All I/O Pins at GND or VCC 1μA

ILI/O Pin Leakage Pin at GND or VCC 1μA

VIL Input Low Voltage -0.5 VCC x 0.3 V

VIH Input High Voltage VCC x 0.7 VCC + 0.5 V

VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0mA 0.4 V

VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0mA 0.2 V

PIN IMPEDANCE CHARACTERISTICS

VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise speciﬁ ed.

Symbol Parameter Conditions Min Max Units

CIN(3) SDA I/O Pin Capacitance VIN = 0V 8 pF

CIN(3) Input Capacitance (other pins) VIN = 0V 6 pF

IWP(5) WP Input Current

(CAT24C256 Rev. C - New Product) VIN < VIH, VCC = 5.5V 200

μA

VIN < VIH, VCC = 3.3V 150

VIN < VIH, VCC = 1.8V 100

VIN > VIH 1

Notes:

(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this

speciﬁ cation is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may

undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20 ns.

(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100

and JEDEC test methods.

(4) Page Mode, VCC = 5V, 25°C

(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;

therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,

as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.

The variable WP input impedance is available only for Die Rev. C, New Product.

CAT24C256

3Doc No. MD-1104, Rev. G

Characteristics subject to change without notice

A.C. CHARACTERISTICS(1)

VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise speciﬁ ed.

Symbol Parameter Standard Fast UnitsMin Max Min Max

FSCL Clock Frequency 100 400 kHz

tHD:STA START Condition Hold Time 4 0.6 μs

tLOW Low Period of SCL Clock 4.7 1.3 μs

tHIGH High Period of SCL Clock 4 0.6 μs

tSU:STA START Condition Setup Time 4.7 0.6 μs

tHD:DAT Data In Hold Time 0 0 μs

tSU:DAT Data In Setup Time 250 100 ns

tR(2) SDA and SCL Rise Time 1000 300 ns

tF(2) SDA and SCL Fall Time 300 300 ns

tSU:STO STOP Condition Setup Time 4 0.6 μs

tBUF Bus Free Time Between STOP and START 4.7 1.3 μs

tAA SCL Low to Data Out Valid 3.5 0.9 μs

tDH Data Out Hold Time 100 100 ns

Ti(2) Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns

tSU:WP WP Setup Time 0 0 μs

tHD:WP WP Hold Time 2.5 2.5 μs

tWR Write Cycle Time 5 5 ms

tPU(2, 3) Power-up to Ready Mode 1 1 ms

Notes:

(1) Test conditions according to “A.C. Test Conditions” table.

(2) Tested initially and after a design or process change that affects this parameter.

(3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.

A.C. TEST CONDITIONS

Input Levels 0.2 x VCC to 0.8 x VCC

Input Rise and Fall Times ≤ 50ns

Input Reference Levels 0.3 x VCC, 0.7 x VCC

Output Reference Levels 0.5 x VCC

Output Load Current Source: IOL = 3mA (VCC ≥ 2.5V); IOL = 1 mA (VCC < 2.5V); CL = 100pF

CAT24C256

Characteristics subject to change without notice

POWER-ON RESET (POR)

The CAT24C256 Die Rev. C incorporates Power-On

Reset (POR) circuitry which protects the internal logic

against powering up in the wrong state.

The device will power up into Standby mode after VCC

exceeds the POR trigger level and will power down

into Reset mode when VCC drops below the POR

trigger level. This bi-directional POR feature protects

the device against ‘brown-out’ failure following a tem-

porary loss of power.

PIN DESCRIPTION

SCL: The Serial Clock input pin accepts the Serial Clock

generated by the Master.

SDA: The Serial Data I/O pin receives input data and

transmits data stored in EEPROM. In transmit mode, this

pin is open drain. Data is acquired on the positive edge,

and is delivered on the negative edge of SCL.

A0, A1 and A2: The Address pins accept the device ad-

dress. These pins have on-chip pull-down resistors.

WP: The Write Protect input pin inhibits all write op-

erations, when pulled HIGH. This pin has an on-chip

pull-down resistor.

FUNCTIONAL DESCRIPTION

The CAT24C256 supports the Inter-Integrated Circuit

(I2C) Bus data transmission protocol, which deﬁ nes a

device that sends data to the bus as a transmitter and a

device receiving data as a receiver. Data ﬂ ow is controlled

by a Master device, which generates the serial clock

and all START and STOP conditions. The CAT24C256

acts as a Slave device. Master and Slave alternate as

either transmitter or receiver. Up to 8 devices may be

connected to the bus as determined by the device ad-

dress inputs A0, A1, and A2.

I2C BUS PROTOCOL

The I2C bus consists of two ‘wires’, SCL and SDA. The

two wires are connected to the VCC supply via pull-up

resistors. Master and Slave devices connect to the 2-

wire bus via their respective SCL and SDA pins. The

transmitting device pulls down the SDA line to ‘transmit’

a ‘0’ and releases it to ‘transmit’ a ‘1’.

Data transfer may be initiated only when the bus is not

busy (see A.C. Characteristics).

During data transfer, the SDA line must remain stable

while the SCL line is HIGH. An SDA transition while

SCL is HIGH will be interpreted as a START or STOP

condition (Figure 1).

START

The START condition precedes all commands. It consists

of a HIGH to LOW transition on SDA while SCL is HIGH.

The START acts as a ‘wake-up’ call to all receivers. Absent

a START, a Slave will not respond to commands.

STOP

The STOP condition completes all commands. It consists

of a LOW to HIGH transition on SDA while SCL is HIGH.

The STOP starts the internal Write cycle (when follow-

ing a Write command) or sends the Slave into standby

mode (when following a Read command).

Device Addressing

The Master initiates data transfer by creating a START

condition on the bus. The Master then broadcasts an

8-bit serial Slave address. The ﬁ rst 4 bits of the Slave

address are set to 1010, for normal Read/Write opera-

tions (Figure 2). The next 3 bits, A2, A1 and A0, select

one of 8 possible Slave devices. The last bit, R/W,

speciﬁ es whether a Read (1) or Write (0) operation is

to be performed.

Acknowledge

After processing the Slave address, the Slave responds

with an acknowledge (ACK) by pulling down the SDA

line during the 9th clock cycle (Figure 3). The Slave will

also acknowledge the byte address and every data

byte presented in Write mode. In Read mode the Slave

shifts out a data byte, and then releases the SDA line

during the 9th clock cycle. If the Master acknowledges

the data, then the Slave continues transmitting. The

Master terminates the session by not acknowledging

the last data byte (NoACK) and by sending a STOP to

the Slave. Bus timing is illustrated in Figure 4.

CAT24C256

5Doc No. MD-1104, Rev. G

Characteristics subject to change without notice

Figure 3. Acknowledge Timing

Figure 2. Slave Address Bits

Figure 1. Start/Stop Timing

Figure 4. Bus Timing

1010

DEVICE ADDRESS

A2A1A0R/W

START

CONDITION

STOP

CONDITION

SDA

SCL

189

START

SCL FROM

MASTER

BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER)

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ACK DELAY (≤ tAA)

ACK SETUP (≥ tSU:DAT)

tHIGH

SCL

SDA IN

SDA OUT

tLOW

tBUF

tSU:STO

tSU:DAT

tHD:DAT

tHD:STA

tSU:STA

tAA tDH

CAT24C256

Characteristics subject to change without notice

WRITE OPERATIONS

Byte Write

In Byte Write mode the Master sends a ST ART, followed

by Slave address, two byte address and data to be

written (Figure 5). The Slave acknowledges all 4 bytes,

and the Master then follows up with a STOP, which in

turn starts the internal Write operation (Figure 6). During

internal Write, the Slave will not acknowledge any Read

or Write request from the Master.

Page Write

The CAT24C256 contains 32,768 bytes of data, arranged

in 512 pages of 64 bytes each. A two byte address word,

following the Slave address, points to the ﬁ rst byte to be

written. The most signiﬁ cant bit of the address word is

‘don’t care’, the next 9 bits identify the page and the last

6 bits identify the byte within the page. Up to 64 bytes

can be written in one Write cycle (Figure 7).

The internal byte address counter is automatically in-

cremented after each data byte is loaded. If the Master

transmits more than 64 data bytes, then earlier bytes will

be overwritten by later bytes in a ‘wrap-around’ fashion

(within the selected page). The internal Write cycle starts

immediately following the STOP.

Acknowledge Polling

Acknowledge polling can be used to determine if the

CAT24C256 is busy writing or is ready to accept com-

mands. Polling is implemented by interrogating the

device with a ‘Selective Read’ command (see READ

OPERATIONS).

The CAT24C256 will not acknowledge the Slave address,

as long as internal Write is in progress.

Hardware Write Protection

With the WP pin held HIGH, the entire memory is pro-

tected against Write operations. If the WP pin is left ﬂ oating

or is grounded, it has no impact on the operation of the

CAT24C256. The state of the WP pin is strobed on the

last falling edge of SCL immediately preceding the ﬁ rst

data byte (Figure 8). If the WP pin is HIGH during the

strobe interval, the CAT24C256 will not acknowledge the

data byte and the Write request will be rejected.

Delivery State

The CAT24C256 is shipped erased, i.e., all bytes are

FFh.

CAT24C256

7Doc No. MD-1104, Rev. G

Characteristics subject to change without notice

Figure 7. Page Write Timing

Figure 6. Write Cycle Timing

A15–A8

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

TA7–A0

BYTE ADDRESS

DATA n+63DATA

DATA n

= Don't Care Bit

tWR

STOP

CONDITION

START

CONDITION

ADDRESS

ACK8th Bit

Byte n

SCL

SDA

Figure 5. Byte Write Timing

A15–A8

SLAVE

ADDRESS

DATA

BUS ACTIVITY:

MASTER

SDA LINE

TA7–A0

BYTE ADDRESS

= Don't Care Bit

Figure 8. WP Timing

1891 8

a7a0d7d0

tSU:WP

tHD:WP

ADDRESS

BYTE DATA

BYTE

SCL

SDA

CAT24C256

Characteristics subject to change without notice

READ OPERATIONS

Immediate Address Read

In standby mode, the CAT24C256 internal address

counter points to the data byte immediately following the

last byte accessed by a previous operation. If that ‘previ-

ous’ byte was the last byte in memory , then the address

counter will point to the 1st memory byte, etc.

When, following a ST ART , the CA T24C256 is presented

with a Slave address containing a ‘1’ in the R/W bit

position (Figure 9), it will acknowledge (ACK) in the 9th

clock cycle, and will then transmit data being pointed

at by the internal address counter . The Master can stop

further transmission by issuing a NoACK, followed by a

STOP condition.

Selective Read

The Read operation can also be started at an address

different from the one stored in the internal address

counter. The address counter can be initialized by per-

forming a ‘dummy’ Write operation (Figure 10). Here the

START is followed by the Slave address (with the R/W

bit set to ‘0’) and the desired two byte address. Instead

of following up with data, the Master then issues a 2nd

START, followed by the ‘Immediate Address Read’ se-

quence, as described earlier.

Sequential Read

If the Master acknowledges the 1st data byte transmitted

by the CAT24C256, then the device will continue trans-

mitting as long as each data byte is acknowledged by

the Master (Figure 11). If the end of memory is reached

during sequential Read, then the address counter will

‘wrap-around’ to the beginning of memory, etc. Sequential

Read works with either ‘Immediate Address Read’ or

‘Selective Read’, the only difference being the starting

byte address.

CAT24C256

9Doc No. MD-1104, Rev. G

Characteristics subject to change without notice

Figure 11. Sequential Read Timing

BUS ACTIVITY :

MASTER

SDA LINE

DATA n+xDATA n

DATA n+1

DATA n+2

SLAVE

ADDRESS

Figure 10. Selective Read Timing

A15– A8

SLAVE

ADDRESS

BUS ACTIVITY :

MASTER

SDA LINE

TA7– A0

BYTE ADDRESS SLAVE

ADDRESS

TDATA

* = Don't Care Bit

Figure 9. Immediate Address Read Timing

SCL

SDA 8th Bit

STOPNO ACKDATA OUT

SLAVE

ADDRESS

KDATA N

BUS ACTIVITY :

MASTER

SDA LINE

CAT24C256

Characteristics subject to change without notice

PDIP 8-Lead 300 mils (L)

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MS-001.

PDIP 8-Lead 300mils (L)

SYMBOL MIN NOM MAX

A 5.33

A1 0.38

A2 2.92 3.30 4.95

b 0.36 0.46 0.56

b2 1.14 1.52 1.78

c 0.20 0.25 0.36

D 9.02 9.27 10.16

E 7.62 7.87 8.25

e 2.54 BSC

E1 6.10 6.35 7.11

eB 7.87 10.92

L 2.92 3.30 3.80

For current Tape and Reel information, download the PDF ﬁ le from:

http://www.catsemi.com/documents/tapeandreel.pdf

PACKAGE OUTLINE DRAWINGS

CAT24C256

11 Doc No. MD-1104, Rev. G

Characteristics subject to change without notice

SOIC 8-Lead 150 mils (W)

Notes:

(1) Complies with JEDEC speciﬁ cation MS-012 dimensions.

(2) All linear dimensions are in millimeters.

E1 E

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW END VIEW

A 1.35 1.75

A1 0.10 0.25

b 0.33 0.51

c 0.19 0.25

D 4.80 5.00

E 5.80 6.20

E1 3.80 4.00

e 1.27 BSC

h 0.25 0.50

L 0.40 1.27

θ 0º 8º

SYMBOL MIN NOM MAX

For current Tape and Reel information, download the PDF ﬁ le from:

http://www.catsemi.com/documents/tapeandreel.pdf

CAT24C256

Characteristics subject to change without notice

SOIC 8-Lead 208 mils (X)

Notes:

(1) Complies with EIAJ speciﬁ cation.

(2) All linear dimensions are in millimeters.

For current Tape and Reel information, download the PDF ﬁ le from:

http://www.catsemi.com/documents/tapeandreel.pdf

SIDE VIEW

TOP VIEW

PIN#1 IDENTIFICATION

END VIEW

SYMBOL MIN NOM MAX

A 2.03

A1 0.05 0.25

b 0.36 0.48

c 0.19 0.25

D 5.13 5.33

E 7.75 8.26

E1 5.13 5.38

e 1.27 BSC

L 0.51 0.76

θ 0º 8º

CAT24C256

13 Doc No. MD-1104, Rev. G

Characteristics subject to change without notice

TSSOP 8-Lead 4.4mm (Y)

E1 E

TOP VIEW

SIDE VIEW END VIEW

θ1

L1 L

SYMBOL MIN NOM MAX

A 1.20

A1 0.05 0.15

A2 0.80 0.90 1.05

b 0.19 0.30

c 0.09 0.20

D 2.90 3.00 3.10

E 6.30 6.40 6.50

E1 4.30 4.40 4.50

e 0.65 BSC

L 1.00 REF

L1 0.50 0.60 0.75

θ1 0° 8°

For current Tape and Reel information, download the PDF ﬁ le from:

http://www.catsemi.com/documents/tapeandreel.pdf

Notes:

(1) All dimensions are in milimiters. Angles in degrees

(2) Complies with JEDEC MO-153.

CAT24C256

Characteristics subject to change without notice

TDFN 8-Pad 3 x 4.9mm (ZD2)

For current Tape and Reel information, download the PDF ﬁ le from:

http://www.catsemi.com/documents/tapeandreel.pdf

PIN #1

IDENTIFICATION

PIN #1 IDENTIFICATION

DAP SIZE

2.6 x 3.3mm

DET AIL A

A3A1

TOP VIEW SIDE VIEW BOTTOM VIEW

FRONT VIEW

DET AIL A

SYMBOL MIN NOM MAX

A 0.70 0.75 0.80

A1 0.00 0.02 0.05

A2 0.45 0.55 0.65

A3 0.20 REF

b 0.25 0.30 0.35

D 2.90 3.00 3.10

D2 0.90 1.00 1.10

E 4.80 4.90 5.00

E2 0.90 1.00 1.10

e 0.65 TYP

L 0.50 0.60 0.70

Notes:

(1) All dimensions are in milimiters.

(2) Complies with JEDEC MO-229.

CAT24C256

15 Doc No. MD-1104, Rev. G

Characteristics subject to change without notice

ORDERING INFORMATION

Notes:

(1) All packages are RoHS-compliant (Lead-free, Halogen-free).

(2) The standard lead ﬁ nish is NiPdAu.

(3) The device used in the above example is a CAT24C256WI-GT3 (SOIC-JEDEC, Industrial Temperature, NiPdAu, Tape & Reel).

(4) For SOIC, EIAJ (X) package the standard lead ﬁ nish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT24C256XI-T2.

(5) The TDFN 3x4.9mm (ZD2) package is available in 2000 pcs/reel, i.e., CAT24C256ZD2I-GT2.

(6) For additional package and temperature options, please contact your nearest ON Semiconductor Sales ofﬁ ce.

Prefix Device # Suffix

24C256 WI

Product

Number

CAT

Temperature Range

I = Industrial (-40°C to +85°C)

Company ID

Package

L: PDIP

W: SOIC, JEDEC

X: SOIC, EIAJ(4)

Y: TSSOP

ZD2: TDFN (3x4.9mm)(5)

G—

Lead Finish

Blank: Matte-Tin(4)

G: NiPdAu

Tape & Reel

T: Tape & Reel

2: 2000/Reel(4)(5)

3: 3000/Reel

CAT24C256

Characteristics subject to change without notice

REVISION HISTORY

Date Revision Comments

10/07/05 A Initial Issue

11/16/05 B Update Ordering Information

Add Tape and Reel Speciﬁ cations

02/02/06 C Update Ordering Information

01/12/07 D

Update Package Outlines. Add SOIC, EIAJ Package Outlines

Update A.C. Characteristics. Add A.C. Test Conditions

Update Figures 1, 3 and 4

Delete Package Marking. Deleted Tape and Reel

Update Ordering Information

05/08/07 E

Update Features/Packages

Update Pin Conﬁ guration

Update Pin Impedance Characteristics

Add Power-On Reset (POR) text

Update Hardware Write Protection

Add WP Timing (Figure 8) (Renumbered Figures 9 & 11)

Add 8-Lead TSSOP Package Outline

Add 8-pad TDFN 3x4.9mm Package Outline

Updated Ordering Information

08/15/07 F Updated PDIP, SOIC, TSSOP, and TDFN Package Outline Drawings

12-Oct-08 G Updated SOIC 8L, 208mil, Package Outline Drawing

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