CY62146ESL MoBL
4-Mbit (256K x 16) St atic RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-43142 Rev. *C Revised June 29, 201 1
Features
■Very high speed : 45 ns
■Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■Ultra low standby power
❐Typical Standby current: 1 A
❐Maximum Standby current: 7 A
■Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■Easy memory expansion with CE and OE features
■Automati c power down when deselected
■Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■Available in Pb-free 44-pin thin small outline package (TSOP) II
package
Functional Description
The CY62146ESL is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
when addresses are not toggling. Placing the device into standby
mode reduces power consumptio n by more than 99% when
deselected (CE HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when the device is
deselected (CE HIGH), the outputs are disabled (OE HIGH),
both Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH) or during a write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the “T ruth Table” on page 11 for a
complete description of read and write modes.
256K x 16
RAM Array I/O0–I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8–I/O15
CE
WE
BHE
A16
A0
A1
A9
A10
BLE
A17
Logic Block Diagram
CY62146ESL MoBL
Document #: 001-43142 Rev. *C Page 2 of 15
Contents
Pin Configuration .............................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ............ ... .............. ... .............. ... ..............4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
Data Retention Characteristics .......................................6
Switching Characteristics ............................... ... ..............7
Switching Waveforms ....................... ... .............. ... ...........8
Truth Table ......................................................................11
Package Diagram ............................................................12
Ordering Information ......................................................12
Acronyms ........................................................................ 13
Document Conventions .......... ... .............. ... ... ................13
Units of Measure ................... ... .............. ... .. ..............13
Document History Page ................ .. ... ............................14
Sales, Solutions, and Legal Information ......................15
Worldwide Sales and Design Support ..................... ..15
Products ....................................................................15
PSoC Solutions .................. ... .............. ... ... .............. ..15
CY62146ESL MoBL
Document #: 001-43142 Rev. *C Page 3 of 15
Pin Configuration
Figure 1. 44-Pin TSOP II (Top View) [1]
Product Portfolio
Product Range VCC Range (V)[2] Speed
(ns)
Power Dissipation
Operating ICC, (mA) Standby, ISB2
(A)
f = 1MHz f = fmax
Typ[3] Max Typ[3] Max Typ [3] Max
CY62146ESL Industrial 2.2 V–3.6 V and 4.5 V–5.5 V 45 2 2.5 15 20 1 7
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15 29
30
A
5
18
17
20
19 27
28
25
26
22
21 23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
15
A
16
A
8
A
9
A
10
A
11
A
13
A
14
A
12
OE
BHE
BLE
CE
WE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
17
Notes
1. NC pins are not connected on the die.
2. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
CY62146ESL MoBL
Document #: 001-43142 Rev. *C Page 4 of 15
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature................................. –65 °C to +150 °C
Ambient temperature with
power applied. .......................................... –55 °C to +125 °C
Supply voltage to ground potential .................–0.5 V to 6.0 V
DC voltage applied to outputs
in High-Z S tate[4, 5] .........................................–0.5 V to 6.0 V
DC input voltage[4, 5].......................................–0.5 V to 6.0 V
Output current into outputs (LOW) ..............................20 mA
Static discharge voltage.............................................>2001V
(MIL-STD-883, Method 3015)
Latch up current.......................................................>200 mA
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typ i cal values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
8. Chip enable (CE) must be HIGH at CMOS lev el to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
Operating Range
Device Range Ambient
Temperature VCC[6]
CY62146ESL Industrial –40 °C to +85 °C 2.2 V–3.6 V ,
and
4.5 V–5.5 V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions 45 ns UnitMin Typ [7] Max
VOH Output high voltage 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 V
2.7 < VCC < 3.6 IOH = –1.0 mA 2.4
4.5 < VCC < 5.5 IOH = –1.0 mA 2.4
VOL Output low voltage 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 V
2.7 < VCC < 3.6 IOL = 2.1mA 0.4
4.5 < VCC < 5.5 IOL = 2.1mA 0.4
VIH Input high voltage 2.2 < VCC < 2.7 1.8 VCC + 0.3 V
2.7 < VCC < 3.6 2.2 VCC + 0.3
4.5 < VCC < 5.5 2.2 VCC + 0.5
VIL Input low voltage 2.2 < VCC < 2.7 –0.3 0.6 V
2.7 < VCC < 3.6 –0.3 0.8
4.5 < VCC < 5.5 –0.5 0.8
IIX Input Leakage Current GND < VI < VCC –1 +1 A
IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 A
ICC VCC Operating Supply
Current f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA, CMOS levels 15 20 mA
f = 1 MHz 2 2.5
ISB1[8] Automatic CE Power
down Current — CMOS
Inputs
CE > VCC 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (Address and Data Only), I/O
f = 0 (OE, BHE, BLE and WE), VCC = VCC(max)
17A
ISB2[8] Automatic CE Power
down Current — CMOS
Inputs
CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max) 17A
CY62146ESL MoBL
Document #: 001-43142 Rev. *C Page 5 of 15
Capacitance
Parameter[9] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz,
VCC = VCC(typ) 10 pF
COUT Output capacitance 10 pF
Thermal Resist ance
Parameter[9] Description Test Conditions TSOP II Unit
JA Thermal resistance
(Junction to ambient) Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board 77 C/W
JC Thermal resistance
(Junction to case) 13 C/W
Figure 2. AC Test Loads and Waveforms
Parameters 2.5 V 3.0 V 5.0 V Unit
R1 16667 1103 1800
R2 15385 1554 990
RTH 8000 645 639
VTH 1.20 1.75 1.77 V
VCC VCC
Output
R2
30 pF
Including
JIG and
Scope
GND 90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: Thé venin Equivalent
All Input Pulses
RTH
R1
TH
Note
9. Tested initially and after any design or process changes that may affect these parameters.
CY62146ESL MoBL
Document #: 001-43142 Rev. *C Page 6 of 15
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ[10] Max Unit
VDR VCC for data retention 1.5 V
ICCDR[11] Data retention current CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V VCC = 1.5 V 1 7 A
tCDR [12] Chip deselect to data
retention time 0ns
tR [13] Operation recovery time 45 ns
Figure 3. Data Retention Waveform
VCC(min)
VCC(min)
tCDR
VDR >1.5 V
DATA RETENTION MODE
tR
VCC
CE
Notes
10.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
11.Chip enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other input s can be left floating.
12.Tested initially and after any design or process changes that may affect these parameters.
13.Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
CY62146ESL MoBL
Document #: 001-43142 Rev. *C Page 7 of 15
Switching Characteristics
Over the Operating Range
Parameter[14] Description 45 ns Unit
Min Max
Read Cycle
tRC Read cycle time 45 ns
tAA Address to data valid 45 ns
tOHA Data hold from address change 10 ns
tACE CE LOW to data valid 45 ns
tDOE OE LOW to data valid 22 ns
tLZOE OE LOW to LOW-Z[15] 5ns
tHZOE OE HIGH to High-Z[15, 16] 18 ns
tLZCE CE LOW to Low-Z[15] 10 ns
tHZCE CE HIGH to High-Z[15, 16] 18 ns
tPU CE LOW to power up 0 ns
tPD CE HIGH to power down 45 ns
tDBE BLE/BHE LOW to data valid 22 ns
tLZBE BLE/BHE LOW to Low-Z[15] 5ns
tHZBE BLE/BHE HIGH to HIGH-Z[15, 16] 18 ns
Wr ite Cycle[17]
tWC Write cycle time 45 ns
tSCE CE LOW to write end 35 ns
tAW Address setup to write en d 35 ns
tHA Address hold from write end 0 ns
tSA Address setup to Write Start 0 ns
tPWE WE pulse width 35 ns
tBW BLE/BHE LOW to write end 35 ns
tSD Data Setup to write end 25 ns
tHD Data Hold from write end 0ns
tHZWE WE LOW to High-Z[15, 16] 18 ns
tLZWE WE HIGH to Low-Z[15] 10 ns
Notes
14.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of
0 to 3 V, and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 5.
15.At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE f or any device.
16.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measu r ed when the outputs enter a high-impedance state.
17.The internal write time o f the memory is defi ned by the overlap o f WE, CE = VIL, BHE , BLE or both = VIL. All signals must be active to initiate a writ e and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
CY62146ESL MoBL
Document #: 001-43142 Rev. *C Page 8 of 15
Switching Waveforms
Figure 4. Read Cycle No.1: Address Transition Controlled. [18, 19]
Figure 5. Read Cycle No. 2: OE Controlled [19, 20]
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGH IMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
Notes
18.The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
19.WE is HIGH for read cycle.
20.Address valid before or similar to CE, BHE, BLE transition LOW.
CY62146ESL MoBL
Document #: 001-43142 Rev. *C Page 9 of 15
Figure 6. Write Cycle No 1: WE Controlled [21, 22, 23]
Figure 7. Write Cycle 2: CE Controlled [21, 22, 23]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATAIN
NOTE 24
tBW
tSCE
DATA I/O
ADDRESS
CE
WE
OE
BHE/BLE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN
tBW
tSA
CE
ADDRESS
WE
DATA I/O
OE
BHE/BLE
NOTE 24
Notes
21.The internal write time of th e memory is defi ned b y the overlap of WE , CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a wr ite and any of th ese
signals can terminate a write by going ina cti ve. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
22.Data I/O is high impedance if OE = VIH.
23.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
24.During this period, the I/Os are in output state. Do not apply input signals.
CY62146ESL MoBL
Document #: 001-43142 Rev. *C Page 10 of 15
Figure 8. Write Cycle 3: WE controlled , OE LOW [25]
Figure 9. Write Cycle 4: BHE/BLE Controlled, OE LOW [25]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
tBW
NOTE 26
CE
ADDRESS
WE
DATA I/O
BHE/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
DATA
IN
t
BW
tSCE
t
PWE
tHZWE
tLZWE
NOTE 26
DATA I/O
ADDRESS
CE
WE
BHE
/BLE
Notes
25.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
26.During this period, the I/Os are in output state. Do not apply input signals.
CY62146ESL MoBL
Document #: 001-43142 Rev. *C Page 11 of 15
Truth Table
CE[27] WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High-Z Deselect/Power down Standby (ISB)
L X X H H High-Z Output disabled Active (ICC)
L H L L L Data Out (I/O0–I/O15) Read Active (ICC)
LHLHLData Out (I/O
0–I/O7);
I/O8–I/O15 in High-Z Read Active (ICC)
L H L L H Data Out (I/O8–I/O15);
I/O0–I/O7 in High-Z Read Active (ICC)
L H H L L High-Z Output disabled Active (ICC)
L H H H L High-Z Output disabled Active (ICC)
L H H L H High-Z Output disabled Active (ICC)
L L X L L Data In (I/O 0–I/O15) Write Active (ICC)
L L X H L Data In (I/O0–I/O7);
I/O8–I/O15 in High-Z Write Active (ICC)
L L X L H Data In (I/O8–I/O15);
I/O0–I/O7 in High-Z Write Active (ICC)
Note
27.Chip enable must be at CMOS levels (not floating). Int ermediate voltage levels on this pin is not permitted.
CY62146ESL MoBL
Document #: 001-43142 Rev. *C Page 12 of 15
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
45 CY62146ESL-45ZSXI 51-85087 44-pin TSOP Type II (Pb-free) Industrial
Ordering Code Definitions
Package Diagram
Figure 10. 44-Pin TSOP II, 51-85087
Temperature Range: x = I = Industrial
ZSX = 44-pin TSOP II (Pb-free)
xx = Speed Grade
Separator
SL = Voltage range (3 V typical; 5 V typical)
E = Process Technology 90 nm
Buswidth = × 16
Density = 4-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
CY xx xxx
621 46ESL -I
MAX
MIN.
DIMENSION IN MM (INCH)
(OPTIONAL)
CAN BE LOCATED
ANYWHERE IN THE
BOTTOM PKG
EJECTOR MARK
Z
A
Z
Z
Z
Z
X
A
10.058 (0.396)
10.262 (0.404)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
TOP VIEW BOTTOM VIEW
PLANE
SEATING
18.517 (0.729)
0.800 BSC
0°-5°
0.400(0.016)
0.300 (0.012)
1.194 (0.047)
0.991 (0.039)
0.150 (0.0059)
0.050 (0.0020)
(0.0315)
18.313 (0.721)
BASE PLANE
0.10 (.004)
11.938 (0.470)
PIN 1 I.D.
44
1
11.735 (0.462)
10.058 (0.396)
10.262 (0.404)
22
23
51-85087 *C
CY62146ESL MoBL
Document #: 001-43142 Rev. *C Page 13 of 15
Acronyms
Document Conventions
Units of Measure
Acronym Description
BHE byte high enable
BLE byte low enable
CE chip enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
SRAM static random access memory
TSOP thin small outline package
VFBGA very fine ball gird array
WE write enable
Symbol Unit of Measure
°C degrees Celsius
Amicroamperes
mA milliamperes
MHz megahertz
ns nanoseconds
pF picofarads
Vvolts
ohms
Wwatts
CY62146ESL MoBL
Document #: 001-43142 Rev. *C Page 14 of 15
Document History Page
Document Title: CY62146ESL Mo BL 4-Mbit (256K x 16) Static RAM
Document Number: 001-43142
REV. ECN NO. Issue Date Orig. of
Change Description o f Change
** 1875228 See ECN VKN/AESA New Data Sheet
*A 2944332 06/04/2010 VKN Added Contents
Added footnote for ISB2 parameter in Electrical Characteristics
Added footnote related to chip enable in Truth Table
Updated Package Diagram
Added Sales, Solutions, and Legal Information
*B 3109186 12/13/2010 PRAS Changed Table Footnotes to Footnotes.
Added Ordering Code Definitions.
*C 3296704 06/29/2011 RAME Removed reference to AN1064 SRAM system guidelines.
Added footno te 9 to parameter sections of Capacitance and Thermal
Resistance.
Added ISB1 to footnote 8.
Added footnote 11.
Changed tRC value as 45 in Data Retention Characteristics table.
Footnote 14 moved to parameter section in Switching Characteristics
Added Units of Measure.
Document #: 001-43142 Rev. *C Revised June 29, 2011 Page 15 of 15
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
CY62146ESL MoBL
© Cypress Semiconductor Corporation, 2008–2011. The information contained herein is subject to change without notice. Cypress Semiconduct o r C orpo rat ion a ssume s no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life supp or t, l ife savi n g, cr iti cal co ntr ol o r safe ty ap pl ic at io ns, unl e ss pu rsu an t to an express written agr e em ent with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-suppo rt systems where a malfun ction or failur e may reasonably be expecte d to result in significant injury t o the user. The inclusion of Cypr ess products i n life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (Unit ed States and fore ign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee prod uct to be used only in conj unction with a Cypre ss
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABI LITY AND FITNESS FOR A PARTICULAR PURP OSE. Cypress reserves the right to make changes without further notice to the materials described h erein. Cypre ss does not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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