Rev. 1.0 9/10 Copyright © 2010 by Silico n Laboratories Si5326
Si5326
ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER
ATTENUATOR
Features
Applications
Description
The Si5326 is a jitter-attenuating precision clock multiplier for applications
requiring sub 1 ps jitter performance. The Si5326 accepts two input clocks ranging
from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to
945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down
separately from a common source. The Si5326 can also use its crystal oscillator
as a clock source for frequency synthesis. The device provides virtually any
frequency translation combination across this operating range. The Si5326 input
clock frequency and clock multiplication ratio are programmable through an I2C or
SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation
DSPLL® technology, which provides frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need for external VCXO and
loop filter components. The DSPLL loop bandwidth is digitally programmable,
providing jitter performance optimization at the application level. Operating from a
single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock
multiplication and jitter attenuation in high performance timing applications.
Generates any frequency from 2 kHz
to 945 MHz and select frequencies to
1.4 GHz from an input frequency of
2 kHz to 710 MHz
Ultra-low jitter clock outputs with jitter
generation as low as 0.3 ps rms
(50 kHz–80 MHz)
Integrated loop filter with selectable
loop bandwidth (60 Hz to 8.4 kHz)
Meets OC-192 GR-253-CORE jitter
specifications
Dual clock inputs with manual or
automatically controlled hitless
switching (LVPECL, LVDS, CML,
CMOS)
Dual clock outputs with selectable
signal format
Support for ITU G.709 and custom
FEC ratios (255/238, 255/237,
255/236)
LOL, LOS, FOS alarm outputs
Digitally-controlled output phase
adjustment
I2C or SPI programmable
On-chip voltage regulator for
1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%
operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant
SONET/SDH OC-48/OC-192/STM-
16/STM-64 line cards
ITU G.709 and custom FEC line
cards
GbE/10GbE, 1/2/4/8/10G Fibre
Channel line cards
GbE/10GbE Synchronous Ethernet
Optical modules
Wireless basestations
Data converter clocking
xDSL
PDH clock synthesis
Test and measurement
Broadcast video
Ordering Information:
See page 65.
Pin Assignments
1
2
3
2930313233343536
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
NC
NC
RST
C2B
INT_C1B
GND
VDD
XA
VDD
RATE0
CKIN2+
CKIN2–
NC
RATE1
CKIN1+
CKIN1–
CS_CA
SCL
SDA_SDO
A1
A2_SS
SDI
CKOUT1–
NC
GND
VDD
NC
CKOUT2–
CKOUT2+
CMODE
GND
Pad
A0
INC
9
18
19
28
XB
LOL
DEC
CKOUT1+
Si5326
2 Rev. 1.0
Functional Block Diagram
DSPLL
®
Loss of Signal/
Frequency Offset
Xtal or Refclock
CKOUT2
CKIN1
CKOUT1
CKIN2
÷ N31
÷ N2
÷ N1_LS
÷ N2_LS
Skew Control
Signal Detect
Device Interrupt
VDD (1.8, 2.5, or 3.3 V)
GND
÷ N32
Loss of Lock
Clock Select
I2C/SPI Port
Control
Rate Select
÷ N1_HS
Xtal/Refclock
Hitless Switching
Mux
Si5326
Rev. 1.0 3
TABLE OF CONTENTS
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7. Pin Descriptions: Si5326 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
9. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
10. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
11. Si5326 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Si5326
4 Rev. 1.0
1. Electrical Specifications
Figure 1. Differential Voltage Characteristics
Figure 2. Rise/Fall Time Characteristics
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Temperature TA-40 25 85 C
Supply Voltage during
Normal Operation
VDD 3.3 V Nominal 2.97 3.3 3.63 V
2.5 V Nominal 2.25 2.5 2.75 V
1.8 V Nominal 1.71 1.8 1.89 V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.
V
ISE , VOSE
VID,VOD
Differential I/Os
VICM, VOCM
Single-Ended
Peak-to-Peak Voltage
Differential Peak-to-Peak Voltage
SIGNAL +
SIGNAL –
(SIGNAL +) – (SIGNAL –)
V
t
SIGNAL +
SIGNAL –
VID = (SIGNAL+) – (SIGNAL–)
V
ICM , VOCM
tFtR
80%
20%
CKIN, CKOUT
Si5326
Rev. 1.0 5
Table 2. DC Characteristics
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Supply Current1IDD LVPECL Format
622.08 MHz Out
Both CKOUTs Enabled
—251 279 mA
LVPECL Format
622.08 MHz Out
1 CKOUT Enabled
—217 243 mA
CMOS Format
19.44 MHz Out
Both CKOUTs Enabled
—204 234 mA
CMOS Format
19.44 MHz Out
1 CKOUT Enabled
—194 220 mA
Disable Mode — 165 — mA
CKINn Inp ut Pins 2
Input Common Mode
Voltage (Input Thresh-
old Voltage)
VICM 1.8 V ± 5% 0.9 — 1.4 V
2.5 V ± 10% 1 — 1.7 V
3.3 V ± 10% 1.1 — 1.95 V
Input Resistance CKNRIN Single-ended 20 40 60 kΩ
Single-Ended Input
Voltage Swing
(See Absolute Specs)
VISE fCKIN < 212.5 MHz
See Figure 1.
0.2 — — VPP
fCKIN > 212.5 MHz
See Figure 1.
0.25 — — VPP
Differential Input
Voltage Swing
(See Absolute Specs)
VID fCKIN < 212.5 MHz
See Figure 1.
0.2 — — VPP
fCKIN > 212.5 MHz
See Figure 1.
0.25 — — VPP
Output Clocks (CKOUTn)3
Common Mode CKOVCM LVPECL 100 load line-
to-line
VDD –
1.42
—V
DD –1.25 V
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx
Family Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
Si5326
6 Rev. 1.0
Differential Output
Swing
CKOVD LVPECL 100 load line-
to-line
1.1 — 1.9 VPP
Single Ended Output
Swing
CKOVSE LVPECL 100 load line-
to-line
0.5 — 0.93 VPP
Differential Output
Voltage
CKOVD CML 100 load line-to-
line
350 425 500 mVPP
Common Mode Output
Voltage
CKOVCM CML 100 load line-to-
line
—V
DD-0.36 — V
Differential Output
Voltage
CKOVD LVDS
100 load line-to-line
500 700 900 mVPP
Low Swing LVDS
100 load line-to-line
350 425 500 mVPP
Common Mode Output
Voltage
CKOVCM LVDS 100 load line-to-
line
1.125 1.2 1.275 V
Differential Output
Resistance
CKORD CML, LVPECL, LVDS — 200 —
Output Voltage Low CKOVOLLH CMOS — — 0.4 V
Output Voltage High CKOVOHLH VDD = 1.71 V
CMOS
0.8 x
VDD
——V
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx
Family Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
Si5326
Rev. 1.0 7
Output Drive Current
(CMOS driving into
CKOVOL for output low
or CKOVOH for output
high. CKOUT+ and
CKOUT– shorted
externally)
CKOIO ICMOS[1:0] =11
VDD =1.8V
—7.5 — mA
ICMOS[1:0] =10
VDD =1.8V
—5.5 — mA
ICMOS[1:0] =01
VDD =1.8V
—3.5 — mA
ICMOS[1:0] =00
VDD =1.8V
—1.75 — mA
ICMOS[1:0] =11
VDD =3.3V
—32 — mA
ICMOS[1:0] =10
VDD =3.3V
—24 — mA
ICMOS[1:0] =01
VDD =3.3V
—16 — mA
ICMOS[1:0] =00
VDD =3.3V
—8 — mA
2-Level LVCMOS Input Pins
Input Voltage Low VIL VDD =1.71V — — 0.5 V
VDD =2.25V — — 0.7 V
VDD =2.97V — — 0.8 V
Input Voltage High VIH VDD =1.89V 1.4 — — V
VDD =2.25V 1.8 — — V
VDD =3.63V 2.5 — — V
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx
Family Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
Si5326
8 Rev. 1.0
3-Level Input Pins4
Input Voltage Low VILL — — 0.15 x VDD V
Input Voltage Mid VIMM 0.45 x
VDD
—0.55xV
DD V
Input Voltage High VIHH 0.85 x
VDD
——V
Input Low Current IILL See Note 4 –20 — — µA
Input Mid Current IIMM See Note 4 –2 — +2 µA
Input High Current IIHH See Note 4 — — 20 µA
LVCMOS Output Pins
Output Voltage Low VOL IO = 2 mA
VDD =1.71V
—— 0.4 V
Output Voltage Low IO = 2 mA
VDD =2.97V
—— 0.4 V
Output Voltage High VOH IO = –2 mA
VDD =1.71V
VDD –
0.4
——V
Output Voltage High IO = –2 mA
VDD =2.97V
VDD –
0.4
——V
Disabled Leakage
Current
IOZ RSTb = 0 –100 — 100 µA
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx
Family Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
Si5326
Rev. 1.0 9
Table 3. Microprocessor Control
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
I2C Bus Lines (SDA, SCL)
Input Voltage Low VILI2C — — 0.25 x VDD V
Input Voltage High VIHI2C 0.7 x VDD —V
DD V
Input Current III2C VIN = 0.1 x VDD
to 0.9 x VDD
–10 — 10 µA
Hysteresis of Schmitt
trigger inputs
VHYSI2C VDD = 1.8V 0.1 x VDD —— V
VDD = 2.5 or 3.3 V 0.05 x VDD —— V
Output Voltage Low VOLI2C VDD =1.8V
IO = 3 mA
— — 0.2 x VDD V
VDD = 2.5 or 3.3 V
IO = 3 mA
—— 0.4 V
Si5326
10 Rev. 1.0
SPI Specifications
Duty Cycle, SCLK tDC SCLK = 10 MHz 40 — 60 %
Cycle Time, SCLK tc100 — — ns
Rise Time, SCLK tr20–80% — — 25 ns
Fall Time, SCLK tf20–80% — — 25 ns
Low Time, SCLK tlsc 20–20% 30 — — ns
High Time, SCLK thsc 80–80% 30 — — ns
Delay Time, SCLK Fall
to SDO Active
td1 —— 25 ns
Delay Time, SCLK Fall
to SDO Transition
td2 —— 25 ns
Delay Time, SS Rise
to SDO Tri-state
td3 —— 25 ns
Setup Time, SS to
SCLK Fall
tsu1 25 — — ns
Hold Time, SS to
SCLK Rise
th1 20 — — ns
Setup Time, SDI to
SCLK Rise
tsu2 25 — — ns
Hold Time, SDI to
SCLK Rise
th2 20 — — ns
Delay Time between
Slave Selects
tcs 25 — — ns
Table 3. Microprocessor Control (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Si5326
Rev. 1.0 11
Table 4. AC Specifications
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Single-Ended Reference Cloc k Input Pin XA (XB with cap to GND)
Input Resistance XARIN RATE[1:0] = LM, ML, MH,
or HM, ac coupled
—12— k
Input Voltage Swing XAVPP RATE[1:0] = LM, ML, MH,
or HM, ac coupled
0.5 — 1.2 VPP
Differential Reference Clock Input Pin s (XA/XB)
Input Voltage Swing XA/XBVPP RATE[1:0] = LM, ML, MH,
or HM
0.5 — 1.2 VPP
,
each.
CKINn Input Pins
Input Frequency CKNF0.002 — 710 MHz
Input Duty Cycle
(Minimum Pulse
Width)
CKNDC Whichever is smaller
(i.e., the 40% / 60%
limitation applies only
to high frequency
clocks)
40 — 60 %
2——ns
Input Capacitance CKNCIN —— 3 pF
Input Rise/Fall Time CKNTRF 20–80%
See Figure 2
——11 ns
CKOUTn Output Pins
(See ordering section for speed grade vs frequency limits)
Output Frequency
(Output not config-
ured for CMOS or
Disabled)
CKOFN1 6 0.002 — 945 MHz
N1 = 5 970 — 1134 MHz
N1 = 4 1.213 — 1.4 GHz
Maximum Output
Frequency in CMOS
Format
CKOF— — 212.5 MHz
Output Rise/Fall
(20–80 %) @
622.08 MHz output
CKOTRF Output not configured for
CMOS or Disabled
See Figure 2
—230350 ps
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKOTRF CMOS Output
VDD =1.71
CLOAD =5 pF
—— 8 ns
Si5326
12 Rev. 1.0
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKOTRF CMOS Output
VDD =2.97
CLOAD =5 pF
—— 2 ns
Output Duty Cycle
Uncertainty @
622.08 MHz
CKODC 100 Load
Line-to-Line
Measured at 50% Point
(Not for CMOS)
——+/-40ps
LVCMOS Input Pins
Minimum Reset Pulse
Width
tRSTMN 1µs
Reset to Microproces-
sor Access Ready
tREADY 10 ms
Input Capacitance Cin —— 3 pF
LVCMOS Output Pins
Rise/Fall Times tRF CLOAD = 20pf
See Figure 2
—25— ns
LOSn Trigger Window LOSTRIG From last CKINn to
Internal detection of LOSn
N3 ≠1
— — 4.5 x N3 TCKIN
Time to Clear LOL
after LOS Cleared
tCLRLOL LOS to LOL
Fold = Fnew
Stable Xa/XB reference
—10—ms
Device Skew
Output Clock Skew tSKEW of CKOUTn to of
CKOUT_m, CKOUTn
and CKOUT_m at same
frequency and signal
format
PHASEOFFSET =0
CKOUT_ALWAYS_ON =1
SQ_ICAL =1
——100ps
Phase Change due to
Temperature Variation
tTEMP Max phase changes from
–40 to +85 °C
—300500 ps
Table 4. AC Specifications (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Si5326
Rev. 1.0 13
PLL Performance
(fin=fout = 622.08 MHz; BW=120 Hz; LVPECL)
Lock Time tLOCKMP Start of ICAL to of LOL — 35 1200 ms
Output Clock Phase
Change
tP_STEP After clock switch
f3 128 kHz
—200— ps
Closed Loop Jitter
Peaking
JPK —0.050.1 dB
Jitter Tolerance JTOL Jitter Frequency Loop
Bandwidth
5000/BW — — ns pk-pk
Phase Noise
fout = 622.08 MHz
CKOPN
1 kHz Offset — –106 –87 dBc/Hz
10 kHz Offset — –121 –100 dBc/Hz
100 kHz Offset — –132 –104 dBc/Hz
1 MHz Offset — –132 –119 dBc/Hz
Subharmonic Noise SPSUBH Phase Noise @ 100 kHz
Offset
—–88–76dBc
Spurious Noise SPSPUR Max spur @ n x F3
(n 1, n x F3 < 100 MHz)
—–93–70dBc
Table 4. AC Specifications (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Si5326
14 Rev. 1.0
Table 5. Jitter Generation
Parameter Symbol Test Condition*Min Typ Max GR-253-
Specification Unit
Measurement
Filter DSPLL
BW2
Jitter Gen
OC-192
JGEN 0.02–80 MHz 120 Hz — 4.2 6.2 30 psPP
—.27.42 N/A ps
rms
4–80 MHz 120 Hz — 3.7 6.4 10 psPP
— .14 0.31 N/A psrms
0.05–80 MHz 120 Hz — 4.4 6.9 10 psPP
— .26 0.41 1.0 ps rms
Jitter Gen
OC-48
JGEN 0.12–20 MHz 120 Hz — 3.5 5.4 40.2 psPP
— .27 0.41 4.02 ps rms
*Note: Test conditions:
1. fIN = fOUT = 622.08 MHz
2. Clock input: LVPECL
3. Clock output: LVPECL
4. PLL bandwidth: 120 Hz
5. 114.285 MHz 3rd OT crystal used as XA/XB input
6. VDD = 2.5 V
7. TA = 85 °C
Table 6. Thermal Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Value Unit
Thermal Resistance Junction to Ambient JA Still Air 32 C°/W
Thermal Resistance Junction to Case JC Still Air 14 C°/W
Si5326
Rev. 1.0 15
Table 7. Absolute Limits
Parameter Symbol Test Condition Min Typ Max Unit
DC Supply Voltage VDD –0.5 — 3.8 V
LVCMOS Input Voltage VDIG –0.3 VDD+0.3 V
CKINn Voltage Level Limits CKNVIN 0—V
DD V
XA/XB Voltage Level Limits XAVIN 0—1.2V
Operating Junction Temperature TJCT –55 — 150 ºC
Storage Temperature Range TSTG –55 — 150 ºC
ESD HBM Tolerance
(100 pF, 1.5 k); All pins except
CKIN+/CKIN–
2——kV
ESD MM Tolerance; All pins
except CKIN+/CKIN–
150 — — V
ESD HBM Tolerance
(100 pF, 1.5 k); CKIN+/CKIN–
750 — — V
ESD MM Tolerance;
CKIN+/CKIN–
100 — — V
Latch-up Tolerance JESD78 Compliant
Si5326
16 Rev. 1.0
2. Typical Phase Noise Performance
Figure 3. Typical Phase Noise Plot
Jitter Band Jitter, RMS
SONET_OC48, 12 kHz to 20 MHz 249 fs
SONET_OC192_A, 20 kHz to 80 MHz 274 fs
SONET_OC192_B, 4 MHz to 80 MHz 166 fs
SONET_OC192_C, 50 kHz to 80 MHz 267 fs
Brick Wall_800 Hz to 80 MHz 274 fs
*Note: Jitter integration bands include low-pass (–20 dB/Dec) and hi-pass
(–60 dB/Dec) roll-offs per Telecordia GR-253-CORE.
Si5326
Rev. 1.0 17
3. Typical Application Circuit
Figure 4. Si5326 Typical Application Circuit (I2C Control Mode)
Note: For an example schematic and layout, refer to the Si5325/26-EVB User’s Guide.
Figure 5. Si5326 Typical Application Circuit (SPI Control Mode)
Note: For an example schematic and layout, refer to the Si5325/26-EVB User’s Guide.
GND PAD
Si5326 INT_C1B
C2B
LOL
RST
CKOUT1+
CKOUT1–
VDD
GND
Ferrite
Bead
System
Power
Supply
C1
C2
C3
Serial Data
Serial Clock
Reset
Interrupt/CKIN1 Invalid Indicator
CKIN2 Invalid Indicator
PLL Loss of Lock Indicator
Clock Outputs
CKOUT2+
CKOUT2–
SDA
SCL
I2C Interface
Serial Port Address
A[2:0]
CMODE
Control Mode (L)
100
0.1 µF
0.1 µF
+
–
100
0.1 µF
0.1 µF
+
–
C4
0.1 µF
0.1 µF
0.1 µF
1 µF
Clock Select/Clock ActiveCS_CA
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
3. I2C-required pull-up resistors not shown.
Notes:
XA
XB
Refclk+
Option 2: 0.1 µF
Refclk–
0.1 µF
RATE[1:0]2
Crystal/Ref Clk Rate
VDD
15 k
15 k
XA
XB
Crystal
Option 1:
Input
Clock
Sources*
CKIN2+
CKIN2–
130 130
82 82
VDD = 3.3 V
130 130
82 82
VDD = 3.3 V
CKIN1+
CKIN1–
GND PAD
INC
DEC Output Phase Control
Si5326
RST
CKOUT1+
CKOUT1–
VDD
GND
Ferrite
Bead
System
Power
Supply
C1
C2
C3
Reset
Clock Outputs
CKOUT2+
CKOUT2–
CMODEControl Mode (H)
CKIN2+
CKIN2–
100
0.1 µF
0.1 µF
+
–
100
0.1 µF
0.1 µF
+
–
C4
0.1 µF
0.1 µF
0.1 µF
1 µF
CKIN1+
CKIN1–
INT_C1B
C2B
SPI Interface
LOL
Interrupt/CLKIN1 Invalid Indicator
CLKIN2 Invalid Indicator
PLL Loss of Lock Indicator
Serial Data Out
Serial Data In
SDO
SDI
Serial Clock
SCLK
Slave SelectSS
Clock Select/Clock Active
CS_CA
GND PAD
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
Notes:
Input
Clock
Sources*
130 130
82 82
VDD = 3.3 V
130 130
82 82
VDD = 3.3 V
XA
XB
Refclk+
Option 2: 0.1 µF
Refclk–
0.1 µF
RATE[1:0]2
Crystal/Ref Clk Rate
VDD
15 k
15 k
XA
XB
Crystal
Option 1:
INC
DEC
Output Phase Control
Si5326
18 Rev. 1.0
4. Functional Description
Figure 6. Functional Block Diagram
The Si5326 is a jitter-attenuating precision clock
multiplier for applications requiring sub 1 ps jitter
performance. The Si5326 accepts two input clocks
ranging from 2 kHz to 710 MHz and generates two
output clocks ranging from 2 kHz to 945 MHz and select
frequencies to 1.4 GHz. The Si5326 can also use its
crystal oscillator as a clock source for frequency
synthesis. The device provides virtually any frequency
translation combination across this operating range.
Independent dividers are available for each input clock
and output clock, so the Si5326 can accept input clocks
at different frequencies and it can generate output
clocks at different frequencies. The Si5326 input clock
frequency and clock multiplication ratio are
programmable through an I2C or SPI interface. Silicon
Laboratories offers a PC-based software utility,
DSPLLsim, that can be used to determine the optimum
PLL divider settings for a given input frequency/clock
multiplication ratio combination that minimizes phase
noise and power consumption. This utility can be
downloaded from http://www.silabs.com/timing.
The Si5326 is based on Silicon Laboratories' 3rd-
generation DSPLL® technology, which provides any
frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The Si5326
PLL loop bandwidth is digitally programmable and
supports a range from 60 Hz to 8.4 kHz. The DSPLLsim
software utility can be used to calculate valid loop
bandwidth settings for a given input clock
frequency/clock multiplication ratio.
The Si5326 supports hitless switching between the two
synchronous input clocks in compliance with GR-253-
CORE that greatly minimizes the propagation of phase
transients to the clock outputs during an input clock
transition (maximum 200 ps phase change). Manual
and automatic revertive and non-revertive input clock
switching options are available. The Si5326 monitors
both input clocks for loss-of-signal (LOS) and provides a
LOS alarm (INT_C1B and C2B) when it detects missing
pulses on either input clock. The device monitors the
lock status of the PLL. The lock detect algorithm works
by continuously monitoring the phase of the input clock
in relation to the phase of the feedback clock. The
Si5326 also monitors frequency offset alarms (FOS),
which indicate if an input clock is within a specified
frequency band relative to the frequency of a reference
clock. Both Stratum 3/3E and SONET Minimum Clock
(SMC) FOS thresholds are supported.The Si5326
provides a digital hold capability that allows the device
to continue generation of a stable output clock when the
selected input reference is lost. During digital hold, the
DSPLL generates an output frequency based on a
historical average frequency that existed for a fixed
amount of time before the error event occurred,
eliminating the effects of phase and frequency
transients that may occur immediately preceding digital
hold.
DSPLL
®
Loss of Signal/
Frequency Offset
Xtal or Refclock
CKOUT2
CKIN1
CKOUT1
CKIN2
÷ N31
÷ N2
÷ N1_LS
÷ N2_LS
Skew Control
Signal Detect
Device Interrupt
VDD (1.8, 2.5, or 3.3 V)
GND
÷ N32
Loss of Lock
Clock Selec t
I2C/SPI Port
Control
Rate Select
÷ N1_HS
Xtal/Refclock
Hitless Switch ing
Mux
Si5326
Rev. 1.0 19
The Si5326 has two differential clock outputs. The
electrical format of each clock output is independently
programmable to support LVPECL, LVDS, CML, or
CMOS loads. If not required, the second clock output
can be powered down to minimize power consumption.
The phase difference between the selected input clock
and the output clocks is adjustable in 200 ps increments
for system skew control using the CLAT[7:0] register.
Fine phase adjustment is available and is set using the
FLAT register bits. The nominal range and resolution of
the FLAT[14:0] skew adjustment word are: ±110 ps and
3 ps, respectively. In addition, the phase of one output
clock may be adjusted in relation to the phase of the
other output clock. The resolution varies from 800 ps to
2.2 ns depending on the PLL divider settings. See
Tab l e 8 for instructions on ensuring output-to-output
alignment. The input to output skew is not specified.
The DSPLLsim software utility determines the phase
offset resolution for a given input clock/clock
multiplication ratio combination. For system-level
debugging, a bypass mode is available which drives the
output clock directly from the input clock, bypassing the
internal DSPLL. The device is powered by a single 1.8,
2.5, or 3.3 V supply.
4.1. External Reference
An external, high quality clock or a low-cost
114.285 MHz 3rd overtone crystal is used as part of a
fixed-frequency oscillator within the DSPLL. This
external reference is required for the device to perform
jitter attenuation. Silicon Laboratories recommends
using a high quality crystal. Specific recommendations
may be found in the Family Reference Manual.
In digital hold, the DSPLL remains locked and tracks the
external reference. Note that crystals can have
temperature sensitivities.
4.2. Further Documentation
Consult the Silicon Laboratories Si53xx Any Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5326 functions.
Additional design support is available from Silicon
Laboratories through your distributor.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing.
Table 8. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table
CKOUT_ALWAYS_ON SQ_ICAL Results
0 0 CKOUT OFF until after the first ICAL
0 1 CKOUT OFF until after the first successful
ICAL (i.e., when LOL is low)
1 0 CKOUT always ON, including during an ICAL
1 1 CKOUT always ON, including during an ICAL.
Use these settings to preserve output-to-output
skew
Si5326
20 Rev. 1.0
5. Register Map
All register bits that are not defined in this map should always be written with the specified Reset Values. The
writing to these bits of values other than the specified Reset Values may result in undefined device behavior.
Registers not listed, such as Register 64, should never be written to.
Register D7 D6 D5 D4 D3 D2 D1 D0
0 FREE_RUN CKOUT_
ALWAYS_
ON
BYPASS_
REG
1 CK_PRIOR2[1:0] CK_PRIOR[1:0]
2 BWSEL_REG[3:0]
3 CKSEL_REG[1:0] DHOLD SQ_ICAL
4 AUTOSEL_REG[1:0] HST_DEL[4:0]
5 ICMOS[1:0]
6 SLEEP SFOUT2_REG[2:0] SFOUT1_REG[2:0]
7FOSREFSEL[2:0]
8 HLOG_2[1:0] HLOG_1[1:0]
9 HIST_AVG[4:0]
10 DSBL2_
REG
DSBL1_
REG
11 PD_CK2 PD_CK1
16 CLAT[7:0]
17 FLAT_VALID FLAT[14:8]
18 FLAT[7:0]
19 FOS_EN FOS_THR[1:0] VALTIME[1:0] LOCK[T2:0]
20 CK2_
BAD_
PIN
CK1_
BAD_
PIN
LOL_PIN INT_PIN
21 INCDEC_
PIN
CK1_ACT-
V_PIN
CKSEL_PIN
22 CK_ACTV_
POL
CK_BAD_
POL
LOL_POL INT_POL
23 LOS2_MSK LOS1_MSK LOSX_MSK
24 FOS2_MSK FOS1_MSK LOL_MSK
25 N1_HS[2:0]
31 NC1_LS[19:16]
32 NC1_LS[15:8]
Si5326
Rev. 1.0 21
33 NC1_LS[7:0]
34 NC2_LS[19:16]
35 NC2_LS[15:8]
36 NC2_LS[7:0]
40 N2_HS[2:0] N2_LS[19:16]
41 N2_LS[15:8]
42 N2_LS[7:0]
43 N31[18:16]
44 N31[15:8]
45 N31[7:0]
46 N32[18:16]
47 N32[15:8]
48 N32[7:0]
55 CLKIN2RATE[2:0] CLKIN1RATE[2:0]
128 CK2_ACT-
V_REG
CK1_ACT-
V_REG
129 LOS2_INT LOS1_INT LOSX_INT
130 CLATPROG-
RESS
DIGHOLD-
VALID
FOS2_INT FOS1_INT LOL_INT
131 LOS2_FLG LOS1_FLG LOSX_FLG
132 FOS2_FLG FOS1_FLG LOL_FLG
134 PARTNUM_RO[11:4]
135 PARTNUM_RO[3:0] REVID_RO[3:0]
136 RST_REG ICAL GRADE_RO[1:0]
138 LOS2_EN
[1:1]
LOS1_EN
[1:1]
139 LOS2_EN
[0:0]
LOS1_EN
[0:0]
FOS2_EN FOS1_EN
142 INDEPENDENTSKEW1[7:0]
143 INDEPENDENTSKEW2[7:0]
Register D7 D6 D5 D4 D3 D2 D1 D0
Si5326
22 Rev. 1.0
6. Register Descriptions
Reset value = 0001 0100
Register 0.
BitD7D6D5D4D3D2D1D0
Name FREE_
RUN
CKOUT_
ALWAYS_
ON
BYPASS_
REG
Type R R/W R/W R R R R/W R
Bit Name Function
7 Reserved Reserved.
6FREE_RUNFree Run.
Internal to the device, route XA/XB to CKIN2. This allows the device to lock to its XA-XB
reference.
0: Disable
1: Enable
5CKOUT_
ALWAYS_ON
CKOUT Always On.
This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL is on
and ICAL is not complete or successful. See Table 8 on page 19.
0: Squelch output until part is calibrated (ICAL).
1: Provide an output. Note: The frequency may be significantly off and variable until the
part is calibrated.
4:2 Reserved Reserved.
1 BYPASS_
REG
Bypass Register.
This bit enables or disables the PLL bypass mode. Use only when the device is in digital
hold or before the first ICAL.
0: Normal operation
1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypassing the
PLL. Bypass mode does not support CMOS clock outputs.
0 Reserved Reserved.
Si5326
Rev. 1.0 23
Reset value = 1110 0100
Reset value = 0100 0010
Register 1.
BitD7D6D5D4D3D2D1D0
Name Reserved CK_PRIOR2 [1:0] CK_PRIOR1 [1:0]
Type RR/WR/W
Bit Name Function
7:4 Reserved Reserved.
3:2 CK_PRIOR2
[1:0]
CK_PRIOR 2.
Selects which of the input clocks will be 2nd priority in the autoselection state machine.
00: CKIN1 is 2nd priority.
01: CKIN2 is 2nd priority.
10: Reserved
11: Reserved
1:0 CK_PRIOR1
[1:0]
CK_PRIOR 1.
Selects which of the input clocks will be 1st priority in the autoselection state machine.
00: CKIN1 is 1st priority.
01: CKIN2 is 1st priority.
10: Reserved
11: Reserved
Register 2.
BitD7D6D5D4D3D2D1D0
Name BWSEL_REG [3:0] Reserved
Type R/W R
Bit Name Function
7:4 BWSEL_REG
[3:0]
BWSEL_REG.
Selects nominal f3dB bandwidth for PLL. See DSPLLsim for settings. After BWSEL_REG
is written with a new value, an ICAL is required for the change to take effect.
3:0 Reserved Reserved.
Si5326
24 Rev. 1.0
Reset value = 0000 0101
Register 3.
BitD7D6D5D4D3D2D1D0
Name CKSEL_REG [1:0] DHOLD SQ_ICAL Reserved
Type R/W R/W R/W R
Bit Name Function
7:6 CKSEL_REG
[1:0]
CKSEL_REG.
If the device is operating in register-based manual clock selection mode
(AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input clock
will be the active input clock. If CKSEL_PIN = 1 and AUTOSEL_REG = 00, the CS_CA
input pin continues to control clock selection and CKSEL_REG is of no consequence.
00: CKIN_1 selected.
01: CKIN_2 selected.
10: Reserved
11: Reserved
5 DHOLD DHOLD.
Forces the part into digital hold. This bit overrides all other manual and automatic clock
selection controls.
0: Normal operation.
1: Force digital hold mode. Overrides all other settings and ignores the quality of all of the
input clocks.
4 SQ_ICAL SQ_ICAL.
This bit determines if the output clocks will remain enabled or be squelched (disabled)
during an internal calibration. See Table 8 on page 19.
0: Output clocks enabled during ICAL.
1: Output clocks disabled during ICAL.
3:0 Reserved Reserved.
Si5326
Rev. 1.0 25
Reset value = 0001 0010
Reset value = 1110 1101
Register 4.
BitD7D6D5D4D3D2D1D0
Name AUTOSEL_REG [1:0] Reserved HIST_DEL [4:0]
Type R/W R R/W
Bit Name Function
7:6 AUTOSEL_
REG [1:0]
AUTOSEL_REG [1:0].
Selects method of input clock selection to be used.
00: Manual (either register or pin controlled, see CKSEL_PIN)
01: Automatic Non-Revertive
10: Automatic Revertive
11: Reserved
See the Si53xx Family Reference Manual for a detailed description.
5 Reserved Reserved.
4:0 HIST_DEL
[4:0]
HIST_DEL [4:0 ].
Selects amount of delay to be used in generating the history information used for Digital
Hold.
See the Si53xx Family Reference Manual for a detailed description.
Register 5.
BitD7D6D5D4D3D2D1D0
Name ICMOS [1:0] Reserved
Type R/W R
Bit Name Function
7:6 ICMOS [1:0] ICMOS [1:0].
When the output buffer is set to CMOS mode, these bits determine the output buffer drive
strength. The first number below refers to 3.3 V operation; the second to 1.8 V operation.
These values assume CKOUT+ is tied to CKOUT-.
00: 8mA/2mA
01: 16mA/4mA
10: 24mA/6mA
11: 32mA/8mA
5:0 Reserved Reserved.
Si5326
26 Rev. 1.0
Reset value = 0010 1101
Register 6.
BitD7D6D5D4D3D2D1D0
Name Reserved SLEEP SFOUT2_REG [2:0] SFOUT1_REG [2:0]
Type RR/W R/W R/W
Bit Name Function
7 Reserved Reserved.
6SLEEPSLEEP.
In sleep mode, all clock outputs are disabled and the maximum amount of internal cir-
cuitry is powered down to reduce power dissipation and noise generation. This bit over-
rides the SFOUTn_REG[2:0] output signal format settings.
0: Normal operation
1: Sleep mode
5:3 SFOUT2_
REG [2:0]
SFOUT2_REG [2:0].
Controls output signal format and disable for CKOUT2 output buffer.
000: Reserved
001: Disable
010: CMOS (Bypass mode not supported)
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
Note: LVPECL requires a nominal VDD 2.5 V.
2:0 SFOUT1_
REG [2:0]
SFOUT1_REG [2:0].
Controls output signal format and disable for CKOUT1 output buffer.
000: Reserved
001: Disable
010: CMOS (Bypass mode not supported)
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
Note: LVPECL requires a nominal VDD 2.5 V.
Si5326
Rev. 1.0 27
Reset value = 0010 1010
Register 7.
BitD7D6D5D4D3D2D1D0
Name Reserved FOSREFSEL [2:0]
Type RR/W
Bit Name Function
7:3 Reserved. Reserved.
2:0 FOSREFSEL
[2:0]
FOSREFSEL [2:0].
Selects which input clock is used as the reference frequency for frequency offset (FOS)
alarms.
000: XA/XB (External reference)
001: CKIN1
010: CKIN2
011: Reserved
100: Reserved
101: Reserved
110: Reserved
111: Reserved
Si5326
28 Rev. 1.0
Reset value = 0000 0000
Reset value = 1100 0000
Register 8.
BitD7D6D5D4D3D2D1D0
Name HLOG_2[1:0] HLOG_1[1:0] Reserved
Type R/W R/W R
Bit Name Function
7:6 HLOG_2 [1:0] HLOG_2 [1:0].
00: Normal operation
01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT2 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
5:4 HLOG_1 [1:0].
00: Normal operation
01: Holds CKOUT1 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT1 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
3:0 Reserved Reserved.
Register 9.
BitD7D6D5D4D3D2D1D0
Name HIST_AVG [4:0] Reserved
Type R/W RRR
Bit Name Function
7:3 HIST_AVG
[4:0]
HIST_AVG [4:0].
Selects amount of averaging time to be used in generating the history information for
Digital Hold.
See the Si53xx Family Reference Manual for a detailed description
2:0 Reserved Reserved.
Si5326
Rev. 1.0 29
Reset value = 0000 0000
Register 10.
BitD7D6D5D4D3D2D1D0
Name Reserved DSBL2_
REG
DSBL1_
REG
Reserved Reserved
Type RR/WR/WRR
Bit Name Function
7:4 Reserved Reserved.
3 DSBL2_REG DSBL2_REG.
This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is
selected, the N2_LS output divider is also powered down.
0: CKOUT2 enabled
1: CKOUT2 disabled
2 DSBL1_REG DSBL1_REG.
This bit controls the powerdown of the CKOUT1 output buffer. If disable mode is
selected, the N1_LS output divider is also powered down.
0: CKOUT1 enabled
1: CKOUT1 disabled
1:0 Reserved Reserved.
Si5326
30 Rev. 1.0
Reset value = 0100 0000
Reset value = 0000 0000
Register 11.
BitD7D6D5D4D3D2D1D0
Name Reserved PD_CK2 PD_CK1
Type RR/WR/W
Bit Name Function
7:2 Reserved Reserved.
1PD_CK2PD_CK2.
This bit controls the powerdown of the CKIN2 input buffer.
0: CKIN2 enabled
1: CKIN2 disabled
0PD_CK1PD_CK1.
This bit controls the powerdown of the CKIN1 input buffer.
0: CKIN1 enabled
1: CKIN1 disabled
Register 16.
BitD7D6D5D4D3D2D1D0
Name CLAT [7:0]
Type R/W
Bit Name Function
7:0 CLAT [7:0] CLAT [7:0].
With INCDEC_PIN = 0, this register sets the phase delay for CKOUTn in units of
1/Fosc. This can take as long as 20 seconds.
01111111 = 127/Fosc (2s compliment)
00000000 = 0
10000000 = -128/Fosc (2s compliment)
If NI_HS[2:0] = 000, increasing CLAT does not work.
Si5326
Rev. 1.0 31
Reset value = 1000 0000
Reset value = 0000 0000
Register 17.
BitD7D6D5D4D3D2D1D0
Name FLAT_
VALID
FLAT [14:8]
Type R/W R/W
Bit Name Function
7FLAT_VALIDFLAT_VALID.
Before writing a new FLAT[14:0] value, this bit must be set to zero, which causes the
existing FLAT[14:0] value to be held internally for use while the new value is being writ-
ten. Once the new FLAT[14:0] value is completely written, set FLAT_VALID = 1 to enable
its use.
0: Memorize existing FLAT[14:0] value and ignore intermediate register values during
write of new FLAT[14:0] value.
1: Use FLAT[14:0] value directly from registers.
6:0 FLAT [14:8] FLAT [14:8].
Fine resolution control for overall device skew from input clocks to output clocks. Positive
values increase the skew. See DSPLLsim for details.
FLAT [14:0] is a 2’s complement number.
Register 18.
BitD7D6D5D4D3D2D1D0
Name FLAT [7:0]
Type R/W
Bit Name Function
7:0 FLAT [7:0] FLAT [7 :0 ].
Fine resolution control for overall device skew from input clocks to output clocks. Positive
values increase the skew. See DSPLLsim for details.
FLAT [14:0] is a 2’s complement number.
Si5326
32 Rev. 1.0
Reset value = 0010 1100
Register 19.
BitD7D6D5D4D3D2D1D0
Name FOS_EN FOS_THR [1:0] VALTIME [1:0] LOCKT [2:0]
Type R/W R/W R/W R/W
Bit Name Function
7FOS_ENFOS_EN.
Frequency Offset Enable globally disables FOS. See the individual FOS enables (FOSX-
_EN, register 139).
0: FOS disable
1: FOS enabled by FOSx_EN
6:5 FOS_THR
[1:0]
FOS_THR [1:0].
Frequency Offset at which FOS is declared (relative to the selected FOS reference):
00: ± 11 to 12 ppm (Stratum 3/3E compliant, with a Stratum 3/3E used for REFCLK
01: ± 48 to 49 ppm (SMC)
10: ± 30 ppm (SONET Minimum Clock (SMC), with a Stratum 3/3E used for REFCLK.
11: ± 200 ppm
4:3 VALTIME [1:0] VALTIME [1:0].
Sets amount of time for input clock to be valid before the associated alarm is removed.
00: 2 ms
01: 100 ms
10: 200 ms
11: 13 seconds
2:0 LOCKT [2:0] LOCKT [2:0].
Sets retrigger interval for one shot monitoring phase detector output. One shot is trig-
gered by phase slip in DSPLL. Refer to the Si53xx Family Reference Manual for more
details.
000: 106 ms
001: 53 ms
010: 26.5 ms
011: 13.3 ms
100: 6.6 ms
101: 3.3 ms
110: 1.66 ms
111: .833 ms
Si5326
Rev. 1.0 33
Reset value = 0011 1110
Register 20.
BitD7D6D5D4D3D2D1D0
Name Reserved CK2_BAD_
PIN
CK1_BAD_
PIN
LOL_PIN INT_PIN
Type RR/WR/WR/WR/W
Bit Name Function
7:4 Reserved Reserved.
3 CK2_BAD_
PIN
CK2_BAD_PIN.
The CK2_BAD status can be reflected on the C2B output pin.
0: C2B output pin tristated
1: C2B status reflected to output pin
2 CK1_BAD_
PIN
CK1_BAD_PIN.
Either LOS1 or INT (see INT_PIN) status can be reflected on the INT_C1B output pin.
0: INT_C1B output pin tristated
1: LOS1 or INT (see INT_PIN) status reflected to output pin
1 LOL_PIN LOL_PIN.
The LOL_INT status bit can be reflected on the LOL output pin.
0: LOL output pin tristated
1: LOL_INT status reflected to output pin
0INT_PININT_PIN.
Reflects the interrupt status on the INT_C1B output pin.
0: Interrupt status not displayed on INT_C1B output pin. Instead, the INT_C1B pin
indicates when CKIN1 is bad. If CK1_BAD_PIN = 0, INT_C1B output pin is tristated.
1: Interrupt status reflected to output pin.
Si5326
34 Rev. 1.0
Reset value = 1111 1111
Register 21.
BitD7D6D5D4D3D2D1D0
Name INCDEC_
PIN
Reserved CK1_ACT-
V_PIN
CKSEL_
PIN
Type R/W Force 1 R R R R R/W R/W
Bit Name Function
7 INCDEC_PIN INCDEC_PIN.
Determines how coarse skew adjustments can be made. The adjustments can be made
via hardware using the INC/DEC pins or via software using the CLAT register.
0: INC and DEC inputs ignored; use CLAT register to adjust skew.
1: INC and DEC inputs control output phase increment/decrement.
6:2 Reserved Reserved.
1 CK1_ACTV_
PIN
CK1_ACTV_PIN.
The CK1_ACTV_REG status bit can be reflected to the CS_CA output pin using the
CK1_ACTV_PIN enable function. CK1_ACTV_PIN is of consequence only when pin con-
trolled clock selection is being used. (See CKSEL_PIN)
0: CS_CA output pin tristated.
1: Clock Active status reflected to output pin.
0 CKSEL_PIN CKSEL_PIN.
If manual clock selection is being used, clock selection can be controlled via the
CKSEL_REG[1:0] register bits or the CS_CA input pin. This bit is only active when
AUTOSEL_REG = Manual.
0: CS_CA pin is ignored. CKSEL_REG[1:0] register bits control clock selection.
1: CS_CA input pin controls clock selection.
Si5326
Rev. 1.0 35
Reset value = 1101 1111
Register 22.
BitD7D6D5D4D3D2D1D0
Name Reserved CK_ACT-
V_POL
CK_BAD_
POL
LOL_POL INT_POL
Type RR/WR/WR/WR/W
Bit Name Function
7:4 Reserved Reserved.
3 CK_ACTV_
POL
CK_ACTV_POL.
Sets the active polarity for the CS_CA signals when reflected on an output pin.
0: Active low
1: Active high
2 CK_BAD_
POL
CK_BAD_POL.
Sets the active polarity for the INT_C1B and C2B signals when reflected on output pins.
0: Active low
1: Active high
1 LOL_POL LOL_POL.
Sets the active polarity for the LOL status when reflected on an output pin.
0: Active low
1: Active high
0INT_POLINT_POL.
Sets the active polarity for the interrupt status when reflected on the INT_C1B output pin.
0: Active low
1: Active high
Si5326
36 Rev. 1.0
Reset value = 0001 1111
Register 23.
BitD7D6D5D4D3D2D1D0
Name Reserved LOS2_
MSK
LOS1_
MSK
LOSX_
MSK
Type R R/W R/W R/W
Bit Name Function
7:3 Reserved Reserved.
2LOS2_MSKLOS2_MSK.
Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS2_FLG register.
0: LOS2 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: LOS2_FLG ignored in generating interrupt output.
1LOS1_MSKLOS1_MSK.
Determines if a LOS on CKIN1 (LOS1_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS1_FLG register.
0: LOS1 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: LOS1_FLG ignored in generating interrupt output.
0LOSX_MSKLOSX_MSK.
Determines if a LOS on XA/XB(LOSX_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOSX_FLG register.
0: LOSX alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: LOSX_FLG ignored in generating interrupt output.
Si5326
Rev. 1.0 37
Reset value = 0011 1111
Register 24.
BitD7D6D5D4D3D2D1D0
Name Reserved FOS2_
MSK
FOS1_
MSK
LOL_MSK
Type R R/W R/W R/W
Bit Name Function
7:3 Reserved Reserved.
2 FOS2_MSK FOS2_MSK.
Determines if the FOS2_FLG is used in the generation of an interrupt. Writes to this reg-
ister do not change the value held in the FOS2_FLG register.
0: FOS2 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: FOS2_FLG ignored in generating interrupt output.
1 FOS1_MSK FOS1_MSK.
Determines if the FOS1_FLG is used in the generation of an interrupt. Writes to this reg-
ister do not change the value held in the FOS1_FLG register.
0: FOS1 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: FOS1_FLG ignored in generating interrupt output.
0LOL_MSKLOL_MSK.
Determines if the LOL_FLG is used in the generation of an interrupt. Writes to this regis-
ter do not change the value held in the LOL_FLG register.
0: LOL alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: LOL_FLG ignored in generating interrupt output.
Si5326
38 Rev. 1.0
Reset value = 0010 0000
Reset value = 0000 0000
Register 25.
BitD7D6D5D4D3D2D1D0
Name N1_HS [2:0] Reserved
Type R/W R
Bit Name Function
7:5 N1_HS [2:0] N1_HS [2:0].
Sets value for N1 high speed divider which drives NCn_LS (n = 1 to 2) low-speed divider.
000: N1= 4 Note: Changing the coarse skew via the INC pin or CLAT register is disabled
for this value.
001: N1= 5
010: N1= 6
011: N1= 7
100: N1= 8
101: N1= 9
110: N1= 10
111: N1= 11
4:0 Reserved Reserved.
Register 31.
BitD7D6D5D4D3D2D1D0
Name Reserved NC1_LS [19:16]
Type RR/W
Bit Name Function
7:4 Reserved Reserved.
3:0 NC1_LS
[19:16]
NC1_LS [19:16].
Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111=2^20
Valid divider values=[1, 2, 4, 6, ..., 2^20]
Si5326
Rev. 1.0 39
Reset value = 0000 0000
Reset value = 0011 0001
Register 32.
BitD7D6D5D4D3D2D1D0
Name NC1_LS [15:8]
Type R/W
Bit Name Function
7:0 NC1_LS
[15:8]
NC1_LS [15:8].
Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111=2^20
Valid divider values=[1, 2, 4, 6, ..., 2^20]
Register 33.
BitD7D6D5D4D3D2D1D0
Name NC1_LS [7:0]
Type R/W
Bit Name Function
7:0 NC1_LS
[19:0]
NC1_LS [7:0].
Sets value for N1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111=2^20
Valid divider values=[1, 2, 4, 6, ..., 2^20]
Si5326
40 Rev. 1.0
Reset value = 0000 0000
Reset value = 0000 0000
Register 34.
BitD7D6D5D4D3D2D1D0
Name Reserved NC2_LS [19:16]
Type RR/W
Bit Name Function
7:4 Reserved Reserved.
3:0 NC2_LS
[19:16]
NC2_LS [19:16].
Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.
00000000000000000000=1
00000000000000000001=2
00000000000000000011=4
00000000000000000101=6
...
11111111111111111111=2^20
Valid divider values=[1, 2, 4, 6, ..., 2^20]
Register 35.
BitD7D6D5D4D3D2D1D0
Name NC2_LS [15:8]
Type R/W
Bit Name Function
7:0 NC2_LS
[15:8]
NC2_LS [15:8].
Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111=2^20
Valid divider values=[1, 2, 4, 6, ..., 2^20]
Si5326
Rev. 1.0 41
Reset value = 0011 0001
Register 36.
BitD7D6D5D4D3D2D1D0
Name NC2_LS [7:0]
Type R/W
Bit Name Function
7:0 NC2_LS [7:0] NC2_LS [7:0].
Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111=2^20
Valid divider values=[1, 2, 4, 6, ..., 2^20]
Si5326
42 Rev. 1.0
Reset value = 1100 0000
Register 40.
BitD7D6D5D4D3D2D1D0
Name N2_HS [2:0] Reserved N2_LS [19:16]
Type R/W R R/W
Bit Name Function
7:5 N2_HS [2:0] N2_HS [2:0].
Sets value for N2 high speed divider, which drives N2LS low-speed divider.
000: 4
001: 5
010: 6
011: 7
100: 8
101: 9
110: 10
111: 11
4 Reserved Reserved.
3:0 N2_LS [19:16] N2_LS [19:16 ].
Sets value for N2 low-speed divider, which drives phase detector.
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111 = 2^20
Valid divider values = [2, 4, 6, ..., 2^20]
Si5326
Rev. 1.0 43
Reset value = 0000 0000
Reset value = 1111 1001
Register 41.
BitD7D6D5D4D3D2D1D0
Name N2_LS [15:8]
Type R/W
Bit Name Function
7:0 N2_LS [15:8] N2_LS [15:8].
Sets value for N2 low-speed divider, which drives phase detector.
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111 = 2^20
Valid divider values = [2, 4, 6, ..., 2^20]
Register 42.
BitD7D6D5D4D3D2D1D0
Name N2_LS [7:0]
Type R/W
Bit Name Function
7:0 N2_LS [7:0] N2_LS [7:0].
Sets value for N2 low-speed divider, which drives phase detector.
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111 = 2^20
Valid divider values = [2, 4, 6, ..., 2^20]
Si5326
44 Rev. 1.0
Reset value = 0000 0000
Reset value = 0000 0000
Register 43.
BitD7D6D5D4D3D2D1D0
Name Reserved N31 [18:16]
Type RR/W
Bit Name Function
7:3 Reserved Reserved.
2:0 N31 [18:16] N31 [18:16].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 2^19
Valid divider values=[1, 2, 3, ..., 2^19]
Register 44.
BitD7D6D5D4D3D2D1D0
Name N31_[15:8]
Type R/W
Bit Name Function
7:0 N31_[15:8] N31_[15:8].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 2^19
Valid divider values=[1, 2, 3, ..., 2^19]
Si5326
Rev. 1.0 45
Reset value = 0000 1001
Reset value = 0000 0000
Register 45.
BitD7D6D5D4D3D2D1D0
Name N31_[7:0]
Type R/W
Bit Name Function
7:0 N31_[7:0 N31_[7:0].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 2^19
Valid divider values=[1, 2, 3, ..., 2^19]
Register 46.
BitD7D6D5D4D3D2D1D0
Name Reserved N32_[18:16]
Type RR/W
Bit Name Function
7:3 Reserved Reserved.
2:0 N32_[18:16] N32_[18:16].
Sets value for input divider for CKIN2.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 2^19
Valid divider values=[1, 2, 3, ..., 2^19]
Si5326
46 Rev. 1.0
Reset value = 0000 0000
Reset value = 0000 1001
Register 47.
BitD7D6D5D4D3D2D1D0
Name N32_[15:8]
Type R/W
Bit Name Function
7:0 N32_[15:8] N32_[15:8].
Sets value for input divider for CKIN2.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 2^19
Valid divider values=[1, 2, 3, ..., 2^19]
Register 48.
BitD7D6D5D4D3D2D1D0
Name N32_[7:0]
Type R/W
Bit Name Function
7:0 N32_[7:0] N32_[7:0].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 2^19
Valid divider values=[1, 2, 3, ..., 2^19]
Si5326
Rev. 1.0 47
Reset value = 0000 0000
Register 55.
BitD7D6D5D4D3D2D1D0
Name Reserved CLKIN2RATE_[2:0] CLKIN1RATE[2:0]
Type RR/W R/W
Bit Name Function
7:6 Reserved Reserved.
5:3 CLKIN2RATE
[2:0]
CLKIN2RATE[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10 - 27 MHz
001: 25 - 54 MHz
010: 50 - 105 MHz
011: 95 - 215 MHz
100: 190 - 435 MHz
101: 375 - 710 MHz
110: Reserved
111: Reserved
2:0 CLKIN1RATE
[2:0]
CLKIN1RATE[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10 - 27 MHz
001: 25 - 54 MHz
010: 50 - 105 MHz
011: 95 - 215 MHz
100: 190 - 435 MHz
101: 375 - 710 MHz
110: Reserved
111: Reserved
Si5326
48 Rev. 1.0
Reset value = 0010 0000
Register 128.
BitD7D6D5D4D3D2D1D0
Name Reserved CK2_ACT-
V_REG
CK1_ACT-
V_REG
Type RRR
Bit Name Function
7:2 Reserved Reserved.
1 CK2_ACTV_
REG
CK2_ACTV_REG.
Indicates if CKIN2 is currently the active clock for the PLL input.
0: CKIN2 is not the active input clock. Either it is not selected or LOS2_INT is 1.
1: CKIN2 is the active input clock.
0 CK1_ACTV_
REG
CK1_ACTV_REG.
Indicates if CKIN1 is currently the active clock for the PLL input.
0: CKIN1 is not the active input clock. Either it is not selected or LOS1_INT is 1.
1: CKIN1 is the active input clock.
Si5326
Rev. 1.0 49
Reset value = 0000 0110
Register 129.
BitD7D6D5D4D3D2D1D0
Name Reserved LOS2_INT LOS1_INT LOSX_INT
Type R RRR
Bit Name Function
7:3 Reserved Reserved.
2 LOS2_INT LOS2_INT.
Indicates the LOS status on CKIN2.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN2 input.
1 LOS1_INT LOS1_INT.
Indicates the LOS status on CKIN1.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN1 input.
0 LOSX_INT LOSX_INT.
Indicates the LOS status of the external reference on the XA/XB pins.
0: Normal operation.
1: Internal loss-of-signal alarm on XA/XB reference clock input.
Si5326
50 Rev. 1.0
Reset value = 0000 0001
Register 130.
BitD7 D6D5D4D3D2D1D0
Name CLATPROG-
RESS
DIGHOLD-
VALID
Reserved FOS2_INT FOS1_INT LOL_INT
Type RRRRRR
Bit Name Function
7CLATPROG-
RESS
CLAT Progress.
Indicates if the last change in the CLAT register has been processed.
0: Coarse skew adjustment not in progress.
1: Coarse skew adjustment in progress.
6DIGHOLD-
VALID
Digital Hold Valid.
Indicates if the digital hold circuit has enough samples of a valid clock to meet digital hold
specifications.
0: Indicates digital hold history registers have not been filled. The digital hold output
frequency may not meet specifications.
1: Indicates digital hold history registers have been filled. The digital hold output
frequency is valid.
5:3 Reserved Reserved.
2FOS2_INTCKIN2 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN2 input.
1FOS1_INTCKIN1 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN1 input.
0LOL_INTPLL Loss of Lock Status.
0: PLL locked.
1: PLL unlocked.
Si5326
Rev. 1.0 51
Reset value = 0001 1111
Register 131.
BitD7D6D5D4D3D2D1D0
Name Reserved LOS2_FLG LOS1_FLG LOSX_FLG
Type R R/W R/W R/W
Bit Name Function
7:3 Reserved Reserved.
2LOS2_FLGCKIN2 Loss-of-Signal Flag.
0: Normal operation.
1: Held version of LOS2_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by LOS2_MSK bit. Flag cleared by writing 0 to
this bit.
1LOS1_FLGCKIN1 Loss-of-Signal Flag.
0: Normal operation
1: Held version of LOS1_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by LOS1_MSK bit. Flag cleared by writing 0 to
this bit.
0 LOSX_FLG External Reference (signal on pins XA/XB) Loss-of-Signal Flag.
0: Normal operation
1: Held version of LOSX_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by LOSX_MSK bit. Flag cleared by writing 0 to
this bit.
Si5326
52 Rev. 1.0
Reset value = 0000 0010
Register 132.
BitD7D6D5D4D3D2D1D0
Name Reserved FOS2_FLG FOS1_FLG LOL_FLG Reserved
Type RR/WR/WR/WR
Bit Name Function
7:4 Reserved Reserved.
3FOS2_FLGCLKIN_2 Frequency Offse t Flag.
0: Normal operation.
1: Held version of FOS2_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by FOS2_MSK bit. Flag cleared by writing 0 to
this bit.
2FOS1_FLGCLKIN_1 Frequency Offse t Flag.
0: Normal operation
1: Held version of FOS1_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by FOS1_MSK bit. Flag cleared by writing 0 to
this bit.
1LOL_FLGPLL Loss of Lock Flag.
0: PLL locked
1: Held version of LOL_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by LOL_MSK bit. Flag cleared by writing 0 to
this bit.
0 Reserved Reserved.
Si5326
Rev. 1.0 53
Reset value = 0000 0001
Reset value = 1010 0010
Register 134.
BitD7D6D5D4D3D2D1D0
Name PARTNUM_RO [11:4]
Type R
Bit Name Function
7:0 PARTNUM_
RO [11:0]
Device ID (1 of 2).
0000 0001 1010: Si5326
Register 135.
BitD7D6D5D4D3D2D1D0
Name PARTNUM_RO [3:0] REVID_RO [3:0]
Type RR
Bit Name Function
7:4 PARTNUM_
RO [11:0]
Device ID (2 of 2).
0000 0001 1010: Si5326
3:0 REVID_RO
[3:0]
Device Revision.
0000: Revision A
0001: Revision B
0010: Revision C
Others: Reserved
Si5326
54 Rev. 1.0
Reset value = 0000 0000
Register 136.
BitD7D6D5D4D3D2D1D0
Name RST_REG ICAL Reserved
Type R/W R/W R
Bit Name Function
7 RST_REG Internal Reset (Same as Pin Reset) .
Note: The I2C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted.
0: Normal operation.
1: Reset of all internal logic. Outputs disabled or tristated during reset.
6ICALStart an Internal Calibrat ion Sequence.
For proper operation, the device must go through an internal calibration sequence. ICAL
is a self-clearing bit. Writing a “1” to this location initiates an ICAL. The calibration is com-
plete once the LOL alarm goes low.
0: Normal operation.
1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-calibra-
tion, LOL will go low.
Notes:
1. A valid stable clock (within 100 ppm) must be present to begin ICAL.
2. If the input changes by more than 500 ppm, the part may do an autonomous ICAL.
3. See Table 9, “Register Locations Requiring ICAL,” on page 63 for register changes that
require an ICAL.
5:0 Reserved Reserved.
Si5326
Rev. 1.0 55
Reset value = 0000 1111
Register 138.
BitD7D6D5D4D3D2D1D0
Name Reserved LOS2_EN
[1:1]
LOS1_EN
[1:1]
Type RR/WR/W
Bit Name Function
7:2 Reserved Reserved.
1LOS2_EN
[1:0]
Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2).
Note: LOS2_EN is split between two registers.
00: Disable LOS monitoring
01: Reserved
10: Enable LOSA monitoring
11: Enable LOS monitoring
LOSA is a slower and less sensitive version of LOS. SEe the Si53xx Family Reference
Manual for details.
0LOS1_EN
[1:0]
Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring
01: Reserved
10: Enable LOSA monitoring
11: Enable LOS monitoring
LOSA is a slower and less sensitive version of LOS. See the Si53xx Family Reference
Manual for details.
Si5326
56 Rev. 1.0
Reset value = 1111 1111
Register 139.
BitD7D6D5D4D3D2D1D0
Name Reserved LOS2_EN
[0:0]
LOS1_EN
[0:0]
Reserved FOS2_EN FOS1_EN
Type RR/WR/WRR/WR/W
Bit Name Function
7:6 Reserved Reserved.
5LOS2_EN
[1:0]
Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2).
Note: LOS2_EN is split between two registers.
00: Disable LOS monitoring
01: Reserved
10: Enable LOSA monitoring
11: Enable LOS monitoring
LOSA is a slower and less sensitive version of LOS. See the Si53xx Family Reference
Manual for details
4LOS1_EN
[1:0]
Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring
01: Reserved
10: Enable LOSA monitoring
11: Enable LOS monitoring
LOSA is a slower and less sensitive version of LOS. See the Si53xx Family Reference
Manual for details.
3:2 Reserved Reserved.
1FOS2_ENEnables FOS on a Per Channel Basis.
0: Disable FOS monitoring
1: Enable FOS monitoring
0FOS1_ENEnables FOS on a Per Channel Basis.
0: Disable FOS monitoring
1: Enable FOS monitoring
Si5326
Rev. 1.0 57
Reset value = 0000 0000
Reset value = 0000 0000
Register 142.
BitD7D6D5D4D3D2D1D0
Name INDEPENDENTSKEW1 [7:0]
Type R/W
Bit Name Function
7:0 INDEPEND-
ENTSKEW1
[7:0]
INDEPENDENTSKEW1.
Eight-bit field that represents a 2’s complement of the phase offset in terms of clocks from
the high speed output divider.
Register 143.
BitD7D6D5D4D3D2D1D0
Name INDEPENDENTSKEW2 [7:0]
Type R/W
Bit Name Function
7:0 INDEPEND-
ENTSKEW2
[7:0]
INDEPENDENTSKEW2.
Eight-bit field that represents a 2’s complement of the phase offset in terms of clocks from
the high speed output divider.
Si5326
58 Rev. 1.0
7. Pin Descriptions: Si5326
Pin # Pin Name I/O Signal Level Description
1RST ILVCMOSExternal Reset.
Active low input that performs external hardware reset of device.
Resets all internal logic to a known state and forces the device reg-
isters to their default value. Clock outputs are tristated during reset.
The part must be programmed after a reset or power on to get a
clock output. See the Si53xx Family Reference Manual for details.
This pin has a weak pull-up.
2, 9, 14,
30, 33
NC — — No Connection.
Leave floating. Make no external connections to this pin for normal
operation.
3 INT_C1B O LVCMOS Interrupt/CKIN1 Invalid Indicator.
This pin functions as a device interrupt output or an alarm output for
CKIN1. If used as an interrupt output, INT_PIN must be set to 1. The
pin functions as a maskable interrupt output with active polarity con-
trolled by the INT_POL register bit.
If used as an alarm output, the pin functions as a LOS (and option-
ally FOS) alarm indicator for CKIN1. Set CK1_BAD_PIN = 1 and
INT_PIN =0.
0 = CKIN1 present
1 = LOS (FOS) on CKIN1
The active polarity is controlled by CK_BAD_POL. If no function is
selected, the pin tristates.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
1
2
3
2930313233343536
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
NC
NC
RST
C2B
INT_C1B
GND
VDD
XA
VDD
RATE0
CKIN2+
CKIN2–
NC
RATE1
CKIN1+
CKIN1–
CS_CA
SCL
SDA_SDO
A1
A2_SS
SDI
CKOUT1–
NC
GND
VDD
NC
CKOUT2–
CKOUT2+
CMODE
GND
Pad
A0
INC
9
18
19
28
XB
LOL
DEC
CKOUT1+
Si5326
Rev. 1.0 59
4C2BOLVCMOSCKIN2 Invalid Indicator.
This pin functions as a LOS (and optionally FOS) alarm indicator for
CKIN2 if CK2_BAD_PIN =1.
0 = CKIN2 present
1 = LOS (FOS) on CKIN2
The active polarity can be changed by CK_BAD_POL. If
CK2_BAD_PIN = 0, the pin tristates.
5, 10, 32 VDD VDD Supply Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capac-
itors should be associated with the following VDD pins:
50.1µF
10 0.1 µF
32 0.1 µF
A 1.0 µF should also be placed as close to the device as is practical.
7
6
XB
XA
IAnalogExternal Crystal or Reference Clock.
External crystal should be connected to these pins to use internal
oscillator based reference. Refer to the Si53xx Family Reference
Manual for interfacing to an external reference. External reference
must be from a high-quality clock source (TCXO, OCXO). Fre-
quency of crystal or external clock is set by RATE[1:0] pins.
8, 31 GND GND Supply Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. Grounding these
pins does not eliminate the requirement to ground the GND PAD on
the bottom of the package.
11
15
RATE0
RATE1
I 3-Level External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crystal or
reference clock to be applied to the XA/XB port. Refer to the Si53xx
Family Reference Manual for settings. These pins have both a weak
pull-up and a weak pull-down; they default to M.
L setting corresponds to ground.
M setting corresponds to VDD/2.
H setting corresponds to VDD.
Note: Tying the corresponding Raten pins to HH (VDD) provides
compatibility to Si5325. Refer to Si5325 data sheet for
operating in this mode.
Some designs may require an external resistor voltage divider when
driven by an active device that will tristate.
16
17
CKIN1+
CKIN1–
IMultiClock Input 1.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
12
13
CKIN2+
CKIN2–
IMultiClock Input 2.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
Pin # Pin Name I/O Signal Level Description
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
Si5326
60 Rev. 1.0
18 LOL O LVCMOS PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator if the
LOL_PIN register bit is set to 1.
0 = PLL locked
1 = PLL unlocked
If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by
the LOL_POL bit. The PLL lock status will always be reflected in the
LOL_INT read only register bit.
19 DEC I LVCMOS Skew Decrement.
A pulse on this pin decreases the input to output device skew by
1/fOSC (approximately 200 ps). There is no limit on the range of
skew adjustment by this method.
Pin control is enabled by setting INCDEC_PIN =1. If
INCDEC_PIN = 0, this pin is ignored and output skew is controlled
via the CLAT register.
If both INC and DEC are tied high, phase buildout is disabled and
the device maintains a fixed-phase relationship between the
selected input clock and the output clock during an input clock
switch.
See the Si53xx Family Reference Manual for more details.
This pin has a weak pull-down.
20 INC I LVCMOS Skew Increment.
A pulse on this pin increases the input to output device skew by
1/fOSC (approximately 200 ps). There is no limit on the range of
skew adjustment by this method.
Pin control is enabled by setting INCDEC_PIN =1. If
INCDEC_PIN = 0, this pin is ignored and output skew is controlled
via the CLAT register.
If both INC and DEC are tied high, phase buildout is disabled and
the device maintains a fixed-phase relationship between the
selected input clock and the output clock during an input clock
switch.
See the Si53xx Family Reference Manual for more details.
Note: INC does not increase skew if NI_HS = 4.
This pin has a weak pull-down.
Pin # Pin Name I/O Signal Level Description
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
Si5326
Rev. 1.0 61
21 CS_CA I/O LVCMOS Input Clock Select/Active Clock Indicator.
Input: In manual clock selection mode, this pin functions as the
manual input clock selector if the CKSEL_PIN is set to 1.
0 = Select CKIN1
1 = Select CKIN2
If CKSEL_PIN = 0, the CKSEL_REG register bit controls this func-
tion and this input tristates. If configured for input, must be tied high
or low.
Output: In automatic clock selection mode, this pin indicates which
of the two input clocks is currently the active clock. If alarms exist on
both clocks, CK_ACTV will indicate the last active clock that was
used before entering the digital hold state. The CK_ACTV_PIN reg-
ister bit must be set to 1 to reflect the active clock status to the
CK_ACTV output pin.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
If CK_ACTV_PIN = 0, this pin will tristate. The CK_ACTV status will
always be reflected in the CK_ACTV_REG read only register bit.
22 SCL I LVCMOS Serial Clock.
This pin functions as the serial clock input for both SPI and I2C
modes.
This pin has a weak pull-down.
23 SDA_SDO I/O LVCMOS Serial Data.
In I2C control mode (CMODE = 0), this pin functions as the bidirec-
tional serial data port.
In SPI control mode (CMODE = 1), this pin functions as the serial
data output.
25
24
A1
A0
ILVCMOSSerial Port Address.
In I2C control mode (CMODE = 0), these pins function as hardware
controlled address bits. The I2C address is 1101 [A2] [A1] [A0].
In SPI control mode (CMODE = 1), these pins are ignored.
These pins have a weak pull-down.
26 A2_SSILVCMOSSerial Port Address/Slave Select.
In I2C control mode (CMODE = 0), this pin functions as a hardware
controlled address bit [A2].
In SPI control mode (CMODE = 1), this pin functions as the slave
select input.
This pin has a weak pull-down.
27 SDI I LVCMOS Serial Data In.
In I2C control mode (CMODE = 0), this pin is ignored.
In SPI control mode (CMODE = 1), this pin functions as the serial
data input.
This pin has a weak pull-down.
Pin # Pin Name I/O Signal Level Description
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
Si5326
62 Rev. 1.0
29
28
CKOUT1–
CKOUT1+
OMultiOutput Clock 1.
Differential output clock with a frequency range of 2 kHz to 1.4 GHz.
Output signal format is selected by SFOUT1_REG register bits. Out-
put is differential for LVPECL, LVDS, and CML compatible modes.
For CMOS format, both output pins drive identical single-ended
clock outputs.
34
35
CKOUT2–
CKOUT2+
OMultiOutput Clock 2.
Differential output clock with a frequency range of 2 kHz to 1.4 GHz.
Output signal format is selected by SFOUT2_REG register bits. Out-
put is differential for LVPECL, LVDS, and CML compatible modes.
For CMOS format, both output pins drive identical single-ended
clock outputs.
36 CMODE I LVCMOS Control Mode.
Selects I2C or SPI control mode for the Si5326.
0 = I2C Control Mode
1 = SPI Control Mode
This pin must not be NC. Tie either high or low.
See the Si53xx Family Reference Manual for details on I2C or SPI
operation.
GND PAD GND GND Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Pin # Pin Name I/O Signal Level Description
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
Si5326
Rev. 1.0 63
Table 9 lists all of the register locations that should be followed by an ICAL after their contents are changed.
Table 9. Register Locations Requiring ICAL
Addr Register
0 BYPASS_REG
0 CKOUT_ALWAYS_ON
1 CK_PRIOR2
1 CK_PRIOR1
2 BWSEL_REG
4HIST_DEL
5ICMOS
7 FOSREFSEL
9HIST_AVG
10 DSBL2_REG
10 DSBL1_REG
11 PD_CK2
11 PD_CK1
19 FOS_EN
19 FOS_THR
19 VALTIME
19 LOCKT
21 INCDEC_PIN
25 N1_HS
31 NC1_LS
34 NC2_LS
40 N2_HS
40 N2_LS
43 N31
46 N32
55 CLKIN2RATE
55 CLKIN1RATE
Si5326
64 Rev. 1.0
Table 10. Si5326 Pull up/Pull down
Pin # Si5326 Pull up/
Pull down
1RST U
11 RATE0 U, D
15 RATE1 U, D
19 DEC D
20 INC D
21 CS_CA U, D
22 SCL D
24 A0 D
25 A1 D
26 A2_SS D
27 SDI D
36 CMODE U, D
Si5326
Rev. 1.0 65
8. Ordering Guide
Ordering Part
Number Output Clock Frequency
Range Package ROHS6,
Pb-Free Temp era tur e Ra nge
Si5326A-C-GM 2 kHz–945 MHz
970–1134 MHz
1.213–1.4 GHz
36-Lead 6 x 6 mm QFN Yes –40 to 85 °C
Si5326B-C-GM 2 kHz–808 MHz 36-Lead 6 x 6 mm QFN Yes –40 to 85 °C
Si5326C-C-GM 2 kHz–346 MHz 36-Lead 6 x 6 mm QFN Yes –40 to 85 °C
Si5325/26-EVB Evaluation Board
Note: Add an R at the end of the device to denote tape and reel options.
Si5326
66 Rev. 1.0
9. Package Outline: 36-Pin QFN
Figure 7 illustrates the package details for the Si5326. Table 11 lists the values for the dimensions shown in the
illustration.
Figure 7. 36-Pin Quad Flat No-lead (QFN)
Table 11. Package Dimensions
Symbol Millimeters Symbol Millimeters
Min Nom Max Min Nom Max
A 0.80 0.85 0.90 L 0.50 0.60 0.70
A1 0.00 0.02 0.05 ——12º
b 0.18 0.25 0.30 aaa — — 0.10
D 6.00 BSC bbb — — 0.10
D2 3.95 4.10 4.25 ccc — — 0.08
e 0.50 BSC ddd — — 0.10
E 6.00 BSC eee — — 0.05
E2 3.95 4.10 4.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
Si5326
Rev. 1.0 67
10. Recommended PCB Layout
Figure 8. PCB Land Pattern Diagram
Figure 9. Ground Pad Recommended Layout
Si5326
68 Rev. 1.0
Table 12. PCB Land Pattern Dimensions
Dimension MIN MAX
e 0.50 BSC.
E5.42 REF.
D5.42 REF.
E2 4.00 4.20
D2 4.00 4.20
GE 4.53 —
GD 4.53 —
X — 0.28
Y0.89 REF.
ZE — 6.31
ZD — 6.31
Notes (General):
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes (Solder Mask Design):
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes (Stencil Design):
1. A stainless steel, laser-cut, and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
center ground pad.
Notes (Card As se m bly):
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
Si5326
Rev. 1.0 69
11. Si5326 Device Top Mark
Mark Method: Laser
Font Size: 0.80 mm
Right-Justified
Line 1 Marking: Si5326Q Customer Part Number
Q = Speed Code: A, B, C
See Ordering Guide for options
Line 2 Marking: C-GM C = Product Revision
G = Temperature Range –40 to 85 °C (RoHS6)
M = QFN Package
Line 3 Marking: YYWWRF YY = Year
WW = Work Week
R = Die Revision
F = Internal code
Assigned by the Assembly House. Corresponds to the year
and work week of the mold date.
Line 4 Marking: Pin 1 Identifier Circle = 0.75 mm Diameter
Lower-Left Justified
XXXX Internal Code
Si5326
70 Rev. 1.0
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Updated LVTTL to LVCMOS is Table 2, “Absolute
Maximum Ratings,” on page 6.
Added Figure 3, “Typical Phase Noise Plot,” on page
16.
Updated Figure 4, “Si5326 Typical Application
Circuit (I2C Control Mode),” and Figure 5, “Si5326
Typical Application Circuit (SPI Control Mode),” on
page 17 to show preferred external reference
interface.
Updated “5.Register Map”.
Added RATE0 and changed RATE to RATE1 and
expanded RATE[1:0] description.
Changed font of register names to underlined italics.
Updated "8. Ordering Guide" on page 65.
Added "9. Package Outline: 36-Pin QFN" on page
66.
Added “10.Recommended PCB Layout”.
Revision 0.2 to Revision 0.3
Changed 1.8 V operating range to ±5%.
Updated Table 1 on page 4.
Updated Table 2 on page 6.
Updated Table 11 on page 66.
Added table under Figure 3 on page 16.
Updated "4. Functional Description" on page 18.
Clarified "5. Register Map" on page 20 including pull-
up/pull-down.
Revision 0.3 to Revision 0.4
Updated Table 1 on page 4.
Added "11. Si5326 Device Top Mark" on page 69.
Revision 0.4 to Revision 0.41
Changed “latency” to “skew” throughout.
Updated Table 1 on page 4.
Updated Thermal Resistance Junction to Ambient
typical specification.
Updated Figure 4 on page 17.
Updated Figure 5, “Si5326 Typical Application
Circuit (SPI Control Mode),” on page 17.
Updated "5. Register Map" on page 20.
Updated "9. Package Outline: 36-Pin QFN" on page
66.
Added Figure 9, “Ground Pad Recommended
Layout,” on page 67
Added Register Map
Revision 0.41 to Revision 0.42
Text added to section "5. Register Map" on page 20.
Revision 0.42 to Revision 0.43
Replaced Figure 9.
Updated Rise/Fall time values.
Revision 0.43 to Revision 0.44
Changed register address labels to decimal.
Revision 0.44 to Revision 1.0
Updated first page format to add chip image and pin
out
Updated Functional Block Diagram
Updated Section “1.Electrical Specifications” to
include ac/dc specifications from the Si53xx Family
Reference Manual (FRM)
Updated typical phase noise performance in Section
“2.Typical Phase Noise Performance”
Added INC/DEC pins to Figure 4 and Figure 5
Clarified the format for FLAT [14:0]
Added list of weak pull up/down resistors in Table 10,
“Si5326 Pull up/Pull down,” on page 64
Updated register maps 19, 20, 46, 47, 55, 142, 143,
185
Added note to typical application circuits in Section
“3.Typical Application Circuit”
Added evaluation board part number to “8.Ordering
Guide”
Updated Section “11.Si5326 Device Top Mark”
Updated Table 5, “Jitter Generation,” on page 14;
filled in all TBDs, and lowered typical RMS values
Si5326
Rev. 1.0 71
NOTES:
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
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