SI5326C-C-GMR - Silicon Labs - Datasheet.Directory

Si5326

ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER

ATTENUATOR

Features

Applications

Description

The Si5326 is a jitter-attenuating precision clock multiplier for applications

requiring sub 1 ps jitter performance. The Si5326 accepts two input clocks ranging

from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to

945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down

separately from a common source. The Si5326 can also use its crystal oscillator

as a clock source for frequency synthesis. The device provides virtually any

frequency translation combination across this operating range. The Si5326 input

clock frequency and clock multiplication ratio are programmable through an I2C or

SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation

DSPLL® technology, which provides frequency synthesis and jitter attenuation in a

highly integrated PLL solution that eliminates the need for external VCXO and

loop filter components. The DSPLL loop bandwidth is digitally programmable,

providing jitter performance optimization at the application level. Operating from a

single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock

multiplication and jitter attenuation in high performance timing applications.

Generates any frequency from 2 kHz

to 945 MHz and select frequencies to

1.4 GHz from an input frequency of

2 kHz to 710 MHz

Ultra-low jitter clock outputs with jitter

generation as low as 0.3 ps rms

(50 kHz–80 MHz)

Integrated loop filter with selectable

loop bandwidth (60 Hz to 8.4 kHz)

Meets OC-192 GR-253-CORE jitter

specifications

Dual clock inputs with manual or

automatically controlled hitless

switching (LVPECL, LVDS, CML,

CMOS)

Dual clock outputs with selectable

signal format

Support for ITU G.709 and custom

FEC ratios (255/238, 255/237,

255/236)

LOL, LOS, FOS alarm outputs

Digitally-controlled output phase

adjustment

I2C or SPI programmable

On-chip voltage regulator for

1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%

operation

Small size: 6 x 6 mm 36-lead QFN

Pb-free, ROHS compliant

SONET/SDH OC-48/OC-192/STM-

16/STM-64 line cards

ITU G.709 and custom FEC line

cards

GbE/10GbE, 1/2/4/8/10G Fibre

Channel line cards

GbE/10GbE Synchronous Ethernet

Optical modules

Wireless basestations

Data converter clocking

xDSL

PDH clock synthesis

Test and measurement

Broadcast video

Ordering Information:

See page 65.

Pin Assignments

2930313233343536

10 11 12 13 14 15 16 17

RST

C2B

INT_C1B

GND

VDD

RATE0

CKIN2+

CKIN2–

RATE1

CKIN1+

CKIN1–

CS_CA

SCL

SDA_SDO

A2_SS

SDI

CKOUT1–

GND

VDD

CKOUT2–

CKOUT2+

CMODE

GND

Pad

INC

LOL

DEC

CKOUT1+

Si5326

2 Rev. 1.0

Functional Block Diagram

DSPLL

Loss of Signal/

Frequency Offset

Xtal or Refclock

CKOUT2

CKIN1

CKOUT1

CKIN2

÷ N31

÷ N2

÷ N1_LS

÷ N2_LS

Skew Control

Signal Detect

Device Interrupt

VDD (1.8, 2.5, or 3.3 V)

GND

÷ N32

Loss of Lock

Clock Select

I2C/SPI Port

Control

Rate Select

÷ N1_HS

Xtal/Refclock

Hitless Switching

Mux

Si5326

Rev. 1.0 3

TABLE OF CONTENTS

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

7. Pin Descriptions: Si5326 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

9. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

10. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

11. Si5326 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Si5326

4 Rev. 1.0

1. Electrical Specifications

Figure 1. Differential Voltage Characteristics

Figure 2. Rise/Fall Time Characteristics

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Ambient Temperature TA-40 25 85 C

Supply Voltage during

Normal Operation

VDD 3.3 V Nominal 2.97 3.3 3.63 V

2.5 V Nominal 2.25 2.5 2.75 V

1.8 V Nominal 1.71 1.8 1.89 V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.

ISE , VOSE

VID,VOD

Differential I/Os

VICM, VOCM

Single-Ended

Peak-to-Peak Voltage

Differential Peak-to-Peak Voltage

SIGNAL +

SIGNAL –

(SIGNAL +) – (SIGNAL –)

SIGNAL +

SIGNAL –

VID = (SIGNAL+) – (SIGNAL–)

ICM , VOCM

tFtR

80%

20%

CKIN, CKOUT

Si5326

Rev. 1.0 5

Table 2. DC Characteristics

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Supply Current1IDD LVPECL Format

622.08 MHz Out

Both CKOUTs Enabled

—251 279 mA

LVPECL Format

622.08 MHz Out

1 CKOUT Enabled

—217 243 mA

CMOS Format

19.44 MHz Out

Both CKOUTs Enabled

—204 234 mA

CMOS Format

19.44 MHz Out

1 CKOUT Enabled

—194 220 mA

Disable Mode — 165 — mA

CKINn Inp ut Pins 2

Input Common Mode

Voltage (Input Thresh-

old Voltage)

VICM 1.8 V ± 5% 0.9 — 1.4 V

2.5 V ± 10% 1 — 1.7 V

3.3 V ± 10% 1.1 — 1.95 V

Input Resistance CKNRIN Single-ended 20 40 60 kΩ

Single-Ended Input

Voltage Swing

(See Absolute Specs)

VISE fCKIN < 212.5 MHz

See Figure 1.

0.2 — — VPP

fCKIN > 212.5 MHz

See Figure 1.

0.25 — — VPP

Differential Input

Voltage Swing

(See Absolute Specs)

VID fCKIN < 212.5 MHz

See Figure 1.

0.2 — — VPP

fCKIN > 212.5 MHz

See Figure 1.

0.25 — — VPP

Output Clocks (CKOUTn)3

Common Mode CKOVCM LVPECL 100  load line-

to-line

VDD –

1.42

—V

DD –1.25 V

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal VDD ≥2.5 V.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx

Family Reference Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

Si5326

6 Rev. 1.0

Differential Output

Swing

CKOVD LVPECL 100  load line-

to-line

1.1 — 1.9 VPP

Single Ended Output

Swing

CKOVSE LVPECL 100  load line-

to-line

0.5 — 0.93 VPP

Differential Output

Voltage

CKOVD CML 100  load line-to-

line

350 425 500 mVPP

Common Mode Output

Voltage

CKOVCM CML 100  load line-to-

line

—V

DD-0.36 — V

Differential Output

Voltage

CKOVD LVDS

100  load line-to-line

500 700 900 mVPP

Low Swing LVDS

100  load line-to-line

350 425 500 mVPP

Common Mode Output

Voltage

CKOVCM LVDS 100 load line-to-

line

1.125 1.2 1.275 V

Differential Output

Resistance

CKORD CML, LVPECL, LVDS — 200 — 

Output Voltage Low CKOVOLLH CMOS — — 0.4 V

Output Voltage High CKOVOHLH VDD = 1.71 V

CMOS

0.8 x

VDD

——V

Table 2. DC Characteristics (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal VDD ≥2.5 V.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx

Family Reference Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

Si5326

Rev. 1.0 7

Output Drive Current

(CMOS driving into

CKOVOL for output low

or CKOVOH for output

high. CKOUT+ and

CKOUT– shorted

externally)

CKOIO ICMOS[1:0] =11

VDD =1.8V

—7.5 — mA

ICMOS[1:0] =10

VDD =1.8V

—5.5 — mA

ICMOS[1:0] =01

VDD =1.8V

—3.5 — mA

ICMOS[1:0] =00

VDD =1.8V

—1.75 — mA

ICMOS[1:0] =11

VDD =3.3V

—32 — mA

ICMOS[1:0] =10

VDD =3.3V

—24 — mA

ICMOS[1:0] =01

VDD =3.3V

—16 — mA

ICMOS[1:0] =00

VDD =3.3V

—8 — mA

2-Level LVCMOS Input Pins

Input Voltage Low VIL VDD =1.71V — — 0.5 V

VDD =2.25V — — 0.7 V

VDD =2.97V — — 0.8 V

Input Voltage High VIH VDD =1.89V 1.4 — — V

VDD =2.25V 1.8 — — V

VDD =3.63V 2.5 — — V

Table 2. DC Characteristics (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal VDD ≥2.5 V.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx

Family Reference Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

Si5326

8 Rev. 1.0

3-Level Input Pins4

Input Voltage Low VILL — — 0.15 x VDD V

Input Voltage Mid VIMM 0.45 x

VDD

—0.55xV

DD V

Input Voltage High VIHH 0.85 x

VDD

——V

Input Low Current IILL See Note 4 –20 — — µA

Input Mid Current IIMM See Note 4 –2 — +2 µA

Input High Current IIHH See Note 4 — — 20 µA

LVCMOS Output Pins

Output Voltage Low VOL IO = 2 mA

VDD =1.71V

—— 0.4 V

Output Voltage Low IO = 2 mA

VDD =2.97V

—— 0.4 V

Output Voltage High VOH IO = –2 mA

VDD =1.71V

VDD –

0.4

——V

Output Voltage High IO = –2 mA

VDD =2.97V

VDD –

0.4

——V

Disabled Leakage

Current

IOZ RSTb = 0 –100 — 100 µA

Table 2. DC Characteristics (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal VDD ≥2.5 V.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx

Family Reference Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

Si5326

Rev. 1.0 9

Table 3. Microprocessor Control

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

I2C Bus Lines (SDA, SCL)

Input Voltage Low VILI2C — — 0.25 x VDD V

Input Voltage High VIHI2C 0.7 x VDD —V

DD V

Input Current III2C VIN = 0.1 x VDD

to 0.9 x VDD

–10 — 10 µA

Hysteresis of Schmitt

trigger inputs

VHYSI2C VDD = 1.8V 0.1 x VDD —— V

VDD = 2.5 or 3.3 V 0.05 x VDD —— V

Output Voltage Low VOLI2C VDD =1.8V

IO = 3 mA

— — 0.2 x VDD V

VDD = 2.5 or 3.3 V

IO = 3 mA

—— 0.4 V

Si5326

10 Rev. 1.0

SPI Specifications

Duty Cycle, SCLK tDC SCLK = 10 MHz 40 — 60 %

Cycle Time, SCLK tc100 — — ns

Rise Time, SCLK tr20–80% — — 25 ns

Fall Time, SCLK tf20–80% — — 25 ns

Low Time, SCLK tlsc 20–20% 30 — — ns

High Time, SCLK thsc 80–80% 30 — — ns

Delay Time, SCLK Fall

to SDO Active

td1 —— 25 ns

Delay Time, SCLK Fall

to SDO Transition

td2 —— 25 ns

Delay Time, SS Rise

to SDO Tri-state

td3 —— 25 ns

Setup Time, SS to

SCLK Fall

tsu1 25 — — ns

Hold Time, SS to

SCLK Rise

th1 20 — — ns

Setup Time, SDI to

SCLK Rise

tsu2 25 — — ns

Hold Time, SDI to

SCLK Rise

th2 20 — — ns

Delay Time between

Slave Selects

tcs 25 — — ns

Table 3. Microprocessor Control (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Si5326

Rev. 1.0 11

Table 4. AC Specifications

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Single-Ended Reference Cloc k Input Pin XA (XB with cap to GND)

Input Resistance XARIN RATE[1:0] = LM, ML, MH,

or HM, ac coupled

—12— k

Input Voltage Swing XAVPP RATE[1:0] = LM, ML, MH,

or HM, ac coupled

0.5 — 1.2 VPP

Differential Reference Clock Input Pin s (XA/XB)

Input Voltage Swing XA/XBVPP RATE[1:0] = LM, ML, MH,

or HM

0.5 — 1.2 VPP

each.

CKINn Input Pins

Input Frequency CKNF0.002 — 710 MHz

Input Duty Cycle

(Minimum Pulse

Width)

CKNDC Whichever is smaller

(i.e., the 40% / 60%

limitation applies only

to high frequency

clocks)

40 — 60 %

2——ns

Input Capacitance CKNCIN —— 3 pF

Input Rise/Fall Time CKNTRF 20–80%

See Figure 2

——11 ns

CKOUTn Output Pins

(See ordering section for speed grade vs frequency limits)

Output Frequency

(Output not config-

ured for CMOS or

Disabled)

CKOFN1 6 0.002 — 945 MHz

N1 = 5 970 — 1134 MHz

N1 = 4 1.213 — 1.4 GHz

Maximum Output

Frequency in CMOS

Format

CKOF— — 212.5 MHz

Output Rise/Fall

(20–80 %) @

622.08 MHz output

CKOTRF Output not configured for

CMOS or Disabled

See Figure 2

—230350 ps

Output Rise/Fall

(20–80%) @

212.5 MHz output

CKOTRF CMOS Output

VDD =1.71

CLOAD =5 pF

—— 8 ns

Si5326

12 Rev. 1.0

Output Rise/Fall

(20–80%) @

212.5 MHz output

CKOTRF CMOS Output

VDD =2.97

CLOAD =5 pF

—— 2 ns

Output Duty Cycle

Uncertainty @

622.08 MHz

CKODC 100  Load

Line-to-Line

Measured at 50% Point

(Not for CMOS)

——+/-40ps

LVCMOS Input Pins

Minimum Reset Pulse

Width

tRSTMN 1µs

Reset to Microproces-

sor Access Ready

tREADY 10 ms

Input Capacitance Cin —— 3 pF

LVCMOS Output Pins

Rise/Fall Times tRF CLOAD = 20pf

See Figure 2

—25— ns

LOSn Trigger Window LOSTRIG From last CKINn to 

Internal detection of LOSn

N3 ≠1

— — 4.5 x N3 TCKIN

Time to Clear LOL

after LOS Cleared

tCLRLOL LOS to LOL

Fold = Fnew

Stable Xa/XB reference

—10—ms

Device Skew

Output Clock Skew tSKEW  of CKOUTn to  of

CKOUT_m, CKOUTn

and CKOUT_m at same

frequency and signal

format

PHASEOFFSET =0

CKOUT_ALWAYS_ON =1

SQ_ICAL =1

——100ps

Phase Change due to

Temperature Variation

tTEMP Max phase changes from

–40 to +85 °C

—300500 ps

Table 4. AC Specifications (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Si5326

Rev. 1.0 13

PLL Performance

(fin=fout = 622.08 MHz; BW=120 Hz; LVPECL)

Lock Time tLOCKMP Start of ICAL to of LOL — 35 1200 ms

Output Clock Phase

Change

tP_STEP After clock switch

f3 128 kHz

—200— ps

Closed Loop Jitter

Peaking

JPK —0.050.1 dB

Jitter Tolerance JTOL Jitter Frequency Loop

Bandwidth

5000/BW — — ns pk-pk

Phase Noise

fout = 622.08 MHz

CKOPN

1 kHz Offset — –106 –87 dBc/Hz

10 kHz Offset — –121 –100 dBc/Hz

100 kHz Offset — –132 –104 dBc/Hz

1 MHz Offset — –132 –119 dBc/Hz

Subharmonic Noise SPSUBH Phase Noise @ 100 kHz

Offset

—–88–76dBc

Spurious Noise SPSPUR Max spur @ n x F3

(n 1, n x F3 < 100 MHz)

—–93–70dBc

Table 4. AC Specifications (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Si5326

14 Rev. 1.0

Table 5. Jitter Generation

Parameter Symbol Test Condition*Min Typ Max GR-253-

Specification Unit

Measurement

Filter DSPLL

BW2

Jitter Gen

OC-192

JGEN 0.02–80 MHz 120 Hz — 4.2 6.2 30 psPP

—.27.42 N/A ps

rms

4–80 MHz 120 Hz — 3.7 6.4 10 psPP

— .14 0.31 N/A psrms

0.05–80 MHz 120 Hz — 4.4 6.9 10 psPP

— .26 0.41 1.0 ps rms

Jitter Gen

OC-48

JGEN 0.12–20 MHz 120 Hz — 3.5 5.4 40.2 psPP

— .27 0.41 4.02 ps rms

*Note: Test conditions:

1. fIN = fOUT = 622.08 MHz

2. Clock input: LVPECL

3. Clock output: LVPECL

4. PLL bandwidth: 120 Hz

5. 114.285 MHz 3rd OT crystal used as XA/XB input

6. VDD = 2.5 V

7. TA = 85 °C

Table 6. Thermal Characteristics

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Value Unit

Thermal Resistance Junction to Ambient JA Still Air 32 C°/W

Thermal Resistance Junction to Case JC Still Air 14 C°/W

Si5326

Rev. 1.0 15

Table 7. Absolute Limits

Parameter Symbol Test Condition Min Typ Max Unit

DC Supply Voltage VDD –0.5 — 3.8 V

LVCMOS Input Voltage VDIG –0.3 VDD+0.3 V

CKINn Voltage Level Limits CKNVIN 0—V

DD V

XA/XB Voltage Level Limits XAVIN 0—1.2V

Operating Junction Temperature TJCT –55 — 150 ºC

Storage Temperature Range TSTG –55 — 150 ºC

ESD HBM Tolerance

(100 pF, 1.5 k); All pins except

CKIN+/CKIN–

2——kV

ESD MM Tolerance; All pins

except CKIN+/CKIN–

150 — — V

ESD HBM Tolerance

(100 pF, 1.5 k); CKIN+/CKIN–

750 — — V

ESD MM Tolerance;

CKIN+/CKIN–

100 — — V

Latch-up Tolerance JESD78 Compliant

Si5326

16 Rev. 1.0

2. Typical Phase Noise Performance

Figure 3. Typical Phase Noise Plot

Jitter Band Jitter, RMS

SONET_OC48, 12 kHz to 20 MHz 249 fs

SONET_OC192_A, 20 kHz to 80 MHz 274 fs

SONET_OC192_B, 4 MHz to 80 MHz 166 fs

SONET_OC192_C, 50 kHz to 80 MHz 267 fs

Brick Wall_800 Hz to 80 MHz 274 fs

*Note: Jitter integration bands include low-pass (–20 dB/Dec) and hi-pass

(–60 dB/Dec) roll-offs per Telecordia GR-253-CORE.

Si5326

Rev. 1.0 17

3. Typical Application Circuit

Figure 4. Si5326 Typical Application Circuit (I2C Control Mode)

Note: For an example schematic and layout, refer to the Si5325/26-EVB User’s Guide.

Figure 5. Si5326 Typical Application Circuit (SPI Control Mode)

Note: For an example schematic and layout, refer to the Si5325/26-EVB User’s Guide.

GND PAD

Si5326 INT_C1B

C2B

LOL

RST

CKOUT1+

CKOUT1–

VDD

GND

Ferrite

Bead

System

Power

Supply

Serial Data

Serial Clock

Reset

Interrupt/CKIN1 Invalid Indicator

CKIN2 Invalid Indicator

PLL Loss of Lock Indicator

Clock Outputs

CKOUT2+

CKOUT2–

SDA

SCL

I2C Interface

Serial Port Address

A[2:0]

CMODE

Control Mode (L)

100 

0.1 µF

–

100 

0.1 µF

–

0.1 µF

1 µF

Clock Select/Clock ActiveCS_CA

1. Assumes differential LVPECL termination (3.3 V) on clock inputs.

2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).

3. I2C-required pull-up resistors not shown.

Notes:

Refclk+

Option 2: 0.1 µF

Refclk–

0.1 µF

RATE[1:0]2

Crystal/Ref Clk Rate

VDD

15 k

Crystal

Option 1:

Input

Clock

Sources*

CKIN2+

CKIN2–

130 130 

82 82 

VDD = 3.3 V

130 130 

82 82 

VDD = 3.3 V

CKIN1+

CKIN1–

GND PAD

INC

DEC Output Phase Control

Si5326

RST

CKOUT1+

CKOUT1–

VDD

GND

Ferrite

Bead

System

Power

Supply

Reset

Clock Outputs

CKOUT2+

CKOUT2–

CMODEControl Mode (H)

CKIN2+

CKIN2–

100 

0.1 µF

–

100 

0.1 µF

–

0.1 µF

1 µF

CKIN1+

CKIN1–

INT_C1B

C2B

SPI Interface

LOL

Interrupt/CLKIN1 Invalid Indicator

CLKIN2 Invalid Indicator

PLL Loss of Lock Indicator

Serial Data Out

Serial Data In

SDO

SDI

Serial Clock

SCLK

Slave SelectSS

Clock Select/Clock Active

CS_CA

GND PAD

1. Assumes differential LVPECL termination (3.3 V) on clock inputs.

2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).

Notes:

Input

Clock

Sources*

130 130 

82 82 

VDD = 3.3 V

130 130 

82 82 

VDD = 3.3 V

Refclk+

Option 2: 0.1 µF

Refclk–

0.1 µF

RATE[1:0]2

Crystal/Ref Clk Rate

VDD

15 k

Crystal

Option 1:

INC

DEC

Output Phase Control

Si5326

18 Rev. 1.0

4. Functional Description

Figure 6. Functional Block Diagram

The Si5326 is a jitter-attenuating precision clock

multiplier for applications requiring sub 1 ps jitter

performance. The Si5326 accepts two input clocks

ranging from 2 kHz to 710 MHz and generates two

output clocks ranging from 2 kHz to 945 MHz and select

frequencies to 1.4 GHz. The Si5326 can also use its

crystal oscillator as a clock source for frequency

synthesis. The device provides virtually any frequency

translation combination across this operating range.

Independent dividers are available for each input clock

and output clock, so the Si5326 can accept input clocks

at different frequencies and it can generate output

clocks at different frequencies. The Si5326 input clock

frequency and clock multiplication ratio are

programmable through an I2C or SPI interface. Silicon

Laboratories offers a PC-based software utility,

DSPLLsim, that can be used to determine the optimum

PLL divider settings for a given input frequency/clock

multiplication ratio combination that minimizes phase

noise and power consumption. This utility can be

downloaded from http://www.silabs.com/timing.

The Si5326 is based on Silicon Laboratories' 3rd-

generation DSPLL® technology, which provides any

frequency synthesis and jitter attenuation in a highly

integrated PLL solution that eliminates the need for

external VCXO and loop filter components. The Si5326

PLL loop bandwidth is digitally programmable and

supports a range from 60 Hz to 8.4 kHz. The DSPLLsim

software utility can be used to calculate valid loop

bandwidth settings for a given input clock

frequency/clock multiplication ratio.

The Si5326 supports hitless switching between the two

synchronous input clocks in compliance with GR-253-

CORE that greatly minimizes the propagation of phase

transients to the clock outputs during an input clock

transition (maximum 200 ps phase change). Manual

and automatic revertive and non-revertive input clock

switching options are available. The Si5326 monitors

both input clocks for loss-of-signal (LOS) and provides a

LOS alarm (INT_C1B and C2B) when it detects missing

pulses on either input clock. The device monitors the

lock status of the PLL. The lock detect algorithm works

by continuously monitoring the phase of the input clock

in relation to the phase of the feedback clock. The

Si5326 also monitors frequency offset alarms (FOS),

which indicate if an input clock is within a specified

frequency band relative to the frequency of a reference

clock. Both Stratum 3/3E and SONET Minimum Clock

(SMC) FOS thresholds are supported.The Si5326

provides a digital hold capability that allows the device

to continue generation of a stable output clock when the

selected input reference is lost. During digital hold, the

DSPLL generates an output frequency based on a

historical average frequency that existed for a fixed

amount of time before the error event occurred,

eliminating the effects of phase and frequency

transients that may occur immediately preceding digital

hold.

DSPLL

Loss of Signal/

Frequency Offset

Xtal or Refclock

CKOUT2

CKIN1

CKOUT1

CKIN2

÷ N31

÷ N2

÷ N1_LS

÷ N2_LS

Skew Control

Signal Detect

Device Interrupt

VDD (1.8, 2.5, or 3.3 V)

GND

÷ N32

Loss of Lock

Clock Selec t

I2C/SPI Port

Control

Rate Select

÷ N1_HS

Xtal/Refclock

Hitless Switch ing

Mux

Si5326

Rev. 1.0 19

The Si5326 has two differential clock outputs. The

electrical format of each clock output is independently

programmable to support LVPECL, LVDS, CML, or

CMOS loads. If not required, the second clock output

can be powered down to minimize power consumption.

The phase difference between the selected input clock

and the output clocks is adjustable in 200 ps increments

for system skew control using the CLAT[7:0] register.

Fine phase adjustment is available and is set using the

FLAT register bits. The nominal range and resolution of

the FLAT[14:0] skew adjustment word are: ±110 ps and

3 ps, respectively. In addition, the phase of one output

clock may be adjusted in relation to the phase of the

other output clock. The resolution varies from 800 ps to

2.2 ns depending on the PLL divider settings. See

Tab l e 8 for instructions on ensuring output-to-output

alignment. The input to output skew is not specified.

The DSPLLsim software utility determines the phase

offset resolution for a given input clock/clock

multiplication ratio combination. For system-level

debugging, a bypass mode is available which drives the

output clock directly from the input clock, bypassing the

internal DSPLL. The device is powered by a single 1.8,

2.5, or 3.3 V supply.

4.1. External Reference

An external, high quality clock or a low-cost

114.285 MHz 3rd overtone crystal is used as part of a

fixed-frequency oscillator within the DSPLL. This

external reference is required for the device to perform

jitter attenuation. Silicon Laboratories recommends

using a high quality crystal. Specific recommendations

may be found in the Family Reference Manual.

In digital hold, the DSPLL remains locked and tracks the

external reference. Note that crystals can have

temperature sensitivities.

4.2. Further Documentation

Consult the Silicon Laboratories Si53xx Any Frequency

Precision Clock Family Reference Manual (FRM) for

detailed information about the Si5326 functions.

Additional design support is available from Silicon

Laboratories through your distributor.

Silicon Laboratories has developed a PC-based

software utility called DSPLLsim to simplify device

configuration, including frequency planning and loop

bandwidth selection. The FRM and this utility can be

downloaded from http://www.silabs.com/timing.

Table 8. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table

CKOUT_ALWAYS_ON SQ_ICAL Results

0 0 CKOUT OFF until after the first ICAL

0 1 CKOUT OFF until after the first successful

ICAL (i.e., when LOL is low)

1 0 CKOUT always ON, including during an ICAL

1 1 CKOUT always ON, including during an ICAL.

Use these settings to preserve output-to-output

skew

Si5326

20 Rev. 1.0

5. Register Map

All register bits that are not defined in this map should always be written with the specified Reset Values. The

writing to these bits of values other than the specified Reset Values may result in undefined device behavior.

Registers not listed, such as Register 64, should never be written to.

0 FREE_RUN CKOUT_

ALWAYS_

BYPASS_

REG

1 CK_PRIOR2[1:0] CK_PRIOR[1:0]

2 BWSEL_REG[3:0]

3 CKSEL_REG[1:0] DHOLD SQ_ICAL

4 AUTOSEL_REG[1:0] HST_DEL[4:0]

5 ICMOS[1:0]

6 SLEEP SFOUT2_REG[2:0] SFOUT1_REG[2:0]

7FOSREFSEL[2:0]

8 HLOG_2[1:0] HLOG_1[1:0]

9 HIST_AVG[4:0]

10 DSBL2_

REG

DSBL1_

REG

11 PD_CK2 PD_CK1

16 CLAT[7:0]

17 FLAT_VALID FLAT[14:8]

18 FLAT[7:0]

19 FOS_EN FOS_THR[1:0] VALTIME[1:0] LOCK[T2:0]

20 CK2_

BAD_

CK1_

BAD_

LOL_PIN INT_PIN

21 INCDEC_

CK1_ACT-

V_PIN

CKSEL_PIN

22 CK_ACTV_

POL

CK_BAD_

POL

LOL_POL INT_POL

23 LOS2_MSK LOS1_MSK LOSX_MSK

24 FOS2_MSK FOS1_MSK LOL_MSK

25 N1_HS[2:0]

31 NC1_LS[19:16]

32 NC1_LS[15:8]