Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015
Features
Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed
to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs)
3.3V Output Capability
5.0V Tolerant I/O Pins
Program Support using the Atmel ATDH2200E System, ATDH2225 ISP cable,
or Third-party Programmers
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT40K and AT94K Devices, Altera® FLEX®, APEX
Devices, Lucent® ORCA® FPGAs, Xilinx® XC3000, XC4000, XC5200,
Spartan®, Virtex® FPGAs, and Motorola® MPA1000 FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density
Arrays
Low-power CMOS FLASH Process
Available in 6mm x 6mm x 1mm 8-pad LAP (Pin-compatible with 8-lead
SOIC/VOIC Packages) and 20-lead PLCC Packages
Emulation of the Atmel AT24C Serial EEPROMs
Low-power Standby Mode
Single Device Capable of Holding 4-Bitstream Files Allowing Simple System
Reconfiguration
Fast Serial Download Speeds up to 33MHz
Endurance: 100,000 Write Cycles Typical
Green (Pb/Halide-free/RoHS Compliant) Package Options
Description
The Atmel® AT17F Series of In-System Programmable Configuration PROMs
(Configurators) provide an easy-to-use, cost-effective configuration memory
solution for FPGAs. The AT17F Series devices are packaged in the 8-pad LAP
and 20-lead PLCC packages (Table 1-1). The AT17F Series Configurators use a
simple serial-access procedure to configure one or more FPGA devices.
The AT17F Series Configurators can be programmed with industry-standard
programmers, the Atmel ATDH2200E Programming Kit or the Atmel ATDH2225
ISP Cable.
Table 1. AT17F Series Packages
Package AT17F040 AT17F080
8-pad LAP Yes Yes
20-lead PLCC Yes Yes
AT17F040 and AT17F080
FPGA Configuration Flash Memory
DATASHEET
AT17F040/080 [DATASHEET]
Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015
2
1. Pin Configurations
Table 1-1. Pin Descriptions
Notes: 1. Internal 20K pull-up resistor
2. Internal 30K pull-up resistor
DATA(1) Three-state DATA Output for Configuration. Open-collector bi-directional pin for programming.
CLK(1) Clock Input. Used to increment the internal address and bit counter for reading and programming.
PAGE_EN(2)
Enable Page Download Mode Input. When PAGE_EN is high the configuration download address
space is partitioned into four equal pages. This gives users the ability to easily store and retrieve
multiple configuration bitstreams from a single configuration device. This input works in conjunction
with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired. When SER_EN is
Low (ISP mode) this pin has no effect.
PAGESEL[1:0](2)
Page Select Input. Used to determine which of the four memory pages are targeted during a serial
configuration download. The address space for each of the pages is shown in Table 1-2. When
SER_EN is Low (ISP mode) these pins have no effect.
RESET/OE(1)
Output Enable (Active High) and RESET (Active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data
output driver.
CE(1)
Chip Enable Input (Active Low). A Low level (with OE High) allows CLK to increment the address
counter and enables the data output driver. A High level on CE disables both the address and bit
counters and forces the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low).
GND Ground. A 0.2μF decoupling capacitor between VCC and GND is recommended.
CEO
Chip Enable Output (when SER_EN is High). This output goes Low when the internal address
counter has reached its maximum value. If the PAGE_EN input is set High, the maximum value is the
highest address in the selected partition. The PAGESEL[1:0] inputs are used to make the four
partition selections. If the PAGE_EN input is set Low, the device is not partitioned and the address
maximum value is the highest address in the device (Table 1-2). In a daisy chain of AT17F Series
devices, the CEO pin of one device must be connected to the CE input of the next device in the chain.
It will stay Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low;
thereafter, CEO will stay High until the entire EEPROM is read again.
A2(1)
Device Selection Input, (when SER_EN Low). The input is used to enable (or chip select) the
device during programming (i.e., when SER_EN is Low). Refer to the Atmel AT17F Programming
Specification available on the Atmel web site for additional details.
READY Open Collector Reset State Indicator. Driven Low during power-up reset, released when power-up
is complete. (recommended 4.7k pull-up on this pin if used).
SER_EN (1)
Serial Enable Input. Must remain High during FPGA configuration operations. Bringing SER_EN
Low enables the 2-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be
tied to VCC.
VCC Device Power Supply. +3.3V (±10%)
3
AT17F040/080 [DATASHEET]
Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015
Table 1-2. Address Space PAGESEL[1:0]
Table 1-3. Pin Configurations
Figure 1-1. Pinouts
Paging Decodes AT17F040 (4Mb) AT17F080 (8Mb)
PAGESEL = 00, PAGE_EN = 1 00000 – 0FFFFh 00000 – 1FFFFh
PAGESEL = 01, PAGE_EN = 1 10000 – 1FFFFh 20000 – 3FFFFh
PAGESEL = 10, PAGE_EN = 1 20000 – 2FFFFh 40000 – 5FFFFh
PAGESEL = 11, PAGE_EN = 1 30000 – 3FFFFh 60000 – 7FFFFh
PAGESEL = XX, PAGE_EN = 0 00000 – 3FFFFh 00000 – 7FFFFh
Name I/O
AT17F040 AT17F080
8-pad LAP 20-lead PLCC 8-pad LAP 20-lead PLCC
DATA I/O 1 2 1 2
CLK I 2 4 2 4
PAGE_EN I 16 16
PAGESEL0 I 11 11
PAGESEL1 I–7–7
RESET/OE I3636
CE I 4 8 4 8
GND 5 10 5 10
CEO O 6 14 6 14
A2 I 6 14 6 14
READY O 15 15
SER_EN I 7 17 7 17
VCC 8 20 8 20
Note: Drawings are not to scale.
4
3
2
1
5
6
7
8
DATA
CLK
RESET/OE
CE
VCC
SER_EN
CEO (A2)
GND
8-pad LAP
(Top View)
20-lead PLCC
(Top View)
CLK
NC
RESET/OE
PAGESEL1
CE
4
5
6
7
8
18
17
16
15
14
NC
GND
PAGESEL0
NC
NC
NC
DATA
NC
VCC
NC
3
2
1
20
19
9
10
11
12
13
NC
SER_EN
PAGE_EN
READY
CEO (A2)
AT17F040/080 [DATASHEET]
Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015
4
2. Block Diagram
Figure 2-1. Block Diagram
Configuration
Page Select
Power-on
Reset
Flash
Memory
Clock/Oscillator
Logic
2-wire Serial Programming
Serial Download Logic
Control Logic
CLK
CEO(A2)
DATA
CE/WE/OE
Data
Address
READY
PAGE_EN
PAGESEL0
PAGESEL1
Reset
CE
RESET/OE
SER_EN
5
AT17F040/080 [DATASHEET]
Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015
3. Device Description
The control signals for the configuration memory device (CE, RESET/OE and CLK) interface directly with the
FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data
from the configuration device without requiring an external intelligent controller.
The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter.
When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its DATA pin.
The CE pin also controls the output of the AT17F Series Configurator. If CE is held High after the RESET/OE
reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven High,
the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is
reset and the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to
avoid contention with other configurators. Upon power-up, the address counter is automatically reset.
4. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The
program is loaded either automatically upon power-up or on command, depending on the state of the FPGA
mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory.
The AT17F Serial Configuration PROM has been designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xilinx applications.
5. Control of Configuration
Most connections between the FPGA device and the AT17F Serial Configurator PROM are simple and
self-explanatory.
The DATA output of the AT17F Series Configurator drives DIN of the FPGA devices.
The master FPGA CCLK output drives the CLK input of the AT17F Series Configurator.
The CEO output of any AT17F Series Configurator drives the CE input of the next Configurator in a
cascade chain of configurator devices.
SER_EN must be connected to VCC (except during ISP).
The READY pin is available as an open-collector indicator of the device’s reset status; it is driven Low
while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete.
PAGE_EN must be held Low if download paging is not desired. The PAGESEL[1:0] inputs must be tied off
High or Low. If paging is desired, PAGE_EN must be High and the PAGESEL pins must be set to High or
Low such that the desired page is selected (Table 1-2).
6. Cascading Serial Configuration Devices
For multiple FPGAs configured as a daisy-chain or for FPGAs requiring larger configuration memories,
cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator asserts its CEO output
Low and disables its DATA line driver. The second configurator recognizes the Low level on its CE input and
enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE
on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive
(High) level.
AT17F040/080 [DATASHEET]
Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015
6
7. Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode, the chip can be programmed by the
2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated
inside the chip. The AT17F parts are read/write at 3.3V nominal. Refer to the AT17F Programming Specification
available on www.atmel.com for more programming details. AT17F devices are supported by the ATDH2200
programming system along with many third party programmers.
8. Standby Mode
The AT17F Series Configurators enter a low-power standby mode whenever SER_EN is High and CE is
asserted High. In this mode, the AT17F Configurator consumes less than 1mA of current at 3.3V. The output
remains in a high-impedance state regardless of the state of the OE input.
7
AT17F040/080 [DATASHEET]
Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015
9. Electrical Characteristics
9.1 Absolute Maximum Ratings*
9.2 Operating Conditions
Table 9-1. Operating Conditions
9.3 DC Characteristics
Table 9-2. DC Characteristics
Operating Temperature . . . . . . . . . . . . . . . . . . . -40C to +85C
Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C
Voltage on Any Pin
with Respect to Ground . . . . . . . . . . . . . . . . .-0.1V to VCC +0.5V
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.0V
Maximum Soldering Temp. (10 sec. @ 1/16in.). . . . . . . . .260C
ESD (RZAP = 1.5K, CZAP = 100pF) . . . . . . . . . . . . . . . . . . 2000V
*Notice: Stresses beyond those listed under
Absolute Maximum Ratings may cause
permanent damage to the device. This is a
stress rating only and functional operation
of the device at these or any other
conditions beyond those listed under
operating conditions is not implied.
Exposure to Absolute Maximum Rating
conditions for extended periods of time
may affect device reliability.
Symbol Description Min Max Units
VCC Supply voltage relative to GND -40C to +85C 2.97 3.63 V
Symbol Description
AT17F040 AT17F080
UnitsMin Max Min Max
VIH High-level Input Voltage 2.0 VCC 2.0 VCC V
VIL Low-level Input Voltage 0 0.8 0 0.8 V
VOH High-level Output Voltage (IOH = -2mA) 2.4 2.4 V
VOL Low-level Output Voltage (IOL = +3mA) 0.4 0.4 V
ICCA Supply Current, Active Mode 20 20 mA
ILInput or Output Leakage Current (VIN = VCC or GND) -10 10 -10 10 μA
ICCS Supply Current, Standby Mode 1 1 mA
AT17F040/080 [DATASHEET]
Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015
8
9.4 AC Characteristics
Table 9-3. AC Characteristics
Notes: 1. AC test load = 50pF
2. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state
active levels.
3. See the Atmel AT17F Programming Specification for procedural information.
Table 9-4. AC Characteristics When Cascading
Notes: 1. AC test load = 50pF
2. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active
levels.
Symbol Description
AT17F040/080
UnitsMin Typ Max
TOE(1) OE to Data Delay 55 ns
TCE(1) CE to Data Delay 60 ns
TCAC(1) CLK to Data Delay 30 ns
TOH Data Hold from CE, OE, or CLK 0 ns
TDF(2) CE or OE to Data Float Delay 15 ns
TLC CLK Low Time 15 ns
THC CLK High Time 15 ns
TSCE
CE Setup Time to CLK
(to guarantee proper counting) 25 ns
THCE
CE Hold Time from CLK
(to guarantee proper counting) 0 ns
THOE
RESET/OE Low Time
(guarantees counter is reset) 20 ns
FMAX Maximum Input Clock Frequency SEREN = 0 10 MHz
FMAX Maximum Input Clock Frequency SEREN = 1 33 MHz
TWR Write Cycle Time(3) 12 μs
TEC Erase Cycle Time(3) 33 s
Symbol Description
AT17F040 AT17F080
UnitsMin Max Min Max
TCDF(2) CLK to Data Float Delay 60 50 ns
TOCK(1) CLK to CEO Delay 60 55 ns
TOCE(1) CE to CEO Delay 60 40 ns
TOOE(1) RESET/OE to CEO Delay 45 35 ns
FMAX Maximum Input Clock Frequency 33 33 MHz
9
AT17F040/080 [DATASHEET]
Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015
Figure 9-1. AC Waveforms
Figure 9-2. AC Waveforms when Cascading
CE
RESET/OE
CLK
DATA
TSCE
TLC THC
TCAC
TOE
TCE
TOH
THOE
TSCE THCE
TDF
TOH
CE
RESET/OE
CLK
DATA
CEO
TCDF
TOCK TOCE
TOCE
TOOE
LAST BIT FIRST BIT
AT17F040/080 [DATASHEET]
Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015
10
10. Ordering Information
10.1 Ordering Code Detail
10.2 Ordering Information
AT17F040-30CU
Atmel Designator
Product Family
Device Density
Package Option
Product Variation
040 = 4 megabit
080 = 8 megabit
17F = FPGA Flash
Configuration Memory
Package Device Grade
C = 8-pad LAP
J = 20-lead PLCC
U = Green, Sn Lead Finish
Industrial Temperature Range
(-40°C to +85°C)
30 = Default Value
Memory Size Atmel Ordering Code Lead Finish Package Voltage Operation Range
4-Mbit
AT17F040-30CU Sn
(Lead-free/Halogen-free)
8CN4
3.3V Industrial
(-40C to 85C)
AT17F040-30JU 20J
8-Mbit
AT17F080-30CU Sn
(Lead-free/Halogen-free)
8CN4
3.3V Industrial
(-40C to 85C)
AT17F080-30JU 20J
Package Type
8CN4 8-pad, 6mm x 6mm x 1.04mm, Leadless Array Package (LAP)
Pin-compatible with 8-lead SOIC/VOIC Packages
20J 20-lead, Plastic J-leaded Chip Carrier (PLCC)
11
AT17F040/080 [DATASHEET]
Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015
11. Packaging Information
11.1 8CN4 — 8-pad LAP
DRAWING NO. REV. TITLE GPC
8CN4 E
12/22/14
8CN4, 8-pad 6x6x1.04mm Body, 1.27mm pitch
Leadless Array Package (LAP) DMH
Package Drawing Contact:
packagedrawings@atmel.com
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN TYP MAX NOTE
A 0.94 1.04 1.14
A1 0.30 0.34 0.38
D 5.89 5.99 6.09
E 5.89 5.99 6.09
e 1.27 BSC
e1 1.10 REF
L 0.95 1.00 1.05 1
L1 1.25 1.30 1.35 1
b 0.45 0.50 0.55 1
Pin1 Corner
Marked Pin1 Indentifier
0.10 mm
TYP
4
3
2
1
5
6
7
8
Top View
L
b
e
L1
e1
Side View
A1
A
Bottom View
E
D
Note: 1. Metal Pad Dimensions.
2. All exposed metal area shall have the following finished platings.
Ni: 0.0005 to 0.015 mm
Au: 0.0005 to 0.001 mm
AT17F040/080 [DATASHEET]
Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015
12
11.2 20J — 20-lead PLCC
TITLE DRAWING NO. REV.
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102mm) maximum
A 4.191 4.572
A1 2.286 3.048
A2 0.508
D 9.779 10.033
D1 8.890 9.042 Note 2
E 9.779 10.033
E1 8.890 9.042 Note 2
D2/E2 7.366 8.382
B 0.660 0.813
B1 0.330 0.533
e 1.270 TYP
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
1.14(0.045) X 45° PIN NO. 1
IDENTIFIER
1.14(0.045) X 45°
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45° MAX (3X)
A
A1
B1
D2/E2
B
e
E1 E
D1
D
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) B
20J
10/04/01
Package Drawing Contact:
packagedrawings@atmel.com
13
AT17F040/080 [DATASHEET]
Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015
12. Revision History
Doc Rev. Date Comments
3039M 01/2015
Removed commercial and 44-lead TQFP package options.
Updated the 8CN4 package outline drawing, template, Atmel logos, and disclaimer page.
Added an ordering code detail.
3039L 10/2010 Changed Endurance from 5,000 to 100,000 and Typ 13 to 33 in AC Characteristics Table.
3039K 02/2008 Removed -30JC, -30JI, -30BJC and -30BJI devices from ordering information.
3039J 03/2006 Added last-time buy for AT17FXXX-30CC and AT17FXXX-30CI.
X
XXX
XX
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