TPS65950 Integrated Power Management/Audio Codec Silicon Revision 1.2 Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SWCS032E October 2008 - Revised January 2011 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Contents 1 2 3 4 2 ...................................................................................................................... 1.1 Features .................................................................................................................... 1.2 TPS65950 Block Diagram ................................................................................................ Terminal Description .......................................................................................................... 2.1 Corner Balls ................................................................................................................ 2.2 Ball Characteristics ........................................................................................................ 2.3 Signal Description ......................................................................................................... Electrical Characteristics .................................................................................................... 3.1 Absolute Maximum Ratings .............................................................................................. 3.2 Minimum Voltages and Associated Currents .......................................................................... 3.3 Recommended Operating Conditions .................................................................................. 3.4 Digital I/O Electrical Characteristics ..................................................................................... Power Module ................................................................................................................... 4.1 Power Providers ........................................................................................................... 4.1.1 VDD1 dc-dc Regulator ......................................................................................... 4.1.1.1 VDD1 dc-dc Regulator Characteristics .......................................................... 4.1.1.2 External Components and Application Schematic ............................................. 4.1.2 VDD2 dc-dc Regulator ......................................................................................... 4.1.2.1 VDD2 dc-dc Regulator Characteristics .......................................................... 4.1.2.2 External Components and Application Schematic ............................................. 4.1.3 VIO dc-dc Regulator ............................................................................................ 4.1.3.1 VIO dc-dc Regulator Characteristics ............................................................ 4.1.3.2 External Components and Application Schematic ............................................. 4.1.4 VDAC LDO Regulator .......................................................................................... 4.1.5 VPLL1 LDO Regulator ......................................................................................... 4.1.6 VPLL2 LDO Regulator ......................................................................................... 4.1.7 VMMC1 LDO Regulator ....................................................................................... 4.1.8 VMMC2 LDO Regulator ....................................................................................... 4.1.9 VSIM LDO Regulator ........................................................................................... 4.1.10 VAUX1 LDO Regulator ........................................................................................ 4.1.11 VAUX2 LDO Regulator ........................................................................................ 4.1.12 VAUX3 LDO Regulator ........................................................................................ 4.1.13 VAUX4 LDO Regulator ........................................................................................ 4.1.14 Internal LDOs ................................................................................................... 4.1.15 CP ................................................................................................................ 4.1.16 USB LDO Short-Circuit Protection Scheme ................................................................. 4.2 Power References ......................................................................................................... 4.3 Power Control .............................................................................................................. 4.3.1 Backup Battery Charger ....................................................................................... 4.3.2 Battery Monitoring and Threshold Detection ................................................................ 4.3.2.1 Power On/Power Off and Backup Conditions .................................................. 4.3.3 VRRTC LDO Regulator ........................................................................................ 4.4 Power Consumption ....................................................................................................... 4.5 Power Management ....................................................................................................... 4.5.1 Boot Modes ...................................................................................................... 4.5.2 Process Modes .................................................................................................. Introduction Contents 11 12 13 14 14 15 20 27 27 27 28 28 32 34 35 35 36 38 38 39 41 41 42 44 45 46 47 48 49 50 51 52 53 54 54 55 55 56 56 56 56 57 58 59 59 59 Copyright (c) 2008-2011, Texas Instruments Incorporated TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 4.5.2.1 4.5.3 5 6 C027.0 Mode ....................................................................................... 59 4.5.2.2 C021.M Mode ...................................................................................... 59 Power-On Sequence ........................................................................................... 59 ................................................................. 59 .................................................................... 60 4.5.3.3 OMAP3 Power-On Sequence .................................................................... 61 4.5.3.4 Power On in Slave_C021_Generic Mode ....................................................... 63 4.5.4 Power-Off Sequence ........................................................................................... 63 4.5.4.1 Power-Off Sequence in Master Modes .......................................................... 63 Real-Time Clock and Embedded Power Controller ................................................................. 65 5.1 RTC ......................................................................................................................... 65 5.1.1 Backup Battery .................................................................................................. 65 5.2 EPC ......................................................................................................................... 65 Audio/Voice Module ........................................................................................................... 66 6.1 Audio/Voice Downlink (RX) Module ..................................................................................... 67 6.1.1 Earphone Output ................................................................................................ 67 6.1.1.1 Earphone Output Characteristics ................................................................ 67 6.1.1.2 External Components and Application Schematic ............................................. 68 6.1.2 8- Stereo Hands-Free ........................................................................................ 68 6.1.2.1 8- Stereo Hands-Free Output Characteristics ................................................ 68 6.1.2.2 External Components and Application Schematic ............................................. 69 6.1.3 Headset .......................................................................................................... 70 6.1.3.1 Headset Output Characteristics .................................................................. 70 6.1.3.2 External Components and Application Schematic ............................................. 72 6.1.4 Headset Pop-Noise Attenuation .............................................................................. 75 6.1.5 Predriver for External Class-D Amplifier ..................................................................... 76 6.1.5.1 Predriver Output Characteristics ................................................................. 76 6.1.5.2 External Components and Application Schematic ............................................. 77 6.1.6 Vibrator H-Bridge ............................................................................................... 78 6.1.6.1 Vibrator H-Bridge Output Characteristics ....................................................... 78 6.1.6.2 External Components and Application Schematic ............................................. 78 6.1.7 Carkit Output .................................................................................................... 79 6.1.8 Digital Audio Filter Module .................................................................................... 80 6.1.9 Digital Voice Filter Module ..................................................................................... 80 6.1.9.1 Voice Downlink Filter (Sampling Frequency at 8 kHz) ........................................ 81 6.1.9.2 Voice Downlink Filter (Sampling Frequency at 16 kHz) ...................................... 82 6.1.10 Boost Stage ..................................................................................................... 82 6.2 Audio/Voice Uplink (TX) Module ......................................................................................... 84 6.2.1 Microphone Bias Module ...................................................................................... 84 6.2.1.1 Analog Microphone Bias Module Characteristics .............................................. 85 6.2.1.2 External Components and Application Schematic ............................................. 86 6.2.1.3 Digital Microphone Bias Module Characteristics ............................................... 87 6.2.1.4 Silicon Microphone Characteristics .............................................................. 89 6.2.2 Stereo Differential Input ........................................................................................ 90 6.2.3 Headset Differential Input ...................................................................................... 90 6.2.4 FM Radio/Auxiliary Stereo Input .............................................................................. 91 6.2.4.1 External Components ............................................................................. 91 6.2.5 PDM Interface for Digital Microphones ...................................................................... 91 4.5.3.1 Timings Before Sequence_Start 4.5.3.2 OMAP2 Power-On Sequence Copyright (c) 2008-2011, Texas Instruments Incorporated Contents 3 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com 10 .......................................................................................... 92 .............................................................................. 93 6.2.8 Carkit Input ...................................................................................................... 93 6.2.9 Digital Audio Filter Module .................................................................................... 94 6.2.10 Digital Voice Filter Module ..................................................................................... 95 6.2.10.1 Voice Uplink Filter (Sampling Frequency at 8 kHz) ........................................... 95 6.2.10.2 Voice Uplink Filter (Sampling Frequency at 16 kHz) .......................................... 97 USB HS 2.0 OTG Transceiver .............................................................................................. 99 7.1 USB Features .............................................................................................................. 99 7.2 USB Transceiver ......................................................................................................... 100 7.2.1 MCPC Carkit Port Timing .................................................................................... 102 7.2.2 USB-CEA Carkit Port Timing ................................................................................ 103 7.2.3 HS USB Port Timing .......................................................................................... 105 7.2.4 PHY Electrical Characteristics ............................................................................... 106 7.2.4.1 5-V Tolerance ..................................................................................... 106 7.2.4.2 LS/FS Single-Ended Receivers ................................................................. 106 7.2.4.3 LS/FS Differential Receiver ..................................................................... 107 7.2.4.4 LS/FS Differential Transmitter .................................................................. 107 7.2.4.5 HS Differential Receiver ......................................................................... 108 7.2.4.6 HS Differential Transmitter ...................................................................... 108 7.2.4.7 CEA/MCPC/UART Driver ........................................................................ 109 7.2.4.8 Pullup/Pulldown Resistors ....................................................................... 110 7.2.4.9 PHY DPLL Electrical Characteristics .......................................................... 110 7.2.4.10 PHY Power Consumption ....................................................................... 111 7.2.5 OTG Electrical Characteristics .............................................................................. 111 7.2.5.1 OTG VBUS Electrical ............................................................................ 112 7.2.5.2 OTG ID Electrical ................................................................................. 112 Battery Interface .............................................................................................................. 114 8.1 General Description ...................................................................................................... 114 8.1.1 Battery Charger Interface Overview ........................................................................ 114 8.1.2 Battery Backup Overview .................................................................................... 114 8.2 Typical Application Schematics ........................................................................................ 114 8.2.1 Functional Configurations .................................................................................... 114 8.2.2 In-Rush Current Limitation Schematic ...................................................................... 115 8.2.3 Configuration With BCI Not Used ........................................................................... 116 8.3 Electrical Characteristics ................................................................................................ 118 8.3.1 Main Charge ................................................................................................... 118 8.3.2 Precharge ...................................................................................................... 121 8.3.3 Constant Voltage Mode ...................................................................................... 122 8.4 Charge Sequence Timing Diagram .................................................................................... 124 8.5 CEA Charger Type ....................................................................................................... 124 MADC ............................................................................................................................. 126 9.1 General Description ...................................................................................................... 126 9.2 Main Electrical Characteristics ......................................................................................... 126 9.3 Channel Voltage Input Range .......................................................................................... 127 9.3.1 Sequence Conversion Time (Real-Time or Nonaborted Asynchronous) .............................. 127 LED Drivers ..................................................................................................................... 129 4 Contents 7 8 9 6.2.6 Uplink Characteristics 6.2.7 Microphone Amplification Stage Copyright (c) 2008-2011, Texas Instruments Incorporated TPS65950 www.ti.com ...................................................................................................... ........................................................................................................................ 11.1 Keyboard Connection ................................................................................................... Clock Specifications ........................................................................................................ 12.1 Features ................................................................................................................... 12.2 Input Clock Specifications .............................................................................................. 12.2.1 Clock Source Requirements ................................................................................. 12.2.2 High-Frequency Input Clock ................................................................................. 12.2.3 32-kHz Input Clock ............................................................................................ 12.2.3.1 External Crystal Description ..................................................................... 12.2.3.2 External Clock Description ...................................................................... 12.3 Output Clock Specifications ............................................................................................ 12.3.1 32KCLKOUT Output Clock .................................................................................. 12.3.2 HFCLKOUT Output Clock .................................................................................... 12.3.3 Output Clock Stabilization Time ............................................................................. Timing Requirements and Switching Characteristics ........................................................... 13.1 Timing Parameters ....................................................................................................... 13.2 Target Frequencies ...................................................................................................... 13.3 I2C Timing ................................................................................................................. 13.4 Audio Interface: TDM/I2S Protocol .................................................................................... 13.4.1 I2S Right- and Left-Justified Data Format ................................................................. 13.4.2 TDM Data Format ............................................................................................. 13.5 Voice/Bluetooth PCM Interfaces ....................................................................................... 13.6 JTAG Interfaces .......................................................................................................... Debouncing Time ............................................................................................................. External Components ....................................................................................................... TPS65950 Package ........................................................................................................... 16.1 TPS65950 Standard Package Symbols .............................................................................. 16.2 Package Thermal Resistance Characteristics ....................................................................... 16.3 Mechanical Data ......................................................................................................... 16.4 ESD Specifications ...................................................................................................... Glossary ......................................................................................................................... 10.1 11 12 13 14 15 16 17 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 General Description Keyboard Copyright (c) 2008-2011, Texas Instruments Incorporated Contents 129 130 130 131 131 132 132 132 135 136 138 140 140 142 143 144 144 144 145 146 146 148 149 151 153 155 160 160 160 161 162 163 5 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com List of Figures 1-1 TPS65950 Block Diagram ....................................................................................................... 13 2-1 PBGA Bottom View .............................................................................................................. 14 4-1 Power Provider Block Diagram ................................................................................................. 33 4-2 VDD1 dc-dc Regulator Efficiency .............................................................................................. 36 4-3 VDD1 dc-dc Application Schematic ............................................................................................ 37 4-4 VDD2 dc-dc Regulator Efficiency .............................................................................................. 39 4-5 VDD2 dc-dc Application Schematic ............................................................................................ 40 4-6 VIO dc-dc Regulator Efficiency in Active Mode .............................................................................. 42 4-7 VIO dc-dc Application Schematic .............................................................................................. 43 4-8 Timings Before Sequence Start 4-9 Timings--OMAP2 Power-On Sequence ...................................................................................... 61 4-10 Timings--OMAP3 Power-On Sequence ...................................................................................... 62 4-11 Timings--Power On in Slave_C021_Generic Model ........................................................................ 63 4-12 Power-Off Sequence in Master Modes ........................................................................................ 64 6-1 Audio/Voice Module Block Diagram ........................................................................................... 67 6-2 Earphone Amplifier ............................................................................................................... 67 6-3 Earphone Speaker ............................................................................................................... 68 6-4 8- Stereo Hands-Free Amplifiers ............................................................................................. 68 6-5 8- Stereo Hands-Free 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 6-33 6 ............................................................................................... ......................................................................................................... Headset Amplifier ................................................................................................................ Headset 4-Wire Stereo Jack Without an External FET...................................................................... Headset 4-Wire Stereo Jack With an External FET ......................................................................... Headset 5-Wire Stereo Jack .................................................................................................... Headset 4-Wire Stereo Jack Optimized ....................................................................................... Headset Pop-Noise Cancellation Diagram .................................................................................... Predriver for External Class D .................................................................................................. Vibrator H-Bridge ................................................................................................................. Carkit Output Downlink Path Characteristics ................................................................................. Digital Audio Filter Downlink Path Characteristics ........................................................................... Digital Voice Filter Downlink Path Characteristics ........................................................................... Voice Downlink Frequency Response With FS = 8 kHz ..................................................................... Voice Downlink Frequency Response With FS = 16 kHz ................................................................... Analog and Digital Microphone Multiplexing .................................................................................. Analog Microphone Pseudodifferential ........................................................................................ Analog Microphone Differential ................................................................................................. Digital Microphone Bias Module Block Diagram ............................................................................. Digital Microphone Bias Module Timing Diagram ............................................................................ Silicon Microphone Module ..................................................................................................... Audio Auxiliary Input ............................................................................................................. Example of PDM Interface Circuitry ........................................................................................... Uplink Amplifier ................................................................................................................... Carkit Input Uplink Path Characteristics ...................................................................................... Digital Audio Filter Uplink Path Characteristics .............................................................................. Digital Audio Filter Uplink Path Characteristics .............................................................................. Voice Uplink Frequency Response With FS = 8 kHz (Frequency Range 0 to 600 Hz) ................................. Voice Uplink Frequency Response With FS = 8 kHz (Frequency Range 3000 to 3600 Hz) ........................... Voice Uplink Frequency Response With FS = 16 kHz (Frequency Range 0 to 600 Hz) ................................ List of Figures 60 70 70 72 73 74 75 76 77 79 79 80 80 81 82 85 87 87 88 89 90 91 92 93 93 94 95 96 96 97 Copyright (c) 2008-2011, Texas Instruments Incorporated TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 6-34 Voice Uplink Frequency Response With FS = 16 kHz (Frequency Range 6200 to 7000 Hz) .......................... 97 7-1 USB 2.0 PHY Overview ......................................................................................................... 99 7-2 USB System Application Schematic.......................................................................................... 101 7-3 MCPC UART and Handshake Mode Data Flow ............................................................................ 102 7-4 MCPC UART and Handshake Mode Timings ............................................................................... 103 7-5 USB-CEA Carkit UART Data Flow ........................................................................................... 104 7-6 USB-CEA Carkit UART Timing Parameters ................................................................................. 105 7-7 HS USB Interface--Transmit and Receive Modes (ULPI 8-Bit) .......................................................... 105 8-1 Typical Application Schematics ............................................................................................... 115 8-2 Typical Application Schematic (In-Rush Current Limitation) .............................................................. 116 8-3 Typical Application Schematic (BCI Not Used) ............................................................................. 117 8-4 Automatic Charge Sequence Timing Diagram .............................................................................. 124 9-1 Conversion Sequence General Timing Diagram 10-1 LED Driver Block Diagram ..................................................................................................... 129 11-1 Keyboard Connection .......................................................................................................... 130 12-1 Clock Overview 12-2 HFCLKIN Clock Distribution ................................................................................................... 133 12-3 Example of Wired-OR Clock Request........................................................................................ 135 12-4 HFCLKIN Squared Input Clock 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 13-1 13-2 13-3 13-4 13-5 13-6 13-7 14-1 16-1 16-2 16-3 ........................................................................... ................................................................................................................. ............................................................................................... 32-kHz Oscillator Block Diagram In Master Mode With Crystal .......................................................... 32-kHz Crystal Input ............................................................................................................ 32-kHz Oscillator Block Diagram Without Crystal Option 1 ............................................................... 32-kHz Oscillator Block Diagram Without Crystal Option 2 ............................................................... 32-kHz Oscillator in Bypass Mode Block Diagram Without Crystal Option 3 ........................................... 32-kHz Square- or Sine-Wave Input Clock .................................................................................. 32.768-kHz Clock Output Block Diagram .................................................................................... 32KCLKOUT Output Clock .................................................................................................... HFCLKOUT Output Clock ..................................................................................................... 32KCLKOUT and HFCLKOUT Clock Stabilization Time .................................................................. HFCLKOUT Behavior ......................................................................................................... I2C Interface--Transmit and Receive in Slave Mode ...................................................................... I2S Interface--I2S Master Mode.............................................................................................. I2S Interface--I2S Slave Mode ............................................................................................... TDM Interface--TDM Master Mode .......................................................................................... Voice/BT PCM Interface--Master Mode (Mode 1) ......................................................................... Voice PCM Interface--Slave Mode (Mode 1) ............................................................................... JTAG Interface Timing ......................................................................................................... Debouncing Sequence Chronogram Example .............................................................................. Printed Device Reference ..................................................................................................... TPS65950 Mechanical Package Top View .................................................................................. Ball Size .......................................................................................................................... Copyright (c) 2008-2011, Texas Instruments Incorporated List of Figures 128 131 135 136 137 139 139 139 140 141 142 142 143 143 145 147 147 148 150 150 152 154 160 161 161 7 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com List of Tables 2-1 Ball Characteristics ............................................................................................................... 15 2-2 Signal Description ................................................................................................................ 20 3-1 Absolute Maximum Ratings ..................................................................................................... 27 3-2 VBAT Min Required Per VBAT Ball and Associated Maximum Current .................................................. 27 3-3 Recommended Operating Maximum Ratings 28 3-4 Digital I/O Electrical Characteristics 29 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 5-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 8 ................................................................................ ........................................................................................... Summary of the Power Providers .............................................................................................. Part Names With Corresponding VDD1 Current Support ................................................................... VDD1 dc-dc Regulator Characteristics ........................................................................................ VDD2 dc-dc Regulator Characteristics ........................................................................................ VIO dc-dc Regulator Characteristics........................................................................................... VDAC LDO Regulator Characteristics ......................................................................................... VPLL1 LDO Regulator Characteristics ........................................................................................ VPLL2 LDO Regulator Characteristics ........................................................................................ VMMC1 LDO Regulator Characteristics....................................................................................... VMMC2 LDO Regulator Characteristics....................................................................................... VSIM LDO Regulator Characteristics .......................................................................................... VAUX1 LDO Regulator Characteristics ....................................................................................... VAUX2 LDO Regulator Characteristics ....................................................................................... VAUX3 LDO Regulator Characteristics ....................................................................................... VAUX4 LDO Regulator Characteristics ....................................................................................... Output Load Conditions ......................................................................................................... CP Characteristics ............................................................................................................... Voltage Reference Characteristics ............................................................................................. Backup Battery Charger Characteristics ...................................................................................... Battery Threshold Levels ........................................................................................................ VRRTC LDO Regulator Characteristics ....................................................................................... Power Consumption ............................................................................................................. Regulator States Depending on Use Cases .................................................................................. BOOT Mode Description ........................................................................................................ C027.0 Mode Description ...................................................................................................... C021.M Mode Description ...................................................................................................... System States .................................................................................................................... Earphone Amplifier Output Characteristics ................................................................................... 8- Stereo Hands-Free Output Characteristics .............................................................................. Headset Output Characteristics ................................................................................................ Output Characteristics of a Headset 4-Wire Stereo Jack Without an External FET..................................... Output Characteristics of a Headset 4-Wire Stereo Jack With an External FET ........................................ Output Characteristics of a Headset 5-Wire Stereo Jack ................................................................... Headset Pop-Noise Characteristics ............................................................................................ Predriver Output Characteristics ............................................................................................... Vibrator H-Bridge Output Characteristics ..................................................................................... MCPC and USB-CEA Carkit Audio Downlink Electrical Characteristics .................................................. Digital Audio Filter RX Electrical Characteristics ............................................................................. Digital Voice Filter RX Electrical Characteristics With FS = 8 kHz ......................................................... Digital Voice Filter RX Electrical Characteristics With FS = 16 kHz ....................................................... Boost Electrical Characteristics Versus FS Frequency (FS 22.05 kHz) ................................................. List of Tables 34 35 35 38 41 44 45 46 47 48 49 50 51 52 53 54 54 55 56 56 57 58 58 59 59 59 65 67 68 70 72 73 74 76 77 78 79 80 81 82 83 Copyright (c) 2008-2011, Texas Instruments Incorporated TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 6-15 Boost Electrical Characteristics Versus FS Frequency (FS 24 kHz) ..................................................... 83 6-16 Analog Microphone Bias Module Characteristics ............................................................................ 85 6-17 Characteristics of Analog Microphone Bias Module With a Bias Resistor ................................................ 86 6-18 Digital Microphone Bias Module Characteristics ............................................................................. 88 6-19 Digital Microphone Bias Module Characteristics (2) ......................................................................... 88 6-20 Silicon Microphone Module Characteristics ................................................................................... 90 6-21 ................................................................................................ MCPC and USB-CEA Carkit Audio Uplink Electrical Characteristics ..................................................... Digital Audio Filter TX Electrical Characteristics ............................................................................. Digital Voice Filter TX Electrical Characteristics With FS = 8 kHz ......................................................... Digital Voice Filter TX Electrical Characteristics With FS = 16 kHz ........................................................ MCPC UART and Handshake Mode Timings ............................................................................... USB-CEA Carkit Interface Timing Parameters ............................................................................. USB-CEA Carkit UART Timing Parameters ................................................................................. HS USB Interface Timing Requirement Parameters ....................................................................... HS USB Interface Switching Requirement Parameters ................................................................... 5V-Tolerant Electrical Summary .............................................................................................. LS/FS Single-Ended Receivers ............................................................................................... LS/FS Differential Receiver .................................................................................................... LS/FS Differential Transmitter ................................................................................................. HS Differential Receiver ....................................................................................................... HS Differential Transmitter .................................................................................................... CEA/MCPC/UART Driver ...................................................................................................... Pullup/Pulldown Resistors ..................................................................................................... PHY DPLL Electrical Characteristics ......................................................................................... PHY Power Consumption...................................................................................................... OTG VBUS Electrical........................................................................................................... OTG ID Electrical ............................................................................................................... 6-22 6-23 6-24 6-25 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 Uplink Amplifier Characteristics 93 94 94 96 97 102 103 104 105 105 106 106 107 107 108 109 109 110 110 111 112 112 8-1 Main Charge Electrical Characteristics VBAT = 3.6 V, RS = 0.22 , unless otherwise specified 8-2 Precharge Electrical Characteristics RS = 0.22 , unless otherwise specified ..................................................................................... 121 8-3 CV Mode Electrical Characteristics 8-4 Precharge Detection Characteristics ......................................................................................... 124 8-5 Main Charge Current Limit Indication ........................................................................................ 125 9-1 Electrical Characteristics ....................................................................................................... 126 9-2 Analog Input Voltage Range 9-3 Sequence Conversion Timing Characteristics .............................................................................. 127 10-1 Electrical Characteristics ....................................................................................................... 129 12-1 TPS65950 Input Clock Source Requirements .............................................................................. 132 12-2 HFCLKIN Input Clock Electrical Characteristics ............................................................................ 135 12-3 HFCLKIN Square Input Clock Timing Requirements With Slicer in Bypass ............................................ 135 12-4 Crystal Electrical Characteristics 12-5 Base Oscillator Switching Characteristics ................................................................................... 137 12-6 32-kHz Crystal Input Clock Timing Requirements .......................................................................... 137 12-7 32-kHz Input Square- or Sine-Wave Clock Source Electrical Characteristics .......................................... 140 12-8 32-kHz Square-Wave Input Clock Source Timing Requirements ........................................................ 140 12-9 32KCLKOUT Output Clock Electrical Characteristics ...................................................................... 141 12-10 32KCLKOUT Output Clock Switching Characteristics ..................................................................... 141 .................................................................. .......................................................................................... .................................................................................................. ............................................................................................. Copyright (c) 2008-2011, Texas Instruments Incorporated List of Tables 118 123 127 136 9 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com 12-11 HFCLKOUT Output Clock Electrical Characteristics ....................................................................... 142 12-12 HFCLKOUT Output Clock Switching Characteristics ...................................................................... 142 13-1 Timing Parameters 13-2 TPS65950 Interface Target Frequencies .................................................................................... 144 13-3 I2C Interface Timing Requirements 13-4 I2C Interface Switching Requirements ....................................................................................... 146 13-5 I2S Interface--Timing Requirements......................................................................................... 147 13-6 I2S Interface--Switching Characteristics .................................................................................... 148 13-7 TDM Interface Master Mode Timing Requirements ........................................................................ 148 13-8 TDM Interface Master Mode Switching Characteristics 13-9 Voice PCM Interface Timing Requirements (Mode 1) ..................................................................... 150 13-10 Voice PCM Interface Switching Characteristics (Mode 1) ................................................................. 150 13-11 JTAG Interface Timing Requirements........................................................................................ 152 13-12 JTAG Interface Switching Characteristics ................................................................................... 152 14-1 Debouncing Time ............................................................................................................... 153 15-1 TPS65950 External Components ............................................................................................. 155 16-1 TPS65950 Nomenclature Description ........................................................................................ 160 16-2 TPS65950 Thermal Resistance Characteristics ............................................................................ 160 10 List of Tables ............................................................................................................. .......................................................................................... ................................................................... 144 145 149 Copyright (c) 2008-2011, Texas Instruments Incorporated TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Integrated Power Management/Audio Codec Check for Samples: TPS65950 1 Introduction The TPS65950 device is a highly integrated power-management and audio coder/decoder (codec) integrated circuit (IC) that supports the power and peripheral requirements of the OMAPTM application processors. The device contains power management, an audio codec, a universal serial bus (USB) high-speed (HS) transceiver, an ac/USB charger, light-emitting diode (LED) drivers, an analog-to-digital converter (ADC), a real-time clock (RTC), and embedded power control. The power portion of the device contains three buck converters, two controllable by a dedicated SmartReflexTM class-3 interface, multiple low-dropout (LDO) regulators, an embedded power controller (EPC) to manage the power-sequencing requirements of OMAP, and an RTC and backup module. The RTC can be powered by a backup battery when the main supply is not present, and the device contains a coin-cell charger to recharge the backup battery as needed. The USB module provides a HS 2.0 on-the-go (OTG) transceiver suitable for direct connection to the OMAP universal transceiver macrocell interface (UTMI) + low pin interface (ULPI) with an integrated charge pump (CP) and full support for the carkit Consumer Electronics Association (CEA)-936A specification. The Li-ion battery charger supports charging from ac chargers, USB host devices, USB chargers, or carkits. The type of charger is detected automatically by the device, which provides hardware-controlled linear charging with ac chargers, USB chargers, and carkits, in addition to software-controlled charging for all charger types. The audio codec in the device includes five digital-to-analog converters (DACs) and two ADCs to provide multiple voice channels and stereo downlink channels that can support all standard audio sample rates through several inter-IC sound (I2STM)/time division multiplexing (TDM) format interfaces. The audio output stages on the device include stereo headset amplifiers, two integrated class-D amplifiers providing stereo differential outputs, predrivers for line outputs, and an earpiece amplifier. The input audio stages include three differential microphone inputs, stereo line inputs, and interface for digital micrphones. Automatic and programmable gain control is available with all necessary digital filtering, side-tone functions, and pop-noise reduction. The device also provides a auxiliary modules, including LED drivers, and ADC, keypad interface, and general-purpose inputs/outputs (GPIOs). The LED driver can power two LED circuits to illuminate a panel or provide user indicators. The drivers also provide pulse width modulation (PWM) circuits to control the illumination levels of the LEDs. The ADC monitors signals entering the device, such as supply and charging voltages, and has multiple additional external ADC inputs for system use. The keypad interface implements a built-in scanning algorithm to decode hardware-based key presses and to reduce software use, with multiple additional GPIOs that can be used as interrupts when they are configured as inputs. This TPS65950 Data Manual describes the electrical and mechanical specifications for the TPS65950. It covers the following topics: * TPS65950 terminals: Assignment, multiplexing, electrical characteristics, and functional description (see Section 2, Terminal Description) * Electrical characteristic requirements: Maximum and recommended operating conditions, digital input/output (I/O) characteristics (see Section 3, Electrical Characteristics) * Power module, including the power provider, power references, power control, power consumption, and power management with the on and off sequences (see Section 4, Power Module) * RTC and EPC (see Section 5, Real-Time Clock and Embedded Power Controller) * Audio/voice module with the electrical characteristics and the application schematics for the downlink and uplink paths (see Section 6, Audio/Voice Module) Copyright (c) 2008-2011, Texas Instruments Incorporated Introduction 11 TPS65950 www.ti.com * * * * * * * * 1.1 1 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Battery charger interface (see Section 8, Battery Interface) Various modules: Monitoring analog-to-digital conversion (MADC), LED drivers, and keyboard (see Section 9, MADC, Section 10, LED Drivers, and Section 11, Keyboard) Clock specifications: Clock slicer, input and output clocks (see Section 12, Clock Specifications) Timing requirements and switching characteristics (ac timings) of the interfaces (see Section 13, Timing Requirements and Switching Characteristics) Deboucing time (see Section 14, Debouncing Time) External components for the application schematics (see Section 15, External Components) Thermal resistance characteristics, device nomenclature, and mechanical data about the available packaging (see Section 16, TPS65950 Package) Glossary of acronyms and abbreviations used in this data manual (see Section 17, Glossary) Features 2 * Power: - Three efficient stepdown converters * VDD1: TPS65950A2 with 1.2A and TPS65950A3 with 1.4A (for 1GHz speed) * VDD2: 600mA * VIO: 700mA - 10 external linear LDOs for clocks and peripherals - SmartReflex dynamic voltage management * Audio: - Voice codec - 15-bit linear codec (8 and 16 kHz) - Differential input main and submicrophones - Differential headset microphone input - Auxiliary/FM input (mono or stereo) - Differential 32- speaker and 16- headset drivers (external predrivers for class D) - 8- stereo class-D drivers - Pulse code modulation (PCM) and TDM interfaces - Bluetooth(R) interface - Automatic level control (ALC) - Digital and analog mixing - 16-bit linear audio stereo DAC (96, 48, 44.1, and 32 kHz, and derivatives) - 16-bit linear audio stereo ADC (48, 44.1, and 32 kHz, and derivatives) - Digital microphone inputs - Carkit * Charger: - Li-ion, Li-on polymer, and cobalt-nickel-manganese charger - Supports charging with ac-regulated charger (maximum 7 V), USB host devices, Mobile Computing Promotion Consortium (MCPC) devices, USB chargers, and carkit chargers (maximum 7 V) - Backup battery charger * USB: - USB 2.0 OTG-compliant HS transceivers - 12-bit ULPI - USB power supply (5-V CP for VBUS) - CEA-2011: OTG transceiver interface specification - CEA-936A: Mini-USB analog carkit interface specification - MCPC ME-universal asynchronous receiver/transmitter (UART) GL-006 specification * Additional features: - LED driver circuit for two external LEDs - 10-bit MADC with 3 to 8 external inputs - RTC and retention modules - HS inter-integrated circuit (I2CTM) serial control - Thermal shutdown and hot-die detection - Keypad interface (up to 8 x 8) - External vibrator (vibrator) control - 19 GPIO devices - 0.4-mm pitch, 209 pin, 7 x 7 mm package 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Bluetooth is a registered trademark of Bluetooth SIG, Inc. Copyright (c) 2008-2011, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TPS65950 www.ti.com 1.2 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 TPS65950 Block Diagram Figure 1-1 is a block diagram of the TPS65950. Device Digital signal(s) Audio RX amplifiers Mic amplifiers Analog volume control D/A converters A/D converters Differential vibrator Carkit preamplifiers Analog signal(s) Interface subchip(D) Audio PLL PIH AUDIO analog Digital mic interface Analog and digital mic bias Clocks Clock generator I2C A pad I2C B pad TAP OCP Clk In/Out Wrapper digital Card Det1 GPIO Audio and voice filters (RX and TX paths) + Vibrator control Bluetooth interface PCM (2) PCM interface PCM (4) TDM/I2S interface TDM (4) SIH Card Det2 GPIO pad AUDIO digital TAP Audio subchip (A-D) TAP TAP Clocks Clocks Clocks SIH_INT OCP OCP SR TAP OCP SIH_INT OCP RTC Felica Vibrator control (D) PMC slave Smart Reflex Slave OCP wrapper 13 MHz/32 kHz Power digital RTC 32 kHz Clock slicer Power control (BBS-backup Thermal monitor system Power provider (LDOs-DCDCs) VRRTC-UVLO) OTG module USB precharge module USB2.0 transceiver ULPI (12) UART(2) USB subchip (A-D) BERDATA Auxiliary subchip (A-D) BCI digital Keypad (D) Power analog USB power supply BERCLK TAP Shundan Clocks SIH OCP PMC master SIH_INT SIH_INT USB digital (ULPI/ registers interrupts CEA and MCPC carkit) Analog carkit interfaces RC oscillator BCITOP Precharge loop Main loop Precharge PM Main DAC Precharge status Main aux Shifters BCI analog LEDTOP Power references (Vref-Iref-BandGap) LED digital MADC digital state-machine LED analog Power subchip (A-D) LedSync MADC analog (SAR-Vref) MADCTOP StartADC 032-003 Figure 1-1. TPS65950 Block Diagram Introduction Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 13 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 2 www.ti.com Terminal Description Figure 2-1 shows the ball locations for the 209-ball plastic ball grid array (PBGA) package and is used with Table 2-1 to locate signal names and ball grid numbers. 032-088 Figure 2-1. PBGA Bottom View 2.1 Corner Balls The four corner balls (see the following list) are not usable for functional pins: * Test * TestV1 * Test.RESET * TestV2 The eight corner adjacent balls are: * RFID.EN * UART1.TXD * JTAG.TDI/BERDATA * JTAG.CLK/BERCLK * PCM.VFS * PCM.VDX * PCM.VDR * PCM.VCK 14 Terminal Description Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 2.2 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Ball Characteristics Table 2-1 describes the terminal characteristics and the signals multiplexed on each pin. The following list describes the column headings in Table 2-1: 1. Ball: Ball number(s) associated with each signal(s) 2. Pin Name: Names of all the signals that are multiplexed on each ball 3. A/D: Analog or digital signal 4. Type: Terminal type when a particular signal is multiplexed on the terminal - I = Input - O = Output - OD = Open drain 5. Reference Level: Voltage applied to the I/O cell (see the power module and battery charger interface [BCI] chapters for values). 6. PU/PD: Denotes the presence of an internal pullup or pulldown. Pullups and pulldowns can be enabled or disabled through software. 7. Min = Minimum value 8. Typ = Typical value 9. Max = Maximum value 10. Buffer Strength: Drive strength of the associated output buffer Table 2-1. Ball Characteristics Pin Name[2] Ball[1] A/D [3] Type[4] Reference Level RL[5] H4 ADCIN0 A I/O VINTANA1.OUT J3 ADCIN1 A I/O VINTANA1.OUT G3 ADCIN2 A I VINTANA2.OUT P5 VCCS A I VBAT + 0.2 N5 VAC A Power VACCHARGER P4 VBATS A I VBAT N4 PCHGAC A I VACCHARGER N6 PCHGUSB A I VBUS N2 VPRECH A O VPRECH N1 BCIAUTO A I VPRECH P6 ICTLUSB1 A O VBUS P1 ICTLUSB2 A O VCCS N7 ICTLAC1 A O VACCHARGER P2 ICTLAC2 A O VCCS R5 VBAT A Power VBAT GPIO0/CD1 D I/O IO_1P8 JTAG.TDO D I/O IO_1P8 GPIO1/CD2 D I/O IO_1P8 JTAG.TMS D I IO_1P8 GPIO2 D I/O IO_1P8 Test1 D I/O IO_1P8 GPIO15 D I/O IO_1P8 Test2 D I/O IO_1P8 GPIO6 D I/O IO_1P8 PWM0 D O IO_1P8 Test3 D I/O IO_1P8 P12 N12 L4 P13 M4 PU[6] (k) PD[6] (k) Min[7] Typ[8] Max[9] Min Typ Max 75 100 202 59 100 144 Buffer Strength (mA)[10] 8 8 2 75 100 202 59 100 144 156 220 450 59 100 144 2 2 2 156 220 450 59 100 144 2 2 75 100 202 59 100 144 4 2 Terminal Description Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 15 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 2-1. Ball Characteristics (continued) Pin Name[2] Reference Level RL[5] PU[6] (k) PD[6] (k) Buffer Strength (mA)[10] A/D [3] Type[4] GPIO7 D I/O IO_1P8 VIBRA.SYNC D I IO_1P8 PWM1 D O IO_1P8 4 Test4 D I/O IO_1P8 2 START.ADC D I IO_1P8 C13 SYSEN D OD/I IO_1P8 C6 CLKEN D O IO_1P8 D7 CLKEN2 D O IO_1P8 G10 CLKREQ D I IO_1P8 F10 INT1 D O IO_1P8 2 F9 INT2 D O IO_1P8 2 A13 NRESPWRON D O IO_1P8 2 B13 NRESWARM D I IO_1P8 2 A11 PWRON D I VBAT B14 NC P7 NSLEEP1 D I IO_1P8 G9 NSLEEP2 D I IO_1P8 D13 CLK256FS (1) D O IO_1P8 VMODE1 D I IO_1P8 Ball[1] N14 J9 F8 Min[7] BOOT0 A/D I/O VBAT J11 BOOT1 A/D I/O VBAT A10 REGEN D OD VBAT H8 MSECURE D I IO_1P8 N16 VREF A Power VREF N15 AGND A Power GND GND I2C.SR.SDA D I/O IO_1P8 VMODE2 D I IO_1P8 I2C.SR.SCL D I/O D4 I2C.CNTL.SDA D D5 I2C.CNTL.SCL D R1 PCM.VCK T2 Max[9] Min Typ Max 2 75 K11 Typ[8] 4.7 100 7.35 202 59 100 144 10 2 2 2 60 100 146 2 5.5 8 12 2 2.5 3.4 12 IO_1P8 2.5 3.4 12 I/O IO_1P8 2.5 3.4 12 I IO_1P8 2.5 3.4 12 D I/O IO_1P8 2 PCM.VDR D I/O IO_1P8 2 T15 PCM.VDX D I/O IO_1P8 2 R16 PCM.VFS D I/O IO_1P8 2 L3 I2S.CLK D I/O IO_1P8 2 K6 I2S.SYNC D I/O IO_1P8 2 K4 I2S.DIN D I IO_1P8 2 K3 I2S.DOUT D O IO_1P8 2 E2 MIC.MAIN.P A I MICBIAS1.OUT F2 MIC.MAIN.M A I MICBIAS1.OUT MIC.SUB.P A I MICBIAS2.OUT DIG.MIC.0 A I VMIC1.OUT MIC.SUB.M A I MICBIAS2.OUT NC C4 2 D6 G2 H2 (1) 16 DIG.MIC.1 A I VMIC2.OUT E3 HSMIC.P A I VINTANA2.OUT F3 HSMIC.M A I VINTANA2.OUT D10 VBAT.LEFT A Power VBAT D9 VBAT.LEFT A Power VBAT B9 IHF.LEFT.P A O VBAT B10 IHF.LEFT.M A O VBAT C10 GND.LEFT A Power GND GND C9 GND.LEFT A Power GND GND D12 VBAT.RIGHT A Power VBAT To avoid reflection on this pin caused by impedance mismatch, a serial resistance (Rs) of 33 must be added. Terminal Description Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 2-1. Ball Characteristics (continued) Pin Name[2] Ball[1] A/D [3] Type[4] Reference Level RL[5] D11 VBAT.RIGHT A Power VBAT B11 IHF.RIGHT.P A O VBAT B12 IHF.RIGHT.M A O VBAT C12 GND.RIGHT A Power GND GND C11 GND.RIGHT A Power GND GND A6 EAR.P A O VINTANA2.OUT A7 EAR.M A O VINTANA2.OUT B4 HSOL A O VINTANA2.OUT PreDriv.LEFT A O VINTANA2.OUT VMID A Power VINTANA2.OUT HSOR A O VINTANA2.OUT PreDriv.RIGHT A O VINTANA2.OUT ADCIN7 A I VINTANA2.OUT F1 AUXL A I VINTANA2.OUT G1 AUXR A I VINTANA2.OUT MICBIAS1.OUT A Power VINTANA2.OUT VMIC1.OUT A Power VINTANA2.OUT MICBIAS2.OUT A Power VINTANA2.OUT VMIC2.OUT A Power VINTANA2.OUT E4 VHSMIC.OUT A Power VINTANA2.OUT D3 MICBIAS.GND Power GND GND PU[6] (k) PD[6] (k) Min[7] Typ[8] Max[9] Min Typ Max 4.7 7.4 10 5.9 7 8.3 Buffer Strength (mA)[10] B7 B5 B8 D1 D2 J4 / J6 /J7 / AVSS1 J8 / E5 A Power GND GND R10 AVSS2 A Power GND GND M15 AVSS3 A Power GND GND C7 AVSS4 A Power GND GND B1 UART1.TXD D OD External 1.8 to 3.3 V GPIO8 D I IO_1P8 UART1.RXD D I IO_1P8 RTSO/ CLK64K.OUT/ BERCLK.OUT D OD VUSB.3P1 ADCIN5 A I VINTANA2.OUT CTSI/ BERDATA.OUT D OD/CMOS/I/O VUSB.3P1 ADCIN3 A I VINTANA2.OUT TXAF A I VUSB.3P1 ADCIN4 A I VINTANA2.OUT RXAF A O VUSB.3P1 ADCIN6 A I VINTANA2.OUT 2 D8 N11 P11 2 4.7 7.4 10 162 280 414 2 N8 N9 L10 MANU D I VUSB.3P1 N10 32KCLKOUT D O IO_1P8 P16 32KXIN A I IO_1P8 P15 32KXOUT A O IO_1P8 A14 HFCLKIN A I IO_1P8 R12 HFCLKOUT D O IO_1P8 R8 VBUS A Power VBUS T10 DP/UART3.RXD A I/O VBUS 2 T11 DN/UART3.TXD A I/O VBUS 2 R11 ID A I/O VBUS 2 L15 UCLK D I IO_1P8 16 STP D I IO_1P8 GPIO9 D I/O IO_1P8 2 DIR D O IO_1P8 16 GPIO10 D I/O IO_1P8 L14 16 75 L13 75 100 100 202 202 59 59 100 100 144 144 2 Terminal Description Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 17 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 2-1. Ball Characteristics (continued) Pin Name[2] Ball[1] A/D [3] Type[4] Reference Level RL[5] PU[6] (k) PD[6] (k) Min[7] Typ[8] Max[9] Min Typ Max 75 100 202 59 100 144 Buffer Strength (mA)[10] NXT D O IO_1P8 GPIO11 D I/O IO_1P8 2 DATA0 D I/O IO_1P8 16 UART4.TXD D I IO_1P8 DATA1 D I/O IO_1P8 UART4.RXD D O IO_1P8 2 DATA2 D I/O IO_1P8 16 UART4.RTSI D I IO_1P8 DATA3 D I/O IO_1P8 UART4.CTSO D O IO_1P8 GPIO12 D I/O IO_1P8 DATA4 D I/O IO_1P8 GPIO14 D I/O IO_1P8 2 DATA5 D I/O IO_1P8 16 GPIO3 D I/O IO_1P8 2 DATA6 D I/O IO_1P8 16 GPIO4 D I/O IO_1P8 2 DATA7 D I/O IO_1P8 16 GPIO5 D I/O IO_1P8 A/D I VBAT M13 16 K14 16 K13 J14 J13 G14 G13 100 140 60 100 140 75 100 202 59 100 144 75 100 202 59 100 144 16 75 F13 75 T16 TEST.RESET T1 TESTV1 A I/O VBAT A16 TESTV2 A I/O VINTANA2.OUT A1 TEST D I IO_1P8 A15 JTAG.TDI/ BERDATA D I IO_1P8 B16 JTAG.TCK/ BERCLK D I IO_1P8 R7 CP.IN A Power VBAT/VBUS T7 CP.CAPP A O CP.CAPP T6 CP.CAPM A O CP.CAPM R6 CP.GND A Power GND GND R9 VBAT.USB A Power VBAT P9 VUSB.3P1 A Power VUSB.3P1 L1 VAUX12S.IN A Power VBAT M2 VAUX1.OUT A Power VAUX1.OUT VAUX2.OUT M3 VAUX2.OUT A Power H15 VPLLA3R.IN A Power VBAT K16 VRTC.OUT A Power VRTC.OUT H14 VPLL1.OUT A Power VPLL1.OUT J15 VSDI.CSI.OUT A Power VSDI.CSI.OUT G16 VAUX3.OUT VAUX3.OUT A Power B2 VAUX4.IN A Power VBAT B3 VAUX4.OUT A Power VAUX4.OUT C1 VMMC1.IN A Power VBAT C2 VMMC1.OUT A Power VMMC1.OUT A3 VMMC2.IN A Power VBAT A4 VMMC2.OUT A Power VMMC2.OUT K2 VSIM.OUT A Power VSIM.OUT P8 VINTUSB1P5. OUT A Power VINTUSB1P5.OUT P10 VINTUSB1P8. OUT A Power VINTUSB1P8.OUT K1 VDAC.IN A Power VBAT L2 VDAC.OUT A Power VDAC.OUT K15 VINT.IN A Power VBAT H3 VINTANA1.OUT A Power VINTANA1.OUT 16 16 75 F14 18 16 60 100 100 100 Terminal Description 202 202 202 59 59 100 100 144 144 59 100 144 30 50 70 60 100 146 2 Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 2-1. Ball Characteristics (continued) Ball[1] Pin Name[2] A/D [3] Type[4] Reference Level RL[5] J2 VINTANA2.OUT A Power VINTANA2.OUT B6 VINTANA2.OUT A Power VINTANA2.OUT L16 VINTDIG.OUT A Power VINTDIG.OUT E15 VDD1.IN A Power VBAT E14 VDD1.IN A Power VBAT D14 VDD1.IN A Power VBAT D16 VDD1.SW A O VBAT D15 VDD1.SW A O VBAT C14 VDD1.SW A O VBAT E13 VDD1.FB A I C16 VDD1.GND A Power GND GND C15 VDD1.GND A Power GND GND B15 VDD1.GND A Power GND GND R13 VDD2.IN A Power VBAT VBAT P14 VDD2.IN A Power N13 VDD2.FB A I T13 VDD2.SW A O VBAT R14 VDD2.SW A O VBAT T14 VDD2.GND A Power GND GND R15 VDD2.GND A Power GND GND P3 VIO.IN A Power VBAT R4 VIO.IN A Power VBAT N3 VIO.FB A I R3 VIO.SW A O VBAT T4 VIO.SW A O VBAT R2 VIO.GND A Power GND GND T3 VIO.GND A Power GND GND M14 BKBAT A Power VBACK C8 IO.1P8 A Power IO_1P8 H13 / H9 / DGND H10 / H11 A Power GND GND LEDGND A Power GND GND GPIO13 D I/O IO_1P8 LEDSYNC D I IO_1P8 LEDA A OD VBAT VIBRA.P A OD VBAT LEDB A OD VBAT VIBRA.M A OD VBAT G8 KPD.C0 D OD IO_1P8 F16 G11 PU[6] (k) PD[6] (k) Min[7] Typ[8] Max[9] Min Typ Max 75 100 202 59 100 144 Buffer Strength (mA)[10] F15 G15 H7 KPD.C1 D OD IO_1P8 G6 KPD.C2 D OD IO_1P8 F7 KPD.C3 D OD IO_1P8 G7 KPD.C4 D OD IO_1P8 F4 KPD.C5 D OD IO_1P8 H6 KPD.C6 D OD IO_1P8 G4 KPD.C7 D OD IO_1P8 K9 KPD.R0 D I IO_1P8 8 10 12 K8 KPD.R1 D I IO_1P8 8 10 12 L8 KPD.R2 D I IO_1P8 8 10 12 K7 KPD.R3 D I IO_1P8 8 10 12 L9 KPD.R4 D I IO_1P8 8 10 12 J10 KPD.R5 D I IO_1P8 8 10 12 K10 KPD.R6 D I IO_1P8 8 10 12 L7 KPD.R7 D I IO_1P8 8 10 12 Terminal Description Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 19 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 2-1. Ball Characteristics (continued) Pin Name[2] Ball[1] C3 C5 A2 2.3 A/D [3] Type[4] GPIO16 D I/O IO_1P8 BT.PCM.VDR D I/O IO_1P8 DIG.MIC.CLK0 D O IO_1P8 GPIO17 D I/O IO_1P8 BT.PCM.VDX D I/O IO_1P8 DIG.MIC.CLK1 D O IO_1P8 RFID.EN D O VMMC2.OUT PU[6] (k) Reference Level RL[5] PD[6] (k) Min[7] Typ[8] Max[9] Min Typ Max 75 100 202 59 100 144 75 100 202 59 100 144 Buffer Strength (mA)[10] Signal Description Table 2-2 lists the signals on the TPS65950; some signals are available on multiple pins. Table 2-2. Signal Description Signal Name Module ADC Charger GPIOs/ JTAG START. ADC 20 Description Type (1) Configuration By Default After Reset Released Ball Signal Type(1) Internal Pull or Not Unused Features(2) ADCIN0 Battery type I/O H4 ADCIN0 I GND ADCIN1 Battery temperature I/O J3 ADCIN1 I GND ADCIN2 General-purpose (GP) ADC input I G3 ADCIN2 I GND VCCS Charge current sensing I P5 VCCS I Cap to GND(3) VAC Charge device input voltage Power N5 VAC Power GND VBATS Charge current sensing I P4 VBATS I Cap to GND(3) PCHGAC ac precharge sense signal. Used also for EEPROM I N4 PCHGAC I GND PCHGUSB USB precharge sense signal I N6 PCHGUSB I GND VPRECH Precharge regulator output O N2 VPRECH O Cap to GND(3) BCIAUTO Linear charge specific boot mode I N1 BCIAUTO I GND ICTLUSB1 USB power device control O P6 ICTLUSB1 O Floating ICTLUSB2 USB power device control O P1 ICTLUSB2 O Floating ICTLAC1 ac power device control O N7 ICTLAC1 O Floating ICTLAC2 ac power device control O P2 ICTLAC2 O Floating VBAT Battery voltage sensing Power R5 VBAT Power VBAT GPIO0/CD1 GPIO0/card detection 1 I/O JTAG.TDO JTAG test data output I/O P12 GPIO0 I PD Floating GPIO1/CD2 GPIO1/card detection 2 I/O JTAG.TMS JTAG test mode state N12 GPIO1 I PD Floating GPIO2 GPIO2 I/O Test1 Test1 pin used in test mode only I/O L4 GPIO2 I PD Floating GPIO15 GPIO15 I/O Test2 Test2 pin used in test mode only I/O P13 GPIO15 I PD Floating GPIO6 GPIO6 I/O PWM0 Pulse width driver 0 O M4 GPIO6 I PD Floating Test3 Test3 pin used in test mode only (controlled by JTAG) I/O GPIO7 GPIO7 I/O VIBRA.SYNC Vibrator on-off synchronization I PWM1 Pulse width driver O N14 GPIO7 I PD Floating Test4 Test4 pin used in test mode only (controlled by JTAG) I/O START.ADC ADC conversion request START.ADC I I I J9 Terminal Description GND Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 2-2. Signal Description (continued) Signal Name Module CONTROL VREF 2 IC SmartReflex I2C PCM TDM ANA.MIC Headset microphone Type(1) Description Configuration By Default After Reset Released Ball Signal Type (1) Internal Pull or Not PU Unused Features(2) SYSEN System enable output OD/I C13 SYSEN OD CLKEN Clock enable O C6 CLKEN O Floating CLKEN2 Clock enable 2 O D7 CLKEN2 O CLKREQ Clock request I G10 CLKREQ I INT1 Output interrupt line 1 O F10 INT1 O Floating INT2 Output interrupt line 2 O F9 INT2 O Floating NRESPWRON Output control the NRESPWRON of the application processor O A13 NRESPWRON O Floating NRESWARM Input, detect user action on the reset button I B13 NRESWARM I GND PWRON Input, detect a control command to start or stop the system I A11 PWRON I VBAT NC Not connected B14 NC NSLEEP1 Sleep request from device 1 I P7 NSLEEP1 I NSLEEP2 Sleep request from device 2 I G9 NSLEEP2 I GND CLK256FS Control for 256 x FS CLK output O D13 CLK256FS O Floating VMODE1 Digital voltage scaling linked with VDD1 I F8 VMODE1 I GND BOOT0 Boot pin 0 I K11 BOOT0 I PD BOOT1 Boot pin 1 I J11 BOOT1 I PD N/A REGEN Enable signal for external LDO OD A10 REGEN OD PU Floating MSECURE Security and digital rights management I H8 MSECURE VREF Reference voltage Power N16 AGND Analog ground for reference voltage Power GND NC Not connected I2C.SR.SDA SmartReflex I2C data VMODE2 Digital voltage scaling linked with VDD2 I2C.SR.SCL SmartReflex I2C data I/O I2C.CNTL.SDA GP I2C data I2C.CNTL.SCL GP I2C clock PCM.VCK Floating Floating PD GND Floating GND N/A I N/A VREF Power N/A N15 AGND Power GND GND C4 Signal not functional(4) D6 VMODE2 I/O D4 I2C.CNTL.SDA I/O PU I/O D5 I2C.CNTL.SCL I/O PU Data clock (voice port) I/O R1 PCM.VCK I/O PCM.VDR Data receive (voice port) I/O T2 PCM.VDR I/O GND PCM.VDX Data transmit (voice port) I/O T15 PCM.VDX I/O Floating PCM.VFS Frame synchronization (voice port) I/O R16 PCM.VFS I/O Floating I2S.CLK Clock signal (audio port) I/O L3 I2S.CLK I/O Floating I2S.SYNC Synchronization signal (audio port) I/O K6 I2S.SYNC I/O Floating I2S.DIN Data receive (audio port) I K4 I2S.DIN I GND I2S.DOUT Data transmit (audio port) O K3 I2S.DOUT O Floating MIC.MAIN.P Main microphone left input (P) I E2 MIC.MAIN.P I Cap to GND MIC.MAIN.M Main microphone left input (M) I F2 MIC.MAIN.M I Cap to GND MIC.SUB.P Main microphone right input (P) I DIG.MIC.0 Digital microphone 0 input data I G2 MIC.SUB.P I Cap to GND MIC.SUB.M Main microphone right input (M) I DIG.MIC.1 Digital microphone 1 input data I H2 MIC.SUB.M I Cap to GND HSMIC.P Headset microphone input (P) I E3 HSMIC.P I Cap to GND HSMIC.M Headset microphone input (M) I F3 HSMIC.M I Cap to GND I/O Floating I I GND N/A N/A Floating Terminal Description Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 21 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 2-2. Signal Description (continued) Module Hands-free Signal Name AUX input VMIC BIAS Signal Type (1) Internal Pull or Not Unused Features(2) Battery voltage input Power D10 VBAT.LEFT Power Battery voltage input Power D9 VBAT.LEFT Power VBAT IHF.LEFT.P Hands-free speaker output left (P) O B9 IHF.LEFT.P O Floating IHF.LEFT.M Hands-free speaker output left (M) VBAT O B10 IHF.LEFT.M O Floating C10 GND.LEFT Power GND GND Power GND GND GND.LEFT GND Power GND GND.LEFT GND Power GND C9 GND.LEFT VBAT.RIGHT Battery voltage input Power D12 VBAT.RIGHT Power VBAT VBAT.RIGHT Battery voltage input Power D11 VBAT.RIGHT Power VBAT GND.RIGHT GND Power GND C12 GND.RIGHT Power GND GND GND.RIGHT GND Power GND C11 GND.RIGHT Power GND GND IHF.RIGHT.P Hands-free speaker output right (P) O B11 IHF.RIGHT.P O Floating IHF.RIGHT.M Hands-free speaker output right (M) O B12 IHF.RIGHT.M O Floating EAR.P Earpiece output differential output (P) O A6 EAR.P O Floating EAR.M Earpiece output differential output (M) O A7 EAR.M O Floating HSOL Differential/single-ended headset left output O B4 HSOL O Floating PreDriv.LEFT Predriver output left P for external class-D amplifier O B7 VMID Power Floating VMID Pseudo-ground for headset output Power HSOR Differential/single-ended headset right output (P) O B5 HSOR O Floating PreDriv.RIGHT Predriver output right P for external class-D amplifier O B8 ADCIN7 I GND ADCIN7 GP ADC input 7 I AUXL Auxiliary audio input left I F1 AUXL I Cap to GND AUXR Auxiliary audio input right I G1 AUXR I Cap to GND MICBIAS1. OUT Analog microphone bias 1 Power D1 MICBIAS1.OUT Power Floating VMIC1.OUT Digital microphone power supply 1 Power MICBIAS2. OUT Analog microphone bias 2 Power D2 MICBIAS2.OUT Power Floating VMIC2.OUT Digital microphone power supply 2 Power VHSMIC.OUT Headset microphone bias Power E4 VHSMIC.OUT Power Floating Dedicated ground for microphones Power GND D3 MICBIAS.GND Power GND GND Power GND GND AVSS1 AVSS2 Power GND Analog ground AVSS3 AVSS4 22 Configuration By Default After Reset Released VBAT.LEFT MICBIAS.GND Headset UART Ball VBAT.LEFT Earpiece Headset Type(1) Description UART1.TXD Headset UART transmit data OD GPIO8 GPIO8 I/O UART1.RXD Headset universal asynchronous receiver/transmitter (UART) receive data/switch detection I J4/J6/ J7/J8/E5 AVSS1 R10 AVSS2 M15 AVSS3 C7 AVSS4 B1 UART1.TXD D8 GPIO8 Terminal Description OD PU Floating I PD Floating Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 2-2. Signal Description (continued) Signal Name Module Type(1) Description Signal RTSO/ CLK64K.OUT/ BERCLK.OUT Ready-to-send output/ 64-kHz output clock/ Bit error ratio (BER) clock out in test mode ADCIN5 GP ADC input 5 Clear-to-send input/ BERDATAOUT in test mode ADCIN3 GP ADC input 3 MCPC ULPI OD/ CMOS/ I/O I GP ADC input 4 I RXAF USB PHY Internal Pull or Not Unused Features(2) N11 RTSO/ CLK64K.OUT/ BERCLK.OUT OD Floating P11 CTSI/ BERDATA.OUT OD GND N8 TXAF I Cap to GND N9 RXAF O Floating I TXAF Clock OD Type (1) I CTSI/ BERDATA.OUT ADCIN4 Configuration By Default After Reset Released Ball O ADCIN6 GP ADC input 6 I MANU Manufacturer pin I L10 MANU I 32KCLKOUT Buffered output of the 32-kHz digital clock O N10 32KCLKOUT O 32KXIN Input of the 32-kHz oscillator I P16 32KXIN I N/A 32KXOUT Output of the 32-kHz oscillator O P15 32KXOUT O Floating HFCLKIN Input of the digital (or sine) HS clock I A14 HFCLKIN I N/A HFCLKOUT HS clock output O R12 HFCLKOUT VBUS VBUS power rail Power R8 VBUS DP/ UART3.RXD USB data P/USB carkit receive data/UART3 receive data I/O T10 DN/ UART3.TXD USB data N/USB carkit transmit data/UART3 transmit data I/O ID USB ID UCLK STP GPIO9 GPIO9 DIR HS USB direction O GPIO10 GPIO10 I/O NXT HS USB next O GPIO11 GPIO11 I/O DATA0 HS USB Data0 I/O UART4.TXD UART4.TXD DATA1 HS USB Data1 I/O UART4.RXD UART4.RXD O DATA2 HS USB Data2 I/O UART4.RTSI UART4.RTSI DATA3 HS USB Data3 UART4.CTSO UART4.CTSO O GPIO12 GPIO12 I/O DATA4 HS USB Data4 I/O GPIO14 GPIO14 I/O DATA5 HS USB Data5 I/O GPIO3 GPIO3 I/O DATA6 HS USB Data6 I/O GPIO4 GPIO4 I/O DATA7 HS USB Data7 I/O GPIO5 GPIO5 I/O PU Floating Floating O Floating Power N/A DP/UART3.RXD I/O N/A T11 DN/UART3.TXD I/O N/A I/O R11 ID I/O Connected to VRUSB3V1 HS USB clock I L15 UCLK O Floating HS USB stop I L14 STP I L13 DIR O Floating M13 NXT O Floating K14 DATA0 O Floating K13 DATA1 O Floating J14 DATA2 O Floating J13 DATA3 O Floating G14 DATA4 O Floating G13 DATA5 O Floating F14 DATA6 O Floating F13 DATA7 O Floating I/O I I PU Floating I/O Terminal Description Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 23 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 2-2. Signal Description (continued) Signal Name Module Test USB CP Type(1) Description Configuration By Default After Reset Released Ball Signal Test.RESET Reset T2 device (except power state-machine) TestV1 Analog test TestV2 Analog test I Type (1) Test.RESET I/O T1 TestV1 I/O Floating I/O A16 TestV2 I/O Floating Test Selection between JTAG mode and application mode for JTAG/GPIOs (with PU or PD) I A1 Test I JTAG.TDI/ BERDATA JTAG.TDI/BERDATA I A15 JTAG.TDI/ BERDATA I GND JTAG.TCK/ BERCLK JTAG.TCK/BERCLK I B16 JTAG.TCK/ BERCLK I GND CP.IN CP input voltage Power R7 CP.IN Power VBAT CP.CAPP CP flying capacitor P O T7 CP.CAPP O Floating CP.CAPM CP flying capacitor M O Floating Power GND GND T6 CP.CAPM R6 CP.GND PD Unused Features(2) T16 O I Internal Pull or Not PD GND Floating CP.GND CP ground Power GND VBAT.USB VBAT.USB USB LDOs (VINTUSB1P5, VINTUSB1P8, VUSB.3P1) VBAT Power R9 VBAT.USB Power VBAT USB.LDO VUSB.3P1 USB LDO output Power P9 VUSB.3P1 Power N/A VAUX12S.IN VAUX1/VAUX2/VSIM LDO input voltage Power L1 VAUX12S.IN Power VBAT VAUX1.OUT VAUX1 LDO output voltage Power M2 VAUX1.OUT Power Floating VAUX2.OUT VAUX2 LDO output voltage Power M3 VAUX2.OUT Power Floating VPLLA3R VPLLA3R.IN Input for VPLL1, VPLL2, VAUX3, VRTC LDOs Power H15 VPLLA3R.IN Power VBAT VRTC VRTC.OUT VRTC internal LDO output (internal use only) Power K16 VRTC.OUT Power N/A VPLL1 VPLL1.OUT LDO output voltage Power H14 VPLL1.OUT Power Floating VPLL2 VSDI.CSI.OUT Output voltage of the regulator Power J15 VSDI.CSI.OUT Power Floating VAUX3 VAUX3.OUT VAUX3 LDO output voltage Power G16 VAUX3.OUT Power Floating VAUX4.IN VAUX4 LDO input voltage Power B2 VAUX4.IN Power VBAT VAUX4.OUT VAUX4 LDO output voltage Power B3 VAUX4.OUT Power Floating VMMC1.IN VMMC1 LDO input voltage Power C1 VMMC1.IN Power VBAT VMMC1.OUT VMMC1 LDO output voltage Power C2 VMMC1.OUT Power Floating VMMC2.IN VMMC2 LDO input voltage Power A3 VMMC2.IN Power VBAT VMMC2.OUT VMMC2 LDO output voltage Power A4 VMMC2.OUT Power Floating VSIM VSIM.OUT VSIM LDO output voltage Power K2 VSIM.OUT Power Floating VINTUSB1 P5 VINTUSB1P5. OUT VINTUSB1P5 internal LDO output (internal use only) Power P8 VINTUSB1P5. OUT Power Floating VINTUSB1 P8 VINTUSB1P8. OUT VINTUSB1P8 internal LDO output (internal use only) Power P10 VINTUSB1P8. OUT Power Floating VDAC.IN Input for VDAC, VINTANA1, and VINTANA2 LDOs Power K1 VDAC.IN Power VBAT VAUX1 VAUX2 VAUX4 VMMC1 VMMC2 Video DAC VDAC.OUT Output voltage of the regulator Power L2 VDAC.OUT Power Floating VINT VINT.IN Input for VINTDIG LDO Power K15 VINT.IN Power VBAT VINTANA1 VINTANA1. OUT VINTANA1 internal LDO output (internal use only) Power H3 VINTANA1.OUT Power N/A VINTANA2. OUT VINTANA2 internal LDO output (internal use only) Power J2 VINTANA2.OUT Power N/A VINTANA2. OUT VINTANA2 internal LDO output (internal use only) Power B6 VINTANA2.OUT Power N/A VINTDIG.OUT VINTDIG internal LDO output (internal use only) Power L16 VINTDIG.OUT Power N/A VINTANA2 VINTDIG 24 Terminal Description Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 2-2. Signal Description (continued) Module Signal Name Type(1) Description Ball Configuration By Default After Reset Released Signal Type (1) Internal Pull or Not Unused Features(2) VDD1.IN VDD1 dc-dc input voltage Power E15 VDD1.IN Power VBAT VDD1.IN VDD1 dc-dc input voltage Power E14 VDD1.IN Power VBAT VDD1.IN VDD1 dc-dc input voltage Power D14 VDD1.IN Power VBAT VDD1.SW VDD1 dc-dc switch O D16 VDD1.SW O Floating VDD1.SW VDD1 dc-dc switch O D15 VDD1.SW O Floating VDD1.SW VDD1 dc-dc switch O C14 VDD1.SW O Floating VDD1.FB VDD1 dc-dc output voltage (feedback) I E13 VDD1.FB I GND VDD1.GND VDD1 dc-dc ground Power GND C16 VDD1.GND Power GND GND VDD1.GND VDD1 dc-dc ground Power GND C15 VDD1.GND Power GND GND VDD1.GND VDD1 dc-dc ground Power GND B15 VDD1.GND Power GND GND VDD2.IN VDD2 dc-dc input voltage Power R13 VDD2.IN Power VBAT VDD2.IN VDD2 dc-dc input voltage Power P14 VDD2.IN Power VBAT VDD2.FB VDD2 dc-dc output voltage (feedback) I N13 VDD2.FB I GND VDD2.SW VDD2 dc-dc switch O T13 VDD2.SW O Floating VDD2.SW VDD2 dc-dc switch O R14 VDD2.SW O Floating VDD2.GND VDD2 dc-dc ground Power GND T14 VDD2.GND Power GND GND VDD2.GND VDD2 dc-dc ground Power GND R15 VDD2.GND Power GND GND VIO.IN VIO dc-dc input voltage Power P3 VIO.IN Power VBAT VIO.IN VIO dc-dc input voltage Power R4 VIO.IN Power VBAT VIO.FB VIO dc-dc output voltage (feedback) I N3 VIO.FB I GND VIO.SW VIO dc-dc switch O R3 VIO.SW O Floating VIO.SW VIO dc-dc switch O T4 VIO.SW O Floating VIO.GND VIO dc-dc ground Power GND R2 VIO.GND Power GND GND VIO.GND VIO dc-dc ground Power GND T3 VIO.GND Power GND GND Backup battery BKBAT Backup battery Power M14 BKBAT Power GND Digital VDD IO.1P8 TPS65950 I/O input Power C8 IO.1P8 Power N/A Power GND GND GND VDD1 VDD2 VIO Digital ground LED driver DGND Digital ground Power GND LEDGND LED driver ground Power GND GPIO13 GPIO13 LEDSYNC LED synchronization input LEDA LED leg A VIBRA.P H-bridge vibrator P LEDB LED leg B VIBRA.M H-bridge vibrator M H13 / H9 / H10 / DGND H11 F16 LEDGND Power GND G11 GPIO13 I OD F15 Signal not functional(4) Floating OD G15 Signal not functional(4) Floating I/O I PD Floating Terminal Description Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 25 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 2-2. Signal Description (continued) Module Keypad Bluetooth/ digital microphone RFID Signal Name Type(1) Description Ball Configuration By Default After Reset Released Signal Type (1) Internal Pull or Not Unused Features(2) KPD.C0 Keypad column 0 OD G8 KPD.C0 OD Floating KPD.C1 Keypad column 1 OD H7 KPD.C1 OD Floating KPD.C2 Keypad column 2 OD G6 KPD.C2 OD Floating KPD.C3 Keypad column 3 OD F7 KPD.C3 OD Floating KPD.C4 Keypad column 4 OD G7 KPD.C4 OD Floating KPD.C5 Keypad column 5 OD F4 KPD.C5 OD Floating KPD.C6 Keypad column 6 OD H6 KPD.C6 OD Floating KPD.C7 Keypad column 7 OD G4 KPD.C7 OD KPD.R0 Keypad row 0 I K9 KPD.R0 I PU Floating KPD.R1 Keypad row 1 I K8 KPD.R1 I PU Floating KPD.R2 Keypad row 2 I L8 KPD.R2 I PU Floating KPD.R3 Keypad row 3 I K7 KPD.R3 I PU Floating KPD.R4 Keypad row 4 I L9 KPD.R4 I PU Floating KPD.R5 Keypad row 5 I J10 KPD.R5 I PU Floating KPD.R6 Keypad row 6 I K10 KPD.R6 I PU Floating KPD.R7 Keypad row 7 I L7 KPD.R7 I PU Floating GPIO16 Bluetooth PCM receive data I/O BT.PCM.VDR GPIO16 I/O C3 GPIO16 I PD Floating DIG.MIC.CLK0 Digital microphone clock 0 O GPIO17 GPIO17 BT.PCM.VDX Bluetooth PCM transmit data C5 GPIO17 I PD Floating DIG.MIC.CLK1 Digital microphone clock 1 O RFID.EN Enable for the radio frequency identification (RFID) device O A2 RFID.EN O I/O Floating Floating (1) I = Input; O = Output; OD = Open drain (2) This column provides the connection when the associated feature is not used or not connected. When there is a pin muxing, not all functions on the muxed pin are used. But even if a function is not used, the Default Configuration column applies. Connection criteria: - Analog pins: - For input: GND - For output: Floating (except VPRECH is connected to GND) - For I/O if input by default: GND (except for audio features input: capacitor to ground with a 100-nF typical value capacitor) - Digital pins: - For input: GND (except keypad and STP are left floating) - For input and pullup: Floating - For output: Floating - For I/O and pullup: Floating N/A (not applicable): When the associated feature is mandatory for good functioning of the TPS65950. (3) The VPRECH, VBATS, and VCCS signals must be connected to each other and with the CPRECH capacitor to GND (see Section 8.2.3, Configuration with BCI Not Used). (4) Signal not functional indicates that no signal is presented on the pad after a release reset. 26 Terminal Description Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 3 Electrical Characteristics 3.1 Absolute Maximum Ratings Table 3-1 lists the absolute maximum ratings. Table 3-1. Absolute Maximum Ratings Parameter Main battery supply voltage Test Conditions Min (1) Voltage on any input Where supply represents the voltage applied to the power supply pin associated with the input Storage temperature range Ambient temperature range Junction temperature (TJ) 3.2 Max Unit 2.1 4.5 V 0.0 1.0*Supply V -55 125 C -40 At 1.4W (Theta JB 11C/W 2S2P board) Junction temperature (TJ) for parametric compliance (1) Typ -40 85 C 105 C 105 C The product can tolerate voltage spikes of 5.2 V for a total duration of 10 milliseconds. Minimum Voltages and Associated Currents Table 3-2 lists the VBAT minimum and maximum currents per VBAT ball. Table 3-2. VBAT Min Required Per VBAT Ball and Associated Maximum Current Category Pin and Module VBAT pin name VDD_VPLLA3R_IN_6POV Internal module supplied Output Voltage (V) VBAT Minimum (V) 340 VPLL1 (LDO) 40 1.0 / 1.2 / 1.3 / 1.8 / 2.8 / 3.0 Maximum (2.7, output voltage selected + 250 mV) VPLL2 (LDO) 100 0.7 / 1.0 / 1.2 / 1.3 / 1.5 / 1.8 / 1.85 / 2.5 / 2.6 / 2.8 / 2.85 / 3.0 / 3.15 Maximum (2.7, output voltage selected + 250 mV) VAUX3 (LDO) 200 1.5 / 1.8 / 2.5 / 2.8 / 3.0 Maximum (2.7, output voltage selected + 250 mV) VDD1 core (DCDC) <1 2.7 VDD2 core (DCDC) <1 2.7 SYSPOR (power ref) <1 2.7 PBIAS (power ref) <1 2.7 VBAT pin name VDD_VDAC_IN_6POV Internal module supplied Maximum Current Specified (mA) 370 VDAC (LDO) 70 1.2 / 1.3 / 1.8 Maximum (2.7, output voltage selected + 250 mV) VINTANA1 (LDO) 50 1.5 Maximum (2.7, output voltage selected + 250 mV) VINTANA2 (LDO) 250 2.5 / 2.75 Maximum (2.7, output voltage selected +250 mV) VIO core (DCDC) <1 2.7 VAUX4 core (LDO) <1 2.7 VBAT pin name VDD_VAUXI2S_IN_6POV 350 Electrical Characteristics Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 27 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 3-2. VBAT Min Required Per VBAT Ball and Associated Maximum Current (continued) Category Internal module supplied Pin and Module Maximum Current Specified (mA) Output Voltage (V) VBAT Minimum (V) VAUX1 (LDO) 200 1.5 / 1.8 / 2.5 / 2.8 / 3.0 Maximum (2.7, output voltage selected + 250 mV) VAUX2 (LDO) 100 1.3 / 1.5 / 1.6 / 1.7 / 1.8 / 1.9 / 2.0 / 2.1 / 2.2 / 2.3 / 2.4 / 2.5 / 2.8 Maximum (2.7, output voltage selected + 250 mV) VSIM (LDO) 50 1.0 / 1.2 / 1.3 / 1.8 / 2.8 / 3.0 Maximum (2.7, output voltage selected + 250 mV) 1.0 / 1.2 / 1.3 / 1.5 / 1.8 / 1.85 / 2.5 / 2.6 / 2.8 / 2.85 / 3.0 / 3.15 Maximum (2.7, output voltage selected + 250 mV) VBAT pin name VDD_VMMC2_IN_6POV 100 VMMC2 (LDO) 100 Power_REGBATT 0.001 VBAT pin name VDD_VMMC1_IN_6POV VMMC1 (LDO) 220 Power_REGBATT Maximum (2.7, output voltage selected + 250 mV) 2.7 131 VINTDIG (LDO) 80 1.0 / 1.2 / 1.3 / 1.5 Maximum (2.7, output voltage selected + 250 mV) VRRTC (LDO) 30 1.5 Maximum (2.7, output voltage selected + 250 mV) VBACKUP (LDO) 1 2.5 / 3.0 / 3.1 / 3.2 Maximum (2.7, output voltage selected + 250 mV) 0.7 / 1.0 / 1.2 / 1.3 / 1.5 / 1.8 / 1.85 / 2.5 / 2.6 / 2.8 / 2.85 / 3.0 / 3.15 output voltage selected + 250 mV VBAT pin name VDD_VAUX4_IN_6POV 100 VAUX4 (LDO) 3.3 1.85 / 2.85 / 3.0 / 3.15 0.001 VBAT pin name VDD_VINT_IN_6POV Internal module supplied 2.7 220 100 Recommended Operating Conditions Table 3-3 lists the recommended operating maximum ratings. Table 3-3. Recommended Operating Maximum Ratings Parameter Min Typ Max Unit 2.7(1) 3.6 4.5 V Backup battery supply voltage 1.8 3.2 3.3 V Ambient temperature range -40 85 C Main battery supply voltage (1) 2.7 V is the minimum threshold for the battery at which the device will turn OFF. However, the minimum voltage at which the device will power ON is 3.2 V 100 mV (if PWRON does not have a switch and is connected to VBAT) considering battery plug as the device switch on event. If PWRON has a switch then 3.2 V is the minimum for the device to turn ON. 3.4 Digital I/O Electrical Characteristics Table 3-4 describes the digital I/O electrical characteristics. * RL: Reference level voltage applied to the I/O cell * VOL: Low-level output voltage * VOH: High-level output voltage * VIL: Low-level input voltage * VIH: High-level input voltage 28 Electrical Characteristics Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 3-4. Digital I/O Electrical Characteristics VOL (V) VOH (V) VIL (V) VIH (V) Min Max Min Max Min Max Min Max Max Freq (MHz) 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 33 30 5.2 5.2 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 33 30 5.2 5.2 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2 START.ADC 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 6 16.7 16.7 SYSEN 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL CLKEN 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 CLKEN2 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 CLKREQ 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 INT1 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 INT2 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL NRESPWRON 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL NRESWARM 0 0.45 RL-0.45 RL 0 0.35xRL 0 Pin Name Load (pF) Rise Fall Time (ns) Output Mode Time (ns) GPIO0/CD1 JTAG.TDO GPIO0/CD2 JTAG.TMS GPIO2 Test1 GPIO15 Test2 GPIO16 PWM0 Test3 GPIO17 VIBRA.SYNC PWM1 Test4 PWRON 5.2 5.2 30 33.3 33.3 30 33.3 33.3 33.3 33.3 30 33.3 33.3 3 30 33.3 33.3 RL 3 30 33.3 33.3 0.65xRL RL 3 30 33.3 33.3 0.35x1.8V 0.65x1.8V VBAT 3 33.3 33.3 NSLEEP1 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 33.3 33.3 NSLEEP2 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 33.3 33.3 CLK256FS 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 12.288 16.3 16.3 VMODE1 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 33.3 33.3 BOOT0 0 RL 3 33.3 33.3 BOOT1 0 RL 3 33.3 33.3 REGEN 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 33.3 33.3 MSECURE 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 33.3 33.3 I2C.SR.SDA 0 0.4 -0.5 0.3xRL 0.7xRL RL+0.5 3.4 VMODE2 0 0.45 0 0.35xRL 0.65xRL RL 3.4 29.4 29.4 I2C.SR.SCL 0 0.4 -0.5 0.3xRL 0.7xRL RL+0.5 3.4 10.0 10.0 I2C.CNTL.SDA 0 0.4 -0.5 0.3xRL 0.7xRL RL+0.5 3.4 I2C.CNTL.SCL 0 0.4 -0.5 0.3xRL 0.7xRL RL+0.5 3.4 10.0 10.0 PCM.VCK 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 1 30 100.0 33.0 PCM.VDR 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 1 30 100.0 100.0 PCM.VDX 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 1 30 100.0 33.0 PCM.VFS 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 1 30 33.0 33.0 I2S.CLK 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 6.5 30 33.0 33.0 I2S.SYNC 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 6.5 30 33.0 33.0 I2S.DIN 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3.25 30 33.0 33.0 I2S.DOUT 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3.25 30 29.0 29.0 UART1.TXD 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 30 33.0 33.0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 33.0 33.0 RTSO/CLD64K.OUT/ BERCLK.OUT 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 30 33.0 33.0 CTSI/BERDATA.OUT 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 30 33.0 33.0 MANU 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 33.0 33.0 32KCLKOUT 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 0.032 30 16 16 HFCLKOUT 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 38.4 30 2.6 2.6 RL-0.45 RL 30 30 Up to 400 Up to 400 GPIO8 UART1.RXD Electrical Characteristics Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 29 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 3-4. Digital I/O Electrical Characteristics (continued) VOL (V) VOH (V) VIL (V) VIH (V) Min Max Min Max Min Max Min Max Max Freq (MHz) 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 60 10 1.0 1.0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 30 10 1.0 1.0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 30 10 1.0 1.0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 30 10 1.0 1.0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 30 10 1.0 1.0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 30 10 1.0 1.0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 30 10 1.0 1.0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 30 10 1.0 1.0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 30 10 1.0 1.0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 30 10 1.0 1.0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 30 10 1.0 1.0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 30 10 1.0 1.0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 30 10 1.0 1.0 Test.RESET 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 33.0 33.0 Test 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 29.0 29.0 JTAG.TDI/ BERDATA 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 33.0 33.0 JTAG.TCK/ BERDATA 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 33.0 33.0 0 0.45 RL-0.45 RL 0 0.35xRL 0.35xRL KPD.C0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL KPD.C1 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL KPD.C2 0 0.45 RL-0.45 RL 0 0.35xRL KPD.C3 0 0.45 RL-0.45 RL 0 KPD.C4 0 0.45 RL-0.45 RL KPD.C5 0 0.45 RL-0.45 KPD.C6 0 0.45 KPD.C7 0 KPD.R0 Pin Name UCLK Load (pF) Rise Fall Time (ns) Output Mode Time (ns) STP GPIO9 DIR GPIO10 NXT GPIO11 DATA0 UART4.TXD DATA1 UART4.RXD DATA2 UART4.RTSI DATA3 UART4.CTSO GPIO12 DATA4 GPIO14 DATA5 GPIO3 DATA6 GPIO4 DATA7 GPIO5 30 GPIO13 3 30 33.3 33.3 RL 0.033 30 29.0 29.0 RL 0.033 30 29.0 29.0 0.65xRL RL 0.033 30 29.0 29.0 0.35xRL 0.65xRL RL 0.033 30 29.0 29.0 0 0.35xRL 0.65xRL RL 0.033 30 29.0 29.0 RL 0 0.35xRL 0.65xRL RL 0.033 30 29.0 29.0 RL-0.45 RL 0 0.35xRL 0.65xRL RL 0.033 30 29.0 29.0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 0.033 30 29.0 29.0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 0.033 3051.8 3051.8 KPD.R1 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 0.033 3051.8 3051.8 KPD.R2 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 0.033 3051.8 3051.8 KPD.R3 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 0.033 3051.8 3051.8 KPD.R4 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 0.033 3051.8 3051.8 KPD.R5 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 0.033 3051.8 3051.8 KPD.R6 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 0.033 3051.8 3051.8 KPD.R7 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 0.033 3051.8 3051.8 GPIO16 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 30 33.3 33.3 DIG.MIC.CLK0 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 2.4 30 41.7 41.7 BT.PCM.VDX 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 1 30 100.0 100.0 GPIO17 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 3 30 33.3 33.3 DIG.MIC.CLK1 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 2.4 30 41.7 41.7 BT.PCM.VDX 0 0.45 RL-0.45 RL 0 0.35xRL 0.65xRL RL 1 30 100.0 100.0 LEDSYNC RFID.EN 30 Electrical Characteristics Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Electrical Characteristics Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 31 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 4 www.ti.com Power Module This section describes the electrical characteristics of the voltage regulators and timing characteristics of the supplies digitally controlled in the TPS65950. Figure 4-1 is a block diagram of the power provider. 32 Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Main battery VPLL1.OUT VPLLA3R.IN VPLL1 VINT.IN 1.0/1.2/1.3/1.8 V 40 mA CVPLL1.OUT VPLL2 VPLL2.OUT 0.7/1.0/1.2/1.3/1.5/1.8/1.85 VPLLA3R.IN VDAC.IN /2.5/2.6/2.8/2.85/3.0/3.15 V 100 mA CVPLL2.OUT VMMC1.OUT CVMMC1.OUT VMMC2.OUT CVMMC2.OUT VAUX1.OUT VMMC1 1.85/2.85 /3.0/3.15 V 220 mA VMMC2 1.0/1.2/1.3/1.5/1.8/1.85/ 2.5/2.6/2.8/2.85 /3.0/3.15 V 100 mA VAUX1 VMMC1.IN VDAC.IN VMMC2.IN VDAC.IN VAUX2.OUT CVAUX2.OUT VAUX3.OUT CVAUX3.OUT VAUX2 1.3/1.5/1.7/1.8/1.9/2.0/ 2.1/2.2/2.3/2.4/2.5/2.8 V 100 mA VAUX3 1.5/1.8/2.5/2.8/3.0 V 200 mA VAUX12S.IN CVAUX4.OUT CVINTDIG.OUT VINTANA.OUT VINTANA2 2.5/2.75 V 250 mA VDAC CVINTANA1.OUT VINTANA2.OUT CVINTANA2.OUT VDAC.OUT 1.2/1.3/1.8 V 70 mA 1.0/1.2/1.3/ 1.8/2.8/3.0 V 50 mA CVDAC.OUT VSIM.OUT CVSIM.OUT LVDD1 VDD1.L VDD1.IN x 3 VDD1 (DC-DC) (3) VDD1.OUT 0.6 V to 1.45 V 1200 mA (See note) VDD1.GND (3) LVDD2 VDD2.L VDD2 (DC-DC) 0.6 V to 1.5 V 600 mA VAUX4.IN (2) VDD2.OUT (2) VIO.IN x 2 VBAT.USB 3.1 V 15 mA CVUSB.3P1 VINTUSB1P8.OUT VIO (DC-DC) LVIO 1.8 V/1.85 V 700 mA VRUSB_1V8 (2) VIO.OUT CVIO.OUT VIO.GND (2) VBAT.USB 1.81 V 30 mA CVINTUSB1P8.OUT VINTUSB1P5.OUT CVINTUSB1P5.OUT VRUSB_3V1 CVDD2.OUT VDD2.GND VIO.L VUSB.3P1 CVDD1.OUT VPLLA3R.IN VDD2.IN x 2 0.7/1.0/1.2/1.3/1.5/1.8/ 1.85/2.5/2.6/2.8/ 2.85/3.0/3.15 V 100 mA VINTDIG.OUT 1.5V 50 mA VAUX12S.IN VAUX4 VAUX4.OUT VINTANA1 VSIM VAUX12S.IN 1.5/1.8/2.5/2.8/3.0 V 200 mA CVAUX1.OUT VINTDIG 1.0/1.2/1.3/1.5 V 80 mA VRUSB_1V5 VBAT.USB 1.525 V 30 mA 032-002 NOTE: For TPS65950A3: 0.6V to 1.2V, 1200mA and 1.2V to 1.45V, 1400mA Figure 4-1. Power Provider Block Diagram NOTE For the component values, see Table 15-1. Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 33 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 4.1 www.ti.com Power Providers Table 4-1 lists the power providers. Table 4-1. Summary of the Power Providers Name Use Type VAUX1 External LDO VAUX2 External LDO VAUX3 External LDO VAUX4 External LDO VMMC1 External VMMC2 External VPLL1 External Voltage Range (V) Default Voltage Depending on Boot Mode (1) Maximum Current OMAP2 Mode OMAP3 Mode 1.5, 1.8, 2.5, 2.8, 3.0 3.0 V 3.0 V 200 mA 1.3, 1.5, 1.7, 1.8, 1.9, 2.0, 2.1, 2.2, 2.3, 2.4, 2.5, 2.8 2.8 V 1.8 V 100 mA 1.5, 1.8, 2.5, 2.8, 3.0 2.8 V 2.8 V 200 mA 0.7, 1.0, 1.2, 1.3 1.5, 1.8, 1.85, 2.5, 2.6, 2.8, 2.85, 3.0, 3.15 1.2 V 2.8 V 100 mA LDO 1.85, 2.85, 3.0, 3.15 1.85 V 3.0 V 220 mA LDO 1.0, 1.2, 1.3, 1.5, 1.8, 1.85, 2.5, 2.6, 2.8, 2.85, 3.0, 3.15 2.6 V 2.6 V 100 mA LDO 1.0, 1.2, 1.3, 1.8, 2.8, 3.0 1.3 V 1.8 V 40 mA 1.3 V 1.3 V 100 mA 50 mA VPLL2 External LDO 0.7, 1.0, 1.2, 1.3, 1.5, 1.8, 1.85, 2.5, 2.6, 2.8, 2.85, 3.0, 3.15 VSIM External LDO 1.0, 1.2, 1.3, 1.8, 2.8, 3.0 1.8 V 1.8 V VDAC External LDO 1.2, 1.3, 1.8 1.8 V 1.8 V 70 mA VIO External SMPS 1.8, 1.85 1.8 V 1.8 V 700 mA VDD1 for TPS65950A2/ TPS65950A3 External SMPS 0.6 ... 1.45 1.3 V 1.2 V 1200 mA VDD1 for TPS65950A3 External SMPS 1.2 ... 1.45 1.3 V 1.2 V 1400mA VDD2 External SMPS 0.6 ... 1.5 1.3 V 1.2 V 600 mA VINTANA1 Internal LDO 1.5 1.5 V 1.5 V 50 mA VINTANA2 Internal LDO 2.5, 2.75 2.75 V 2.75 V 250 mA VINTDIG Internal LDO 1.0, 1.2, 1.3, 1.5 1.5 V 1.5 V 80 mA USBCP Internal CP 5 5V 5V 100 mA VUSB1V5 Internal LDO 1.5 1.5 V 1.5 V 30 mA VUSB1V8 Internal LDO 1.8 1.8 V 1.8 V 30 mA VUSB3V1 Internal LDO 3.1 3.1 V 3.1 V 15 mA VRRTC Internal LDO 1.5 1.5 V 1.5 V 30 mA VBRTC Internal LDO 1.3 1.3 V 1.3 V 100 A (1) 34 For the significance of boot mode, see Section 4.5, Power Management. Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 4.1.1 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 VDD1 dc-dc Regulator 4.1.1.1 VDD1 dc-dc Regulator Characteristics The VDD1 dc-dc regulator is a stepdown dc-dc converter with a configurable output voltage. The programming of the output voltage and the characteristics of the dc-dc converter are SmartReflex-compatible. The regulator can be put in sleep mode to reduce its leakage (PFM) or power-down mode when it is not being used. Table 4-3 lists the characteristics of the regulator. Table 4-2. Part Names With Corresponding VDD1 Current Support Device Name VDD1 Current Support TPS65950A2ZXN/R (some bug fixes, see errata) 1.2 A TPS65950A3ZXN/R (same as TPS65950A2 + 1 GHz support with higher current support) 1.4 A Table 4-3. VDD1 dc-dc Regulator Characteristics Parameter Comments Min Typ Input voltage range 2.7 3.6 Output voltage 0.6 Output voltage step Covering the 0.6 to 1.45-V range Output accuracy (1) 0.6 to < 0.8 V -6% 0.8 to 1.45 V -4% Output current Ground current (IQ) 82% 100 mA < IO < 400 mA 85% 400 mA < IO < 600 mA 80% 600 mA < IO < 800 mA 75% 1200 mA Active mode, Output Voltage 1.2 V to1.45 V for TPS65950A3 1400 mA Sleep mode 10 mA Off at 30C 3 A Load regulation 0 < IO < IMax Transient load regulation (3) IO = 10 mA to 600 +10 mA, Maximum slew rate is 600mA/100 ns. 30 300 mV 50 mV 10 mV 10 mV 0.25 1 ms <10 100 s 8 16 mV/s 500 700 -65 Startup time From sleep mode to on mode with constant load 4 Output shunt resistor (pulldown) A 20 300 mVPP ac input, 10-s rise and fall time Slew rate (rising or falling) (4) 50 2.2 Line regulation (4) MHz Active mode, Output Voltage 0.6 V to 1.45 V for TPS65950A2/TPS65950A3 VIN = VMax (2) (3) V mV 4% Active, unloaded, not switching (1) V 6% IO = 10 mA, sleep Short-circuit current Recovery time 4.5 1.45 3.2 Sleep, unloaded Transient line regulation Unit 12.5 Switching frequency Conversion efficiency (2), Figure 4-2 in active and sleep modes Max Accuracy includes all variations (line and load regulations, line and load transients, temperature, and process). Under current load condition step: 600 mA in 100 ns with a 20% external capacitor accuracy or 400 mA in 100 ns with a 50% external capacitor accuracy VBAT = 3.6 V, VDD1 = 1.2 V, Fs = 3.2 MHz, L = 1 H, LDCR = 100 m, C = 10 F, ESR = 10 m For negative transient load, the output voltage must discharge completely and settle to its final value within 100 ms. Transient load is specified at Vout max with a 50% external capacitor accuracy and includes temperature and process variation. Load current varies proportionally with the output voltage. The slew rate is for increasing and decreasing voltages and the maximum load current is 1.1 A. Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 35 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 4-3. VDD1 dc-dc Regulator Characteristics (continued) Parameter Comments Min Typ Max Unit 0.7 1 1.3 H 0.1 Value DCR External coil External capacitor (1) Saturation current for TPS65950A2 1.8 Saturation current for TPS65950A3 2.1 Value 8 Equivalent series resistance (ESR) at switching frequency 0 A 10 12 F 20 m See Table 2-2 for how to connect the VDD1/2 dc-dc converter when it is not used. Figure 4-2 shows the efficiency of the VDD1 dc-dc regulator in active and sleep modes. Output voltage = 1.3 V, VBAT = 3.6 V 90 80 70 Effciency (%) 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 Iload (A) 032-004 Figure 4-2. VDD1 dc-dc Regulator Efficiency 4.1.1.2 External Components and Application Schematic Figure 4-3 is an application schematic with the external components on the VDD1 dc-dc regulator. 36 Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Device VDD1.IN (D14) VDD1.IN (E14) VDD1.IN (E15) VDD1.SW (C14) LVDD1 VDD1.SW (D15) VDD1.SW (D16) CVDD1.OUT VDD1.GND (B15) VDD1.GND (C15) VDD1.GND (C16) 032-005 Figure 4-3. VDD1 dc-dc Application Schematic NOTE For the component values, see Table 15-1. Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 37 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 4.1.2 www.ti.com VDD2 dc-dc Regulator 4.1.2.1 VDD2 dc-dc Regulator Characteristics The VDD2 dc-dc regulator is a programmable output stepdown dc-dc converter with an internal field effect transistor (FET). Like the VDD1 regulator, the VDD2 regulator can be placed in sleep or power-down mode and is SmartReflex-compatible. The VDD2 regulator differs from VDD1 in its current load capability. Table 4-4 lists the characteristics of the regulator. Table 4-4. VDD2 dc-dc Regulator Characteristics Parameter Comments Input voltage range Output voltage Min Typ Max Unit 2.7 3.6 4.5 V 1 1.5 0.6 Output voltage step Covering the 0.6-V to 1.45-V range, 1.5 V is a single programmable value. 12.5 Output accuracy (1) 0.6 to < 0.8 V -6% 0.8 o 1.5 V -4% Switching frequency Conversion efficiency and sleep mode 6% 4% 3.2 (2) , Figure 4-4 in active mode Output current Ground current (IQ) IO = 10 mA, sleep 82% 100 mA < IO < 300 mA 85% 300 mA < IO < 500 mA 80% MHz Active mode 700 Sleep mode 10 Off at 30C 1 Sleep, unloaded mA A 50 Active, unloaded, not switching 300 Short-circuit current VIN = VMax Load regulation 0 < IO < IMax Transient load regulation (3) IO = 10 mA to (IMax/2) + 10 mA, Maximum slew rate is IMax/2/100 ns. 1.2 -65 Line regulation Transient line regulation V mV 300 mVPP ac input, 10-s rise and fall time A 20 mV 50 mV 10 mV 10 mV Output shunt resistor (internal pulldown) 500 700 Startup time 0.25 1 ms 25 100 s Recovery time From sleep mode to on mode with constant load Slew rate (rising or falling) (4) Value External coil (1) (2) (3) (4) (5) 38 8 16 mV/s 1 1.3 H DCR Saturation current External capacitor (5) 4 0.7 0.1 900 Value 8 ESR at switching frequency 0 mA 10 12 F 20 m Accuracy includes all variations (line and load regulations, line and load transients, temperature, and process) VBAT = 3.8 V, VDD2 = 1.3 V, Fs = 3.2 MHz, L = 1 H, LDCR = 100 m, C = 10 F, ESR = 10 m Output voltage must discharge the load current completely and settle to its final value within 100 s. Load current varies proportionally with the output voltage. The slew rate is for increasing and decreasing voltages and the maximum load current is 600 mA. Under current load condition step: Imax/2 (300 mA) in 100 ns with a 20% external capacitor accuracy or Imax/3 (200 mA) in 100 ns with a 50% external capacitor accuracy Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 See Table 2-2 for how to connect the VDD2 dc-dc converter when it is not used. Figure 4-4 shows the efficiency of the VDD2 dc-dc regulator in active and sleep modes. Output voltage = 1.3 V, VBAT = 3.6 V 90 80 70 Effciency (%) 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 Iload (A) 032-006 Figure 4-4. VDD2 dc-dc Regulator Efficiency 4.1.2.2 External Components and Application Schematic Figure 4-5 is an application schematic with the external components of the VDD2 dc-dc regulator. Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 39 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Device VDD2.IN (D13) VDD2.IN (P14) LVDD2 VDD2.SW (T13) VDD2.SW (R14) CVDD2.OUT VDD2.GND (T14) VDD2.GND (R15) 032-007 Figure 4-5. VDD2 dc-dc Application Schematic NOTE For the component values, see Table 15-1. 40 Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 4.1.3 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 VIO dc-dc Regulator 4.1.3.1 VIO dc-dc Regulator Characteristics The I/Os and memory dc-dc regulator is a 600-mA stepdown dc-dc converter (internal FET) with two output voltage settings. It supplies the memories and all I/O ports in the application and is one of the first power providers to switch on in the power-up sequence. This dc-dc regulator can be placed in sleep or power-down mode; however, care must be taken in the sequencing of this power provider, because numerous electrostatic discharge (ESD) blocks are connected to this supply. Table 4-5 lists the characteristics of the regulator. Table 4-5. VIO dc-dc Regulator Characteristics Parameter Comments Input voltage range Min Typ Max Unit 2.7 3.6 4.5 V 1.8 1.85 Output voltage (1) Output accuracy (2) -4% 4% -3% 3% Switching frequency Conversion efficiency and sleep modes V 3.2 (3) Figure 4-6 in active mode Output current Ground current (IQ) IO = 10 mA, sleep 85% 100 mA < IO < 400 mA 85% 400 mA < IO < 600 mA 80% MHz On mode 700 Sleep mode Off at 30C 1 Sleep, unloaded 50 Active, unloaded, not switching 300 mVPP ac, input rise and fall time 10 s Start-up time Recovery time From sleep mode to on mode with constant load Output shunt resistor (internal pulldown) Value External coil External capacitor (1) (2) (3) (4) 0.7 50 mV 10 mV 0.25 1 ms <10 100 s 500 700 1 1.3 H DCR Saturation current A 300 Load transient (4) Line transient mA 10 0.1 900 Value 8 ESR at switching frequency 1 mA 10 12 F 20 m This voltage is tuned according to the platform and transient requirements. 4% accuracy includes all variations (line and load regulation, line and load transient, temperature, process). 3% accuracy is dc accuracy only. VBAT = 3.8 V, VIO = 1.8 V, Fs = 3.2 MHz, L = 1 H, LDCR = 100 m, C = 10 F, ESR = 10 m Load transient can also be specified as 0 < IO < IOUTmax/2, t = 1 s, 100 mV but this is not included in 4% accuracy. Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 41 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Figure 4-6 shows the efficiency of the VIO dc-dc regulator in active and sleep modes. Output voltage = 1.2 V, VBAT = 3.8 V 100 90 80 70 Effciency (%) 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 Iload (A) 032-008 Figure 4-6. VIO dc-dc Regulator Efficiency in Active Mode 4.1.3.2 External Components and Application Schematic Figure 4-7 is an application schematic with the external components of the VIO dc-dc regulator. 42 Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Device VIO.IN (R4) VIO.IN (P3) VIO.SW (R3) LVIO VIO.SW (T4) CVIO.OUT VIO.GND (R2) VIO.GND (T3) 032-009 Figure 4-7. VIO dc-dc Application Schematic NOTE For the component values, see Table 15-1. Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 43 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 4.1.4 www.ti.com VDAC LDO Regulator The VDAC programmable LDO regulator is a high power-supply ripple rejection (PSRR), low-noise, linear regulator that powers the host processor dual-video DAC. It is controllable with registers through I2C and can be powered down. Table 4-6 lists the characteristics of the regulator. Table 4-6. VDAC LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VDAC.OUT to analog ground Filtering capacitor ESR 20 2.7 F 600 m Electrical Characteristics VIN Input voltage VOUT Output voltage IOUT Rated output current On mode 2.7 3.6 4.5 V 1.164 1.2 1.236 V 1.261 1.3 1.339 1.746 1.8 1.854 On mode 70 Low-power mode mA 5 dc load regulation On mode: 0 < IO < IMax dc line regulation On mode, VIN = VINmin to VINmax at IOUT = IOUTmax Turn-on time IOUT = 0, CL = 1 F (within 10% of VOUT) Wake-up time Full load capability Ripple rejection f < 20 kHz 65 20 kHz < f < 100 kHz 45 f = 1 MHz 40 20 mV 3 mV 100 s 10 s dB VIN = VOUT + 1 V, IO = IMax Output noise 100 Hz < f < 5 kHz 400 nV/Hz 5 kHz < f < 400 kHz 125 400 kHz < f < 10 MHz Ground current 50 On mode, IOUT = 0 150 On mode, IOUT = IOUTmax 350 Low-power mode, IOUT = 0 15 Low-power mode, IOUT = 1 mA 25 Off mode at 55C VDO 44 Dropout voltage On mode, IOUT = IOUTmax Transient load regulation ILoad: IMin - IMax Slew: 60 mA/s Transient line regulation VIN drops 500 mV Slew: 40 mV/s Power Module A 1 -40 250 mV 40 mV 10 mV Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 4.1.5 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 VPLL1 LDO Regulator The VPLL1 programmable LDO regulator is high-PSRR, low-noise, linear regulator used for the host processor phase-locked loop (PLL) supply. Table 4-7 lists the characteristics of the regulator. Table 4-7. VPLL1 LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VPLL1.OUT to analog ground Filtering capacitor ESR 20 2.7 F 600 m Electrical Characteristics VIN Input voltage VOUT Output voltage IOUT Rated output current On mode and low-power mode 2.7 3.6 4.5 V 0.97 1.0 1.03 V 1.164 1.2 1.236 1.261 1.3 1.339 1.746 1.8 1.854 2.716 2.8 2.884 2.91 3.0 3.090 On mode 40 Low-power mode mA 5 dc load regulation On mode: 0 < IO < IMax dc line regulation On mode, VIN = VINmin to VINmax at IOUT = IOUTmax Turn-on time IOUT = 0, CL = 1 F (within 10% of VOUT) Wake-up time Full load capability Ripple rejection f < 10 kHz 50 10 kHz < f < 100 kHz 40 f = 1 MHz 30 20 mV 3 mV 100 s 10 s dB VIN = VOUT + 1 V, IO = IMax Ground current On mode, IOUT = 0 70 On mode, IOUT = IOUTmax Low-power mode, IOUT = 0 15 Low-power mode, IOUT = 1 mA 16 Off mode at 55C VDO Dropout voltage On mode, IOUT = IOUTmax Transient load regulation ILoad: IMin - IMax Slew: 60 mA/s Transient line regulation VIN drops 500 mV Slew: 40 mV/s 1 -40 250 mV 40 mV 10 mV Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 A 110 45 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 4.1.6 www.ti.com VPLL2 LDO Regulator The VPLL2 programmable LDO regulator is a high-PSRR, low-noise, linear regulator used for the host processor PLL supply. Table 4-8 lists the characteristics of the regulator. Table 4-8. VPLL2 LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VPLL2.OUT to analog ground Filtering capacitor ESR 20 2.7 F 600 m Electrical Characteristics VIN Input voltage 2.7 3.6 4.5 V 0.672 0.97 1.164 1.261 1.455 1.746 1.795 2.425 2.522 2.716 2.765 2.91 3.05 0.7 1.0 1.2 1.3 1.5 1.8 1.85 2.5 2.6 2.8 2.85 3.0 3.15 0.728 1.03 1.236 1.339 1.545 1.854 1.906 2.575 2.678 2.884 2.936 3.09 3.245 V VOUT Output voltage On mode and low-power mode IOUT Rated output current On mode Low-power mode dc load regulation On mode: 0 < IO < IMax dc line regulation On mode, VIN = VINmin to VINmax at IOUT = IOUTmax Turn-on time IOUT = 0, CL = 1 F (within 10% of VOUT) Wake-up time Full load capability Ripple rejection f < 10 kHz 10 kHz < f < 100 kHz f = 1 MHz VIN = VOUT + 1 V, IO = IMax Ground current On mode, IOUT = 0 On mode, IOUT = IOUTmax Low-power mode, IOUT = 0 Low-power mode, IOUT = 1 mA Off mode at 55C 70 160 17 20 1 A Dropout voltage On mode, IOUT = IOUTmax 250 mV Transient load regulation ILoad: IMin - IMax Slew: 40 mA/s 40 mV Transient line regulation VIN drops 500 mV Slew: 40 mV/s 10 mV VDO 46 Power Module 100 5 mA 20 mV 3 mV 100 s 10 s 50 40 30 -40 dB Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 4.1.7 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 VMMC1 LDO Regulator The VMMC1 LDO regulator is a programmable linear voltage converter that powers the multimedia channel (MMC) slot. It includes a discharge resistor and overcurrent (short -ircuit) protection. This LDO regulator can also be turned off automatically when MMC card extraction is detected. The VMMC1 LDO can be powered through an independent supply other than the battery; for example, a charge pump (CP). In this case, the input from the VMMC1 LDO can be higher than the battery voltage. Table 4-9 lists the characteristics of the regulator. Table 4-9. VMMC1 LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VMMC1.OUT to analog ground Filtering capacitor ESR 2.7 F 600 m 5.5 V 1.85 1.9055 2.85 2.9355 3.0 3.09 3.15 3.2445 V 20 Electrical Characteristics VIN Input voltage 2.7 1.7945 2.7645 2.91 3.0555 3.6 VOUT Output voltage On mode and low-power mode IOUT Rated output current On mode Low-power mode dc load regulation On mode: 0 < IO < IMax dc line regulation On mode, VIN = VINmin to VINmax at IOUT = IOUTmax Turn-on time IOUT = 0, CL = 1 F (within 10% of VOUT) Wake-up time Full load capability Ripple rejection f < 10 kHz 10 kHz < f < 100 kHz f = 1 MHz VIN = VOUT + 1 V, IO = IMax Ground current On mode, IOUT = 0 On mode, IOUT = IOUTmax Low-power mode, IOUT = 0 Low-power mode, IOUT = 5 mA Off mode at 55C 70 290 17 20 1 A Dropout voltage On mode, IOUT = IOUTmax 250 mV Transient load regulation ILoad: IMin - IMax Slew: 40 mA/s 40 mV Transient line regulation VIN drops 500 mV Slew: 40 mV/s 10 mV VDO 220 5 mA 20 mV 3 mV 100 s 10 s 50 40 25 -40 dB Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 47 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 4.1.8 www.ti.com VMMC2 LDO Regulator The VMMC2 LDO regulator is a programmable linear voltage converter that powers MMC slot 2. It includes a discharge resistor and overcurrent (short-circuit) protection. The VMMC2 LDO can be powered through an independent supply other than the battery (for example, a CP). In this case, the input from the VMMC2 LDO can be higher than the battery voltage. Table 4-10 lists the characteristics of the regulator. Table 4-10. VMMC2 LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VMMC2.OUT to analog ground Filtering capacitor ESR 20 2.7 F 600 m Electrical Characteristics VIN Input voltage 2.7 3.6 5.5 V 0.7 1.164 1.261 1.455 1.746 1.795 2.425 2.522 2.716 2.765 2.91 3.056 1.0 1.2 1.3 1.5 1.8 1.85 2.5 2.6 2.8 2.85 3.0 3.15 1.03 1.236 1.339 1.545 1.854 1.906 2.575 2.678 2.884 2.936 3.09 3.245 V VOUT Output voltage On mode and low-power mode IOUT Rated output current On mode Low-power mode dc load regulation On mode: 0 < IO < IMax dc line regulation On mode, VIN = VINmin to VINmax at IOUT = IOUTmax Turn-on time IOUT = 0, CL = 1 F (within 10% of VOUT) Wake-up time Full load capability Ripple rejection f < 10 kHz 10 kHz < f < 100 kHz f = 1 MHz VIN = VOUT + 1 V, IO = IMax Ground current On mode, IOUT = 0 On mode, IOUT = IOUTmax Low-power mode, IOUT = 0 Low-power mode, IOUT = 50 A Off mode at 55C 70 170 17 20 1 A Dropout voltage On mode, IOUT = IOUTmax 250 mV Transient load regulation ILoad: IMin - IMax Slew: 40 mA/s 40 mV Transient line regulation VIN drops 500 mV Slew: 40 mV/s 10 mV VDO 48 Power Module 100 5 mA 20 mV 3 mV 100 s 10 s 50 40 30 -40 dB Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 4.1.9 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 VSIM LDO Regulator The VSIM voltage regulator is a programmable, low-dropout, linear voltage regulator that supplies the subscriber identity module (SIM)-card and the SIM-card driver. This LDO regulator can be turned off automatically when SIM card extraction is detected. Table 4-11 lists the characteristics of the regulator. Table 4-11. VSIM LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VSIM.OUT to analog ground Filtering capacitor ESR 20 2.7 F 600 m Electrical Characteristics VIN Input voltage 2.7 3.6 4.5 V 0.97 1.164 1.261 1.746 2.716 2.91 1.0 1.2 1.3 1.8 2.8 3.0 1.03 1.236 1.339 1.854 2.884 3.09 V VOUT Output voltage On mode and low-power mode IOUT Rated output current On mode Low-power mode 50 1 mA dc load regulation On mode: 0 < IO < IMax 20 mV dc line regulation On mode, VIN = VINmin to VINmax at IOUT = IOUTmax Turn-on time IOUT = 0, CL = 1 F (within 10% of VOUT) Wake-up time Full load capability Ripple rejection f < 10 kHz 10 kHz < f < 100 kHz f = 1 MHz VIN = VOUT + 1 V, IO = IMax Ground current On mode, IOUT = 0 On mode, IOUT = IOUTmax Low-power mode, IOUT = 0 Low-power mode, IOUT = 1 mA Off mode at 55C 70 120 15 16 1 A Dropout voltage On mode, IOUT = IOUTmax 250 mV Transient load regulation ILoad: IMin - IMax Slew: 40 mA/s 40 mV Transient line regulation VIN drops 500 mV Slew: 40 mV/s 10 mV VDO 3 mV 100 s 10 s 50 40 30 -40 dB Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 49 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com 4.1.10 VAUX1 LDO Regulator The VAUX1 GP LDO regulator powers the auxiliary devices. The VAUX1 regulator can also support an inductive load such as a vibrator. While operating in vibrator mode, the VAUX1 LDO has the following features: * Programmable, register-controlled, soft-start function * Enabled through the VIBRA.SYNC pin * Programmable, register-controlled, duty cycle (PWM generator) based on a nominal 4-Hz cycle derived from an internal 32-kHz clock Table 4-12 lists the characteristics of the regulator. Table 4-12. VAUX1 LDO Regulator Characteristics Parameter Test Conditions Min Typ Max Unit 0.3 1 2.7 F 20 600 m 70 700 H 15 50 Output Load Conditions Filtering capacitor Connected from VAUX1.OUT to analog ground Filtering capacitor ESR Vibrator inductive load (1) Connected from VAUX1.OUT to analog ground Vibrator load resistance (1) Electrical Characteristics VIN Input voltage VOUT Output voltage On mode and low-power mode IOUT Rated output current On mode Low-power mode dc load regulation On mode: IOUT = IOUTmax to 0 dc line regulation On mode, VIN = VINmin to VINmax at IOUT = IOUTmax Turn-on time IOUT = 0, CL = 1 F (within 10% of VOUT) Soft-start function for inductive load 2.7 3.6 4.5 V 1.455 1.746 2.425 2.716 2.91 1.5 1.8 2.5 2.8 3.0 1.545 1.854 2.575 2.884 3.09 V Turn-off time VDO (1) 50 200 5 mA 20 mV 3 mV 100 500 s 5000 s 10 s Wake-up time Full load capability Ripple rejection f < 10 kHz 10 kHz < f < 100 kHz f = 1 MHz VIN = VOUT + 1 V, IO = IMax Ground current On mode, IOUT = 0 On mode, IOUT = IOUTmax Low-power mode, IOUT = 0 Low-power mode, IOUT = 5 mA Off mode at 55C 70 270 15 20 1 A Dropout voltage On mode, IOUT = IOUTmax 250 mV Transient load regulation ILoad: IMin - IMax Slew: 40 mA/s 40 mV Transient line regulation VIN drops 500 mV Slew: 40 mV/s 10 mV 50 40 25 -40 dB Parameter not tested, used for design specification only Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 4.1.11 VAUX2 LDO Regulator The VAUX2 GP LDO regulator powers the auxiliary devices. Table 4-13 lists the characteristics of the regulator. Table 4-13. VAUX2 LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VAUX2.OUT to analog ground Filtering capacitor ESR 20 2.7 F 600 m Electrical Characteristics VIN Input voltage 2.7 3.6 4.5 V -3% 1.3 1.5 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.8 3% V 100 5 mA 20 mV 3 mV 100 s 10 s VOUT Output voltage On mode and low-power mode IOUT Rated output current On mode Low-power mode dc load regulation On mode: IOUT = IOUTmax to 0 dc line regulation On mode, VIN = VINmin to VINmax at IOUT = IOUTmax Turn-on time IOUT = 0, CL = 1 F (within 10% of VOUT) Wake-up time Full load capability Ripple rejection f < 10 kHz 10 kHz < f < 100 kHz f = 1 MHz VIN = VOUT + 1 V, IO = IMax Ground current On mode, IOUT = 0 On mode, IOUT = IOUTmax Low-power mode, IOUT = 0 Low-power mode, IOUT = 5 mA Off mode at 55C 70 170 17 20 1 A Dropout voltage On mode, IOUT = IOUTmax 250 mV Transient load regulation ILoad: IMin - IMax Slew: 40 mA/s 40 mV Transient line regulation VIN drops 500 mV Slew: 40 mV/s 10 mV VDO 50 40 25 -40 dB Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 51 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com 4.1.12 VAUX3 LDO Regulator The VAUX3 GP LDO regulator powers the auxiliary devices. Table 4-14 lists the characteristics of the regulator. Table 4-14. VAUX3 LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VAUX3.OUT to analog ground Filtering capacitor ESR 20 2.7 F 600 m Electrical Characteristics VIN Input voltage 2.7 3.6 4.5 V 1.455 1.746 2.425 2.716 2.91 1.5 1.8 2.5 2.8 3.0 1.545 1.854 2.575 2.884 3.09 V VOUT Output voltage On mode and low-power mode IOUT Rated output current On mode Low-power mode dc load regulation On mode: IOUT = IOUTmax to 0 dc line regulation On mode, VIN = VINmin to VINmax at IOUT = IOUTmax Turn-on time IOUT = 0, CL = 1 F (within 10% of VOUT) Wake-up time Full load capability Ripple rejection f < 10 kHz 10 kHz < f < 100 kHz f = 1 MHz VIN = VOUT + 1 V, IO = IMax Ground current On mode, IOUT = 0 On mode, IOUT = IOUTmax Low-power mode, IOUT = 0 Low-power mode, IOUT = 5 mA Off mode at 55C 70 270 15 20 1 A Dropout voltage On mode, IOUT = IOUTmax 250 mV Transient load regulation ILoad: IMin - IMax Slew: 40 mA/s 40 mV Transient line regulation VIN drops 500 mV Slew: 40 mV/s 10 mV VDO 52 Power Module 200 5 mA 20 mV 3 mV 100 s 10 s 50 40 25 -40 dB Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 4.1.13 VAUX4 LDO Regulator The VAUX4 GP LDO regulator powers the auxiliary devices. The VAUX4 regulator has an independent supply input pin and can be preregulated by an external voltage. Table 4-15 lists the characteristics of the regulator. Table 4-15. VAUX4 LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VAUX4.OUT to analog ground Filtering capacitor ESR 20 2.7 F 600 m Electrical Characteristics VIN Input voltage 2.7 3.6 4.5 V 0.672 0.97 1.164 1.261 1.455 1.746 1.795 2.425 2.522 2.716 2.765 2.91 3.056 0.7 1.0 1.2 1.3 1.5 1.8 1.85 2.5 2.6 2.8 2.85 3.0 3.15 0.728 1.03 1.236 1.339 1.545 1.854 1.906 2.575 2.678 2.884 2.936 3.09 3.245 V VOUT Output voltage On mode and low-power mode IOUT Rated output current On mode Low-power mode dc load regulation On mode: IOUT = IOUTmax to 0 dc line regulation On mode, VIN = VINmin to VINmax at IOUT = IOUTmax Turn-on time IOUT = 0, CL = 1 F (within 10% of VOUT) Wake-up time Full load capability Ripple rejection f < 10 kHz 10 kHz < f < 100 kHz f = 1 MHz VIN = VOUT + 1 V, IO = IMax Ground current On mode, IOUT = 0 On mode, IOUT = IOUTmax Low-power mode, IOUT = 0 Low-power mode, IOUT = 5 mA Off mode at 55C 70 170 17 20 1 A Dropout voltage On mode, IOUT = IOUTmax 250 mV Transient load regulation ILoad: IMin - IMax Slew: 40 mA/s 40 mV Transient line regulation VIN drops 500 mV Slew: 40 mV/s 10 mV VDO 100 5 mA 20 mV 3 mV 100 s 10 s 50 40 30 -40 dB Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 53 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com 4.1.14 Internal LDOs Table 4-16 lists the regulators that power the device, and the output loads associated with them. Table 4-16. Output Load Conditions Regulator VINTDIG LDO Parameter Test Conditions Filtering capacitor Connected from VINTDIG.OUT to analog ground Filtering capacitor ESR VINTANA1 LDO Filtering capacitor Connected from VINTANA1.OUT to analog ground Filtering capacitor F 600 m 2.7 F 600 m 2.7 F 0.3 1 0.3 600 m Connected from VUSB.3P1 to GND 0.3 1 1 2.7 F 0 10 600 m Connected from VINTUSB1P8.OUT to GND 0.3 1 2.7 F 0 10 600 m 20 Filtering capacitor ESR VRUSB_1V5 LDO Filtering capacitor Unit 2.7 Connected from VINTANA2.OUT to analog ground Filtering capacitor ESR VRUSB_1V8 LDO Filtering capacitor Max 1 20 Filtering capacitor ESR VRUSB_3V1 LDO Filtering capacitor Typ 0.3 20 Filtering capacitor ESR VINTANA2 LDO Min Connected from VINTUSB1P5 to GND Filtering capacitor ESR 0.3 1 2.7 F 0 10 600 m 4.1.15 CP The CP generates a 4.8-V (nominal) power supply voltage from the battery to the VBUS pin. The input voltage range is 2.7 to 4.5 V for the battery voltage. The CP operating frequency is 1 MHz. The CP tolerates 7 V on VBUS when it is in power-down mode. The CP integrates a short-circuit current limitation at 450 mA. Table 4-17 lists the characteristics of the CP. Table 4-17. CP Characteristics Parameter Test Conditions Min Typ Max Unit F Output Load Conditions Filtering capacitor Connected from VBUS to VSSP 1.41 4.7 6.5 Flying capacitor Connected from CP to CN 1.32 2.2 3.08 F 20 m Filtering capacitor ESR Electrical Characteristics VIN Input voltage VO Output voltage Iload Rated output current On mode: VIN = VBAT 2.7 3.6 4.5 V 4.6 4.8 5.25 V VBAT > 3 V at VBUS 0 100 2.7 V < VBAT < 3 V, at VBUS 0 50 Efficiency ILoad = 100 mA, VBAT = 3.6 V Setting time ILOADmax/2 to ILOAmax in 5 s 55% 100 Startup time Short-circuit limitation current 250 400 s 3 ms 350 450 mA dc load regulation ILOADmin to ILOADmax 250 500 mV dc line regulation 3.0 V to VBATmax ILoad = 100 mA 250 350 mV IVBUS_5Vmax/2 - IVBUS_5Vmax 50 s, C = 2*4.7 F 300 350 Transient load regulation 0 - IVBUS_5Vmax/2, 50 s, C = 2*4.7 F Transient line regulation 54 mA VBATmin to VBATmax in 50 s, C = 2*4.7 F Power Module mV 350 300 350 mV Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 4.1.16 USB LDO Short-Circuit Protection Scheme The short-circuit current for the LDOs and dc-dc converters in TPS65950 is approximately twice the maximum load current. In certain cases when the output of the block is shorted to ground, the power dissipation can exceed the 1.2-W requirement if no action is taken. A short-circuit protection scheme is included in the TPS65950 to ensure that if the output of an LDO or dc-dc is short-circuited, the power dissipation does not exceed the 1.2-W level. The three USB LDOs, VRUSB3V1, VRUSB1V8, and VRUSB1V5, are included in this short-circuit protection scheme, which monitors the LDO output voltage at a frequency of 1 Hz and generates an interrupt (sc_it) when a short circuit is detected. The scheme compares the LDO output voltage to a reference voltage and detects a short circuit if the LDO voltage drops below this reference value (0.5 or 0.75 V programmable). In the case of the VRUSB3V1 and VRUSB1V8 LDOs, the reference is compared with a divided-down voltage (1.5 V typical). If a short circuit is detected on VRUSB3V1, the power subchip FSM switches this LDO to sleep mode. If a short circuit is detected on VRUSB1V8 or VRUSB1V5, the power subchip FSM switches off the relevant LDO. 4.2 Power References The bandgap voltage reference is filtered (resistance/capacitance [RC] filter) using an external capacitor connected across the VREF output and an analog ground (REFGND). The VREF voltage is scaled, distributed, and buffered in the device. The bandgap is started in fast mode (not filtered), and is set automatically by the D machine in slow mode (filtered, less noisy) when required. Table 4-18 lists the characteristics of the voltage references. Table 4-18. Voltage Reference Characteristics Parameter Test Conditions Min Typ Max Unit Connected from VREF to REFGND 0.3 1 2.7 F Input voltage On mode 2.7 3.6 4.5 V Internal bandgap reference voltage On mode, measured through TESTV terminal 1.272 1.285 1.298 V Reference voltage (VREF terminal) On mode 0.725 0.75 0.7575 V Retention mode reference On mode 0.492 0.5 0.508 V 0.9 1 1.1 A 25 20 15 10 10 A 1 V/Hz Output Load Condition Filtering capacitor Electrical Characteristics VIN IREF NMOS sink Ground current Bandgap IREF block Preregulator VREF buffer Retention reference buffer Output spot noise 100 Hz A-weighted noise (rms) 200 nV (ms) P-weighted noise (rms) 150 nV (ms) Integrated noise 20 Hz to 100 kHz 2.2 IBIAS trim bit LSB Ripple rejection < 1 MHz from VBAT Start-up time V 0.1 A 1 ms 60 dB Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 55 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 4.3 www.ti.com Power Control 4.3.1 Backup Battery Charger If the backup battery is rechargeable, it can be recharged from the main battery. A programmable voltage regulator powered by the main battery allows recharging of the backup battery. The backup battery charge must be enabled using a control bit register. Recharging starts when two conditions are met: * Main battery voltage > backup battery voltage * Main battery > 3.2 V The comparators of the backup battery system (BBS) give the two thresholds of the backup battery charge startup. The programmed voltage for the charger gives the end-of-charge threshold. The programmed current for the charger gives the charge current. Overcharging is prevented by measurement of the backup battery voltage through the GP ADC. Table 4-19 lists the characteristics of the backup battery charger. Table 4-19. Backup Battery Charger Characteristics Parameter Test Conditions Min Typ Max VBACKUP-to-MADC input attenuation VBACKUP from 1.8 to 3.3 V Backup battery charging current VBACKUP = 2.8 V, BBCHEN = 1, BBISEL = 00 10 25 45 A VBACKUP = 2.8 V, BBCHEN = 1, BBISEL = 01 105 150 270 A VBACKUP = 2.8 V, BBCHEN = 1, BBISEL = 10 350 500 900 A VBACKUP = 2.8 V, BBCHEN = 1, BBISEL = 11 0.7 1 1.8 mA VBACKUP = 0 V, BBCHEN = 1, BBISEL = 00 17.5 25 45 A VBACKUP = 0 V, BBCHEN = 1, BBISEL = 01 105 150 270 A VBACKUP = 0 V, BBCHEN = 1, BBISEL = 10 350 500 900 A VBACKUP = 0 V, BBCHEN = 1, BBISEL = 11 0.7 1 1.8 mA IVBACKUP = -10 A, BBSEL = 00 2.4 2.5 2.6 V IVBACKUP = -10 A, BBSEL = 01 2.9 3.0 3.1 V IVBACKUP = -10 A, BBSEL = 10 3.0 3.1 3.2 V IVBACKUP = -10 A, BBSEL = 11 3.1 3.2 3.3 V Min Typ Max Unit 3.1 3.2 3.3 V 2.55 2.7 2.85 V 2.5 2.5 2.65 2.85 2.95 2.95 V 1.6 1.95 1.8 2.1 2.0 2.25 V End backup battery charging voltage: VBBCHGEND 4.3.2 0.33 Unit V/V Battery Monitoring and Threshold Detection 4.3.2.1 Power On/Power Off and Backup Conditions Table 4-20 lists the threshold levels of the battery. Table 4-20. Battery Threshold Levels Parameter Test Conditions Main battery charged threshold VMBCH Measured on VBAT terminal Main battery low threshold VMBLO VBACKUP = 3.2 V, measured on VBAT terminal (monitored on terminal ONNOFF) Main battery high threshold VMBHI Measured on terminal VBAT, VBACKUP = 0 V Measured on terminal VBAT, VBACKUP = 3.2 V Batteries not present threshold VBNPR Measured on terminal VBACKUP with VBAT < 2.1 V Measured on terminal VBAT with VBACKUP = 0 V (monitored on terminal VRRTC) 56 Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 4.3.3 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 VRRTC LDO Regulator The VRRTC voltage regulator is a programmable, low dropout, linear voltage regulator supplying (1.5 V) the embedded real-time clock (32.768-kHz oscillator) and dedicated I/Os of the digital host counterpart. The VRRTC regulator is also the supply voltage of the power-management digital state-machine. The VRRTC regulator is supplied from the UPR line, switched on by the main or backup battery, depending on the system state. The VRRTC output is present as long as a valid energy source is present. The VRRTC line is supplied by an LDO when VBAT > 2.7, and a clamp circuit when in backup mode. Table 4-21 describes the regulator characteristics. Table 4-21. VRRTC LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VRTC.OUT to analog ground Filtering capacitor ESR 20 2.7 F 600 m Electrical Characteristics VIN Input voltage On mode 2.7 VBAT 4.5 V VOUT Output voltage On mode 1.45 1.5 1.55 V IOUT Rated output current On mode 30 Sleep mode mA 1 DC load regulation On mode: IOUT = IOUTmax to 0 DC line regulation On mode, VIN = VINmin to VINmax at IOUT = IOUTmax Turn-on time IOUT = 0, at VOUT = VOUTfinal 3% 100 s Wake-up time On mode from low power to On mode, IOUT = 0, at VOUT = VOUTfinal 3% 100 s From backup to On mode, IOUT = 0, at VOUT = VOUTfinal 3% 100 Ripple rejection (VRRTC) f < 10 kHz 50 10 kHz < f < 100 kHz 40 f = 1 MHz 30 100 mV 100 mV dB VIN = VOUT + 1 V, IO = IMAX Ground current On mode, IOUT = 0 70 On mode, IOUT = IOUTmax 100 Sleep mode, IOUT = 0 10 Sleep mode, IOUT = 1 mA 11 Off mode VDO (1) Dropout voltage (1) On mode, IOUT = IOUTmax Transient load regulation ILOAD: IMIN - IMAX Slew: 40 mA/s Transient line regulation VIN drops 500 mV Slew: 40 mV/s Overshoot Softstart Pull down resistance Default in off mode A 1 -40 250 mV 40 mV 10 mV 3% 250 320 450 For nominal output voltage Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 57 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 4.4 www.ti.com Power Consumption Table 4-22 describes the power consumption, depending on the use cases. NOTE Typical power consumption is obtained in nominal operating conditions with the TPS65950 in stand-alone mode. Table 4-22. Power Consumption Mode Description Typical Consumption Backup Only the RTC date is maintained with a couple of registers in the backup domain. No main source is connected. Consumption is on the backup battery. VBAT not present 2.25 * 3.2 = 7.2 W Wait-on The phone is apparently off for the user, a main battery is present and well-charged. The RTC registers (registers in the backup domain) are maintained. Wake-up capabilities (like the PWRON button) are available. VBAT = 3.8 V 64 * 3.8 = 243.2 W Active No Load The subsystem is powered by the main battery, all supplies are enabled with full current capability, internal reset is released, and the associated processor is running. VBAT = 3.8 V 3291 * 3.8 = 12505 W Sleep No Load The main battery powers the subsystem, selected supplies are enabled but in low-consumption mode, and the associated processor is in low-power mode. VBAT = 3.8 V 496 * 3.8 = 1884.4 W Table 4-23 lists the regulator states for each mode. Table 4-23. Regulator States Depending on Use Cases Regulator 58 Mode Backup Wait-On Sleep No Load Active No Load VAUX1 OFF VAUX2 OFF OFF OFF OFF OFF SLEEP VAUX3 ON OFF OFF OFF OFF VAUX4 OFF OFF SLEEP ON VMMC1 OFF OFF OFF OFF VMMC2 OFF OFF SLEEP ON VPLL1 OFF OFF SLEEP ON VPLL2 OFF OFF SLEEP ON VSIM OFF OFF OFF OFF VDAC OFF OFF OFF OFF VINTANA1 OFF OFF SLEEP ON VINTANA2 OFF OFF SLEEP ON VINTDIG OFF OFF SLEEP ON VIO OFF OFF SLEEP ON VDD1 OFF OFF SLEEP ON VDD2 OFF OFF SLEEP ON VUSB_1V5 OFF OFF OFF OFF VUSB_1V8 OFF OFF OFF OFF VUSB_3V1 OFF OFF SLEEP SLEEP Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 4.5 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Power Management 4.5.1 Boot Modes The modes corresponding to the BOOT0-BOOT1 combination value are listed in Table 4-24. Table 4-24. BOOT Mode Description 4.5.2 Name Description BOOT0 BOOT1 Reserved 0 0 MC027 Master_C027_Generic 01 0 1 MC021 Master_C021_Generic 10 1 0 SC021 Slave_C021_Generic 11 1 1 Process Modes The process modes parameter defines: * The boot voltage for the host core * The boot sequence associated with the process * The dynamic voltage and frequency scaling (DVFS) protocol associated with the process 4.5.2.1 C027.0 Mode Table 4-25 lists the parameters for C027.0 mode. Table 4-25. C027.0 Mode Description Boot core voltage 1.3 V Power sequence VIO followed by VDD1 and VPLL DVFS protocol 4.5.2.2 VMODE1/2 C021.M Mode Table 4-26 lists the parameters for C021.M mode. Table 4-26. C021.M Mode Description Boot core voltage 1.2 V Power sequence VIO followed by VPLL1, VDD2, VDD1 SmartReflex IF (I2C high speed) DVFS protocol 4.5.3 Power-On Sequence 4.5.3.1 Timings Before Sequence_Start The starting time of the power-on sequence relative to external events is shown in Figure 4-8. Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 59 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Vbkup User_Action Starting_Event is main battery insertion Vbat 61 ms - 2 cycle32k Sequence_Start Starting_Event is charger insertion VAC 61 ms - 2 cycle32k Sequence_Start Starting_Event is VBUS insertion Vbus 61 ms - 2 cycle32k Sequence_Start Starting_Event is PWRON button PWRON Pushbutton debouncing - 30 ms Sequence_Start Starting_Event is PWRON rising when device is in slave mode PWRON 0 ms Sequence_Start 032-010 Figure 4-8. Timings Before Sequence Start 4.5.3.2 OMAP2 Power-On Sequence Figure 4-9 shows the timing and control that must occur in Master_C027_Generic mode. Sequence_Start occurs according to the events shown in Figure 4-8. 60 Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Sequence_Start 4638 ms battery detection REGEN 1068 ms - 3 MHz oscillator setting + clock switch VIO 1.8 V 1072 ms for VIO stabilization VDD1 1.3 V 1007 ms for VDD1 stabilization VDD2 1.3 V 1052 ms for VDD2 stabilization VPLL1 1.3 V 122 ms for LDO stabilization 32KCLKOUT 610 ms SYSEN 2034 ms for DcDc I/O stabilization CLKEN 3418 ms 5.2 ms HFCLKOUT 61 ms NRESPWRON 032-011 Figure 4-9. Timings--OMAP2 Power-On Sequence 4.5.3.3 OMAP3 Power-On Sequence Figure 4-10 shows the timing and control that must occur in Master_C021_Generic mode. Sequence_Start occurs according to the events shown in Figure 4-8. Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 61 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Sequence_Start 4608 ms battery detection REGEN 1068 ms - 3 MHz oscillator setting + clock switch VIO 1.8 V 1179 ms for VIO stabilization VPLL1 1.8 V 1022 ms for LDO stabilization and start DcDc ramping VDD2 1.2 V 1099 ms for VDD2 stabilization and VDD1 start ramping VDD1 1.2 V 1175 ms for VDD1 stabilization 32KCLKOUT 61 ms SYSEN 1179 ms for VIO stabilization CLKEN 1953 ms ~ 5.3 ms HFCLKOUT 61 ms NRESPWRON 032-012 Figure 4-10. Timings--OMAP3 Power-On Sequence 62 Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 4.5.3.4 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Power On in Slave_C021_Generic Mode Figure 4-11 describes the timing and control that must occur in the Slave_C021_Generic mode. Sequence_Start is a symbolic internal signal to ease the description of the power sequences and occurs according to the different events detailed in Figure 4-8. PWRON 4791 ms - 3 MHz oscillator setting + internal reg REGEN 1068 ms for external supply ramp VIO 1.8 V 1179 ms for VIO dc-dc stablilization 1.8 V VPLL1 1022 ms VDD2 1.2 V 1099 ms for VDD2 stabilization VDD1 1.2 V 1175 ms for VDD1 stabilization 32KCLKOUT 61 ms SYSEN 1099 ms for VDD2 stabilization CLKEN 1953 ms for digital clock setting HFCLKOUT 64 ms NRESPWRON 030-022 Figure 4-11. Timings--Power On in Slave_C021_Generic Model 4.5.4 Power-Off Sequence This section describes the signal behavior required to power down the system. 4.5.4.1 Power-Off Sequence in Master Modes Figure 4-12 shows the timing and control that occur during the power-off sequence in master modes. Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 63 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com VBAT DEVOFF(register) 18 ms NRESPWRON 1.2 ms REGEN 18 ms 32KCLKOUT 1.2 ms DCDCs 1.2 ms LDOs 18 ms SYSEN 18 ms HFCLKOUT 126 ms CLKEN 3.42 ms before detection of starting event NEXT_Startup_event 032-013 NOTE: All timings are typical values with the default setup (depending on the resynchronization between power domains, state machinery priority, etc.). Figure 4-12. Power-Off Sequence in Master Modes If the value of the HF clock is not 19.2 MHz (with the values of the CFG_BOOT HFCLK_FREQ bit field set accordingly), the delay between DEVOFF and NRESPWRON/CLK32KOUT/SYSEN/HFCLKOUT is divided by two (approximately 9 s). This is caused by the internal frequency used by power STM switching from 3 to 1.5 MHz if the HF clock value is 19.2 MHz. The DEVOFF event is PWRON falling edge in slave mode and DEVOFF internal register write in master mode. 64 Power Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 5 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Real-Time Clock and Embedded Power Controller The TPS65950 device contains an RTC to provide clock and timekeeping functions and an EPC to provide battery supervision and control. 5.1 RTC The RTC provides the following basic functions: * Time information (seconds/minutes/hours) directly in binary-coded decimal (BCD) code * Calendar information (day/month/year/day of the week) directly in BCD code * Interrupt generation periodically (1 second/1 minute/1 hour/1 day) or at a precise time (alarm function) * 32-kHz oscillator drift compensation and time correction * Alarm-triggered system wake-up event 5.1.1 Backup Battery The TPS65950 implements a backup mode in which a backup battery can keep the RTC running to maintain clock and time information even if the main supply is not present. If the backup battery is rechargeable, the device also provides a backup battery charger so it can be recharged when the main battery supply is present. The backup domain powers the following: * Internal 32.768-kHz crystal oscillator * RTC * Eight GP storage registers * Backup domain low-power regulator (VBRTC) 5.2 EPC The EPC provides five system states for optimal power use by the system, as listed in Table 5-1. Table 5-1. System States System State NO SUPPLY Description The system is not powered by any battery. BACKUP The system is powered only with the backup battery and maintains only the VBRTC supply. WAIT-ON The system is powered by the main battery and maintains only the VRRTC supply. It can accept switch-on requests. ACTIVE The system is powered by the main battery; all supplies can be enabled with full current capability. SLEEP The main battery powers the system; selected supplies are enabled, but in low consumption mode. Three categories of events can trigger state transitions: * Hardware events: Supply/battery insertion, wake-up requests, USB plug, and RTC alarm * Software events: Switch-off commands, switch-on commands, and sleep-on commands * Monitoring events: Supply/battery level check, main battery removal, main battery fail, and thermal shutdown Copyright (c) 2008-2011, Texas Instruments Incorporated Real-Time Clock and Embedded Power Controller Submit Documentation Feedback Product Folder Link(s): TPS65950 65 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 6 www.ti.com Audio/Voice Module The audio codec in the device includes five DACs and two ADCs to provide multiple voice channels and stereo downlink channels that can support all standard audio sample rates through I2S/TDM format interfaces. The audio output stages on the device include stereo headset amplifiers, two integrated class-D amplifiers providing stereo differential outputs, predrivers for line outputs, and an earpiece amplifier. The input audio stages include three differential microphone inputs, stereo line inputs, and interface for digital micrphones. Automatic and programmable gain control is available with all necessary digital filtering, side-tone functions, and pop-noise reduction. Figure 6-1 is a block diagram of the audio/voice module. HFCLKIN High-speed 2 I C (control) Headset microphone Voice PCM interface Bluetooth PCM interface Audio TDM/I2S interface Main microphone Stereo headset Sub microphone Stereo hands-free class D Mono ear piece Bias LDOs (x3) Carkit/MCPC speaker/ microphone Digital microphones (up to 4) Vibrator H-bridge Stereo auxiliary input Audio/voice module Device 032-014 Figure 6-1. Audio/Voice Module Block Diagram 66 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 6.1 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Audio/Voice Downlink (RX) Module The audio/voice module includes the following output stages: * Mono/stereo single-ended headset amplifier * Stereo differential integrated class-D 8- hands-free amplifiers * Predriver output signals for external class-D amplifiers (single-ended) * Mono differential earpiece amplifier * Vibrator H-bridge 6.1.1 Earphone Output 6.1.1.1 Earphone Output Characteristics Analog signals from the audio and/or voice interface are fed to the earphone amplifier. This amplifier, with different gains, provides a full differential signal on terminals EARP and EARM. Figure 6-2 shows the earphone amplifier. Table 6-1 lists the output characterstics of the earphone amplifier. 0 dBFs Digital PGA Gain = 0 dB Analog PGA Gain = 2 dB DAC Amp 6 dB 4.0 Vpp diff 032-015 Figure 6-2. Earphone Amplifier Table 6-1. Earphone Amplifier Output Characteristics Parameter Test Conditions Differential load impedance Gain range (1) Min Typ 26 32 Max 100 100 pF Audio path -86 36 Voice path -60 36 Absolute gain error -1 At 1.4 Vrms differential output voltage Load impedance = 32 Peak-to-peak differential output voltage (0 dBFs) Default gain Total harmonic distortion At 0 dBFs -65 -60 At -6 dBFs -70 -65 Default gain (2) Load impedance = 32 mW 4.0 At -20 dBFs VPP dB -60 -30 Idle channel noise (20 Hz to 20 kHz, A-weighted) Gain = 0 dB Load = 32 Output PSRR (for all gains) 20 Hz to 4 kHz 90 20 Hz to 20 kHz 70 (2) dB 61.25 At -60 dBFs (1) dB 1 Maximum output power (2) Unit -90 -85 dBFs dB Audio digital filter = -62 to 0 dB (1-dB steps) and 0 to 12 dB (6-dB steps) Voice digital filter = -36 to 12 dB (1-dB steps) ARXPGA (volume control) = -24 to 12 dB (2-dB steps) Output driver = 0, 6, 12 dB The default gain setting assumes the ARXPGA has 2-dB gain setting (volume control) and output driver at 6-dB gain setting. Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 67 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 6.1.1.2 www.ti.com External Components and Application Schematic Figure 6-3 is a simplified schematic of the earphone speaker. Chip On Board EARP CEAR 32 W EARM 032-016 Figure 6-3. Earphone Speaker NOTE For the component values, see Table 15-1. 6.1.2 8- Stereo Hands-Free The digital signal from the audio and/or voice interface is fed to two class-D amplifiers. These 8- speaker amplifiers provide a stereo differential signal on terminal pairs (IHF.RIGHT.P, IHF.RIGHT.M and IHF.LEFT.P, IHF.LEFT.M). 6.1.2.1 8- Stereo Hands-Free Output Characteristics Figure 6-4 shows the 8- stereo hands-free amplifier. Table 6-2 lists the output characteristics of the 8- stereo hands-free amplifier. Digital PGA Gain = 0 dB DAC Analog PGA Gain = 0 dB Amp 10.4 dB 5.0 Vpp diff 032-017 Figure 6-4. 8- Stereo Hands-Free Amplifiers Table 6-2. 8- Stereo Hands-Free Output Characteristics Parameter Test Conditions VBAT voltage Load impedance 68 Audio/Voice Module Min Typ Max 3.0 3.6 4.6 6 8 Unit V Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 6-2. 8- Stereo Hands-Free Output Characteristics (continued) Parameter Test Conditions Gain range (1) Max Unit Audio path -75.6 34.4 dB Voice path -49.6 34.4 Absolute gain error Min Typ -1 Maximum output power (load impedance = 8 ) Peak-to-peak differential output voltage Total harmonic distortion (load impedance = 8 , gain setting = 0 dB) (VBAT > 3.6 V) 1 VBAT > 3.6 V 400 VBAT > 4.0 V 700 VBAT > 3.6 V (0 dBFs) 5.0 VBAT > 4.0 V (2 dBFs) 6.25 At 0 dBFs -60 dB mW VPP -40 At -10 dBFs -60 At -20 dBFs -45 At -60 dBFs -20 dBFs Total harmonic distortion (load impedance = 8 , (VBAT > 4.2 V) 2 dBFs -60 Idle channel noise (20 Hz to 20 kHz) 0 dB gain -88 dBFs PSRR (input signal 1 kHz sine, 300 mVPP GSM ripple at 217 Hz with 10-s rise/fall times, at 12.5% duty cycle) From VBAT 80 dB Power on load = 400 mW Load impedance = 8 Efficiency Power dissipation Power on load = 400 mW Load impedance = 8 Idle current consumption on VBAT Without input signal Clock frequency for the ramp generation IDDQ current (1) 75 dB 70% 175 mW 426.6 kHz 6 384 At 25C -40 mA 0.6 A Audio digital filter = -62 to 0 dB (1-dB steps) and 0 to 12 dB (6-dB steps) Voice digital filter = -36 to 12 dB (1-dB steps) ARXPGA (volume control) = -24 to 12 dB (2-dB steps) Output driver = 10.4 dB 6.1.2.1.1 Short-Circuit Protection There is short-circuit protection for hands-free amplifiers to limit power dissipation to 1.2 W. The short-circuit protection can be disabled by register. If a short circuit is detected, the short-circuit detection block switches off the hands-free speaker output stages. A software restart is required to restart the class-D amplifier. 6.1.2.2 External Components and Application Schematic Figure 6-5 is a simplified schematic of the 8- stereo hands-free. Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 69 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com On board Chip VBAT VBAT.RIGHT/LEFT CHFR/CHFL Ferrite chip bead IHF.RIGHT/LEFT.P LHFR.P/LHFL.P CHFR.P/CHFL.P 8W Ferrite chip bead IHF.RIGHT/LEFT.M LHFR.M/LHFL.M CHFR.M/CHFL.M GND.RIGHT/LEFT 032-018 Figure 6-5. 8- Stereo Hands-Free NOTE For the component values, see Table 15-1. For ferrite bead, choose one with high impedance at high frequencies, but with very low impedance at low frequencies. For example, MPZ1608S221A (recommended), N2012ZPS121, or MDP BKP1608HS271. 6.1.3 Headset The analog signal from the audio and/or voice interface is fed to two single-ended headset amplifiers. There are two configurations: * Stereo single-ended mode: Left and right headset amplifiers with different gains (-6, 0, 6 dB) provide the stereo signal on the HSOL and HSOR terminals. A pseudo-ground is provided on the VMID terminal to eliminate external capacitors. * Stereo single-ended mode ac-coupled: Left and right headset amplifiers with different gains (-6, 0, 6 dB) provide the stereo signal on the HSOL and HSOR terminals. The external capacitor is required to eliminate the dc component of the signal. 6.1.3.1 Headset Output Characteristics Figure 6-6 shows the headset amplifier. Table 6-3 lists the output characteristics of the headset amplifier. 0 dBFs Digital PGA Gain = 0 dB DAC Analog PGA Gain = 0 dB Amp 0 dB 1.5 Vpp 032-019 Figure 6-6. Headset Amplifier Table 6-3. Headset Output Characteristics Parameter Test Conditions Load impedance 70 Audio/Voice Module Min Typ 14 16 Max Unit Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 6-3. Headset Output Characteristics (continued) Parameter Gain range Test Conditions (1) Min Typ 100 100 Max pF Audio path -92 30 Voice path -66 30 -1 1 Absolute gain error Maximum output power At 0.53 Vrms differential output voltage Load impedance = 16 Peak-to-peak output voltage (0 dBFs) Default gain (2) Unit dB dB 17.56 mW 1.5 VPP Single-Ended Mode ac-Coupled Total harmonic distortion Default gain (2) Load = 16 At 0 dBFs -80 -75 At -6 dBFs -74 -69 At -20 dBFs -70 -65 dB At -60 dBFs -30 -25 Idle channel noise (20 Hz to 20 kHz, A-weighted) Default gain (3) Load = 16 -90 -85 SNR (A-weighted over 20-kHz bandwidth) At 0 dBFs 86 dB Output PSRR (for all gains) 20 Hz to 4 kHz 90 dB 20 Hz to 20 kHz 70 Crosstalk between right and left channels 82 -60 dB dB Single-Ended Mode (Pseudo-Ground Provided on HSOVMID) Total harmonic distortion At 0 dBFs -75 -70 At -6 dBFs -74 -69 At -20 dBFs -70 -65 At -60 dBFs -30 -25 Idle channel noise (20 Hz to 20 kHz, A-weighted) Default gain (3) Load = 16 -90 -85 Output PSRR (for all gains) 20 Hz to 4 kHz 85 20 Hz to 20 kHz 65 Default gain (3) Load = 16 (1) (2) (3) dB dB dB Audio digital filter = -62 to 0 dB (1-dB steps) and 0 to 12 dB (6-dB steps) Voice digital filter = -36 to 12 dB (1-dB steps) ARXPGA (volume control) = -24 to 12 dB (2-dB steps) Output driver = -6, 0, 6 dB The default gain setting assumes the ARXPGA has 0 dB gain setting (volume control) and output driver at 0 dB gain setting. The default gain setting assumes the ARXPGA has 0 dB gain setting (volume control) and output driver at 0 dB gain setting. Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 71 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 6.1.3.2 www.ti.com External Components and Application Schematic Figure 6-7 is a schematic of a headset 4-wire stereo jack without an external FET. Table 6-4 lists the output characteristics of this configuration. On board Chip 4-wire stereo jack Rsb Rb VHSMIC .OUT CHM.P HSMIC.P Cb CHM.O CHM.M HSMIC.M Rs Cs HSOL Rl Cl Cs Rs Rl HSOR Cl 032-20 Figure 6-7. Headset 4-Wire Stereo Jack Without an External FET Table 6-4. Output Characteristics of a Headset 4-Wire Stereo Jack Without an External FET Parameter Rsb Test Conditions Min Cb < 200 pF 0 Cb = 100 nF 300 Cb = 1 F 500 Rb + Rsb 2.2 Cs The input capacitors and output resistors form a high-pass filter (HPF) with the corner frequency = 1/(2Rout/Cs) 22 RL CL Rs required to ensure 16 to 32 <100 pF 0 HS amplifier stability 16 to 32 1 nF 4 16 2 nF 24 72 2.7 47 k F 18 3 nF 12 20 32 24 4 nF 16 24 24 32 32 16 Unit 8 24 16 Max 12 32 16 Typ 5 nF 20 24 28 32 36 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 NOTE For other component values, see Table 15-1. Table 6-5 is a schematic of a headset 4-wire stereo jack with an external FET. Table 6-5 lists the output characteristics of this configuration. On board Chip 4-wire stereo jack Rsb Rb VHSMIC .OUT CHM.P HSMIC .P CHM.O Cb CHM.M HSMIC .M Rs Cs HSOL Rl Cl Cs Rs Rl HSOR GPIO_6 ( MUTE ) Cl External FET 032-021 Figure 6-8. Headset 4-Wire Stereo Jack With an External FET Table 6-5. Output Characteristics of a Headset 4-Wire Stereo Jack With an External FET Parameter Test Conditions Rsb Min Cb < 200 pF 0 Cb = 100 nF 300 Cb = 1 F 500 Rb + Rsb 2.2 Cs The input capacitors and output resistors form a HPF with the corner frequency = 1/(2Rout/Cs) 22 Rs required to ensure HS amplifier stability and no distortion caused by the parasitic diode of the external FET RL CL 16 <2 nF 15 32 20 3 nF 24 2.7 47 k F 12 24 4 nF 24 16 24 32 16 Unit 20 32 16 Max 10 24 16 Typ 32 5 nF 20 24 28 32 36 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 73 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com NOTE For other component values, see Table 15-1. Figure 6-9 is a schematic of a headset 5-wire stereo jack. Table 6-6 lists the output characteristics of this configuration. On board Chip 5-wire stereo jack Rsb VHSMIC.OUT Rb CHM.P HSMIC.P Cb CHM.O CHM.M HSMIC.M Rs HSOL Rl HSOVMID Cl Rs Rl HSOR Cl CHM.O 032-022 Figure 6-9. Headset 5-Wire Stereo Jack Table 6-6. Output Characteristics of a Headset 5-Wire Stereo Jack Parameter Rsb Test Conditions Min Cb < 200 pF 0 Cb = 100 nF 300 Cb = 1 F 500 Rb + Rsb Rs required to ensure HS amplifier stability 2.2 RL CL 16 to 32 <100 pF 0 16 to 32 1 nF 4 16 2 nF 24 2.7 k 8 12 24 4 nF 24 16 24 32 74 20 32 16 Unit 18 3 nF 24 16 Max 12 32 16 Typ 32 5 nF 20 24 28 32 36 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 NOTE For other component values, see Table 15-1. Figure 6-10 is a schematic of a headset 4-wire stereo jack optimized. On board Chip 4-wire stereo jack Rsb VHSMIC.OUT Rb CHM.P HSMIC Cb CHM.O CHM.M HSMIC.M mA + Cs Rs Rl HSOL Ampli_HS - mA mA Cl Rl + - Cs Rs HSOR Ampli_HS Gain = -1 Cl 032-023 Figure 6-10. Headset 4-Wire Stereo Jack Optimized NOTE For other component values, see Table 15-1. 6.1.4 Headset Pop-Noise Attenuation Pop noise occurs when the audio output amplifier is switched on. Although the speaker is ac-coupled through an external capacitor, the sharp rise time given by the activation of the amplifier causes a large spike to propagate to the speakers. Pop attenuation is achieved through a precharge and discharge of the external coupling capacitor. The antipop system using an internal current generator controlling the ramp of charge or discharge is implemented for the headset output. The pop-noise effect can be dramatically reduced by an external FET controlled by a 1.8-V output signal (MUTE pin). Figure 6-11 is a diagram of headset pop noise. Table 6-7 lists the characteristics of headset pop noise. Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 75 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com HSO HSO MUTE RAMP_DELAY Application mode RAMP_DELAY EXTMUTE VMID_EN HSR/L_GAIN(1:0) RAMP_EN V VMID dV/dt 0 t 0 t 0 t 032-024 Figure 6-11. Headset Pop-Noise Cancellation Diagram Table 6-7. Headset Pop-Noise Characteristics Parameter Test Conditions dv/dt Ramp of charge or discharge Pop-noise (A-weighted) ac-coupling capacitor = 47 F Serial resistor = 33 External FET: Rdson = 0.12 6.1.5 Min Typ Max Unit 170 V/s 1 mV Predriver for External Class-D Amplifier Two predriver amplifiers provide a stereo signal on the PreD.LEFT and PreD.RIGHT terminals to drive an external class-D amplifier. These terminals are available if a stereo, single-ended, ac-coupled headset is used. 6.1.5.1 Predriver Output Characteristics Table 6-8 lists the output characteristics of the predriver. 76 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 6-8. Predriver Output Characteristics Parameter Test Conditions Load impedance Min Typ Max Unit 10 k 50 Gain range (1) pF Audio path -92 30 Voice path -66 30 Absolute gain error -1 1 (2) Peak-to-peak output voltage (0 dBFs) Default gain Total harmonic distortion At 0 dBFs -80 -75 At -6 dBFs -74 -69 At -20 dBFs -70 -65 At -60 dBFs -30 -25 -90 -85 Default gain (2) Load > 10 k // 50 pF 1.5 (3) Idle channel noise (20 Hz to 20 kHz, A-weighted) Default gain Load = 10 SNR (A-weighted over 20-kHz bandwidth) At 0 dBFs Default gain (3) At -60 dBFS 30 Output PSRR (for all gains) 20 Hz to 4 kHz 90 20 Hz to 20 kHz 70 (1) (2) (3) 83 dB dB VPP 88 dB dB dB dB Audio digital filter = -62 to 0 dB (1-dB steps) and 0 to 12 dB (6-dB steps) Voice digital filter = -36 to 12 dB (1-dB steps) ARXPGA (volume control) = -24 to 12 dB (2-dB steps) Output driver = -6, 0, 6 dB The default gain setting assumes the ARXPGA has a 0 dB gain setting (volume control) and output driver has a 0 dB gain setting. The default gain setting assumes the ARXPGA has a 0 dB gain setting (volume control) and output driver has a 0 dB gain setting. 6.1.5.2 External Components and Application Schematic Figure 6-12 is a simplified schematic of the external class-D predriver. On board RPR/RPL Chip CPL/CPR PreDriverD IN+ Class D (TPA2010D1...) IN- Closed to external class C CPR.O/CPL.O RPL.O/RPR.O CPL.M/CPR.M RPR.M/RPL.M 032-025 Figure 6-12. Predriver for External Class D In Figure 6-12, input resistor (RPR or RPL) sets the gain of the external class D. For TPS2010D1, the gain is defined according to the following equation: Gain (V/V) = 2*150*103/(RPR or RPL) RPR or RPL > 15 k Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 77 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com NOTE For other component values, see Table 15-1. 6.1.6 Vibrator H-Bridge A digital signal from the pulse width modulated generator is fed to the vibrator H-bridge driver. The vibrator H-bridge is a differential driver that drives vibrator motors. The differential output allows dual rotation directions. 6.1.6.1 Vibrator H-Bridge Output Characteristics Table 6-9 lists the output characteristics of the vibrator H-bridge. Table 6-9. Vibrator H-Bridge Output Characteristics Parameter Test Conditions VBAT voltage Differential output swing (16- load) Min Typ Max 2.8 3.6 4.8 VBAT = 2.8 V 3.6 VBAT = 3.5 V 4.3 Load capacitance 8 16 Load inductance 30 Total harmonic distortion 8 100 pF 60 300 H 10% Operating frequency 6.1.6.2 V VPP Output resistance (summed for both sides) Load resistance Unit 20 10k Hz External Components and Application Schematic Figure 6-13 is a simplified schematic of the vibrator H-bridge. On board VBAT Chip VBAT.RIGHT CV.V Ferrite chip bead LV.P VIBRA.P CV.P Vibrator Ferrite chip bead LV.M VIBRA.M CV.M VIBRA.GND (LED.GND) 032-026 Figure 6-13. Vibrator H-Bridge 78 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 NOTE For other component values, see Table 15-1. Example of ferrite: BLM 18BD221SN1. 6.1.7 Carkit Output The USB-CEA carkit uses the DP/DM pad to output audio signals (see the CEA-936A: Mini-USB Analog Carkit Interface Specification). The MCPC carkit uses the RXAF analog pad to output audio signals. Figure 6-14 shows the carkit output downlink full path characteristics for audio and USB. 0 dBFs Digital PGA Gain = 0 dB Analog PGA Gain = 0 dB DAC USB Amp -0.6 dB Amp 0 dB 1.35 VPP 032-027 Figure 6-14. Carkit Output Downlink Path Characteristics Table 6-10 lists the electrical characteristics of the MCPC and USB-CEA carkit audio. Table 6-10. MCPC and USB-CEA Carkit Audio Downlink Electrical Characteristics Parameter Conditions Output load USB-CEA (DP/DM) MCPC (RXAF) Gain range (1) Min Typ Max 20 Unit k 5 Audio path -92 30 Voice path -66 30 Absolute gain error At 1 kHz -1 Peak-to-peak differential output voltage (0 dBFs) Gain = 0 dB 1.5 1 Total harmonic distortion At 0 dBFs -80 -75 At -6 dBFs -74 -69 At -20 dBFs -70 -65 At -60 dBFs -30 -25 dB dB VPP dB THD+N (20 Hz to 20 kHz, A-weighted) At 0 dBFs 60 dB Idle channel noise (20 Hz to 20 kHz, A-weighted), default gain setting (2) USB-CEA -77 dBFs MCPC -80 Output PSRR 20 Hz to 20 kHz 60 Supply voltage (VINTANA1) 1.3 Isolation between D+/D- during audio mode (20 Hz to 20 kHz) 1.35 USB-CEA stereo Crosstalk RX/TX (1 VPP output) USB-CEA mono/stereo At 0 dBFs V dB -90 dB -60 MCPC (2) V 1.4 60 Crosstalk between right and left channels (1) dB 1.5 Common mode output voltage for USB-CEA Signal noise ratio (20 Hz to 20 kHz, A-weighted) -77 dB -65 60 dB Audio digital filter = -62 to 0 dB (1-dB steps) and 0 to 12 dB (6-dB steps); Voice digital filter = -36 to 12 dB (1-dB steps); ARXPGA (volume control) = -24 to 12 dB (2-dB steps); Output driver (USB-CEA and MCPC) = -1 dB The default gain setting assumes the ARXPGA has 0-dB gain setting (volume control) and output driver at 0.6-dB gain setting. Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 79 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 6-10. MCPC and USB-CEA Carkit Audio Downlink Electrical Characteristics (continued) Parameter Conditions Phone speaker amplifier output impedance at 1 kHz 6.1.8 Max Unit USB-CEA (DP/DM) Min Typ 200 MCPC (RXAF) 200 Digital Audio Filter Module Figure 6-15 shows the digital audio filter downlink full path characteristics of the audio interface. High-pass filter Audio interface Low-pass filter Digital modulator Randomizer DAC 032-028 Figure 6-15. Digital Audio Filter Downlink Path Characteristics The HPF can be bypassed. Table 6-11 lists the audio filter frequency responses relative to reference gain at 1 kHz. Table 6-11. Digital Audio Filter RX Electrical Characteristics Parameter Conditions Min Typ Passband Passband ripple 0 to 0.42FS (1) -0.25 0.1 Stopband Stopband attenuation F = 0.6FS (1) to 0.8FS (1) Unit 0.25 dB FS 75 dB 15.8/FS Linear phase FS 0.6 60 Group delay (1) Max 0.42 (1) -1.4 s 1.4 FS is the sampling frequency (8, 11.025, 12, 16, 22.05, 24, 32, 44.1, or 48 kHz). 6.1.9 Digital Voice Filter Module Figure 6-16 shows the digital voice filter downlink full path characteristics of the voice interface. Voice interface High-pass filter Low-pass filter Digital modulator Randomizer DAC 032-029 Figure 6-16. Digital Voice Filter Downlink Path Characteristics The global HPF or only the third-order HPF can be bypassed (when the third-order HPF is skipped, the first-order HPF remains active). 80 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 6.1.9.1 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Voice Downlink Filter (Sampling Frequency at 8 kHz) Figure 6-17 shows the voice downlink frequency response with FS = 8 kHz. Table 6-12 lists the voice filter frequency responses relative to the reference gain at 1 kHz with FS = 8 kHz. Voice Downlink (RX) Filter 8 kHz 2 1.5 1 Gain (dB) 0.5 Rx_8K_1st_HPF Specification Rx_8K_3rd_HPF 0 -0.5 -1 -1.5 -2 -2.5 -3 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency (Hz) 032-030 Figure 6-17. Voice Downlink Frequency Response With FS = 8 kHz Table 6-12. Digital Voice Filter RX Electrical Characteristics With FS = 8 kHz Parameter Test Conditions Frequency response relative to reference gain at 1 kHz (first-order 100 Hz HPF) 200 Hz Min Typ -8 Max Unit -20 dB -0.5 300 to 3300 Hz -0.5 0 0.5 3400 Hz -1.5 0 0.1 4000 Hz -17 4600 Hz -40 > 6000 Hz -45 Pole when third-order HPF is disabled (first-order HPF) 2.5 Hz Group delay 0.5 ms Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 81 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 6.1.9.2 www.ti.com Voice Downlink Filter (Sampling Frequency at 16 kHz) Figure 6-18 shows the voice downlink frequency response with FS = 16 kHz. Table 6-13 lists the voice filter frequency responses relative to the reference gain at 1 kHz with FS = 16 kHz. Voice Downlink (RX) Filter 16 kHz 2 1.5 1 Gain (dB) 0.5 0 Rx_8K_1st_HPF Rx_8K_3rd_HPF Specification -0.5 -1 -1.5 -2 -2.5 -3 0 1000 2000 3000 4000 5000 6000 7000 Frequency (Hz) 032-031 Figure 6-18. Voice Downlink Frequency Response With FS = 16 kHz Table 6-13. Digital Voice Filter RX Electrical Characteristics With FS = 16 kHz Parameter Test Conditions Frequency response relative to reference gain at 1 kHz (first-order HPF) Min Typ Max Unit 300 to 6600 Hz -0.5 0 0.5 dB 6800 Hz -1.5 0 0.1 8000 Hz -17 9200 Hz -40 > 12000 Hz Pole when third-order HPF is disabled (first-order HPF) -45 5 Hz 6.1.10 Boost Stage The boost effect adds emphasis to low frequencies. It compensates for an HPF created by the capacitance resistor (CR) filter of the headset (in ac-coupling configuration). There are four modes. Three effects are available, with slightly different frequency responses, and the fourth setting disables the boost effect: * Boost effect 1 * Boost effect 2 * Boost effect 3 * Flat equalization: The boost effect is in bypass mode. Table 6-14 and Table 6-15 list typical values according to frequency response versus input frequency and FS frequency. 82 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 6-14. Boost Electrical Characteristics Versus FS Frequency (FS 22.05 kHz) FS = 8 kHz FS = 11.025 kHz FS = 12 kHz FS = 16 kHz FS = 22.05 kHz Frequency (Hz) 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 10 4.51 5.13 5.62 5.10 5.51 5.80 5.22 5.58 5.83 5.54 5.77 5.92 5.76 5.89 5.97 12 4.08 4.83 5.46 4.80 5.32 5.71 4.95 5.41 5.76 5.36 5.66 5.87 5.65 5.83 5.94 15.2 3.43 4.32 5.18 4.28 4.97 5.54 4.47 5.11 5.61 5.03 5.47 5.79 5.45 5.71 5.90 18.2 2.91 3.86 4.89 3.82 4.63 5.36 4.04 4.80 5.45 4.71 5.26 5.69 5.24 5.59 5.84 20.5 2.56 3.53 4.65 3.49 4.37 5.21 3.72 4.56 5.32 4.45 5.09 5.60 5.06 5.49 5.79 29.4 1.62 2.49 3.78 2.45 3.42 4.57 2.68 3.74 4.73 3.51 4.39 5.24 4.35 5.02 5.59 39.7 1.05 1.71 2.93 1.67 2.55 3.84 1.88 2.80 4.06 2.66 3.63 4.72 3.67 4.45 5.27 50.4 0.71 1.20 2.26 1.17 1.91 3.17 1.33 2.13 3.41 2.01 2.95 4.19 2.89 3.85 4.88 60.3 0.51 0.92 1.79 0.89 1.49 2.65 1.00 1.68 2.89 1.57 2.43 3.72 2.39 3.35 4.52 76.7 0.32 0.61 1.26 0.59 1.05 1.99 0.69 1.18 2.22 1.11 1.79 3.04 1.76 2.66 3.94 97.5 0.20 0.39 0.87 0.38 0.70 1.43 0.44 0.79 1.62 0.75 1.27 2.36 1.24 2.00 3.28 131.5 0.12 0.21 0.50 0.20 0.39 0.88 0.25 0.47 1.02 0.42 0.78 1.59 0.75 1.30 2.41 157 0.08 0.15 0.36 0.15 0.28 0.65 0.17 0.33 0.75 0.31 0.57 1.22 0.55 0.99 1.93 200 0.05 0.09 0.22 0.09 0.17 0.41 0.11 0.21 0.49 0.19 0.37 0.82 0.36 0.66 1.38 240 0.03 0.06 0.15 0.06 0.12 0.29 0.07 0.14 0.35 0.14 0.26 0.60 0.25 0.48 1.04 304 0.02 0.04 0.09 0.04 0.07 0.18 0.04 0.09 0.22 0.08 0.16 0.38 0.16 0.30 0.70 463 0.00 0.01 0.03 0.01 0.03 0.07 0.02 0.04 0.09 0.03 0.07 0.17 0.07 0.13 0.32 704 0.00 0.00 0.01 0.00 0.01 0.03 0.01 0.01 0.03 0.01 0.03 0.07 0.03 0.06 0.14 1008 0.00 0.00 0.00 0.00 0.00 0.01 0.00 0.00 0.01 0.00 0.01 0.03 0.01 0.02 0.06 1444 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.01 0.02 2070 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.01 3770 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 Unit dB Table 6-15. Boost Electrical Characteristics Versus FS Frequency (FS 24 kHz) FS = 24 kHz FS = 32 kHz FS = 44.1 kHz FS = 48 kHz FS = 96 kHz Frequency (Hz) 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 10 5.79 5.90 5.97 5.89 5.89 5.99 5.95 5.98 6.04 5.96 5.99 6.01 5.71 5.83 5.90 12 5.70 5.85 5.95 5.84 5.84 5.98 5.92 5.97 6.03 5.94 5.98 6.00 5.54 5.68 5.81 15.2 5.53 5.76 5.91 5.73 5.73 5.96 5.87 5.94 6.02 5.89 5.95 5.99 5.40 5.57 5.73 18.2 5.35 5.65 5.87 5.62 5.62 5.93 5.80 5.90 6.00 5.83 5.93 5.98 5.28 5.48 5.68 20.5 5.19 5.56 5.83 5.52 5.52 5.91 5.74 5.87 5.99 5.78 5.90 5.97 5.19 5.42 5.64 29.4 4.55 5.18 5.64 5.10 5.07 5.79 5.51 5.75 5.94 5.57 5.79 5.92 4.87 5.18 5.48 39.7 3.81 4.62 5.37 4.52 4.52 5.64 5.12 5.53 5.85 5.26 5.59 5.84 4.47 4.91 5.30 50.4 3.14 4.06 5.02 3.94 3.95 5.43 4.69 5.27 5.72 4.88 5.37 5.73 4.08 4.63 5.11 60.3 2.62 3.51 4.69 3.46 3.54 5.21 4.30 5.00 5.59 4.49 5.13 5.62 3.72 4.37 4.95 76.7 1.97 2.90 4.15 2.76 2.76 4.78 3.68 4.52 5.34 3.91 4.70 5.40 3.18 3.92 4.67 97.5 1.41 2.22 3.51 2.10 2.09 4.27 2.99 3.94 4.99 3.24 4.15 5.07 2.59 3.41 4.33 131.5 0.88 1.49 2.65 1.40 1.40 3.49 2.15 3.10 4.35 2.38 3.35 4.51 1.86 2.69 3.75 157 0.65 1.13 2.15 1.04 1.04 2.96 1.70 2.58 3.90 1.90 2.82 4.08 1.47 2.24 3.35 200 0.41 0.76 1.55 0.70 0.70 2.28 1.19 1.93 3.23 1.35 2.15 3.44 1.03 1.68 2.77 240 0.30 0.55 1.18 0.50 0.50 1.81 0.89 1.51 2.71 1.02 1.70 2.92 0.77 1.31 2.32 304 0.18 0.35 0.80 0.33 0.32 1.27 0.58 1.04 2.05 0.68 1.19 2.24 0.51 0.90 1.75 463 0.08 0.16 0.37 0.14 0.14 0.64 0.27 0.50 1.12 0.31 0.58 1.25 0.23 0.43 0.95 704 0.03 0.06 0.16 0.06 0.06 0.29 0.12 0.23 0.56 0.14 0.27 0.62 0.10 0.20 0.46 1008 0.01 0.03 0.07 0.03 0.02 0.14 0.06 0.11 0.30 0.06 0.13 0.31 0.05 0.10 0.23 1444 0.00 0.01 0.03 0.01 0.01 0.06 0.03 0.05 0.16 0.03 0.06 0.15 0.02 0.05 0.11 2070 0.00 0.00 0.01 0.00 0.00 0.02 0.01 0.02 0.09 0.01 0.03 0.07 0.01 0.02 0.05 3770 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.04 0.00 0.00 0.01 0.00 0.00 0.01 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 Unit dB 83 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 6.2 www.ti.com Audio/Voice Uplink (TX) Module The voice uplink path includes two input amplification stages dedicated to ten analog input terminals: * MIC_MAIN_P, MIC_MAIN_M (differential main handset input) * MIC_SUB_P, MIC_SUB_M (differential sub handset input) * HSMICP, HSMICM (differential headset input) * AUXL (common terminal: single-ended auxiliary/FM radio left channel input) * AUXR (common terminal: single-ended auxiliary/FM radio right channel input) * CEA carkit and MCPC transmit audio (TXAF) microphone through DINP/DINM pins For all cases, only two analog input amplifiers can be used, because two ADCs are available. The voice uplink path also includes two pulse density modulated (PDM) interfaces for digital microphones. Two stereo digital microphone interfaces are available. The left and right FM channels can be connected to any audio output stage (for example, earpiece, headset speakers, etc.) through a connection matrix. 6.2.1 Microphone Bias Module Three bias generators provide an external voltage of 2.2 V to bias the analog microphones (MICBIAS1, MICBIAS2, and HSMICBIAS terminals). The typical output current is 1 mA for each analog bias microphone. Two bias generators can provide an external voltage of 1.8 V to bias digital microphones (DIGMIC_0 and DIGMIC_1). The typical output current is 5 mA for each digital bias microphone. NOTE One bias generator can bias two digital microphones at the same time; in this case, the typical output current is 10 mA. Figure 6-19 shows the multiplexing for the analog and digital microphones. 84 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Dig Mic Bia LDO PWDNZ MICBIAS2 1.8 V Analog microphone or digital microphone PWDN Analog Mic Bias Dig Mic Bia LDO PWDNZ 2 .2 V 1.8 V MICBIAS1 Analog microphone or digital microphone PWDN Analog Mic Bias Analog Mic Bias 2 .2 V 2 .2 V HSMICBIAS Analog microphone (headset mic) DIG.MIC.CLK1 (Muxed with Bluetooth interface) CLK = 50 *Fs DIG.MIC.CLK0 (Muxed with Bluetooth interface) Comp DIG.MIC.0 or MIC.SUB.P Comp Comp DIG.MIC.1 or MIC.SUB.M Comp Mic amp right MIC.MAIN.P Mic amp left MIC.MAIN.M 032-032 Figure 6-19. Analog and Digital Microphone Multiplexing 6.2.1.1 Analog Microphone Bias Module Characteristics Table 6-16 lists the characteristics of the analog microphone bias module. Table 6-16. Analog Microphone Bias Module Characteristics Parameter Test Conditions Bias voltage Load current Min Typ Max Unit 2.15 2.2 2.25 V 1 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 mA 85 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 6-16. Analog Microphone Bias Module Characteristics (continued) Parameter Test Conditions Output noise Min Typ P-weighted 20 Hz to 6.6 kHz External capacitor 0 Internal resistance 50 Max Unit 1.8 VRMS 200 pF 70 k 60 NOTE If the value of the external capacitor is greater than 200 pF, the analog microphone bias becomes unstable. To stabilize it, a serial resistor must be added. Table 6-17 lists the characteristics of the analog microphone bias module with a bias resistor. Table 6-17. Characteristics of Analog Microphone Bias Module With a Bias Resistor Parameter Test Conditions RSB Min CB < 200 pF 0 CB = 100 pF 300 CB = 1 F 500 RB + RSB 6.2.1.2 Typ Max Unit 2.2 to 2.7 k External Components and Application Schematic Figure 6-20 and Figure 6-21 show the external components and application schematics for the analog microphone. Device On board RMM.O/RMS.O MICBIAS1/2.OUT CMM.B/CMS.B CMM.P/CMS.P MIC.SUB.P/MIC.MAIN.P RMM.MP/RMS.MP MIC.SUB.M/MIC.MAIN.M CMM.M/CMS.M CMM.O/ CMS.O MICBIAS.GND 032-033 Figure 6-20. Analog Microphone Pseudodifferential 86 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 NOTE For other component values, see Table 15-1. On board Device RMM.BP/RMS.SP MICBIAS1/2.OUT RMM.GM /2 or RMS.GM/2 CMM.B/CMS.B CMM.P/CMS.P MIC.SUB.P/MIC.MAIN.P 47pF CMM.PM/CMS.PM Close to device Close to device MIC.SUB.M/MIC.MAIN.M CMM.M/CMS.M CMM.GM or CMS.GM RMM.GM /2 or RMS.GM/2 CMM.GP or CMS.GP MICBIAS.GND 032-034 Figure 6-21. Analog Microphone Differential NOTE For other component values, see Table 15-1. NOTE To improve the rejection, it is highly recommended to ensure that MICBIAS_GND is as clean as possible. This ground must be shared with AGND of TPS65950 and must not share with AVSS4, which is the ground used by RX class-AB output stages. In differential mode, adding a low-pass filter (made by RSB and CB) is highly recommended if coupling between RX output stages and the microphone is too high (and there is not enough attenuation by the echo cancellation algorithm). The coupling can come from: * The internal TPS65950 coupling between MICBIAS.OUT voltage and RX output stages * Coupling noise between MICBIAS.GND and AVSS4 In pseudodifferential mode, the dynamic resistance of the microphone improves the rejection versus MICBIAS.OUT: PSRR = 20*log((RB + RDyn_mic)/RB) 6.2.1.3 Digital Microphone Bias Module Characteristics Figure 6-22 is a block diagram of the digital microphone bias module. Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 87 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com 2.75 V Audio PLL VMIC1/2.OUT 1.8 V Dig mic bia s(LDO) VRIO=1.8 V Digial MIC clock generator 50* Fs DIG.MIC.CLK0/1 50* Fs BUF DIGMIC left Q R Q S Audio digital filter Comparator DIG.MIC.0/1 0.9 V Audio digital filter Q S DIGMIC right Q R Comparator 032-035 Figure 6-22. Digital Microphone Bias Module Block Diagram Table 6-18 and Table 6-19 list the characteristics of the digital microphone bias module. Table 6-18. Digital Microphone Bias Module Characteristics Parameter Test Conditions Min Bias voltage Typ Max Unit 10 mA 1.8 Load current PSRR (from VBAT) 20 Hz to 6.6 kHz 60 External capacitor 0.3 ESR for capacitor V At 100 kHz 0.02 dB 1 3.3 F 0.6 Table 6-19. Digital Microphone Bias Module Characteristics (2) Parameter Test Conditions Min Comparator high threshold Comparator low threshold 0.3*VDD_IO Startup time Typ Max 0.5*VDD_IO 0.7*VDD_IO Unit 0.5*VDD_IO 2 s DIG.MIC.0 (tHOLD) from DIG.MIC.CLK0 edge 4 ns DIG.MIC.1 (tHOLD) from DIG.MIC.CLK1 edge 4 ns 88 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Figure 6-23 is a timing diagram of the digital microphone bias module. DIG.MIC.CLK0/1 DIG.MIC.0/1 thold thold 032-036 Figure 6-23. Digital Microphone Bias Module Timing Diagram 6.2.1.4 Silicon Microphone Characteristics Based on silicon micro-electrical-mechanical system (MEMS) technology, the new microphone achieves the same acoustic and electrical properties as conventional microphones, but is more rugged and exhibits higher heat resistance. These properties offer designers greater flexibility and new opportunities to integrate microphones. The silicon microphone is the integration of mechanical elements and electronics on a common silicon substrate through microfabrication technology. The complementary metal oxide semiconductor (CMOS) MEMS microphone is more like an analog IC than a classic electric condenser microphone (ECM). It is powered as an IC with a direct connection to the power supply. The on-chip isolation between the power input and the rest of the system adds power supply rejection (PSR) to the component, making the CMOS MEMS microphone inherently more immune to power supply noise than an ECM and eliminating the need for additional filtering circuitry to keep the power supply line clean. Figure 6-24 is a schematic of the silicon microphone module. Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 89 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Optional On board depending on dynamic of microphone 1 kW Device RSM MICBIAS1/2.OUT CSM CSM.P Silicon microphone SPM0204HE5-PB (SPM0102ND3-C) MIC.SUB.P/MIC.MAIN.P 4 1 Power Output GND GND 3 2 CSM.PG MIC.SUB.M/MIC.MAIN.M CSM.M MICBIAS.GND 032-037 Figure 6-24. Silicon Microphone Module Table 6-20 lists the characteristics of the silicon microphone module. Table 6-20. Silicon Microphone Module Characteristics Parameter Test Conditions Bias voltage Min Typ Max 2.2 Load current V 1 Output noise P-weighted 20 Hz to 6.6 kHz Unit 1.8 mA VRMS NOTE For other component values, see Table 15-1. 6.2.2 Stereo Differential Input The stereo differential inputs (the MIC_MAIN_P and MIC_MAIN_M, and the MIC_SUB_P and MIC_SUB_M terminals) can be amplified by the microphone amplification stages. The amplification stage outputs are connected to the two ADC inputs. 6.2.3 Headset Differential Input The headset differential inputs (the HSMICP and HSMICM terminals) can be amplified by the microphone amplification stage. The amplification stage outputs are connected to the ADC input. 90 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 6.2.4 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 FM Radio/Auxiliary Stereo Input The auxiliary inputs AUXL/FML and AUXR/FMR can be used as the left and right stereo inputs, respectively, of the FM radio. In that case (because both input amplifiers are busy), the other input terminals are discarded and set to a high-impedance state. Both microphone amplification stages amplify the FM radio stereo signal. Both amplification stage outputs are connected to the ADC input. The left and right channel inputs of the FM radio can also be output through an audio output stage (mono output stage in case of mono input FM radio, stereo output stage in case of stereo input FM radio). 6.2.4.1 External Components Figure 6-25 shows the external components of the auxiliary stereo input. On board Chip CAUXL/R AUXL/R CAUXL/R.M 032-038 Figure 6-25. Audio Auxiliary Input NOTE For other component values, see Table 15-1. 6.2.5 PDM Interface for Digital Microphones The PDM interface is used as digital microphone inputs; each microphone is directly connected to the TX filter decimator to extract the audio samples at the desired accuracy and sample rate. Each digital microphone is stereo (two paths). The digital microphone interface is DIG.MIC.CLK (clock input to the microphone) and DIG.MIC (PDM data output from the microphone). The appropriate frequency of DIG.MIC.CLK is generated by the audio PLL, and the ratio between DIG.MIC.CLK and the sample rate is 50 (see Figure 6-26). The PDM interface is available only when FS = 48 kHz. The data signal output is a 3-state output from the microphone. When a falling-edge DIG.MIC.CLK is detected, DIG.MIC is actively driven. When a rising DIG.MIC.CLK is detected, DIG.MIC is high impedance. The latter DIG.MIC.CLK half-cycle is reserved for stereo operation (the second microphone receives DIG.MIC.CLK inverted). The - converter in the digital microphones produces PDM. Digital microphone characteristics: * PDM clock rate 2.4 MHz * Fourth-order - converter in the microphone component Figure 6-26 is an example of PDM interface circuitry. Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 91 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com 2.75 V Digital mic bias (LDO) MICBIAS 1.8 V Digital mic clock generator 50* Fs 50* Fs DIG.MIC.CLK BUF Comparator DIG.MIC 0.9 V Comparator DIG.MIC.CLK Left Left Right DIG.MIC Right 032-039 Figure 6-26. Example of PDM Interface Circuitry 6.2.6 Uplink Characteristics Figure 6-27 shows the uplink amplifier. Table 6-21 lists the characteristics of the uplink amplifier. Amp 0 to 30 dB ADC Digital PGA Gain = 0 to 31 dB 032-040 Figure 6-27. Uplink Amplifier 92 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 6-21. Uplink Amplifier Characteristics Parameter Test Conditions Speech delay Min Typ Voice path Max 0.5 Gain range (1) Unit ms 0 61 -1 1 dB dB Absolute gain 0 dBFs at 1.02 kHz Peak-to-peak differential input voltage (0 dBFs) For differential input 0 dB gain setting 1.5 VPP Peak-to-peak single-ended input voltage (0 dBFs) For single-ended input 0 dB gain setting 1.5 VPP Input impedance (2) 70k At -1 dBFs -80 -75 dB At -6 dBFs -74 -69 At -10 dBFs -70 -65 At -20 dBFs -60 -55 At -60 dBFs -20 -15 20 Hz to 20 kHz, A-weighted, gain = 0 dB -85 -78 16 kHz: < 20 Hz to 7 kHz, gain = 0 dB -90 8 kHz: P-weighted voice, gain = 18 dB -87 16 kHz: < 20 Hz to 7 kHz, gain = 18 dB -82 40k Total harmonic distortion (sine wave at 1.02 kHz) Idle channel noise Crosstalk A/D to D/A Gain = 0 dB -80 Crosstalk path between two microphones Intermodulation distortion (1) (2) dBFs dB -70 dB Two-tone method -60 dB Gain range is defined by: Preamplifier = 0 to 30 dB; Filter = 0 to 31 dB (1-dB steps) Impedance varies in the specified range with gain selection. 6.2.7 Microphone Amplification Stage Microphone amplification stages perform single-to-differential conversion for single-ended inputs. Two programmable gains from 0 to 30 dB can be set: * Automatic level control for main microphone or submicrophone input. The gain step is 1 dB. * Level control by register for line-in or carkit input, or headset microphone. The gain step is 6 dB. The amplification stage outputs are connected to the ADC input (ADC left and right). 6.2.8 Carkit Input The USB-CEA carkit uses the DP pad to input the audio signal. The MCPC carkit uses the TXAF analog pad to input the audio signal. Figure 6-28 shows the uplink carkit full path uplink characteristics for audio and USB. Amp CEA -1.02 dB MCPC 0.56 dB Amp 0 to 30 dB ADC Digital PGA Gain = 0 to 31 dB 032-041 Figure 6-28. Carkit Input Uplink Path Characteristics Table 6-22 lists the electrical characteristics of the MCPC and USB-CEA carkit audio. Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 93 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 6-22. MCPC and USB-CEA Carkit Audio Uplink Electrical Characteristics Parameter Gain range Test Conditions Min (1) Absolute gain, 0 dBFs at 1.02 kHz (1) (2) (3) Speech delay Typ -1 60 USB-CEA default gain setting -1.5 1.5 MCPC default gain setting -1.5 1.5 Voice path Input common mode voltage (4) Phone microphone amplifier input impedance at 1 kHz Max 0.5 USB-CEA 1.3 USB-CEA 8 120 MCPC 5 100 Peak-to-peak single-ended input voltage (0 dBFs) Default setting Total harmonic distortion (sine wave at 1 kHz), default gain setting At -1 dBFs Unit dB dB ms 1.9 V k -74 1.414 VPP -60 dB At -6 dBFs At -10 dBFs At -20 dBFs At -60 dBFs THD + N (20 Hz to 20 kHz, A-weighted) At 0 dBFs Signal noise ratio (20 Hz to 20 kHz, A-weighted) Idle channel noise (20 Hz to 20 kHz, A-weighted), default gain setting Output PSRR (20 Hz to 20 kHz, A-weighted) (1) (2) (3) (4) 60 dB At 0 dBFs 60 dB USB-CEA -77 MCPC -80 USB-CEA 50 MCPC 35 -77 dBFs dB Gain range is defined by: MCPC/CEA amplifier = 0.56 dB/-1.02 dB; Preamplifier = 0 to 30 dB; Filter = 0 to 31 dB (1-dB steps). The CEA default gain setting assumes 0 dB on the preamplifier, 1 dB on the digital filter, and the MCPC/CEA amplifier at -1.02 dB. The MCPC default gain setting assumes 0 dB on the preamplifier, 0 dB on the digital filter, and the MCPC/CEA amplifier at 0.56 dB. Full-scale input voltage is 1 V minimum. 6.2.9 Digital Audio Filter Module Figure 6-29 shows the digital audio filter uplink full path characteristics for the audio interface. PDM from digital microphone interface A/D output Error cancellation SINC filter differentiator 4th order SINC filter integrator 4th order 1st order highpass filter Low-pass filter Audio interface 032-042 Figure 6-29. Digital Audio Filter Uplink Path Characteristics The HPF can be bypassed. It is controlled by the MISC_SET_2 ATX_HPF_BYP bit, address 0x49. Table 6-23 lists the audio filter frequency responses relative to reference gain at 1 kHz. Table 6-23. Digital Audio Filter TX Electrical Characteristics Parameter Test Conditions Passband Passband gain In region 0.0005*FS to 0.42*FS (1) Stopband Stopband attenuation In region 0.6*FS to 1*FS (1) Group delay (1) 94 Min Typ Max Unit 0.0005 0.42 FS -0.25 0.25 dB 0.6 FS 60 dB 15.8/FS s FS is the sampling frequency (8, 11.025, 12, 16, 22.05, 24, 32, 44.1, or 48 kHz). Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 6.2.10 Digital Voice Filter Module Figure 6-30 shows the digital voice filter uplink full path characteristics of the voice interface. A/D output SINC filter integrator Error cancellation SINC filter differentiator Low-pass filter High-pass filter Voice interface 032-043 Figure 6-30. Digital Audio Filter Uplink Path Characteristics The global HPF or only the third-order HPF can be bypassed (when the third-order HPF is skipped, the first-order HPF remains active). It is controlled by the MISC_SET_2 VTX_3RD_HPF_BYP bit, address 0x49, the for the third-order HPF, and by the VTX_HPF_BYP bit for the global HPF. 6.2.10.1 Voice Uplink Filter (Sampling Frequency at 8 kHz) Figure 6-31 and Figure 6-32 show the voice uplink frequency response with a sampling frequency of 8 kHz. Voice Uplink (TX) Filter 8 kHz 2 Gain (dB) 0 1st order HPF Specification 3rd order HPF -2 -4 -6 -8 -10 0 100 200 300 400 500 600 Frequency (Hz) 032-044 Figure 6-31. Voice Uplink Frequency Response With FS = 8 kHz (Frequency Range 0 to 600 Hz) Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 95 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Voice Uplink (TX) Filter 8 kHz 2 Gain (dB) 0 -2 1st order HPF Specification 3rd order HPF -4 -6 -8 -10 3000 3100 3200 3300 3400 3500 3600 Frequency (Hz) 032-045 Figure 6-32. Voice Uplink Frequency Response With FS = 8 kHz (Frequency Range 3000 to 3600 Hz) Table 6-24 lists the voice filter frequency responses relative to reference gain at 1 kHz with FS = 8 kHz. Table 6-24. Digital Voice Filter TX Electrical Characteristics With FS = 8 kHz Parameter Test Conditions Frequency response relative to reference gain at 1 kHz Min Typ 100 Hz 200 Hz -8 Max Unit -20 dB -0.5 300 to 3300 Hz -0.5 0 0.5 3400 Hz -1.5 0 0.1 4000 Hz -17 4600 Hz -40 >6000 Hz -45 Pole when HPF is disabled (first-order HPF) 24 Hz Group delay 0.5 ms 96 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 6.2.10.2 Voice Uplink Filter (Sampling Frequency at 16 kHz) Figure 6-33 and Figure 6-34 show the voice uplink frequency response with a sampling frequency of 16 kHz. Voice Uplink (TX) Filter 16 kHz 2 0 Gain (dB) -2 1st order HPF Specification -4 -6 -8 -10 0 100 200 300 400 Frequency (Hz) 500 600 032-046 Figure 6-33. Voice Uplink Frequency Response With FS = 16 kHz (Frequency Range 0 to 600 Hz) Voice Uplink (TX) Filter 16 kHz 2 Gain (dB) 0 -2 1st order HPF Specification -4 -6 -8 -10 6200 6400 6600 6800 7000 Frequency (Hz) 032-047 Figure 6-34. Voice Uplink Frequency Response With FS = 16 kHz (Frequency Range 6200 to 7000 Hz) Table 6-25 lists the voice filter frequency responses relative to reference gain at 1 kHz with FS = 16 kHz. Table 6-25. Digital Voice Filter TX Electrical Characteristics With FS = 16 kHz Parameter Test Conditions Frequency response relative to reference gain at 1 kHz (first-order HPF) Max Unit 300 to 6600 Hz -0.5 0.5 dB 6800 Hz -1.5 0.1 8000 Hz -0.5 0 -17 9200 Hz -1.5 0 -40 12000 Hz Min Typ -45 Audio/Voice Module Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 97 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 6-25. Digital Voice Filter TX Electrical Characteristics With FS = 16 kHz (continued) Parameter Test Conditions Pole when third-order HPF is disabled (first-order HPF) 98 Audio/Voice Module Min Typ 47 Max Unit Hz Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 7 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 USB HS 2.0 OTG Transceiver The TPS65950 includes a USB OTG transceiver with CEA and MCPC carkit interfaces that support USB 480 Mbps HS, 12 Mbps full-speed (FS), and USB 1.5 Mbps low-speed (LS) through a 4-pin ULPI. The carkit block ensures the interface between the phone and a carkit device. The TPS65950 USB supports CEA and MCPC carkit standards. Figure 7-1 is a block diagram of the USB 2.0 physical layer (PHY). USB OTG device Audio accessory Hands-free headset UART control OMAP (LINK) PC Device USB PHY ULPI Phone connector (USB or MCPC) Carkit ADC inputs (optional) Charger 032-048 Figure 7-1. USB 2.0 PHY Overview 7.1 USB Features The device has a USB OTG carkit transceiver that allows system implementation that complies with the following specifications: * Universal Serial Bus 2.0 Specification * On-The-Go Supplement to the USB 2.0 Specification * CEA-2011: OTG Transceiver Interface Specification * CEA-936A: Mini-USB Analog Carkit Interface Specification * MCPC ME-UART GL-006 Specification * UTMI+ Low Pin Interface Specification The features of the individual specifications are: * Universal Serial Bus 2.0 Specification (hereafter referred to as the USB 2.0 specification): - 5-V-tolerant data line at HS/FS, FS-only, and LS-only transmission rates - 7-V-tolerant video bus (VBUS) line - Integrated data line serial termination resistors (factory-trimmed) - Integrated data line pullup and pulldown resistors - On-chip 480-MHz PLL from the internal system clock (19.2, 26, and 38.4 MHz) - Synchronization (SYNC)/end-of-period (EOP) generation and checking - Data and clock recovery from the USB stream - Bit-stuffing/unstuffing and error detection - Resume signaling, wakeup, and suspend detection - USB 2.0 test modes * On-The-Go Supplement to the USB 2.0 Specification (hereafter referred to as the OTG supplement to the USB 2.0 specification): - 3-pin LS/FS serial mode (DAT_SE0) - 4-pin LS/FS serial mode (VP_VM) * CEA-2011: OTG Transceiver Interface Specification: USB HS 2.0 OTG Transceiver Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 99 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 * * * 7.2 www.ti.com - 3-pin LS/FS serial mode (DAT_SE0) - 4-pin LS/FS serial mode (VP_VM) CEA-936A: Mini-USB Analog Carkit Interface Specification (hereafter referred to as the CEA-936A specification): - 5-pin CEA mini-USB analog carkit interface - UART signaling - Audio (mono/stereo) signaling - UART transactions during audio signaling - Basic and smart 4-wire/5-wire carkit, chargers, and accessories - ID CEA resistor comparators MCPC ME-UART GL-006 Specification (hereafter referred to as the MCPC ME-UART specification): - 11-pin MCPC Association of Radio Industries and Businesses (ARIB)-USBi (USB interface standard) analog carkit interface - UART signaling UTMI+ Low Pin Interface Specification (hereafter referred to as the ULPI specification): - 12-pin ULPI with 8-pin parallel data for USB signaling and register access - 60-MHz clock generation - Register mapping USB Transceiver Figure 7-2 is an application schematic of the USB system. 100 USB HS 2.0 OTG Transceiver Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 VBAT C VBUS.FC C VINTUSB.1P8 C VBUS.IN C VBAT.USB .* C VINTUSB.1P5 VINTUSB.1P8 VUSB.3P1 VINTUSB.1P5 CP.CAPN CP.CAPP CP.IN CP.GND C VUSB.3P1 CP.OUT UCLK USB CP STP Device ID DIR DP/UART3.RXD NXT DATA0/RX DATA1/TX Host processor DM/UART3.TXD USB 2.0 HS-OTG transceiver with CEA/MCPC carkit interface VBUS USBCEA carkit connector GND DATA2/RTSI DATA3/CTSO C VBUS1 DATA4 C VBUS2 DATA5 DATA6 RTSO MANU GND DP-RXD DM-TXD VBUS PWR_Supply RTSO Reserved Man_Specific CTSI D RTSO1 D RTSO2 GND D CTSI1 D CTSI2 R RTSO C RXAF RF_TRX C TXAF CTSI RXAF TXAF DATA7 MCPC connector 032-049 Figure 7-2. USB System Application Schematic NOTE For the component values, see Table 15-1. USB HS 2.0 OTG Transceiver Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 101 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 7.2.1 www.ti.com MCPC Carkit Port Timing MCPC UART specification: * 11-pin MCPC ARIB-USBI analog carkit interface * Integrated 50 RRTSO resistor * UART signaling (from 600 bps to 460.8 kbps) * Audio (mono/stereo) signaling: In this mode, the ULPI data bus is redefined as a 4-pin UART interface, which exchanges data through a direct access to the FS/LS analog transmitter and receiver. The UART data are sent and received on the USB D+/D- pads, and the handshake signals are sent and received on the RTSO/CTSI pads. Figure 7-3 shows the MCPC UART and handshake mode data flow. ULPI MCPC connector Device DATA0: UART_TX DATA1: UART_RX DATA2: UART_RTS DATA3: UART_CTS DP/RXD/MIC_R DM/TXD/SPKR_L RTSO CTSI 032-050 Figure 7-3. MCPC UART and Handshake Mode Data Flow Table 7-1 lists the McPC UART and handshake mode timings. Table 7-1. MCPC UART and Handshake Mode Timings Notation Parameter Min Max Unit CK5 td(UART_TXH-DM) Delay time, UART_TX rising edge to DM transition 10 37 ns CK6 td(UART_TXL-DM) Delay time, UART_TX falling edge to DM transition 2.5 13 ns CK7 td(DPH-UART_RX) Delay time, DP rising edge to UART_RX transition 17 40 ns CK8 td(DPL-UART_RX) Delay time, DP falling edge to UART_RX transition 26 50 ns CK9 td(UART_CTSH-RTSO) Delay time, UART_CTS rising edge to RTSO transition 1 18 ns CK10 td(UART_CTSL-RTSO) Delay time, UART_CTS falling edge to RTSO transition 1 18 ns CK11 td(CTSIH-UART_RTS) Delay time, CTSI rising edge to UART_RTS transition 3 16 ns CK12 td(CTSIL-UART_RTS) Delay time, CTSI falling edge to UART_RTS transition 3 16 ns 102 USB HS 2.0 OTG Transceiver Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Figure 7-4 shows the MCPC UART and handshake mode timings. UART_TX CK5 CK6 CK7 CK8 CK9 CK10 CK11 CK12 DM DP UART_RX UART_CTS RTSO CTSI UART_RTS 032-051 Figure 7-4. MCPC UART and Handshake Mode Timings 7.2.2 USB-CEA Carkit Port Timing CEA carkit mode lets the link communicate through the USB PHY to a remote carkit in CEA audio + data during audio (DDA) mode as defined in the CEA-936A specification. In this mode, the ULPI data bus is redefined as a 2-pin UART interface, which exchanges data through a direct access to the FS/LS analog transmitter and receiver. UART data are sent and received on the USB D+/D- pads. D+/D- are also used in this mode to carry audio I/O signals. Table 7-2 assumes testing over the recommended operating conditions (see the CEA-936A specification). Table 7-2. USB-CEA Carkit Interface Timing Parameters Parameter Min Max Unit tPH_DP_CON Phone D+ connect time 100 tCR_DP_CON Carkit D+ connect time 150 ms tPH_DM_CON Phone D- connect time tPH_CMD_DLY Phone command delay tPH_MONO_ACK Phone mono acknowledge tPH_DISC_DET Phone D+ disconnect time 150 tCR_DISC_DET Carkit D- disconnect detect 50 tPH_AUD_BIAS Phone audio bias tCR_AUD_DET Carkit audio detect 400 800 tCR_UART_DET Carkit UART detect (DDA enabled) 700 1200 ns tPH_STLO_DET Phone stereo D+ low detect 30 100 ms tPH_PLS_POS Phone D- interrupt pulse width 200 600 ns tCR_PLS_NEG Carkit D+ interrupt pulse width 200 600 ns tDAT_AUD_POL DDA polarity 20 60 ms tACC_COL_DET Accessory identification (ID) collision detect 2 3 ms 300 ms 10 ms 2 ms 10 ms 150 1 Submit Documentation Feedback Product Folder Link(s): TPS65950 ms ms USB HS 2.0 OTG Transceiver Copyright (c) 2008-2011, Texas Instruments Incorporated ms s 103 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 7-2. USB-CEA Carkit Interface Timing Parameters (continued) Parameter Min Max Unit 200 400 s 10 15 ms tACC_INT_PW Accessory ID interrupt pulse width tACC_INT_WAIT Accessory ID interrupt wait time tACC_CMD_WAIT Accessory ID command wait time 0 tPH_INT_PW Phone ID interrupt pulse width 4 8 ms tPH_INT_WAIT Phone ID interrupt wait time 4 8 ms tPH_CMD_WAIT Phone ID command wait time 0 ms tPH_UART_RPT Phone command repeat time 50 ms tCR_UART_RSP Carkit UART response tCR_INT_RPT Carkit interrupt repeat time fUART_DFLT Default UART signaling rate (typical rate) ms 30 ms 9600 bps 50 ms Figure 7-5 shows the USB-CEA carkit UART data flow. ULPI Device USB-CEA connector DATA0: UART_TX DP/RXD/MIC DATA1: UART_RX DM/TXD/SPKR 032-052 Figure 7-5. USB-CEA Carkit UART Data Flow Table 7-3 lists the USB-CEA carkit UART timing parameters. Table 7-3. USB-CEA Carkit UART Timing Parameters Min Max CK1 Notation td(UART_TXH-DM) Delay time, UART_TX rising edge to DM transition Parameter 4.0 11 ns CK2 td(UART_TXL-DM) Delay time, UART_TX falling edge to DM transition 4.0 11 ns At 38.4 MHz 205 234 At 19.2 MHz 310 364 At 38.4 MHz 205 234 At 19.2 MHz 310 364 CK3 td(DPH-UART_RX) Delay time, DP rising edge to UART_RX transition CK4 td(DPL-UART_RX) Delay time, DP falling edge to UART_RX transition Unit ns ns Figure 7-6 shows the USB-CEA carkit UART timings. UART_TX CK1 CK2 CK3 CK4 DM DP UART_RX 032-053 Figure 7-6. USB-CEA Carkit UART Timing Parameters 104 USB HS 2.0 OTG Transceiver Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 7.2.3 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 HS USB Port Timing The ULPI interface supports an 8-bit data bus and the internal clock mode. The 4-bit data bus and the external clock mode are not supported. The HS functional mode supports an operating rate of 480 Mbps. Table 7-4 and Table 7-5 assume testing over the recommended operating conditions (see Figure 7-7). HSU0 HSU1 HSU1 UCLK HSU5 HSU4 STP HSU2 HSU2 DIR_&_NXT HSU3 DATA[7:0] HSU6 HSU3 Data_OUT HSU7 Data_IN 032-054 Figure 7-7. HS USB Interface--Transmit and Receive Modes (ULPI 8-Bit) NOTE ULPI data [7:0] lines are set to 1 after USB PHY power up, and before the clock signal is stable. The input timing requirements are given by considering a rising or falling time of 1 ns. Table 7-4. HS USB Interface Timing Requirement Parameters Notation Parameter Min Max Unit HSU4 ts(STPV-CLKH) Setup time, STP valid before UCLK rising edge 6 ns HSU5 th(CLKH-STPIV) Hold time, STP valid after UCLK rising edge 0 ns HSU6 ts(DATAV-CLKH) Setup time, DATA[0:7] valid before UCLK rising edge 6 ns HSU7 th(CLKH-DATIV) Hold time, DATA[0:7] valid after UCLK rising edge 0 ns Table 7-5. HS USB Interface Switching Requirement Parameters (1) Min Typ Max Unit HSU0 Notation fp(CLK) UCLK clock frequency Parameter Steady state 58.42 60 61.67 MHz HSU1 tW(CLK) UCLK duty cycle Steady state 48.3% 50% 51.7% td(CLKH-DIR) Delay time, UCLK rising edge to DIR transition Steady state 0 9 td(CLKH-NXTV) Delay time, UCLK rising edge to NXT transition Steady state 0 9 td(CLKH-DATV) Delay time, UCLK rising edge to DATA[0:7] Steady state transition 0 9 HSU2 HSU3 (1) ns ns ns The capacitive load for output data and control load is 10 pF (rising and falling time is 2 ns). The capacitive load for the CLK port is 6 pF (rising and falling time is 1 ns). The HS USB interface has only one state: steady state. USB HS 2.0 OTG Transceiver Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 105 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 7.2.4 www.ti.com PHY Electrical Characteristics The PHY is the physical signaling layer of the USB 2.0. It contains the drivers and receivers required for physical data and protocol signaling on the DP and DM lines. The PHY interfaces to the USB controller through UTMI. There are two main classes of transmitters and receivers in the PHY: * FS and LS transceivers. These are the legacy USB1.x transceivers. * HS transceivers To bias the transistors and run the logic, the PHY also contains reference generation circuitry which consists of: * A digital phase-locked loop (DPLL) that does a frequency multiplication to achieve the 480-MHz low-jitter lock necessary for USB, and the clock required for the switched capacitor resistance block * A switched capacitor resistance block that replicates an external resistor on chip Built-in pullup and pulldown resistors are used as part of the protocol signaling. The PHY also contains circuitry that protects it from an accidental 5-V short on the DP and DM lines and from 8-kV IEC ESD strikes. 7.2.4.1 5-V Tolerance When the voltage on DP or DM exceeds 3.6 V, a stress condition is detected. In this case, the current is drawn from the DP/DM line, to prevent damage caused by the stress voltage. In this condition, the VRUSB_3V supply can be charged as high as 3.6 V. Table 7-6 lists the tolerances. Table 7-6. 5V-Tolerant Electrical Summary Parameter Comments Min Typ Max Unit Continuous short-circuit stress DCSTRESS 50% TX/50% RX/50% LS/50% FS/VBUS = 5.25 V 24 h Worst case overshoot and undershoot stress ACSTRESS tHI = 60 ns/tLO = 100 ns/tR = tF = 4 ns/ VHI = 4.6 V/VLO = -1.0 V/RSRC = 39/ 50% TX/50% RX/VBUS = 5.25 V 24 h Internal DP/DM stress voltage VDX_STRESS Force 5.25 V VBUS/DP/DM 4.3 V V3P1 stress voltage V3P1_STRES S Force 5.25 V VBUS/DP/DM/ID 3.6 V DP/DM input stress current IDX_STRESS Force 5.25 V VBUS/DP/DM ID input stress current IID_STRESS Force 5.25 V VBUS/DP/DM/ID 7.2.4.2 30 mA 25 A LS/FS Single-Ended Receivers In addition to the differential receiver, there is a single-ended receiver (SE-, SE+) for each of the two data lines D+/-. The main purpose of the single-ended receivers is to qualify the D+ and D- signals in the FS/LS modes of operation. Table 7-7 lists the parameters of the LS/FS single-ended receivers. Table 7-7. LS/FS Single-Ended Receivers Parameter Comments Min Typ Max -2 0 2 Unit USB Single-Ended Receivers Skew between VP and VM SKWVP_VM Single-ended hysteresis VSE_HYS High (driven) VIH Low VIL Switching threshold VTH 106 Driver outputs unloaded 0 2 0.8 USB HS 2.0 OTG Transceiver ns mV V 0.8 V 2 V Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 7-7. LS/FS Single-Ended Receivers (continued) Parameter Comments Min Typ Max Unit UART Receiver CEA VIH_SER DP_PULLDOWN asserted Serial interface input low VIL_SER DP_PULLDOWN asserted 2 Switching threshold VTH MCPC DP pullup RMCPCDP Internal pullup Open-drain input high level ZIH Internal MCPC DP pullup asserted Open-drain input low level ZIL External open-drain NMOS impedance to ground. With internal MCPC DP pullup asserted. Output high level VOH (*) At DATA1 pin Output low level VOL At DATA1 pin V 0.8 0.8 V 2 V 10k UART Receiver MCPC From DP.RXD 7.2.4.3 4.7k Open 100 VIO - 0.45 V 0.45 V LS/FS Differential Receiver A differential input receiver (RX) retrieves the LS/FS differential data signaling. The differential voltage on the line is converted to digital data by a differential comparator on DP/DM. This data is then sent to a clock and data recovery circuit that recovers the clock from the data. In an additional serial mode, the differential data is directly output on the RXRCV pin. Table 7-8 lists the parameters of the LS/FS differential receiver. Table 7-8. LS/FS Differential Receiver Parameter Comments Typ Max -16 0 16 ns 0 100 200 s 2.5 V SKWVP_VM Receiver power-up time TPWR_UP_RCV Differential common mode range VCM 0.8 Differential input sensitivity VDI 0.2 7.2.4.4 Driver outputs unloaded Min Skew between VP/VM Unit V LS/FS Differential Transmitter The USB transceiver (TX) uses a differential output driver to drive the USB data signal D+/- onto the USB cable. The driver outputs support 3-state operation to achieve bidirectional half-duplex transactions. Table 7-9 lists the parameters of the LS/FS differential transmitter. Table 7-9. LS/FS Differential Transmitter Parameter Comments B-device (dual-role) unconfigured average current IB_OTG_UNCFG B-device (secure remote password [SRP] capable, peripheral only) unconfigured average current IB_PO_UNCFG FS fall time/rise time tFf, tFr 10%-90% CL = 50 pF on DP and DM FS rise and fall time matching TFRFM 10%-90% CL = 50 pF on DP and DM FS width of SE0 interval during differential transition tFst Pulldowns R = 15 k on DP and DM Pullup R = 1.5 k at 3.6 V on DP only LS fall time/rise time tLF, tLR 10%-90% CL = [200-600] pF on DP and DM Pullup R = 1.5 k at 3.6 V for DM only LS rise and fall time matching TLRFM 10%-90% CL = [200-600] pF on DP and DM Pullup R = 1.5 k at 3.6 V for DM only Min Typ Max Unit 150 A 8 mA 4 20 ns 90% 110% 0 V = VBUS = 5.25 V, tAVG = 1 ms 14 ns 75 300 ns 80% 120% USB HS 2.0 OTG Transceiver Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 107 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 7-9. LS/FS Differential Transmitter (continued) Parameter Comments Min Max Unit 210 ns 200 s -2 2 ns -1 1 ns CL = [200-600] pF on DP and DM Pullup R = 1.5 k at 3.6 V for DM only -25 25 ns tUSDJ2 CL = [200-600] pF on DP and DM Pullup R = 1.5 k at 3.6 V for DM only -10 10 ns Output signal cross-over voltage Vcrs Pulldowns R = 15 k on DP and DM Pullup R = 1.5 k at 3.6 V on DM only 1.3 2 V High (driven) VOH Pulldowns R = 15 k on DP and DM 2.8 3.3 3.6 V Low VOL Pullups R = 1.5 k at 3.6 V on DP and DM 0 0.1 0.3 V Driver output resistance ZDRV/RS 28 36 44 LS width of SE0 interval during differential transition tLST Pulldowns R = 15 k on DP and DM Pullup R = 1.5 k at 3.6 V on DM only Driver power-up time TPWR_UP_TXD Pulldowns R = 15 k on DP and DM Pullup R = 1.5 k at 3.6 V on DM only FS source driver jitter to next transition tSDJ1 CL = 50 pF on DP and DM FS source driver jitter for paired transitions tSDJ2 CL = 50 pF on DP and DM LS upstream facing port source driver jitter (next transition) tUSDJ1 LS upstream facing port source driver jitter (next transition) 7.2.4.5 0 Typ 100 HS Differential Receiver The HS receiver consists of the following blocks: * A differential input comparator to receive the serial data * A squelch detector to qualify the received data * An oversampler-based clock data recovery scheme followed by a nonreturn to zero inverted (NRZI) decoder, bit unstuffing, and a serial-to-parallel converter to generate the UTMI DATAOUT Table 7-10 lists the parameters of the HS differential receiver. Table 7-10. HS Differential Receiver Parameter Comments Min Typ Max Unit Input Levels for HS HS squelch detection threshold VHSSQ (Differential signal amplitude) 100 125 150 mV HS disconnect detection threshold VHSDSC (Differential signal amplitude) 525 600 625 mV HS data signaling common mode voltage range VHSCM -50 200 500 mV HS differential input sensitivity VDIHS 100 mV (Differential signal amplitude) -100 Input Impedance for HS Internal specification for input capacitance CHSLOAD 11 pF Internal CHSLOAD DP/DM matching CHSLOADM 0.2 pF External Components With the Total Budget Combined (Without USB Cable Load) External capacitance on DP or DM 2 pF External series resistance on DP or DM 1 7.2.4.6 HS Differential Transmitter The HS transmitter is always operated on the UTMI parallel interface. The parallel data on the interface is serialized, bit-stuffed, NRZI-encoded, and transmitted as a dc output current on DP or DM, depending on the data. Each line has an effective 22.5- load to ground, which generates the voltage levels for signaling. A disconnect detector is also part of the HS transmitter. A disconnect on the far end of the cable causes the impedance seen by the transmitter to double, thereby doubling the differential amplitude seen on the DP/DM lines. 108 USB HS 2.0 OTG Transceiver Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 7-11 lists the parameters of the HS differential transmitter. Table 7-11. HS Differential Transmitter Parameter Comments Min Typ Max Unit Output Levels for HS HS TX idle level VHSOI Absolute voltage DP/DM - Both internal/external 45 -10 0 10 mV HS TX data signaling high VHSOH Absolute voltage DP/DM - Both internal/external 45 360 400 440 mV HS data signaling low VHSOL -10 0 10 mV Chirp J level VCHIRPJ Differential voltage 700 800 1100 mV Chirp K level VCHIRPK Differential voltage -900 -800 -500 mV HS TX disconnect threshold VDISCOUT Absolute voltage DP/DM--No external 45 700 mV 500 ps Driver Characteristics Rise time tHSR (10%-90%) Fall time tHSF (10%-90%) 500 Driver output resistance ZHSDRV Also serves as HS termination 40.5 7.2.4.7 ps 45 49.5 Typ Max Unit CEA/MCPC/UART Driver Table 7-12 lists the parameters of the CEA/MCPC/UART driver. Table 7-12. CEA/MCPC/UART Driver Parameter Comments Min UART Driver CEA Phone UART edge rates tPH_UART_EDGE DP_PULLDOWN asserted Serial interface output high VOH_SER ISOURCE = 4 mA Serial interface output low VOL_SER ISINK = -4 mA 1 s 2.4 3.3 3.6 V 0 0.1 0.4 V UART Driver MCPC to DM.TX. Input high level VIH (*) At DATA0 pin Input low level VIL At DATA0 pin VIO - 0.45 V MCPC DM external pullup RMCPCDM External pullup MCPC DM pullup supply MCPCVDDEXT External pullup supply Open-drain output high level ZOH Open-drain output low level VOL With open-drain NMOS to ground is ON and external pullup is asserted. Pulse match tolerance QPLS_MTCH ZCR_SPKR_IN = 60 k at f = 1 kHz Phone D- interrupt pulse width tPH_PLS_POS ZCR_SPKR_IN = 60 k at f = 1 kHz 200 600 ns Phone positive pulse voltage VPH_PLS_POS ZCR_SPKR_IN = 60 k at f = 1 kHz 2.8 3.6 V 0.45 V 4.7k 10k 1.8 3.3 V External pullup asserted HiZ HiZ means high impedance equivalent to open 0 0.6 V Carkit Pulse Driver 5% USB HS 2.0 OTG Transceiver Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 109 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 7.2.4.8 www.ti.com Pullup/Pulldown Resistors Table 7-13 lists the parameters of the pullup/pulldown resistors. Table 7-13. Pullup/Pulldown Resistors Parameter Comments Min Typ Max 0.9 1.1 1.575 1.425 2.2 3.09 Unit Pullup Resistors Bus pullup resistor on upstream port (idle bus) RPUI Bus idle Bus pullup resistor on upstream port (receiving) RPUA Bus driven/driver outputs unloaded High (floating) VIHZ Pullups/pulldowns on DP and DM lines Phone D+ pullup voltage VPH_DP_UP Driver outputs unloaded k 2.7 3.6 V 3 3.3 3.6 V 14.25 18 24.8 k 3.6 V 75 pF 0.342 V Pulldown Resistors Phone D+/- pulldown RPH_DP_DWN RPH_DM_DWN High (floating) VIHZ Upstream facing port CINUB OTG device leakage VOTG_DATA_LKG Input impedance exclusive of pullup/pulldown (1) ZINP Driver outputs unloaded Pullups/pulldowns on DP and DM lines 2.7 D+/- Data Line (1) 22 Driver outputs unloaded (waiver from usb.org standards committee) 80 120 k Waiver received from usb.org standards committee on ZINP 300kmin specification 7.2.4.9 PHY DPLL Electrical Characteristics USB DPLL supports input frequencies of 12, 13, 19.2, 24, and 26 MHz. The input frequency must be programmed through frequency select bits. USB DPLL provides a low jitter and gives eight equidistant phases of the 480-MHz clock for the USB receiver. Table 7-14 lists the electrical characteristics of the PHY DPLL. Table 7-14. PHY DPLL Electrical Characteristics Parameter Comments Min Typ Max Unit 12 13 Input clock 19.2 MHz 24 26 Digital supply VINTDIG 1.35 1.5 1.65 V Analog 1.5-V supply VRUSB_1V5 1.35 1.5 1.65 V Analog 1.8-V supply VRUSB_1V8 1.62 1.8 1.98 V Output frequency (eight phases) 480 MHz RMS period jitter (output) 10 ps Deterministic period jitter (output) 50 ps Frequency band: 1 to 10 Hz RMS jitter per phase noise frequency band (input) 110 310 Frequency band: 10 to 100 Hz 90 Frequency band: 100 to 1000 Hz 30 Frequency band: 1 to 10 kHz 10 Frequency band: 10 to 100 kHz 10 Frequency band: 0.1 to 0.5 MHz 290 Frequency band: 0.5 to 1 MHz 650 USB HS 2.0 OTG Transceiver ps Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 7-14. PHY DPLL Electrical Characteristics (continued) Parameter Comments Min Typ Max Unit 100 ps Frequency error (input) 150 ppm Frequency error (output) 500 ppm Phase-to-phase variation 35 ps Noise on digital 1.5-V supply 100 mV Noise on analog 1.5-V supply 50 mV Noise on analog 1.8-V supply 36 mV Deterministic period jitter (input) 7.2.4.10 PHY Power Consumption Table 7-15 lists, by mode, the power consumption values of the modules. Table 7-15. PHY Power Consumption Supply Min Typ Max Unit HS Mode VUSB.3P1 8.5 mA VINTUSB1P8.OUT 25 mA VINTUSB1P5.OUT 24 mA VINTDIG.OUT 0.3 mA VUSB.3P1 13 mA VINTUSB1P8.OUT 5.4 mA VINTUSB1P5.OUT 17.5 mA 0.3 mA FS Mode VINTDIG.OUT LS Mode VUSB.3P1 12.5 mA VINTUSB1P8.OUT 5.4 mA VINTUSB1P5.OUT 17.5 mA 0.3 mA VUSB.3P1 0 mA VINTUSB1P8.OUT 0 mA VINTUSB1P5.OUT 2 A VINTDIG.OUT 0 mA VUSB.3P1 0 mA VINTUSB1P8.OUT 0 mA VINTUSB1P5.OUT 2 A VINTDIG.OUT 0 mA VINTDIG.OUT Low-Power/Suspend Mode Power-Down Mode 7.2.5 OTG Electrical Characteristics The OTG block integrates three main functions: * USB plug detection function on VBUS and ID * ID resistor detection * VBUS level detection USB HS 2.0 OTG Transceiver Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 111 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 7.2.5.1 www.ti.com OTG VBUS Electrical Table 7-16 lists the OTG VBUS electrical parameters. Table 7-16. OTG VBUS Electrical Parameter Comments Min Typ Max Unit 15 s 0.5 0.6 0.7 V VBUS Wake-Up Comparator VBUS wake-up delay DELVBUS_WK_UP VBUS wake-up threshold VVBUS_WK_UP VBUS Comparators A-device session valid VA_SESS_VLD 0.8 1.1 1.4 V A-device VBUS valid VA_VBUS_VLD 4.4 4.5 4.6 V B-device session end VB_SESS_END 0.2 0.5 0.8 V B-device session valid VB_SESS_VLD 2.1 2.4 2.7 V 100 k VBUS Line A-device VBUS input impedance to ground RA_BUS_IN SRP (VBUS pulsing) capable A-device not driving VBUS B-device VBUS SRP pulldown RB_SRP_DWN 5.25 V/8 mA, pullup voltage = 3 V 0.656 10 B-device VBUS SRP pullup RB_SRP_UP (5.25 V - 3 V)/8 mA, pullup voltage =3V 0.281 1 B-device VBUS SRP rise time maximum for OTG-A communication tRise_SRP_UP_Max 0 to 2.1 V with < 13 F load B-device VBUS SRP rise time minimum for standard host connection tRise_SRP_UP_Min 0.8 to 2.0 V with > 97 F load VBUS line maximum voltage 7.2.5.2 k 2 k 36 ms 60 ms If VBUS_CHRG bit is low* 7 V OTG ID Electrical Table 7-17 lists the OTG ID electrical parameters. Table 7-17. OTG ID Electrical Parameter Comments Min Typ Max Unit ID Wake-Up Comparator ID wake-up comparator RID_WK_UP Wake up when ID shorted to ground through a resistor lower than 445 k (1%) 445 k ID Comparators--ID External Resistor Specifications ID ground comparator RID_GND ID_GND interrupt when ID shorted to ground through a resistor lower than 10 0 5 10 ID 100k comparators RID_100K ID_100K interrupt when 102 k (1%) resistor plugged in 101 102 103 k ID 200k comparators RID_200K ID_200K interrupt when 200 k (1%) resistor plugged in 198 200 202 k ID 440k comparators RID_440K ID_440K interrupt when 440 k (1%) resistor plugged in 435 440 445 k ID float comparator RID_FLOAT ID_FLOAT interrupt when ID shorted to ground through a resistor higher than 560 k Phone ID pullup to VPH_ID_UP RPH_ID_UP ID unloaded (VRUSB) 70 Phone ID pullup voltage VPH_ID_UP Connected to VRUSB 2.5 1400 k ID Line ID line maximum voltage 112 USB HS 2.0 OTG Transceiver 200 286 k 3.2 V 5.25 V Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 USB HS 2.0 OTG Transceiver Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 113 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 8 Battery Interface 8.1 General Description 8.1.1 www.ti.com Battery Charger Interface Overview The TPS65950 has a BCI for complete battery management. The main function of the BCI is to control the charging of either 1-cell Li-ion or Li-ion polymer batteries, or 1-cell Li-ion batteries with cobalt-nickel-manganese anodes. It supports regulated ac chargers of 7-V absolute maximum and can charge with USB host devices, MCPC devices, USB chargers, or carkits of 7-V absolute maximum. The BCI can perform software-controlled linear charging with the sources mentioned, software-controlled pulsed charging with current-limited ac chargers, and automatic linear charging with ac chargers, USB chargers, and carkits. The battery is monitored using the 10-bit ADC from the MADC to measure battery voltage, battery temperature, battery type, battery charge current, USB device input voltage, and ac charger input voltage. The magnitude of the charging current and the charging voltage is set by 10 bits of a programming register converted by a 10-bit DAC, whose output sets the reference input of the charging current and charging voltage control loop. The BCI also performs monitoring functions: * ac charger detection * VBUS detection * Battery detection * ac charger overvoltage detection * VBUS overvoltage detection * Battery overvoltage detection * Battery voltage level detection * Battery charge current level detection * Battery temperature out-of-range detection * Battery end-of-charge detection * Battery overcurrent detection * Watchdog 8.1.2 Battery Backup Overview The TPS65950 implements a backup mode, in which the backup battery keeps the RTC running. A rechargeable backup battery can be recharged from the main battery. When the main battery is below 2.7 V or is removed, the backup battery powers the backup if the backup battery voltage is greater than 1.8 V. The backup domain powers up the following: * Internal 32.768-kHz oscillator * RTC * Hash table (20 registers of 8 bits each) * Eight GP storage registers 8.2 8.2.1 Typical Application Schematics Functional Configurations The BCI can be used in different configurations (see Figure 8-1). Each configuration requires a dedicated typical application schematic: * ac charge supported (see Figure 8-1A, Figure 8-1B, and Figure 8-1D) * USB charge supported (see Figure 8-1A and Figure 8-1C) 114 Battery Interface Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com ac constant voltage mode supported (see Figure 8-1A and Figure 8-1B) ac charger with current nonlimited (see Figure 8-1D) ICTLAC1 ICTLUSB 1 ICTLUSB2 ICTLAC2 ICTLUSB 2 PCHGUSB PCHGAC VBUS VAC VBUS VAC ICTLUSB2 TAC CPRECH CCOMPUSB RSCOMPUSB CPRECH CCOMPAC RSCOMPAC RLIMITUSB Rs VCCs RLIMITUSB PCHGUSB ICTLAC 2 RLIMITAC PCHGAC VCCS VCCS VBATS VPRECH ICTLUSB2 RLIMITAC PCHGAC RLIMITAC PCHGAC PCHGUSB ICTLAC 1 VPRECH ICTLAC2 VPRECH ICTLUSB 1 VPRECH CPRECH TUSB TAC ICTLAC 1 CCOMPUSB RSCOMPUSB VAC ICTLUSB1 ICTLAC2 PCHGUSB VBUS ICTLAC1 VCCS VBATS Main charge Rs precharge and VCCs power paths VCCs Power Rs Rs VBATS VCCS VBATS Power Main charge precharge and VCCs power paths VCCs Power Main charge precharge and VCCs power paths VBAT VCCs Power Main charge precharge and VCCs power paths VBAT VBAT Battery pack Battery pack Battery pack USB driver Charger device ICTLUSB1 CPRECH VAC Charger device TUSB VBUS USB driver USB driver Charger device TAC USB driver Charger device CCOMPUSB RSCOMPUSB * * SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 VBAT Thermistor ID resistor ADIN 0 GND (B) CCV ADIN 1 Thermistor ADIN 0 GND (A) GND ADIN 1 ID resistor ID resistor ADIN 0 Thermistor ADIN 0 Thermistor ADIN 1 ID resistor CCV ADIN 1 CCV CCV Battery pack GND (C) (D) 032-055 A. B. C. D. Schematic that supports ac charge, ac constant voltage mode, and USB charge. With this ac compensation schematic, constant voltage mode is possible, but only current limited chargers are supported. Schematic that supports only ac charge and ac constant voltage mode. With this ac compensation schematic, constant voltage mode is possible, but only current limited chargers are supported. Schematic that supports only USB charge. Schematic that supports only ac charge. With this ac compensation schematic, constant voltage mode is not possible, but current nonlimited chargers are supported. Figure 8-1. Typical Application Schematics NOTE For the component values, see Table 15-1. 8.2.2 In-Rush Current Limitation Schematic With the typical application schematic supporting constant voltage mode (Figure 8-1 A and B), battery in-rush current is limited by the charging device. The application schematic can be enhanced to support in-rush current at the charging device plug to maximum 850 mA as detailed by Figure 8-2. T3, R3, and C3 are connected between VAC and ICTLAC1 and intentionally bring in-rush cucation. The described enhancement is not required for Figure 8-1 D, where constant voltage mode is not supported. Figure 8-2 shows a typical application schematic with in-rush current limitation. Battery Interface Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 115 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Charger device VAC R3 T3 C3 ICTLAC1 TAC CCOMPAC ICTLAC2 RSCOMPAC RLIMITAC VCCS Rs To battery pack 032-056 Figure 8-2. Typical Application Schematic (In-Rush Current Limitation) 8.2.3 Configuration With BCI Not Used Figure 8-3 shows how to connect the BCI when it is not in use. The SUSPENDM bit must be set to disable the BCI internally. 116 Battery Interface Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 USB driver Device VBUS I = 52 VAC A maximum inside the BCI ICTLAC1 OPEN ICTLUSB1 OPEN ICTLAC2 OPEN ICTLUSB2 OPEN VPRECH CPRECH PCHGAC PCHGUSB VCCS VBATS BCIAUTO VBAT POWER Battery pack Provided by external charger device ADIN0 Th er m i s t o r ADCIN1 ID r es is t o r ADIN2 GND 032-057 Figure 8-3. Typical Application Schematic (BCI Not Used) Battery Interface Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 117 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 8.3 www.ti.com Electrical Characteristics This section describes the electrical characteristics of the BCI in the TPS65950. 8.3.1 Main Charge Table 8-1 lists the electrical characteristics of the main charge. Table 8-1. Main Charge Electrical Characteristics VBAT = 3.6 V, RS = 0.22 , unless otherwise specified Parameter VAC input voltage range Test Conditions (1) VBUS input voltage range (external) Min Typ Max dc voltage 4.8 5.4 7 V dc voltage 4.4 5 7 V 1.7 A Charge current range VAC accessory supply mode consumption VBAT = 3.6 V, consumption on VBAT when ACCSUPEN = 1 and ACPATHEN = 1 connected to VBAT, current limitation enabled 0.75 1 VBAT = 3.6 V, consumption on VBAT when ACCSUPEN = 1 and ACPATHEN = 1 connected to VBAT, current limitation disabled 0.525 0.7 VBUS accessory supply mode VBAT = 3.6 V, consumption on VBAT when ACCSUPEN consumption = 1 and USBPATHEN = 1 connected to VBAT, current limitation enabled 0.64 0.85 VBAT = 3.6 V, consumption on VBAT when ACCSUPEN = 1 and USBPATHEN = 1 connected to VBAT, current limitation disabled 0.415 0.55 ICTLAC1 output voltage swing IICTLAC1 = -10 A, ACPATHEN = 1, PWMEN = 1, (PWM charge) PWMDTYCY = 0x000 VAC-0.3 IICTLUSB1 = -10 A, USBPATHEN = 1, LINCHEN = 1, MESBAT = 1, CHGVREG = 0x000 VAC-0.3 V 0.35 VBUS-0.3 V IICTLUSB1 = 10 A, USBPATHEN = 1, LINCHEN = 1, MESBAT = 1, CHGVREG = 0x3FF ICTLAC2 output voltage swing IICTLAC2 = -10 A, ACPATHEN = 1, LINCHEN = 1, (linear charge) ACPATHEN = 0 0.35 VCCS-0.3 V IICTLAC2 = 10 A, ACPATHEN = 1, LINCHEN = 1, ACPATHEN = 1 ICTLUSB2 output voltage swing (linear charge) IICTLUSB2 = -10 A, USBPATHEN = 1, LINCHEN = 1, USBPATHEN = 0 0.35 VCCS-0.3 V IICTLUSB2 = 10 A, USBPATHEN = 1, LINCHEN = 1, USBPATHEN = 1 PWM mode output current PWM = 1 (ICTLAC1 = 0), VAC = 6.8 V PWM = 0 (ICTLAC1 = VAC), VAC = 6.8 V (1) 118 mA 0.35 IICTLAC1 = 10 A, ACPATHEN = 1, LINCHEN = 1, MESBAT = 1, CHGVREG = 0x3FF ICTLUSB1 output voltage swing (linear charge) mA V IICTLAC1 = 10 A, ACPATHEN = 1, PWMEN = 1, PWMDTYCY = 0x3FF ICTLAC1 output voltage swing IICTLAC1 = -10 A, ACPATHEN = 1, LINCHEN = 1, (linear charge) MESBAT = 1, CHGVREG = 0x000 Unit 0.35 5.0 mA -2.0 The maximum voltage value of the charging device is 7 V (process limitation). The minimum voltage value of the charging device is: VBATMAX + 2 PMOS drop + 0.22 resistor drop (where VBATMAX is the maximum voltage value of the battery; that is, 4.2 V for Li-ion battery) User must consider maximum dissipation while using maximum ac/USB voltage (7 V) or maximum current load (1.7 A). Battery Interface Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 8-1. Main Charge Electrical Characteristics VBAT = 3.6 V, RS = 0.22 , unless otherwise specified (continued) Parameter Max Unit CHGIREG = (value relative to ICHG = 0.6 A), VAC = 5.4 V, C = 100 nF connected to ICTLAC1, VBAT threshold = 4.55 V, measure charge current from removal to 10% Miller compensation 150 s CHGIREG = (value relative to ICHG = 0.6 A), VAC = 5.4 V, C = 100 nF connected to ICTLAC1, VBAT threshold = 4.55 V, measure charge current from removal to 10% Regular compensation 150 USB main charge battery removal switch-off time CHGIREG = (value relative to ICHG = 0.6 A), VBUS = 5.0 V, C = 100 nF connected to ICTLUSB1, VBAT threshold = 4.55 V, measure charge current from removal to 10% 150 s VAC-to-MADC input attenuation VAC from 4.8 V to 6.8 V (maximum MADC input voltage = 1.224 V) VBAT-to-MADC input attenuation VBAT from 3.0 V to 4.5 V (maximum MADC input voltage = 1.35 V) Current-to-voltage conversion slope (2) ac main charge battery removal switch-off time Current-to-voltage conversion positive offset Current-to-voltage conversion negative offset Charge voltage and charge current DAC Test Conditions Typ 0.12 0.15 0.18 V/V 0.2 0.25 0.3 V/V (VCCS-VBATS) rising from 0 V to 0.17 V: CGAIN = 0 equivalent to 0-775 mA range 0.704 0.88 1.056 mV/m A (VCCS-VBATS) rising from 0 V to 0.33 V: CGAIN = 1 equivalent to 0-1500 mA range 0.352 0.44 0.528 OFFSEN = 1, OFFSN[1:0] = 00, CGAIN = 0, OFFSIGN = 0 18.7 OFFSEN = 1, OFFSN[1:0] = 01, CGAIN = 0, OFFSIGN = 0 38.8 OFFSEN = 1, OFFSN[1:0] = 10, CGAIN = 0, OFFSIGN = 0 60.1 OFFSEN = 1, OFFSN[1:0] = 11, CGAIN = 0, OFFSIGN = 0 82.6 OFFSEN = 1, OFFSN[1:0] = 00, CGAIN = 0, OFFSIGN = 1 -18.2 OFFSEN = 1, OFFSN[1:0] = 01, CGAIN = 0, OFFSIGN = 1 -35.6 OFFSEN = 1, OFFSN[1:0] = 10, CGAIN = 0, OFFSIGN = 1 -52.2 OFFSEN = 1, OFFSN[1:0] = 11, CGAIN = 0, OFFSIGN = 1 -67.6 Linear range mV mV 1FF 3BA hex Differential nonlinearity -2 2 LSB Integrated nonlinearity -2 2 LSB -25 25 mV Offset ADIN0 dc current source ADIN0 = 1 V ADCIN1 dc current source ADCIN1 = 1 V, ITHSENS[2:0] = 000 (maximum MADC input voltage = 0.875 V), After TRIM done by ISRCTRIM[3:0], at ambient temperature (2) Min 7 10 13 A 9.875 10 10.125 A MADC output code = (VCCS - VBATS) x 4 with CGAIN = 0 MADC output code = (VCCS - VBATS) x 2 with CGAIN = 1 Battery Interface Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 119 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 8-1. Main Charge Electrical Characteristics VBAT = 3.6 V, RS = 0.22 , unless otherwise specified (continued) Parameter ADCIN1 dc current source for temperature measurement Constant current loop accuracy Min Typ Max Unit ADCIN1 = 1 V, ITHSENS[2:0] = 000 (maximum MADC input voltage = 0.875 V), after TRIM done by ISRCTRIM[3:0] Test Conditions 9.5 10 10.5 A ITHSENS[2:0] = 001 14 20 26 ITHSENS[2:0] = 010 21 30 39 ITHSENS[2:0] = 011 28 40 52 ITHSENS[2:0] = 100 35 50 65 ITHSENS[2:0] = 101 42 60 78 ITHSENS[2:0] = 110 49 70 91 ITHSENS[2:0] = 111 56 80 104 After trimming (1.10%), VAC = 5.4 V or VBUS = 5.0 V, VBAT = 3.6 V, CHGIREG = (value relative to ICHG = 0.6 A), VCCS-VBATS rising voltage, monitoring ICTLAC1 or ICTLUSB1, CGAIN = 1, overtemperature (ambient 0C to 50C) (including the bandgap accuracy overtemperature 0.5% and the Rsense resistor accuracy 1%) -11% 11% After trimming (0.55%), VAC = 5.4 V or VBUS = 5.0 V, VBAT = 3.6 V, CHGIREG = (value relative to ICHG = 0.6 A), VCCS-VBATS rising voltage, monitoring ICTLAC1 or ICTLUSB1, CGAIN = 0, overtemperature (ambient 0C to 50C) (including the bandgap accuracy overtemperature 0.5% and the Rsense resistor accuracy 1%) -3.15% 3.15% Constant current loop offset At error amplifier input, before loop trim. Including DAC offset, I-to-V offset after I-to-V trim, error amplifier offset -46.8 46.8 Constant voltage loop accuracy After trimming (0.14%), VAC = 5.4 V or VBUS = 5.0 V, at room temperature, CHGVREG = (value relative to VBAT = 4.37 V), VBAT rising voltage, monitoring ICTLAC1 or ICTLUSB1 -0.28% 0.28% After trimming (0.14%), VAC = 5.4 V or VBUS = 5.0 V overtemperature (ambient 0C to 50C), CHGVREG = (value relative to VBAT = 4.37 V), VBAT rising voltage, monitoring ICTLAC1 or ICTLUSB1 (including the bandgap accuracy overtemperature 0.5%) -0.82% 0.82% Charger presence detect threshold mV VBAT = 3.6 V, rising edge VBAT+0.3 VBAT+0.4 VBAT+0.6 VBAT = 3.6 V, falling edge VBAT VBAT+0.1 VBAT+0.3 Battery threshold when default VAC = 5.4 V or VBUS = 5.0 V, VBATOVEN = 1, value (3) VBATOVTH(3:0) = default, MESBAT = 1, VBAT rising voltage, monitoring VBATOV status signal 4.45 4.55 4.65 V ac charger overvoltage threshold when default value (3) VBAT = 3.6 V, VACCHGOVEN = 1, VACCHGOVTH(3:0) = default, VAC rising voltage, monitoring VACCHGOV status signal 6.24 6.5 7 V VBUS overvoltage threshold when default value (3) VBAT = 3.6 V, VBUSOVEN = 1, VBUSOVTH(3:0) = default, VBUS rising voltage, monitoring VBUSOV status signal 5.28 5.5 5.9 V Main charge main battery presence impedance detection threshold Measured through ADCIN1 rising voltage and sourced current, monitoring BATSTS value 67.5 75 82.5 k Main charge main battery presence voltage detection threshold Force ADCIN1 voltage, monitor BATSTS value Temperature detection accuracy For low temperature (2C/3C) For high temperature (43C/50C) Battery voltage accuracy Tested for VBAT = 2.9, 3.6, and 4.2 V Current charge accuracy Tested for ICHG = 600 mA (3) 120 750 -3 -5 V mV 3 5 C VBAT-0.1 VBAT VBAT+0.1 V ICHG-0.04 ICHG ICHG+0.04 A Can be changed by programming the associated threshold register Battery Interface Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 8-1. Main Charge Electrical Characteristics VBAT = 3.6 V, RS = 0.22 , unless otherwise specified (continued) Parameter Battery Rs 8.3.2 Test Conditions Min Typ ESR (including FUSE) Max Unit 0.5 Precharge During slow precharge and fast precharge, a precharge voltage loop is always enabled and limits the battery voltage charge to 3.6 V typical. To use the constant voltage loop, a battery voltage prescaler is also always enabled. The voltage loop is nonlinear. A fast comparator switches off the external power portable media operating system (PMOS) when VBAT is higher than 3.6 V and switches on the PMOS when VBAT is lower than 3.6 V. When the USB charger is used, fast precharge is not available (to comply with USB standards). In precharge mode, the threshold of the ac charger overvoltage detection is forced to 6.8 V. Table 8-2 lists the precharge electrical characteristics. Table 8-2. Precharge Electrical Characteristics RS = 0.22 , unless otherwise specified Parameter ICTLAC1 output voltage swing (precharge) Test Conditions IICTLAC1 = -10 A, VBAT = 1.5 V, VCCS = VBAT+200 mV, VAC = 5.4 V, SYSACTIV = 0 Min Typ IICTLUSB1 = -10 A, VBAT = 1.5 V, VCCS = VBAT+200 mV, VAC = 0.0 V, VBUS = 5 V, SYSACTIV = 0 0.35 VAC-0.3 V IICTLUSB1 = 10 A, VBAT = 1.5 V, VCCS = VBAT, VAC = 0.0 V, VBUS = 5 V, SYSACTIV = 0 ICTLAC2 output voltage swing (precharge) IICTLAC2 = -10 A, VBAT = 1.5 V, VCCS = VBAT+200 mV, VAC = 5.4 V, SYSACTIV = 0 0.35 VCCS-0.3 V IICTLAC2 = 10 A, VBAT = 1.5 V, VCCS = VBAT, VAC = 5.4 V, SYSACTIV = 0 ICTLUSB2 output voltage swing (precharge) IICTLUSB2 = -10 A, VBAT = 1.5 V, VCCS = VBAT+200 mV, VAC = 0.0 V, VBUS = 5 V, SYSACTIV = 0 Unit V IICTLAC1 = 10 A, VBAT = 1.5 V, VCCS = VBAT, VAC = 5.4 V, SYSACTIV = 0 ICTLUSB1 output voltage swing (precharge) Max VAC-0.3 0.35 VCCS-0.3 V IICTLUSB2 = 10 A, VBAT = 1.5 V, VCCS = VBAT, VAC = 0.0 V, VBUS = 5 V, SYSACTIV = 0 0.35 In fast precharge, Rlimit = 700 k, VAC = 5.4 V, VBAT threshold = 3.6 V, measure charge current from removal to 10% 150 s USB precharge battery removal In precharge, Rlimit = 500 k, VBUS = 5.0 V, switch-off time VBAT threshold = 3.6 V, measure charge current from removal to 10% 150 s ac precharge battery removal switch-off time PCHGPOR voltage threshold VAC = 5.4 V or VBUS = 5.0 V, PCHGPOR raise when VPRECH voltage higher than the voltage threshold PCHGCLK click frequency VAC = 5.4 V or VBUS = 5.0 V (including temperature variation) VAC = 5.4 V or VBUS = 5.0 V (at room temperature) 1.2 18.5 32 V 45.4 kHz 24.3 32 39.68 PCHGVREF band gap voltage VAC = 5.4 V or VBUS = 5.0 V 0.7125 0.75 0.7875 VPRECH regulator output VAC = 5.4 V or VBUS = 5.0 V 1.4 1.5 1.6 Small precharge output current VBAT = 0.0 V, VAC = 5.4 V or (VBUS = 5.0 V and USBSLOWPCHG = 1) 3 5 7 mA Slow precharge loop accuracy After TRIMinG, VAC = 5.4 V or VBUS = 5.0 V, VBAT = 1.5 V, VCCS-VBATS rising voltage, monitoring ICTLAC1 or ICTLUSB1 14 17.2 20.3 mV Battery Interface Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 V V 121 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 8-2. Precharge Electrical Characteristics RS = 0.22 , unless otherwise specified (continued) Min Typ Max Unit Fast precharge loop accuracy Parameter After TRIMinG, PCHGAC or PCHGUSB floating, VAC = 5.4 V, VBAT = 3.0 V, VCCS-VBATS rising voltage, monitoring ICTLAC1 or ICTLUSB1 56 68.8 81.2 mV Precharge constant voltage loop limitation System did not start after VBAT > 3.2 V, VBATS input. 3.4 3.6 3.8 V VBUSOVPRECH threshold (for USB reliability) VBUS input 5.04 5.25 5.46 V ac charger overvoltage threshold VBAT = 2.8 V, VAC input 6.5 6.8 7.3 V VBUS overvoltage threshold VBAT = 2.8 V, VBUS input 6.5 6.8 7.3 V Battery voltage threshold to start ac fast precharge VBATS input 1.8 2.0 2.2 V Battery voltage threshold to start ac slow precharge VBATS input 1.0 1.2 1.4 V Charger presence detect threshold VBATS = 2.8 V, rising edge VBAT+0.3 VBAT+ 0.4 VBAT+0.6 V VBATS = 2.8 V, falling edge VBAT VBAT+ 0.1 VBAT+0.3 VBUS presence detect threshold Test Conditions Rising edge 4.4 Falling edge 4.3 BCIAUTO detection impedance To obtain CVENACA = BCIAUTOACA = 0 threshold To obtain CVENACA = BCIAUTOACA = 1 V 10 k mV 140 BCIAUTO detection voltage threshold CVENACA = 0 below the voltage threshold 100 150 200 CVENACA = 1 below the voltage threshold 700 750 800 BCIAUTO detection output current Measured on BCIAUTO pin 4.5 7.5 9.5 A Precharge main battery presence impedance detection threshold Measured through ADCIN1 rising voltage and sourced current, monitoring BATSTS value 115 140 192 k Precharge main battery presence voltage detection threshold Force ADCIN1 voltage, monitor BATSTS value. 750 mV Precharge main battery presence detection output current Measured on ADCIN1 pin 5.5 A 8.3.3 Constant Voltage Mode The BCI supports a constant voltage (CV) mode. CV mode is automatically started when there is no battery pack, a regulated ac charger is plugged in, and CVENAC = 1. The charging device outputs a constant voltage at the VBAT node. To start CV mode, the precharge analog hardware detects whether a battery pack is open using the battery presence comparator, and detects whether an ac charger is connected using the ac charger presence comparator. CV mode is disabled when VAC is greater than 6.5 V typical. ac overvoltage protection is also enabled during CV mode. Hardware implementation for CV mode uses the main charge constant voltage loop. In CV mode, a 35-mA typical load is synced internally to keep the regulated VBAT voltage output stable. An 80-F typical external capacitor must be connected to the VBAT node. Table 8-3 lists the electrical characteristics of CV mode. 122 Battery Interface Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 8-3. CV Mode Electrical Characteristics (1) Parameter Test Conditions Min Typ Max Unit Main charge constant voltage mode VAC = 5.4 V, ADCIN1 pin floating, LDOOK = 1 CBAT Battery node capacitor 37 ESR (including FUSE) VBAT regulated voltage, including dc (posttrim), dc load regulation, and dc line regulation Typical condition is VBAT for VAC = 5.4 V, ILOAD = 0.5 A 3.88 80 167 F 0.4 0.5 4.0 4.12 V 1 A dc load regulation: VAC = VACmin, ILOAD varying from 0 to ILOADmax dc line regulation: ILOAD = ILOADmax, VAC varying from VACmin to VACmax Maximum condition is ILOAD = 0, VAC = 6.2 V Minimum condition is ILOAD = 1 A, VAC = 4.8 V ILOAD BCI VBAT load current VAC = 5.4 V VAC 15 35 55 mA 4.8 5.4 6.2 V Transient load regulation during internal LDO startup VBAT(Iout 20 mA) - VBAT(Iout 500 mA) in load change time = 1 s (BCI in precharge CV mode) 300 300 mV Transient load during LDO and dc-dc startup VBAT(Iout 30 mA) - VBAT(Iout 830 mA) in load change time = 1 s (BCI in main charge CV mode) 300 300 mV Transient load regulation VBAT(Iout 30 mA) - VBAT(Iout 300 mA) in load change time = 1 s (BCI in main charge CV mode) (ESR = 0.4 ) 100 100 mV (1) In CV mode, an external FET characteristic is critical. This mode has been validated for FDJ1027P FET. Battery Interface Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 123 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 8.4 www.ti.com Charge Sequence Timing Diagram Figure 8-4 is the charge sequence timing diagram. VBAT CHGV (BCI) 4.20V VBATOV4 (BCI) 3.95V VBAT>3.2V (Power) 3.2V POR (Power) 2.65V FASTPRECH (BCI 2.0V SLOWPRECH (BCI) 1.2V ICHG Time CHGI (BCI) 600mA ICHGLOW (BCI) 240mA Slow Precharge Current 100mA ICHGEOC (BCI) 80mA Small Precharge Current 5mA Charge End Charge Completion Constant Voltage Main charge Constant Current Main charge FAST Pre charge SLOW Pre charge Time SMALL Pre charge CHARGE MODES Time 032-058 Figure 8-4. Automatic Charge Sequence Timing Diagram 8.5 CEA Charger Type Depending on the device and according to the charger type, the DM and DP lines have different characteristics: * Hub: DP and DM not shorted, DM low * Charger: DP and DM shorted * Carkit: DP and DM not shorted, DM high These characteristics reflect to which of these devices the phone is connected. Table 8-4 lists the important characteristics in precharge detection. Table 8-4. Precharge Detection Characteristics Symbol Parameter Comments Min Unit 100 mA 100 mA ICCINIT Supply current of unconfigured function/hub ICRINIT Charger: DP and DM shorted Supply current of unconfigured charger/carkit Carkit: DP and DM not shorted, DM high TDELAY Delay for power up all blocks 1000 s TDMOD_DELAY Time pulling down DM line 19.5 s 124 Hub: DP and DM not shorted, DM low Max Battery Interface Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 8-4. Precharge Detection Characteristics (continued) Symbol Parameter TCHECK Repeat time check process TPULSE DP pullup pulse width Comments Min Max Unit 500 ms 20 ms In main charge, the basic chargers and basic carkits indicate their default current limit, versus the value of the ID resistor, between the ID pin and the ground, and also versus the data bus D connection type (shorted or not shorted). Table 8-5 lists the output current limit ranges according to the device type and parameters. Table 8-5. Main Charge Current Limit Indication Parameter Device Type Phone-powered accessory Output Current Limit ID Resistor (1%) Output Voltage (nom) D+/D- Connection (1) ID Pin State ID Pin Current Limit Implemented Min Max 102k N/A (2) Not shorted N/A N/A N/A N/A Low N/A 450 650 200k 5.0 V Shorted High No 450 650 High Yes 750 950 Low N/A 750 950 High No 750 950 Charger 5-wire 440k 5.0 V Shorted 4.5 V Shorted High Yes 1.8 3.0 (3) N/A 450 650 Unit mA mA A 200k 5.0 V D-high Used for muting 440k 5.0 V D-high Used for muting N/A 750 950 Smart carkit 5-wire N/A 5.0 V D-high N/A N/A 0.450 3.0 (3) A Carkit 4-wire N/A 5.0 V D-high N/A N/A 0.450 3.0 (3) A Basic carkit 5-wire (1) (2) (3) mA Shorted indicates that D+ (DP) is shorted to D- (DM). N/A = Not applicable The maximum current limit in this configuration is for safety. It does not indicate normal current loads for the phone. Battery Interface Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 125 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 9 MADC 9.1 General Description www.ti.com The TPS65950 shares the MADC resource with the host processors in the system (hardware and software conversion modes) and its BCI. Therefore, the TPS65950 must: * Manage potential concurrent requests of conversions and priority among resource users * Flag, using interrupt signals, the end-of-sequence of conversions * Grant quarter-bit accuracy for modem conversion of battery voltage The quarter-bit accurate start signal is provided through a STARTADC from the host processor (real-time conversion). The MADC generates interrupt signals to the host processors. Interrupts are handled primarily by the MADC internal secondary interrupt handler (SIH) and secondly at the upper level (outside the MADC) by the TPS65950 primary interrupt handler (PIH). The MADC indicates to the BCI module, through a data ready signal, that conversion results are available. 9.2 Main Electrical Characteristics Table 9-1 lists the electrical characteristics of the MADC. Table 9-1. Electrical Characteristics Parameter Conditions Min Resolution Input dynamic range for external input Typ Max 10 Except ADIN0 and ADCIN1 and internal MADC input (0 to 1.5 V) 0 MADC voltage reference Unit Bit 2.5 1.5 V V Differential nonlinearity For all channels (except ADIN2 through ADIN7 channels) -1 1 LSB Integral nonlinearity Best fitting. For all channels (except ADIN2 through ADIN7) -2 2 LSB -1 1 LSB -2 2 LSB Best fitting considering offset of 25 least-significant bits (LSBs) -3.75 3.75 LSB Best fitting -28.5 28.5 mV Differential nonlinearity for ADIN2 through ADIN7 Integral nonlinearity for ADIN2 through ADIN7 Offset Best fitting for codes 230 to maximum Input bias Maximum source input resistance Rs (for all 16 internal or external inputs) Input current leakage (for all 16 internal or external inputs) 126 A 1 Input capacitor CBANK MADC 10 pF 100 k 1 A Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 9.3 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Channel Voltage Input Range Table 9-2 lists the channel voltage input ranges. Table 9-2. Analog Input Voltage Range Channel Min Typ Max Unit Prescaler ADIN0: Battery type/GP input 0 1.5 V No prescaler dc current source for battery identification through external resistor (10 A typical) ADCIN1: Battery temperature 0 1.5 V No prescaler dc current source for temperature measurement through external resistor (10 to 80 A programmable) ADIN2: GP input (1) 0 2.5 V MADC prescaler from 0 to >1.5 V (1) 0 2.5 V MADC prescaler from 0 to >1.5 V ADIN4: GP input (1) 0 2.5 V MADC prescaler from 0 to >1.5 V ADIN5: GP input (1) 0 2.5 V MADC prescaler from 0 to >1.5 V (1) 0 2.5 V MADC prescaler from 0 to >1.5 V ADIN7: GP input (1) 0 2.5 V MADC prescaler from 0 to >1.5 V ADIN3: GP input ADIN6: GP input (1) GP inputs must be tied to ground when TPS65950 internal power supplies (VINTANA1 and VINTANA2) are off. 9.3.1 Sequence Conversion Time (Real-Time or Nonaborted Asynchronous) Table 9-3 lists the sequence conversion timing characteristics. Figure 9-1 is a conversion sequence general timing diagram. Table 9-3. Sequence Conversion Timing Characteristics Parameter Comments Min Typ Max 1 Unit F Running frequency MHz T = 1/F Clock period N Number of analog inputs to convert in a single sequence 0 16 Tstart SW1, SW2, or USB asynchronous request or real-time STARTADC request 3 4 s Tsettling time Settling time to wait before sampling a stable analog input (capacitor bank charge time) 20 s s 1 5 12 Tsettling is calculated from the max ((Rs + Ron)*Cbank) of the 16 possible input sources (internal or external). Ron is the resistance of the selection analog input switches (5 k). This time is software-programmable in the open-core protocol (OCP) register. Tstartsar The successive approximation registers ADC start time. Tadc time The successive approximation registers ADC conversion time. Tcapture time Tcapture time is the conversion result capture time. Tstop 1 s 10 s s 2 1 2 Full conversion sequence time One channel (N = 1) (1) 22 39 All channels (N = 16) (1) 352 624 Conversion sequence time Without Tstart and Tstop: One channel (N = 1) (1) 18 33 Without Tstart and Tstop: All channels (N = 16) (1) 288 528 STARTADC period is T 0.33 24 STARTADC pulse duration (1) s s s s Total sequence conversion time general formula: Tstart + N*(1 + Tsettling + Tadc + Tcapture) +Tstop MADC Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 127 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 9-3 shows the information in Figure 9-1. The Busy parameter shows that a conversion sequence is running, and the channel N result register parameter corresponds to the result register of RT/GP/BCI selected channel. T one conversion Tstart Tstartsar Tcapture Tsettling Tadc Tstop madc_clk Busy mux_sel_lowv[3:0] channel N selected Acquire_lowv start_sar_lowv out_lowv[9:0] channel N result register new channel N value channel X value old value new value 032-059 Figure 9-1. Conversion Sequence General Timing Diagram 128 MADC Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 10 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 LED Drivers 10.1 General Description Two arrays of parallel LEDs are driven (dedicated for the phone light). The parallel LEDs are supplied by VBAT and the external resistor value is given for each of them. The TPS65950 has two open-drain LED drivers for keypad backlighting. The keypad backlighting must incorporate any required current limiting and be rated for operation at the main battery voltage. Figure 10-1 is a block diagram of the LED driver. Table 10-1 lists the electrical characteristics of the LED driver. BATT 120 W *16... LEDB 160 W BATT LEDSYNC LEDGND Device 032-060 Figure 10-1. LED Driver Block Diagram For the component values, see Table 15-1. Table 10-1. Electrical Characteristics Parameter Software On resistance Typ Max IO = 160 mA Conditions Min 3 4 IO = 60 mA 10 12 LED Drivers Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 Unit 129 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 11 www.ti.com Keyboard 11.1 Keyboard Connection The keyboard is connected to the chip using: * KBR (7:0) input pins for row lines * KBC (7:0) output pins for column lines Figure 11-1 shows the keyboard connection. Device VCC Internal pullup Keyboard controller 8x8 Keyboard matrix kbd_r_0 kbd_r_1 kbd_r_2 kbd_r_3 kbd_r_4 kbd_r_5 kbd_r_6 kbd_r_7 kbd_c_0 kbd_c_1 kbd_c_2 kbd_c_3 kbd_c_4 kbd_c_5 kbd_c_6 kbd_c_7 032-061 Figure 11-1. Keyboard Connection When a key button of the keyboard matrix is pressed, the corresponding row and column lines are shorted together. To allow key press detection, all input pins (KBR) are pulled up to VCC and all output pins (KBC) are driven low. Any action on a button generates an interrupt to the sequencer. The decoding sequence is written to allow detection of simultaneous press actions on several key buttons. The keyboard interface can be used with a smaller keyboard area than 8 x 8. To use a 6 x 6 keyboard, KBR(6) and KBR(7) must be tied high to prevent any scanning process distribution. 130 Keyboard Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 12 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Clock Specifications The TPS65950 includes several I/O clock pins. The TPS65950 has two sources of high-stability clock signals: the external high-frequency clock (HFCLKIN) input and an onboard 32-kHz oscillator (an external 32-kHz signal can be provided). Figure 12-1 is an overview of the clocks. Device OR 32KXIN OR 32KCLKOUT 32KXOUT 32 kHz OR HFCLKIN HFCLKOUT 032-062 Figure 12-1. Clock Overview 12.1 Features The TPS65950 accepts two sources of high-stability clock signals: * 32KXIN/32KXOUT: Onboard 32-kHz crystal oscillator (an external 32-kHz input clock can be provided) * HFCLKIN: External high-frequency clock (19.2, 26, or 38.4 MHz). The TPS65950 can provide: * 32KCLKOUT digital output clock * HFCLKOUT digital output clock with the same frequency as the HFCLKIN input clock Clock Specifications Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 131 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com 12.2 Input Clock Specifications The clock system accepts two input clock sources: * 32-kHz crystal oscillator clock or sinusoidal/squared clock * HFCLKIN high-frequency input clock 12.2.1 Clock Source Requirements Table 12-1 lists the input clock requirements. Table 12-1. TPS65950 Input Clock Source Requirements Pad Clock Frequency 32KXIN 32KXOUT HFCLKIN (1) 32.768 kHz 19.2, 26, 38.4 MHz Stability Duty Cycle Crystal 30 ppm 40%/60% Square wave - 45%/55% Sine wave - Square wave 150 ppm Sine wave - - See (1) - HFCLK duty cycle and frequency is not altered by the internal circuit. The input clock accuracy must match that of the system requirement, for example, OMAP device. 12.2.2 High-Frequency Input Clock HFCLKIN is the high-frequency input clock. It can be a square- or sine-wave input clock. If a square-wave input clock is provided, it is recommended to switch the block to bypass mode when possible to avoid loading the clock. Figure 12-2 shows the HFCLKIN clock distribution. HFCLKIN Slicer HFCLKOUT Clock generator Slicer bypass SLICER_OK CLKEN2 Timer CLKEN Main state-machine CLKREQ SLEEP1 SLEEP2 Optional request configurable by software only for legacy support 032-063 Figure 12-2. HFCLKIN Clock Distribution 132 Clock Specifications Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Clock Specifications Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 133 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com When a device needs a clock signal other than 32.768 kHz, it makes a clock request and activates the CLKREQ pin. As a result, the TPS65950 immediately sets CLKEN to 1 to warn the clock provider in the system about the clock request and starts a timer (maximum of 5.2 ms using the 32.768-kHz clock). When the timer expires, the TPS65950 opens a gated clock, the timer automatically reloads the defined value, and a high-frequency output clock signal is available through the HFCLKOUT pin. The output drive of HFCLKOUT is programmable (minimum load 10 pF, maximum load 40 pF) and must be at 40 pF by default. With a register setting, the mirroring of CLKEN can be enabled on CLKEN2. When this mirroring feature is not enabled, CLKEN2 can be used as a GP output controlled through I2C accesses. CLKREQ, when enabled, has a weak pulldown resistor to support the wired-OR clock request. Figure 12-3 shows an example of the wired-OR clock request. Device PERIPH1 VIO CLKREQ PERIPH2 VIO PERIPHn VIO 032-064 Figure 12-3. Example of Wired-OR Clock Request 134 Clock Specifications Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 NOTE The timer default value must be the worst case (10 ms) for the clock providers. For legacy or workaround support, the signals NSLEEP1 and NSLEEP2 can also be used as a clock request even if it is not their primary goal. By default, this feature is disabled and must be enabled individually by setting the register bits associated with each signal. When the external clock signal is present on the HFCLKIN ball, it is possible to use this clock instead of the internal RC oscillator and then synchronize the system on the same clock. The RC oscillator can then go to idle mode. Table 12-2 lists the input clock electrical characteristics of the HFCLKIN input clock. Table 12-2. HFCLKIN Input Clock Electrical Characteristics Parameter Configuration Mode Slicer Min Frequency Typ Max 19, 26, or 38.4 Startup time LP/HP (sine wave) Input dynamic range LP/HP (sine wave) 0.3 BP/PD (square wave) Current consumption 0.7 4 s 1.45 VPP 1.85 0 Unit MHz (1) LP 175 HP 235 A BP/PD 39 nA Harmonic content of input signal (with 0.7-VPP amplitude): second component LP/HP (sine wave) -25 dBc Voltage input high (VIH) BP (square wave) Voltage input low (VIL) BP (square wave) (1) 1 V 0.6 V Bypass input max voltage is the same as the maximum voltage provided for the I/O interface (IO.1P8V). Table 12-3 lists the input clock timing requirements of the HFCLKIN input clock when the source is a square wave. Table 12-3. HFCLKIN Square Input Clock Timing Requirements With Slicer in Bypass Name Parameter Description CH0 1/tC(HFCLKIN) Frequency, HFCLKIN CH1 tW(HFCLKIN) Pulse duration, HFCLKIN low or high Typ Max tR(HFCLKIN) Rise time, HFCLKIN CH4 tF(HFCLKIN) Fall time, HFCLKIN (1) Unit 19.2, 26, or 38.4 0.45*tC(HFCLKIN) MHz 0.55*tC(HFCLKIN) ns 5 ns 5 ns (1) CH3 (1) Min Default drive capability is 40 pF. Figure 12-4 shows the timing of the HFCLKIN squared input clock. CH0 CH1 CH1 HFCLKIN 032-065 Figure 12-4. HFCLKIN Squared Input Clock 12.2.3 32-kHz Input Clock A 32.768-kHz input clock (often abbreviated to 32-kHz) generates the clocks for the RTC. It has a low-jitter mode where the current consumption increases for lower jitter. It is possible to use the 32-kHz input clock with an external crystal or clock source. Depending on the mode, the 32K oscillator is configured as being either: Clock Specifications Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 135 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 * * www.ti.com An external 32.768-kHz crystal through the 32KXIN/32KXOUT balls (see Figure 12-5). This configuration is available for master mode only (for more information, see Section 13, Timing Requirements and Switching Characteristics). An external square or sine wave of 32.768 kHz through 32KXIN with amplitude of 1.8 or 1.85 V (see Figure 12-7, Figure 12-8, and Figure 12-9). This configuration is available for master and slave modes (for more information, see Section 13, Timing Requirements and Switching Characteristics). 12.2.3.1 External Crystal Description Figure 12-5 is a block diagram of the 32-kHz oscillator with crystal in master mode. Current control circuit and mode selection Bias generator and startup circuit Signal swing limiting circuit Y Signal shaping (1) VBATOK Internal GND XI (1) VBATOK XO C1 XTAL Internal GND C2 External to device 032-066 NOTE: Switches close by default and open only if register access enables very-low-power mode when VBAT < 2.7 V. Figure 12-5. 32-kHz Oscillator Block Diagram In Master Mode With Crystal CXIN and CXOUT represent the total capacitance of the printed circuit board (PCB) and components, excluding the crystal. Their values depend on the datasheet of the crystal, the internal capacitors, and the parallel capacitor. The frequency of the oscillations depends on the value of the capacitors. The crystal must be in the fundamental mode of operation and parallel resonant. NOTE For the values of CXIN and CXOUT, see Table 15-1. Table 12-4 lists the required electrical constraints. Table 12-4. Crystal Electrical Characteristics Parameter Min Parallel resonance crystal frequency Max 32.768 Input voltage, Vin (normal mode) 136 Typ 1.0 Clock Specifications 1.3 Unit kHz 1.55 V Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 12-4. Crystal Electrical Characteristics (continued) Parameter Min Typ Internal capacitor on each input (Cint) Max pF Parallel input capacitance (Cpin) 1 Nominal load cap on each oscillator input CXIN and CXOUT (1) pF CXIN = CXOUT = Cosc*2 - (Cint + Cpin) pF 1.6 1.8 pF 75 k Pin-to-pin capacitance Crystal ESR Unit 10 (2) Crystal shunt capacitance, CO 1 pF Crystal tolerance at room temperature, 25C -30 30 ppm Crystal tolerance versus temperature range (-40C to 85C) -200 200 ppm 1 W 0.5 W Maximum drive power Operating drive level (1) Nominal load capacitor on each oscillator input defined as CXIN = CXOUT = Cosc*2 - (Cint + Cpin). Cosc is the load capacitor defined in the crystal oscillator specification, Cint is the internal capacitor, and Cpin is the parallel input capacitor. The crystal motional resistance Rm relates to the equivalent series resistance (ESR) by the following formula: (2) 2 ESR = Rm C 1+ O CL Measured with the load capacitance specified by the crystal manufacturer. If CXIN = CXOUT = 10 pF, then CL = 5 pF. Parasitic capacitance from the package and board must also be considered. When selecting a crystal, the system design must consider the temperature and aging characteristics of a crystal versus the user environment and expected lifetime of the system. Table 12-5 and Table 12-6 list the switching characteristics of the oscillator and the input requirements of the 32.768-kHz input clock, respectively. Figure 12-6 shows the crystal oscillator output in normal mode. Table 12-5. Base Oscillator Switching Characteristics Name Parameter Description fP Oscillation frequency tSX Startup time Min Typ Max 32.768 kHz 0.5 IDDA Active current consumption IDDQ Current consumption Unit LOJIT <1:0> = 00 1.8 LOJIT <1:0> = 11 8 Low battery mode (1.2 V) 1 Startup 8 s A A Table 12-6. 32-kHz Crystal Input Clock Timing Requirements Name Parameter Description OC0 1/tC(32KHZ) Frequency, 32 kHz OC1 tW(32KHZ) Pulse duration, 32 kHz low or high Min Typ Max 32.768 0.40*tC(32KHZ) OC0 OC1 Unit kHz 0.60*tC(32KHZ) s OC1 32KX 032-067 Figure 12-6. 32-kHz Crystal Input Clock Specifications Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 137 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com 12.2.3.2 External Clock Description Figure 12-7 and Figure 12-8 show the 32-kHz oscillator with a 32.768-kHz square or sine signal in master and slave modes. Figure 12-9 shows an external clock source when the oscillator is configured in bypass mode. Thus, there are three configurations: * A square- or sine-wave input can be applied to the 32KXIN pin with an amplitude of 1.85 or 1.8 V. The 32KXOUT pin can be driven to a dc value of the square- or sine-wave amplitude divided by 2. This configuration, shown in Figure 12-7, is recommended if a large load is applied on the 32KXOUT pin. * A square- or sine-wave input can be applied to the 32KXIN pin with an amplitude of 1.85 or 1.8 V. The 32KXOUT pin can be left floating. This configuration, showed in Figure 12-8, is used if no charge is applied on the 32KXOUT pin. * The oscillator is in bypass mode and a square-wave input can be applied to the 32KXIN pin with an amplitude of 1.8 V. The 32KXOUT pin can be left floating. This configuration, shown in Figure 12-9, is used if the oscillator is in bypass mode. Current control circuit and mode selection Bias generator and startup circuit Signal swing limiting circuit Signal shaping (1) VBATOK Square/sine wave: Vpp = VRRTC or VIO_1P8V Internal GND XI XO DC level: DC Vpp/2 Y (1) VBATOK Internal GND 032-068 (1) Switches close by default and open only if register access enables very-low-power mode when VBAT < 2.7 V. Figure 12-7. 32-kHz Oscillator Block Diagram Without Crystal Option 1 138 Clock Specifications Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Current control circuit and mode selection Bias generator and startup circuit Signal swing limiting circuit Y Signal shaping (1) VBATOK XI XO (1) VBATOK Floating Internal GND Square/sine wave: Vpp = VRRTC or VIO_1P8V Internal GND 032-069 (1) Switches close by default and open only if register access enables very-low-power mode when VBAT < 2.7 V. Figure 12-8. 32-kHz Oscillator Block Diagram Without Crystal Option 2 Current control circuit and mode selection Bias generator and startup circuit Signal swing limiting circuit Y Signal shaping (1) VBATOK Internal GND XI XO Floating Square wave: Vpp = VIO_1P8V (1) VBATOK Internal GND 032-070 (1) Switches close by default and open only if register access enables very-low-power mode when VBAT < 2.7 V. Figure 12-9. 32-kHz Oscillator in Bypass Mode Block Diagram Without Crystal Option 3 Clock Specifications Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 139 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 12-7 lists the electrical constraints required by the 32-kHz input square- or sine-wave clock used. Table 12-7. 32-kHz Input Square- or Sine-Wave Clock Source Electrical Characteristics Name Parameter Description Min Typ Max Unit f Frequency 32.768 kHz CI Input capacitance 35 pF CFI On-chip foot capacitance to GND on each input (see Figure 12-7, Figure 12-8, and Figure 12-9) 10 VPP Square-/sine-wave amplitude in bypass mode or not VIH Voltage input high, square wave in bypass mode VIL Voltage input low, square wave in bypass mode (1) pF 1.8 (1) V 0.8 V 0.6 V Bypass input maximum voltage is the same as the maximum voltage provided for the I/O interface. Table 12-8 lists the input requirements of the 32-kHz square-wave input clock. Table 12-8. 32-kHz Square-Wave Input Clock Source Timing Requirements Name Parameter Description CK0 1/tC(32KHZ) Frequency, 32 kHz CK1 tW(32KHZ) Pulse duration, 32 kHz low or high CK3 tR(32KHZ) CK4 tF(32KHZ) (1) Min Typ Max Unit 32.768 MHz 0.55*tC(32KHZ) s Rise time, 32 kHz (1) 0.1*tC(32KHZ) s Fall time, 32 kHz (1) 0.1*tC(32KHZ) s 0.45*tC(32KHZ) The capacitive load is 30 pF. Figure 12-10 shows the timing of the 32-kHz square- or sine-wave input clock. CK0 CK1 CK1 32KX 032-071 Figure 12-10. 32-kHz Square- or Sine-Wave Input Clock 12.3 Output Clock Specifications The TPS65950 provides two output clocks: * 32KCLKOUT * HFCLKOUT 12.3.1 32KCLKOUT Output Clock Figure 12-11 is a block diagram of the 32.768-kHz clock output. 140 Clock Specifications Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 IO_1P8 (1.8 V) OR 32KXIN 32-kHz OSC OR 32KCLKOUT 32 kHz 32KXOUT RTC 032-072 Figure 12-11. 32.768-kHz Clock Output Block Diagram The TPS65950 has an internal 32.768-kHz oscillator connected to an external 32.768-kHz crystal through the 32KXIN/32KXOUT balls or an external digital 32.768-kHz clock through the 32KXIN input (see Figure 12-11). The TPS65950 also generates a 32.768-kHz digital clock through the 32KCLKOUT pin and can broadcast it externally to the application processor or any other devices. The 32KCLKOUT clock is broadcast by default in the TPS65950 active mode, but can be disabled if it is not used. The 32.768-kHz clock (or signal) also clocks the RTC embedded in the TPS65950. The RTC is not enabled by default. The host processor must set the correct date and time and enable the RTC. The 32KCLKOUT output buffer can drive several devices (up to a 40-pF load). At startup, the 32.768-kHz output clock (32KCLKOUT) must be stabilized (frequency/duty cycle) before the signal output. Depending on the startup condition, this can delay the startup sequence. Table 12-9 lists the electrical characteristics of the 32KCLKOUT output clock. Table 12-9. 32KCLKOUT Output Clock Electrical Characteristics Name Parameter Description Min f Frequency CL Load capacitance VOUT Output clock voltage, depending on output reference level IO_1P8 (see Section 2) VOH Voltage output high VOL (1) Typ Max Unit 32.768 kHz 40 pF 1.8 (1) V VOUT - 0.45 VOUT V 0 0.45 V Voltage output low The output voltage depends on output reference level, which is IO_1P8 (see Section 2, Terminal Description). Table 12-10 lists the timing characteristics of the 32KCLKOUT output clock. Figure 12-12 shows the waveform of the 32KCLKOUT output clock. Table 12-10. 32KCLKOUT Output Clock Switching Characteristics Name Parameter Description CK0 1/tC(32KCLKOUT) Frequency CK1 tW(32KCLKOUT) Pulse duration, 32KCLKOUT low or high Min Typ Max 32.768 0.40*tC(32KCLKOUT) Unit MHz 0.60*tC(32KCLKOUT) Clock Specifications Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 ns 141 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 12-10. 32KCLKOUT Output Clock Switching Characteristics (continued) Name CK2 CK3 (1) Parameter Description Min Typ Max Rise time, 32KCLKOUT (1) tR(32KCLKOUT) tF(32KCLKOUT) Fall time, 32KCLKOUT (1) Unit 16 ns 16 ns The output capacitive load is 30 pF. CK0 CK1 CK1 32KCLKOUT 032-073 Figure 12-12. 32KCLKOUT Output Clock 12.3.2 HFCLKOUT Output Clock Table 12-11 lists the electrical characteristics of the HFCLKOUT output clock. Table 12-11. HFCLKOUT Output Clock Electrical Characteristics Name Parameter Description Min f Frequency CL Load capacitance VOUT Output clock voltage, depending on output reference level IO_1P8 (see Section 2) VOH Voltage output high VOL Voltage output low (1) Typ Max 19.2, 26, or 38.4 Unit MHz 30 1.8 (1) pF V VOUT - 0.45 VOUT V 0 0.45 V The output voltage depends on output reference level, which is IO_1P8 (see Section 2). Table 12-12 lists the timing characteristics of the HFCLKOUT output clock. Table 12-12. HFCLKOUT Output Clock Switching Characteristics Name Parameter Description CHO1 1/tC(HFCLKOUT) Frequency CHO2 tW(HFCLKOUT) Pulse duration, HFCLKOUT low or high Typ Max Unit 19.2, 26, or 38.4 0.40*tC(HFCLKOUT) MHz 0.60*tC(HFCLKOUT) ns 2.6 ns 2.6 ns (1) CHO3 tR(HFCLKOUT) Rise time, HFCLKOUT CHO4 tF(HFCLKOUT) Fall time, HFCLKOUT (1) (1) Min The output capacitive load is 30 pF. Figure 12-13 shows the waveform of the HFCLKOUT output clock. CHO1 CHO2 CHO2 HFCLKOUT 032-074 Figure 12-13. HFCLKOUT Output Clock 142 Clock Specifications Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 12.3.3 Output Clock Stabilization Time Figure 12-14 shows the 32KCLKOUT and HFCLKOUT clock stabilization time. XIN Starting_Event Tstartup CLK32KOUTEN CLK32KOUT CLKEN Delay1 HFCLKOUTEN HFCLKOUT Delay2 NRESPWRON 032-075 NOTE: Tstartup, Delay1, and Delay2 depend on the boot mode (see Section 4.5, Power Management). NOTE: Ensure that the high frequency oscillator start-up time is in spec for the boot mode used. During power-up the internal delay, Delay1 above is fixed (5.2 ms and 5.3 ms depending on boot mode). The start-up time for the oscillator must be less than the fixed delay. Figure 12-14. 32KCLKOUT and HFCLKOUT Clock Stabilization Time Figure 12-15 shows the behavior of HFLCKOUT. HFCLKIN HFCLKOUT 032-076 Figure 12-15. HFCLKOUT Behavior Clock Specifications Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 143 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 13 www.ti.com Timing Requirements and Switching Characteristics 13.1 Timing Parameters The timing parameter symbols used in the timing requirement and switching characteristic tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies are abbreviated as shown in Table 13-1. Table 13-1. Timing Parameters Lowercase Subscripts Symbol Parameter c Cycle time (period) d Delay time dis Disable time en Enable time h Hold time su Setup time START Start-bit t Transition time v Valid time w Pulse duration (width) X Unknown, changing, or don't care level H High L Low V Valid IV Invalid AE Active edge FE First edge LE Last edge Z High impedance 13.2 Target Frequencies Table 13-2 assumes testing over the recommended operating conditions. Table 13-2. TPS65950 Interface Target Frequencies I/O Interface 2 SmartReflex I C 2 I C interface GP I2C USB USB JTAG 144 Target Frequency Interface Designation 1.5 V Slave HS mode 3.6 Mbps Slave fast-speed mode 400 kbps Slave standard mode 100 kbps HS 480 Mbps FS 12 Mbps LS 1.5 Mbps RealView(R) ICE tool 30 MHz XDS560 and XDS510 tools 30 MHz LauterbachTM tool 30 MHz Timing Requirements and Switching Characteristics Submit Documentation Feedback Product Folder Link(s): TPS65950 Copyright (c) 2008-2011, Texas Instruments Incorporated TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 13-2. TPS65950 Interface Target Frequencies (continued) I/O Interface TDM/I2S Voice/Bluetooth PCM interface (1) (2) Target Frequency Interface Designation 1.5 V Inter-IC sound (I2STM) 1/(64 * Fs) (1) Right-justified 1/(64 * Fs) (1) Left-justified 1/(64 * Fs) (1) TDM 1/(128 * Fs) (1) PCM (master mode) 1/(65 * Fs) (2) 1/(33 to 65 * Fs) (2) PCM (slave mode) Fs = 8 to 48 kHz; 96 kHz for RX path only (TDM/I2S interface) Fs = 8 or 16 kHz (voice/Bluetooth PCM interface) 13.3 I2C Timing The TPS65950 provides two I2C HS slave interfaces (one for GP and one for SmartReflex). These interfaces support the standard mode (100 kbps), fast mode (400 kbps), and HS mode (3.4 Mbps). The GP I2C module embeds four slave hard-coded addresses (ID1 = 48h, ID2 = 49h, ID3 = 4Ah, and ID4 = 4Bh). The SmartReflex I2C module uses one slave hard-coded address (ID5). Master mode is not supported. Table 13-3 and Table 13-4 assume testing over the recommended operating conditions (see Figure 13-1). Start Restart I1 I2 I2C.SCL 1 8 9 1 I8 8 9 I8 I3 I2C.SDA Stop I4 I7 MSB LSB ACK I9 MSB LSB ACK 032-077 2 Figure 13-1. I C Interface--Transmit and Receive in Slave Mode Table 13-3. I2C Interface Timing Requirements (1) Notation Parameter (2) Min Max Unit Slave HS Mode I3 tsu(SDA-SCLH) Setup time, SDA valid to SCL high 10 I4 th(SCLL-SDA) Hold time, SDA valid from SCL low 0 ns I7 tsu(SCLH-SDAL) Setup time, SCL high to SDA low 160 ns I8 th(SDAL-SCLL) Hold time, SCL low from SDA low 160 ns I9 tsu(SDAH-SCLH) Setup time, SDA high to SCL high 160 ns 70 ns Slave Fast-Speed Mode (1) (2) I3 tsu(SDA-SCLH) Setup time, SDA valid to SCL high 100 I4 th(SCLL-SDA) Hold time, SDA valid from SCL low 0 ns I7 tsu(SCLH-SDAL) Setup time, SCL high to SDA low 0.6 ns I8 th(SDAL-SCLL) Hold time, SCL low from SDA low 0.6 ns I9 tsu(SDAH-SCLH) Setup time, SDA high to SCL high 0.6 ns 0.9 ns The input timing requirements are given by considering a rising or falling time of: 80 ns in HS mode (3.4 Mbps) 300 ns in fast-speed mode (400 Kbps) 1000 ns in standard mode (100 Kbps) SDA equals I2C.SR.SDA or I2C.CNTL.SDA SCL equals I2C.SR.SCL or I2C.CNTL.SCL Copyright (c) 2008-2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics Submit Documentation Feedback Product Folder Link(s): TPS65950 145 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 13-3. I2C Interface Timing Requirements (continued) Notation Parameter Min Max Unit Slave Standard Mode I3 tsu(SDA-SCLH) Setup time, SDA valid to SCL high 250 ns I4 th(SCLL-SDA) Hold time, SDA valid from SCL low 0 ns I7 tsu(SCLH-SDAL) Setup time, SCL high to SDA low 4.7 ns I8 th(SDAL-SCLL) Hold time, SCL low from SDA low 4 ns I9 tsu(SDAH-SCLH) Setup time, SDA high to SCL high 4 ns Table 13-4. I2C Interface Switching Requirements (1) Notation Parameter (2) Min Max Unit Slave HS Mode I1 tw(SCLL) Pulse duration, SCL low 160 ns I2 tw(SCLH) Pulse duration, SCL high 60 ns (3) s 0.6 s 4.7 s 4 s Slave Fast-Speed Mode I1 tw(SCLL) Pulse duration, SCL low I2 tw(SCLH) Pulse duration, SCL high I1 tw(SCLL) Pulse duration, SCL low I2 tw(SCLH) Pulse duration, SCL high 1.3 Slave Standard Mode (1) (2) (3) The capacitive load is: 100 pF in HS mode (3.4 Mbps) 400 pF in fast-speed mode (400 Kbps) 400 pF in standard mode (100 Kbps) SDA equals I2C.SR.SDA or I2C.CNTL.SDA SCL equals I2C.SR.SCL or I2C.CNTL.SCL SCL low timing for slave fast-speed mode is compatibile with 0.79 s. 13.4 Audio Interface: TDM/I2S Protocol The TPS65950 acts as a master for the TDM and I2S interface or as a slave only for the I2S interface. If the TPS65950 is the master, it must provide frame synchronization (TDM/I2S_SYNC) and bit clock (TDM/I2S_CLK) to the host processor. If the TPS65950 is the slave, it receives frame synchronization and bit clock. The TPS65950 supports the I2S, TDM, left-justified, and right-justified data formats, but does not support TDM slave mode. 13.4.1 I2S Right- and Left-Justified Data Format Table 13-5 and Table 13-6 assume testing over the recommended operating conditions (see Figure 13-2 and Figure 13-3). 146 Timing Requirements and Switching Characteristics Submit Documentation Feedback Product Folder Link(s): TPS65950 Copyright (c) 2008-2011, Texas Instruments Incorporated TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Right channel Left channel I2S.SYNC I1 I2 I0 I1 I2 I2 I2S.CLK I4 I4 I3 I2S.DIN 23 22 1 22 1 I5 I2S.DOUT I4 I3 0 8 dummy bits 0 8 dummy bits I3 23 22 1 22 1 I5 I5 23 I4 I3 0 8 dummy bits 23 0 8 dummy bits 23 22 I5 23 22 032-078 Figure 13-2. I2S Interface--I2S Master Mode Left channel Right channel I2S.SYNC I1 I6 I0 I1 I7 I6 I2S.CLK I4 I4 I3 23 I2S.DIN 22 1 22 1 I5 23 I2S.DOUT I4 I3 I4 I3 0 8 dummy bits 0 8 dummy bits I5 23 I3 22 1 22 1 I5 23 0 8 dummy bits 23 0 8 dummy bits 23 22 I5 22 032-079 Figure 13-3. I2S Interface--I2S Slave Mode The timing requirements in Table 13-5 are valid on the following conditions of input slew and output load: * Rise and fall time range of inputs (SYNC, DIN) is tR/tF = 1.0 ns/6.5 ns * Capacitance load range of outputs (CLK, SYNC, DOUT) is CLoad = 1 pF/30 pF The input timing requirements in Table 13-5 are given by considering a rising or falling time of 6.5 ns. Table 13-5. I2S Interface--Timing Requirements Notation Parameter Min Max Unit Master Mode I3 tsu(DIN-CLKH) Setup time, I2S.DIN valid to I2S.CLK high2 25 ns I4 th(DIN-CLKH) Hold time, I2S.DIN valid from I2S.CLK high. 0 ns I0 tc(CLK) Cycle time, I2S.CLK (1) I1 tw(CLK) Pulse duration, I2S.CLK high or low (2) Slave Mode (1) (2) 1/64 * Fs 0.45 * P ns 0.55 * P ns Fs = 8 to 48 kHz; 96 kHz for RX path only P = I2S.CLK period Copyright (c) 2008-2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics Submit Documentation Feedback Product Folder Link(s): TPS65950 147 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 13-5. I2S Interface--Timing Requirements (continued) Notation Parameter Min Max Unit I3 tsu(DIN-CLKH) Setup time, I2S.DIN valid to I2S.CLK high 5 ns I4 th(DIN-CLKH) Hold time, I2S.DIN valid from I2S.CLK high. 5 ns I6 tsu(SYNC-CLKH) Setup time, I2S.SYNC valid to I2S.CLK high 5 ns I7 th(SYNC-CLKH) Hold time, I2S.SYNC valid from I2S.CLK high 5 ns The capacitive load for Table 13-6 is 7 pF. Table 13-6. I2S Interface--Switching Characteristics Notation Parameter Min Max Unit Master Mode I0 tc(CLK) Cycle time, I2S.CLK (1) I1 tw(CLK) Pulse duration, I2S.CLK high or low (2) I2 td(CLKL-SYNC) I5 td(CLKL-DOUT) 1/64 * Fs ns 0.45 * P 0.55 * P ns Delay time, I2S.CLK falling edge to I2S.SYNC transition -10 10 ns Delay time, I2S.CLK falling edge to I2S.DOUT transition -10 10 ns 0 20 ns Slave Mode I5 (1) (2) td(CLKL-DOUT) Delay time, I2S.CLK falling edge to I2S.DOUT transition Fs = 8 to 48 kHz; 96 kHz for RX path only P = I2S.CLK period 13.4.2 TDM Data Format Table 13-7 and Table 13-8 assume testing over the recommended operating conditions (see Figure 13-4). Channel 1 Channel 2 Channel 3 Channel 4 I2S.SYNC T0 T1 T2 T2 T1 T2 T2 I2S.CLK I2S.DIN T4 T4 T4 T4 T4 T4 T4 T4 T3 T3 T3 T3 T3 T3 T3 T3 23 22 1 T5 I2S.DOUT 23 22 0 T5 1 23 22 8 dummy bits T5 23 22 0 0 1 T5 1 23 22 8 dummy bits 0 23 22 8 dummy bits 8 dummy bits 1 T5 0 T5 1 23 22 8 dummy bits 0 1 T5 0 T5 23 22 1 0 8 dummy bits 032-080 Figure 13-4. TDM Interface--TDM Master Mode The timing requirements in Table 13-7 are valid on the following conditions of input slew and output load: * Rise and fall time range of inputs (SYNC, DIN) is tR/tF = 1.0 ns/6.5 ns * Capacitance load range of outputs (CLK, SYNC, DOUT) is CLoad = 1 pF/30 pF Table 13-7 lists the master mode timing requirements for the TDM interface. Table 13-7. TDM Interface Master Mode Timing Requirements Notation 148 Parameter T3 tsu(DIN-CLKH) Setup time, TDM.DIN valid to TDM.CLK high T4 th(DIN-CLKH) Hold time, TDM.DIN valid from TDM.CLK high Timing Requirements and Switching Characteristics Submit Documentation Feedback Product Folder Link(s): TPS65950 Min Max Unit 25 ns 0 ns Copyright (c) 2008-2011, Texas Instruments Incorporated TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 13-8 lists the master mode switching characteristics of the TDM interface. Table 13-8. TDM Interface Master Mode Switching Characteristics Notation (1) (2) Parameter Min (1) T0 tc(CLK) Cycle time, TDM.CLK T1 tw(CLK) Pulse duration, TDM.CLK high or low (2) T2 td(CLKL-SYNC) T5 td(CLKL-DOUT) Max 1/64 * Fs Unit ns 0.45*P 0.55*P ns Delay time, TDM.CLK rising edge to TDM.SYNC transition -10 10 ns Delay time, TDM.CLK rising edge to TDM.DOUT transition -10 12 ns Fs = 8 to 48 kHz; 96 kHz for RX path only P = TDM.CLK period 13.5 Voice/Bluetooth PCM Interfaces The PCM interface transfers voice data at 8-kHz (default narrowband mode) or 16-kHz (wideband mode) sample rates. The CM interface can act as a slave or master. No PLL is used for the PCM interface, but dividers are used to derive the 8- or 16-kHz clock from HFCLKIN (only when HFCLKIN = 26 MHz). If the system master clock is not 26 MHz, the voice PCM interface is not available. For the Bluetooth interface, the PCM is supported to transfer voice data to the Bluetooth chip at 8-kHz (default narrowband mode) or 16-kHz sample rate. The TPS65950 acts as a master for the Bluetooth interface. The frame synchronization and the bit clock are shared from the voice PCM interface. If the system master clock is not 26 MHz, the Bluetooth interface is not available. Two modes are available for the PCM interfaces: mode 1 (writing on the PCM_VCK rising edge) and mode 2 (writing on the PCM_VCK falling edge). Table 13-9 and Table 13-10 assume testing over the recommended operating conditions (see Figure 13-5 and Figure 13-6). PCM.VFS P2 P2 P1 P0 P2 P1 PCM.VCK P4 P4 P3 PCM.VDR 15 P3 14 1 P5 PCM.VDX 15 0 49 dummy bits 1 0 14 P5 P5 14 15 49 dummy bits 15 14 032-081 Figure 13-5. Voice/BT PCM Interface--Master Mode (Mode 1) Copyright (c) 2008-2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics Submit Documentation Feedback Product Folder Link(s): TPS65950 149 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com PCM.VFS P7 P7 P1 P6 P0 P6 P1 PCM.VCK P4 P4 P3 PCM.VDR 15 P3 14 1 P5 PCM.VDX 0 49 dummy bits 15 49 dummy bits 15 14 P5 15 14 1 0 14 032-082 Figure 13-6. Voice PCM Interface--Slave Mode (Mode 1) The timing requirements in Table 13-9 are valid on the following conditions of input slew and output load: * Rise and fall time range of inputs (SYNC, DIN) is tR/tF = 1.0 ns/6.5 ns * Capacitance load range of outputs (CLK, SYNC, DOUT) is CLoad = 1 pF/30 pF Table 13-9 lists the timing requirements for the voice PCM interface, mode 1. Table 13-9. Voice PCM Interface Timing Requirements (Mode 1) Notation Parameter Min Max Unit Voice/Bluetooth PCM Master Mode P3 P4 tsu(VDR-VCK) th(VDR-VCK) Setup time, PCM.VDR valid to PCM. VCK transition (1) 30 ns Hold time, PCM.VDR valid from PCM.VCK transition (1) 0 ns 1/(33 to 65 * Fs) ns Voice PCM Slave Mode P0 (3) P1 tw(VCK) Pulse duration, PCM.VCK high or low P3 tsu(VDR-VCK) Setup time, PCM.VDR valid to PCM. VCK transition (1) P4 th(VDR-VCK) P6 th(VFS-VCK) P7 (1) (2) (3) Cycle time, PCM.VCK (2) tc(VCK) tSU(VFS-VCK) 0.45 * P 0.55 * P ns 10 ns Hold time, PCM.VDR valid from PCM. VCK transition (1) 5 ns Hold time, PCM.VFS valid from PCM.VCK transition (1) 5 ns (1) 10 ns Setup time, PCM.VFS valid to PCM. VCK transition Writing on PCM.VCK rising edge (mode 1) and writing on PCM.VCK falling edge (mode 2). Fs = 8 or 16 kHz P = PCM.CLK period Table 13-10 lists the switching characteristics of the voice PCM interface, mode 1. Table 13-10. Voice PCM Interface Switching Characteristics (Mode 1) Notation Parameter Min Max Unit Voice/Bluetooth PCM Master Mode (1) (2) 150 P0 tc(VCK) Cycle time, PCM.VCK (1) P1 tw(VCK) Pulse duration, PCM.VCK high or low (2) 1/65 * Fs 0.45 * P 0.55 * P ns ns Fs = 8 or 16 kHz P = PCM.CLK period Timing Requirements and Switching Characteristics Submit Documentation Feedback Product Folder Link(s): TPS65950 Copyright (c) 2008-2011, Texas Instruments Incorporated TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 13-10. Voice PCM Interface Switching Characteristics (Mode 1) (continued) Notation Parameter P2 td(VCK-VFS) Delay time, PCM.VCK transition to PCM.VFS transition P5 td(VCL-VDX) Delay time, PCM.VCK transition to PCM.VDX transition (3) Min Max -10 10 + Pvoice Unit ns -10 10 ns 0 20 ns Voice PCM Slave Mode P5 (3) td(VCL-VDX) Delay time, PCM.VCK transition to PCM.VDX transition When TPS65950 is master, the PCM.VFS is delivered one cycle time of 26-MHz voice clock (Pvoice=38.4 ns) after the PCM.VCK rising edge. 13.6 JTAG Interfaces The TPS65950 Joint Test Action Group (JTAG) test access port (TAP) controller handles standard IEEE JTAG interfaces. This section describes the timing requirements for the tools used to test TPS65950 power management. The JTAG/TAP module provides a JTAG interface according to IEEE Standard 1149.1a. This interface uses the four I/O pins TMS, TCK, TDI, and TDO. The TMS, TCK, and TDI inputs contain a pullup device, which makes their state high when they are not driven. The output TDO is a 3-state output, which is high impedance except when data are shifted between TDI and TDO: * TCK is the test clock signal. * TMS is the test mode select signal. * TDI is the scan path input. * TDO is the scan path output. TMS and TDO are multiplexed at the top level with the GPIO0 and GPIO1 pins. The dedicated external test pin switches from functional mode (GPIO0 and GPIO1) to JTAG mode (TMS and TDO). The JTAG operations are controlled by a state-machine that follows the IEEE Standard 1149.1a state diagram. This state-machine is reset by the TPS65950 internal power-on reset (POR). A test mode is selected by writing a 6-bit word (instruction) into the instruction register and then accessing the related data register. Table 13-11 and Table 13-12 assume testing over the recommended operating conditions (see Figure 13-7). The input timing requirements are given by considering a rising or falling edge of 7 ns. The capacitive load is 35 pF. JL1 JL2 JL2 JTAG.TCK JL3 JL4 JL5 JL6 JTAG.TDI JTAG.TMS JL7 JTAG.TDO 032-083 Figure 13-7. JTAG Interface Timing Copyright (c) 2008-2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics Submit Documentation Feedback Product Folder Link(s): TPS65950 151 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 13-11. JTAG Interface Timing Requirements Notation Parameter Min Max Unit Clock JL1 tc(TCK) Cycle time, JTAG.TCK period JL2 tw(TCK) Pulse duration, JTAG.TCK high or low (1) 30 0.48*P ns 0.52*P ns Read Timing (1) JL3 tsu(TDIV-TCKH) Setup time, JTAG.TDI valid before JTAG.TCK high 8 ns JL4 th(TDIV-TCKH) Hold time, JTAG.TDI valid after JTAG.TCK high 5 ns JL5 tsu(TMSV-TCKH) Setup time, JTAG.TMS valid before JTAG.TCK high 8 ns JL6 th(TMSV-TCKH) Hold time, JTAG.TMS valid after JTAG.TCK high 5 ns P = JTAG.TCK clock period Table 13-12. JTAG Interface Switching Characteristics Notation Parameter Min Max 0 14 Unit Write Timing JL7 152 td(TCK-TDOV)) Delay time, JTAG, TCK active edge to JTAG.TDO valid Timing Requirements and Switching Characteristics Submit Documentation Feedback Product Folder Link(s): TPS65950 ns Copyright (c) 2008-2011, Texas Instruments Incorporated TPS65950 www.ti.com 14 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Debouncing Time Table 14-1 lists the debouncing functions. Table 14-1. Debouncing Time Debouncing Functions Block Programmable Debouncing Time Default Battery monitoring No 580 s 580 s Main battery low threshold detection (<2.7 V) No 60 s 60 s Main battery plug detection (with charger connected) No 60 s 60 s BCI (automatic charge) No 1 x 50 ms 1 x 50 ms BCI No 9 x 50 ms 9 x 50 ms Power No 125.6 s 125.6 s USB plug detection/VBUS precharge (same debouncing as charger plug) (1) BCI No 9 x 50 ms 9 x 50 ms Battery presence plug/unplug (1) BCI No 9 x 50 ms 9 x 50 ms BCI No 4 x 50 ms 4 x 50 ms Plug/unplug detection VBUS (2) USB Yes 0 to 250 ms (32/32,468-second steps) 28 ms Plug/unplug detection ID (3) USB Yes 0 to 250 ms (32/32,468-second steps) 50 ms Power Yes 0 to 250 ms 30 ms Thermistor No 60 s 60 s No 60 s 60 s No 31.25 ms 31.25 ms Main battery charged threshold (<3.2 V) Charger unplug detection (1) Charger plug detection (1) Debouncing functions interrupt generation debounce for charger plug Battery thermistor in/out of range (1) Debouncing functions interrupt generation debounce for VBUS and ID (4) Hot-die detection Thermal shutdown detection PWRON (5) Start/stop button Button reset No 60 s 60 s SIM card plug/unplug GPIO Yes 0 or 30 ms 1 ms 0 ms Headset detection (plug/unplug) GPIO Yes 0 or 30 ms 1 ms 0 ms MMC1/2 (plug/unplug) GPIO Yes 0 or 30 ms 1 ms 0 ms NRESWARM (1) (2) (3) (4) (5) According to the capture of the event, debouncing time can vary between 50 ms and 50 ms + dT (dT included in 0 < dT > 50 ms). Figure 14-1 shows and explains this possible variation of the debouncing time. Programmable in the VBUS_DEBOUNCE register Programmable in the ID_DEBOUNCE register Programmable in the RESERVED_E[2:0] CFG_VBUSDEB register The PWRON signal is debounced 1024 x CLK32K (maximum 1026 x CLK32K) falling edge in master mode. Debouncing Time Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 153 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Event1 Event2 31 ms 32K clock 50 ms 50-ms clock Event1 detected on 32K clock synchronized with 50-ms clock Event1 Debounced after 50 ms 50 ms dT Event2 Debounced after 50 ms + dT 50 ms + dT 032-084 Figure 14-1. Debouncing Sequence Chronogram Example Event 1 is correctly debounced after 50 ms. Event 2 is debounced after 50 ms + dT because the capture of the event is considered after the next rising edge of the 50-ms clock. 154 Debouncing Time Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 15 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 External Components Table 15-1 lists the external components of the TPS65950. Table 15-1. TPS65950 External Components Function Component Reference Value Note Link Power Supplies Capacitor CVDD1.IN 10 F Range 50% ESR minimum = 1 m ESR maximum = 20 m Taiyo Yuden: JMK212BJ106KD Capacitor CVDD1.OUT 10 F Range 50% ESR minimum = 1 m ESR maximum = 20 m Taiyo Yuden: JMK212BJ106KD Inductor LVDD1 1 H Range 30% DCR maximum = 100 m Capacitor CVDD2.IN 10 F Range 50% ESR minimum = 1 m ESR maximum = 20 m Taiyo Yuden: JMK212BJ106KD Capacitor CVDD2.OUT 10 F Range 50% ESR minimum = 1 m ESR maximum = 20 m Taiyo Yuden: JMK212BJ106KD Inductor LVDD2 1 H Range 30% DCR maximum = 100 m 10 F Range 50% ESR minimum = 1 m ESR maximum = 20 m Taiyo Yuden: JMK212BJ106KD VDD1 VDD2 Capacitor CVIO.IN Figure 4-1 Figure 4-1 Capacitor CVIO.OUT 10 F Range 50% ESR minimum = 1 m ESR maximum = 20 m Taiyo Yuden: JMK212BJ106KD Inductor LVVIO 1 H Range 30% DCR maximum = 100 m VRUSB_3V Capacitor CVUSB.3P1 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 300 m Figure 4-1 Figure 7-2 VRUSB_1V5 Capacitor CVINTUSB1P5.OUT 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Figure 4-1 Figure 7-2 VRUSB_1V8 Capacitor CVINTUSB1P8.OUT 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Figure 4-1 Figure 7-2 Capacitor CVDAC.IN 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m VIO VDAC Figure 4-1 Figure 4-1 Capacitor CVDAC.OUT 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m VPLLA3R Capacitor CVPLLA3R.IN 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Figure 4-1 VPLL1 Capacitor CVPLL1.OUT 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Figure 4-1 VPLL2/VDSI.CSI Capacitor CVPLL2.OUT 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Figure 4-1 External Components Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 155 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 15-1. TPS65950 External Components (continued) Function Component Capacitor Reference CVMMC1.IN Value Note 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m VMMC1 Capacitor CVMMC1.OUT 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Capacitor CVMMC2.IN 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m VMMC2 Link Figure 4-1 Figure 4-1 Capacitor CVMMC2.OUT 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m VSIM Capacitor CVSIM.OUT 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Figure 4-1 VAUX12S Capacitor CVAUX12S.IN 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Figure 4-1 VAUX1 Capacitor CVAUX1.OUT 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Figure 4-1 VAUX2 Capacitor CVAUX2.OUT 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Figure 4-1 VAUX3 Capacitor CVAUX3.OUT 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Figure 4-1 Capacitor CVAUX4.IN 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m VAUX4 Figure 4-1 Capacitor CVAUX4.OUT 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m VINT Capacitor CVINT.IN 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Figure 4-1 VINTANA1 Capacitor CVINTANA1.OUT 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Figure 4-1 VINTANA2 Capacitor CVINTANA2.OUT 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Figure 4-1 VINTDIG Capacitor CVINTDIG.OUT 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Figure 4-1 VBAT.USB Capacitor CVBAT.USB 1 F Range: 0.3 to 2.7 F ESR minimum = 20 m ESR maximum = 600 m Figure 7-2 Capacitor CVBUS.FC 2.2 F 40% ESR maximum = 20 m Capacitor CVBUS.IN Capacitor CVBUS USB CP 156 10 F 4.7 F 40% Figure 7-2 ESR maximum = 20 m External Components Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 15-1. TPS65950 External Components (continued) Function Component Reference Value Note Link MCPC 0.1 F Capacitor CTXAF Capacitor CRXAF 1 F Resistor RRTSO 22 /100 Diode DCTSI1 NNCD5.6J Diode DCTSI2 NNCD5.6J Diode DRTSO1 NNCD5.6J Diode DRTSO2 Figure 7-2 NNCD5.6J 32.768 kHz Capacitor CXIN 10 pF Capacitor CXOUT 10 pF Quartz X32.768kHz 32.768 kHz Range: 9 to 12.5 pF Figure 12-5 30 ppm (at 25C) 200 ppm (-40C to 85C) Audio Earpiece 8- hands-free right 8- hands-free left Headset left Headset right Headset microphone External class-D predriver left Capacitor CEAR Ferrite bead LHFR.M 100 pF NEC: N2012ZPS121 Figure 6-3 Ferrite bead LHFR.P NEC: N2012ZPS121 Capacitor CHFR 1 F Capacitor CHFR.M 1 nF Capacitor CHFR.P 1 nF Ferrite bead LHFL.M Ferrite bead LHFL.P Capacitor CHFL 1 F Capacitor CHFL.M 1 nF Capacitor CHFL.P Capacitor CS 22 F/47 F Resistor RS 0 to 33 Capacitor CI 47 pF Capacitor CS 22 F/47 F Resistor RS 0 to 33 Capacitor CI 47 pF Capacitor CHM.M 100 nF Capacitor CHM.P 100 nF Capacitor CHM.O 47 pF Resistor RB + RSB Capacitor CB Capacitor CPL.O Capacitor CPL 1 F Resistor RPL >15 k Resistor RPL.M >15 k Resistor RPL.O 10 k Capacitor CPL.M 1 F Figure 6-5 NEC: N2012ZPS121 NEC: N2012ZPS121 Figure 6-5 1 nF Figure 6-7 through Figure 6-10 Figure 6-7 through Figure 6-10 Figure 6-7 through Figure 6-10 2.2 k/2.7 k 0 to 200 pF If greater than 200 pF, a serial resistor is required for bias stability. 50 pF Figure 6-12 External Components Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 157 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com Table 15-1. TPS65950 External Components (continued) Function External class-D predriver right Vibrator H-bridge Main microphone (pseudodifferential mode) Submicrophone (pseudodifferential mode) Main microphone (differential mode) Component 158 Value CPR.O Capacitor CPR 1 F Resistor RPR >15 k Resistor RPR.M >15 k Resistor RPR.O 10 k Capacitor CPR.M 1 F Ferrite bead LV.M Ferrite bead LV.P Capacitor CV.V 1 F Capacitor CV.M 1 nF Capacitor CV.P 1 nF Capacitor CMM.M 100 nF Capacitor CMM.P 100 nF Capacitor CMM.O 47 pF Resistor RMM.O ~500 Resistor RMM.MP ~1.7 k Capacitor CMM.B 0 to 200 pF Capacitor CMS.M 100 nF Capacitor CMS.P 100 nF Capacitor CMS.O 47 pF Resistor RMS.O ~500 Resistor RMS.MP ~1.7 k Capacitor CMS.B 0 to 200 pF Capacitor CMM.M 100 nF Capacitor CMM.P 100 nF Capacitor CMM.PM 47 pF Capacitor CMM.O 47 pF Capacitor CMM.GM 47 pF Capacitor CMM.GP 47 pF Resistor RMM.BP 1 k Resistor RMM.GM 1 k Capacitor CMM.B 0 to 200 pF Capacitor CMS.M 100 nF Capacitor CMS.P 100 nF Capacitor CMS.PM 47 pF Capacitor CMS.O 47 pF CMS.GM 47 pF CMS.GP 47 pF Resistor RMS.BP 1 k Resistor RMS.GM 1 k Capacitor CMS.B Capacitor CVMIC1.OUT Submicrophone (differential Capacitor mode) Capacitor VMIC1 Reference Capacitor Note Link 50 pF Figure 6-12 BLM18BD221S1N BLM18BD221S1N 0 to 200 pF 1 F Figure 6-13 Figure 6-20 If greater than 200 pF, a serial resistor is required for bias stability. Figure 6-20 If greater than 200 pF, a serial resistor is required for bias stability. Figure 6-21 If greater than 200 pF, a serial resistor is required for bias stability. Figure 6-21 If greater than 200 pF, a serial resistor is required for bias stability. Range: 0.3 to 3.3 F ESR minimum = 20 m ESR maximum = 600 m External Components Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Table 15-1. TPS65950 External Components (continued) Function VMIC2 Silicon microphone Auxiliary left Auxiliary right Component Reference Value Capacitor CVMIC2.OUT 1 F Capacitor CSM 1 F Capacitor CSM.P 100 nF Capacitor CSM.M 100 nF Capacitor CSM.PG 47 nF Resistor RSM >500 Capacitor CAUXL 100 nF Capacitor CAUXL.M 47 pF Capacitor CAUXR 100 nF Capacitor CAUXR.M Note Link Range: 0.3 to 3.3 F ESR minimum = 20 m ESR maximum = 600 m Figure 6-24 Figure 6-25 47 pF LED Driver Resistor RLED.A 120 Requirerd for each LED Resistor RLED.B 160 k Requirerd for each LED Figure 10-1 Battery Charger ICTLAC1 ICTLUSB1 Capacitor CCOMPAC 100 nF Figure 8-1 Figure 8-2 Resistor RSCOMPAC 51 Figure 8-1 Figure 8-2 FET TAC Resistor RLimitAC FET T3 Capacitor Resistor FDJ1027P 700 k Figure 8-1 Figure 8-2 FDY100PZ Figure 8-2 C3 1 nF Figure 8-2 R3 100 k Figure 8-2 Capacitor CCOMPUSB 100 nF Resistor RSCOMPUSB FET TUSB 51 FDJ1027P Resistor RLimitUSB 500 k VPRECH Capacitor CPRECH 1 F VCCS Resistor RS 220 m Resistor RBCI.AUTO <10 k >140 k Capacitor CCV BCI AUTO VBAT Figure 8-1 Figure 8-2 Fairchild Figure 8-1 Fairchild Figure 8-1 Figure 8-1 For more information, see Table 8-2. 80 F Figure 8-3 Figure 8-1 I2C Bus--External Pullup I2C SmartReflex I2C control Resistor RPSR.SDA Resistor RPSR.SCL Resistor R Resistor RCNTL.SCL Pullups for various bus capacitances (CL) and I2C speeds (standard, fast, and HS) If CL = 10 pF: Standard = 118 k, Fast = 35.4 k, HS = 4.7 k If CL = 12 pF: Standard = 98.3 k, Fast = 29.5 k, HS = 3.9 k If CL = 50 pF: Standard = 23.6 k, Fast = 7.1 k, HS = 940 Section 13.3 If CL = 100 pF: Standard = 11.8 k, Fast = 3.54 k, HS = 470 If CL 12 pF, there is no need for an external pullup; the internal 3-k pullup can be used. If an external pullup is used, disable the internal 3-k pullup (reference the GPPUPDCTR1 register; see the TRM). External Components Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 159 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 16 www.ti.com TPS65950 Package 16.1 TPS65950 Standard Package Symbols Table 15-1 shows the TPS65950 printed device reference. Pin 1 indicator o YMLLLLS $ 032-001 Figure 16-1. Printed Device Reference Table 16-1 lists the symbols used in the TPS65950 nomenclature. Table 16-1. TPS65950 Nomenclature Description Field Prototype (X), preproduction (P), or qualified/production device (blank) (1) A Mask set version descriptor (initial silicon = blank, first silicon revision = A, second silicon revision = B,...) (2) YM LLLLS $ (1) (2) Meaning P Year month Lot code Fab planning code A blank in the symbol or part number is collapsed so there are no gaps between characters. Initial silicon version is ES1.0; first revision can be named ES2.0, ES1.1 or ES1.01, depending on the level of change. Note: Device name is a maximum of 10 characters. 16.2 Package Thermal Resistance Characteristics Table 16-2 lists the thermal resistance characteristics for the recommended package types used for the TPS65950. Table 16-2. TPS65950 Thermal Resistance Characteristics Package RJA(C/W) RJB(C/W) RJC(C/W) Board Type TPS65950 38.4 15.2 19.2 (1) 1S2P (2) 15.5 (1) 1S0P (2) TPS65950 (1) (2) 160 56.5 19.2 Not applicable. Because the POP package has a memory package on top, no heat sink can be used. The board types are defined by JEDEC (reference JEDEC standard JESD51-9, Test Board for Area Array Surface Mount Package Thermal Measurements). TPS65950 Package Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 16.3 Mechanical Data Figure 16-2 is the top view of the TPS65950 mechanical package. 6.00 0.40 T R P N M L K J H G F E D C B A 5 15 13 11 9 7 3 1 16 14 12 10 8 6 4 2 Top View 032-086 Figure 16-2. TPS65950 Mechanical Package Top View Figure 16-3 shows the ball size. 0.22 mm 0.26(0.05) mm 032-087 Figure 16-3. Ball Size TPS65950 Package Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 161 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com 16.4 ESD Specifications The device has built-in ESD protection to the limits specified below. It is recommended that the leads are shorted together, or the device placed in conductive foam, during storage or handling to prevent electrostatic damage. ESD Method (1) 162 Standard Reference Performance Human Body Model (HBM) EIA / JESD22-A114D 1000V for internal pins 2000V for external pins (1) Charge Device Model (CDM) EIA / JESD22-C101C 500V List of external pins: VAC, VBUS, DP/UART3.RXD, DN/UART3.TXD, ID, VPLL1.OUT, VMMC1.OUT, VMMC2.OUT, VSIM.OUT. TPS65950 Package Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com 17 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 Glossary ADC Analog-to-digital converter ALC Automatic level control ARIB Association of Radio Industries and Businesses ASIC Application-specific integrated circuit BCI Battery charger interface BGA Ball grid array BT Bluetooth BW Signal bandwidth CMOS Complementary metal oxide semiconductor Codec Coder/decoder CMT Cellular mobile telephone CPU Central processing unit DAC Digital-to-analog converter DBB Digital baseband DCR Direct current (dc) resistance DM Data manual DSP Digital signal processor DVFS Dynamic voltage and frequency scaling ESD Electrostatic discharge ESR Equivalent series resistance FET Field effect transistor FSR Full-scale range GP General-purpose GPIO General-purpose input/output hiZ High impedance HS High speed or high security HW Hardware I2C Inter-integrated circuit I2S Inter-IC sound IC Integrated circuit ICN Idle channel noise ID Identification IDDQ Direct drain quiescent current IF Interface IO or I/O Input/output JTAG Joint Test Action Group, IEEE 1149.1 standard LED Light emitting diode LDO Low-dropout regulator LJF Left-justified format Glossary Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 163 TPS65950 SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 www.ti.com LS Low speed MADC Monitoring analog-to-digital converter MCPC Mobile Computing Promotion Consortium MEMS Micro-electrical-mechanical system NA, N/A Not applicable NRZI Nonreturn to zero inverted OCP Open-core protocol OTG On-the-go PBGA Plastic ball grid array PCB Printed circuit board PCM Pulse-code modulation PD Pulldown PDM Pulse density modulated PFM Pulse frequency modulation PLL Phase-locked loop PMOS Portable media operating system POL Polarity POR Power-on reset PSRR Power supply ripple rejection PU Pullup PWL Pulse-width length PWT Pulse-width time PWM Pulse-width modulation RFID Radio frequency identification RJF Right-justified format RTC Real-time clock RX Receive SDI Serial display Interface SMPS Switch-mode power supply SNR Signal-to-noise ratio SRP Secure remote password SW Software SYNC/SYNCHRO Synchronization 164 SYS System TAP Test access port TBD To be defined TDM Time division multiplexing THRU Feed through TRM Technical reference manual TX Transmit Glossary Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 TPS65950 www.ti.com SWCS032E - OCTOBER 2008 - REVISED JANUARY 2011 UART Universal asynchronous receiver/transmitter ULPI UTMI+ low pin interface UPR Uninterrupted power rail USB Universal serial bus UTMI USB transceiver macrocell interface Glossary Copyright (c) 2008-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65950 165 PACKAGE OPTION ADDENDUM www.ti.com 14-Nov-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS65950A2ZXN ACTIVE NFBGA ZXN 209 260 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR TPS65950A2ZXNR ACTIVE NFBGA ZXN 209 2000 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR TPS65950A3ZXN ACTIVE NFBGA ZXN 209 260 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR TPS65950A3ZXNR ACTIVE NFBGA ZXN 209 2000 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR TPS65950BZXN OBSOLETE NFBGA ZXN 209 TBD Call TI Call TI TPS65950BZXNR OBSOLETE NFBGA ZXN 209 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 14-Nov-2011 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS65950A2ZXNR NFBGA ZXN 209 2000 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 TPS65950A3ZXNR NFBGA ZXN 209 2000 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65950A2ZXNR NFBGA ZXN 209 2000 336.6 336.6 31.8 TPS65950A3ZXNR NFBGA ZXN 209 2000 336.6 336.6 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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