Digital Delay Units series DDU-11 5 Taps ECL Interfaced Test Conditions: @ Input pulse-width: 150% of total delay. m@ Input pulse rise-time: =-6 ns. @ Input pulse voltage: .7V @ Rise-time measured from 20% to 80% of leading edge. m Delay time measured at 50% of leading edge. m All measurements taken Vee 5.2V and T, 25C. m Unless otherwise specified, all time-delays Features: are referenced to the input pin. m@ Input & Output Buffered @ 5 Equally Spaced Taps @ Fits in Standard 16 Pins DIP aco Specifications: ; t Total Delay Tolerance: + 5% or better, | f- + _- a ~ fo or 2 ns whichever is greater. m No. Taps: 5 equally spaced. e | m Rise-time: 2 ns typical. ' = Supply voltage: - 5.2V | = Operating Temperature: - 30C to 85C. abo Max. ; @ Power Dissipation: 200 mw typ. (no load). =: | \ t = Temperature coefficient: 100 PPM/C. m DC Parameters: See ECL-10K Logic Table on Page 6. 100 4 ca a] oo ca yo a 4 ' 5 8 Total Delay ootye fn +- mn nerf oe | 500 Part No. Delay Tap (ns) (ns) So oo + *DDU-11-5 4 tt 3 f.380 *DDU-11-10 8 2+ 4 m *DDU-11-20 16 4+ 5 + or case stand-offs DDU-11-25 25 5+ 10 DDU-11-50 50 10+20 Tapet 2 3 4 DDU-11-75 75 15+20 Pay 3 ie 48 DDU-11-100 100 20 + 2.0 Ve pone =i = DDU-11-150 150 30 + 2.0 oe | DDU-11-200 200 40 + 2.0 wot DDU-11-250 250 50+2.5 a DELAY LINE DDU-11-300 300 60 + 3.0 6RD *$ | DDU-11-400 400 80 + 4.0 ee 3 DDU-11-500 500 100 + 5.0 pull-down resistor on output tape pop ore, ded insite uni 'ull-down resistor on output taps not provided inside unit. Time delay measurements referenced to {st tap. 3.5 ns + 1 ns inherent delay. 3 Mt. Prospect Avenue, Clifton. New Jersey 07013 m (201) 773-2299 m FAX (201) 773-9672 = TWX 710-989-7008 14