Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TPS706 SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 TPS706 150-mA, 6.5-V, 1-A IQ Voltage Regulators with Enable 1 Features 3 Description * * * * * * * * * * The TPS706 series of linear voltage regulators are ultralow, quiescent current devices designed for power-sensitive applications. A precision band-gap and error amplifier provides 2% accuracy over temperature. Quiescent current of only 1 A makes these devices ideal solutions for battery-powered, always-on systems that require very little idle-state power dissipation. These devices have thermalshutdown, current-limit, and reverse-current protection for added safety. 1 Input Voltage Range: 2.7 V to 6.5 V Ultralow IQ: 1 A Reverse Current Protection Low ISHDN: 150 nA Supports 200-mA Peak Output Low Dropout: 245 mV at 50 mA 2% Accuracy Over Temperature Available in Fixed-Output Voltages: 1.2 V to 5 V Thermal Shutdown and Overcurrent Protection Packages: SOT-23-5, WSON-6 2 Applications * * * * * * * These regulators can be put into shutdown mode by pulling the EN pin low. The shutdown current in this mode goes down to 150 nA, typical. The TPS706 series is available in WSON-6 and SOT23-5 packages. Smartphones and Tablets Portable and Battery-Powered Applications Camera Modules Set-Top Boxes Wearables Solid State Drives Medical Equipment Device Information(1) PART NUMBER TPS706 PACKAGE BODY SIZE (NOM) SOT-23 (5) 2.90 mm x 1.60 mm WSON (6) 2.00 mm x 2.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. space space space Typical Application Circuit GND Current vs VIN and Temperature 3 IN VOUT OUT 1 mF 2.2 mF GND EN TPS706 NC TJ = -40C TJ = +25C TJ = +85C TJ = +125C 2.8 Ground Pin Current (PA) VIN 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 4 4.25 4.5 4.75 5 5.25 5.5 5.75 Input Voltage (V) 6 6.25 6.5 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS706 SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 Functional Block Diagram ....................................... 11 7.3 Feature Description................................................. 11 7.4 Device Functional Modes........................................ 13 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Application .................................................. 15 9 Power Supply Recommendations...................... 15 10 Layout................................................................... 16 10.1 Layout Guidelines ................................................. 16 10.2 Layout Examples................................................... 18 11 Device and Documentation Support ................. 19 11.1 11.2 11.3 11.4 11.5 Device Support...................................................... Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 19 19 19 19 12 Mechanical, Packaging, and Orderable Information ........................................................... 19 4 Revision History Changes from Original (October 2014) to Revision A * 2 Page Made changes to product preview data sheet; released as Production Data ........................................................................ 1 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 TPS706 www.ti.com SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 5 Pin Configuration and Functions DBV Package SOT-23-5 (Top View) 1 GND 2 5 3 EN 4 OUT NC OUT 1 NC 2 GND 3 GND IN DRV Package WSON-6 (Top View) 6 IN 5 NC 4 EN Pin Functions PIN NO. I/O DESCRIPTION 3 I Enable pin. Driving this pin high enables the device. Driving this pin low puts the device into low current shutdown. This pin can be left floating to enable the device. The maximum voltage must remain below 6.5 V. 3 2 -- 6 1 I NC 2, 5 4 -- No internal connection OUT 1 5 O Regulated output voltage. Connect a small 2.2-F or greater ceramic capacitor from this pin to ground to assure stability. -- -- The thermal pad is electrically connected to the GND node. Connect to the GND plane for improved thermal performance. NAME DRV DBV EN 4 GND IN Thermal pad Ground Unregulated input to the device Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 3 TPS706 SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings specified at TJ = -40C to 125C, unless otherwise noted; all voltages are with respect to GND (1) Voltage Maximum output current MIN MAX UNIT VIN -0.3 7 V VEN -0.3 7 V VOUT -0.3 7 V IOUT Internally limited PDISS See Thermal Information Output short-circuit duration Indefinite Continuous total power dissipation Junction temperature, TJ -55 150 C Storage temperature, Tstg -55 150 C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT 2000 Charged device model (CDM), per JEDEC specification JESD22-C101 (2) V 500 JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted) MIN NOM MAX VIN Input voltage 2.7 6.5 VOUT Output voltage 1.2 5 IOUT Output current 0 150 VEN Enable voltage 0 CIN Input capacitor 0 1 COUT Output capacitor 2 2.2 TJ Operating junction temperature 6.5 -40 UNIT V V mA V F 47 F 125 C 6.4 Thermal Information TPS706 THERMAL METRIC (1) DBV DRV 5 PINS 6 PINS RJA Junction-to-ambient thermal resistance 212.1 73.1 RJC(top) Junction-to-case (top) thermal resistance 78.5 97.0 RJB Junction-to-board thermal resistance 39.5 42.6 JT Junction-to-top characterization parameter 2.86 2.9 JB Junction-to-board characterization parameter 38.7 42.9 RJC(bot) Junction-to-case (bottom) thermal resistance N/A 12.8 (1) 4 UNIT C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 TPS706 www.ti.com SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 6.5 Electrical Characteristics At TJ = -40C to 125C, VIN = VOUT(nom) + 1 V or 2.7 V (whichever is greater), IOUT = 1 mA, VEN = 2 V, and CIN = COUT = 2.2-F ceramic, unless otherwise noted. Typical values are at TJ = 25C. PARAMETER TEST CONDITIONS VIN Input voltage range VOUT Output voltage range VOUT(accuracy) VOUT DC output accuracy MIN Output current limit (3) IGND Ground pin current ISHDN Shutdown current VOUT 3.3 V, TJ = -40C to 85C -1% 1% 3 10 mV 20 50 mV 295 650 mV 975 1540 mV 320 500 mA IOUT = 0 mA, VOUT 3.3 V 1.3 2.55 A IOUT = 150 mA 350 A VEN 0.4 V, VIN = 2.7 V 150 nA 80 dB 62 dB 52 dB 190 VRMS 2.8 V VOUT 3.3 V, IOUT = 50 mA 2.8 V VOUT 3.3 V, IOUT = 150 mA VOUT = 0.9 x VOUT(nom) 200 f = 10 Hz PSRR Power-supply rejection ratio f = 100 Hz f = 1 kHz Vn Output noise voltage VEN(HI) IEN IREV 0.9 Enable pin high (disabled) 0 EN pin current EN = 1.0 V, VIN = 5.5 V Reverse current (flowing out of IN pin) Reverse current (flowing into OUT pin) Thermal shutdown temperature TJ Operating junction temperature (1) (2) (3) BW = 10 Hz to 100 kHz, IOUT = 10 mA, VIN = 2.7 V, VOUT = 1.2 V Enable pin high (enabled) TSD V 5.0 2% VIN = VOUT(nom) + 1.5 V or 3 V (whichever is greater), 100 A IOUT 150 mA I(CL) V 1.2 Load regulation UNIT 6.5 -2% (VOUT(nom) + 1 V, 2.7 V) VIN 6.5 V Dropout voltage (1) (2) MAX VOUT < 3.3 V Line regulation VDO TYP 2.7 V 0.4 V 300 nA VOUT = 3 V, VIN = VEN = 0 V 10 nA VOUT = 3 V, VIN = VEN = 0 V 100 nA Shutdown, temperature increasing 158 C Reset, temperature decreasing 140 C -40 125 C VDO is measured with VIN = 0.98 x VOUT(nom). Dropout is only valid when VOUT 2.8 V because of the minimum input voltage limits. Measured with VIN = VOUT + 3 V for VOUT 2.5 V. Measured with VIN = VOUT + 2.5 V for VOUT > 2.5 V. 6.6 Timing Requirements At TJ = -40C to 125C, VIN = VOUT(nom) + 1 V or 2.7 V (whichever is greater), RL = 47 , VEN = 2 V, and CIN = COUT = 2.2-F ceramic, unless otherwise noted. Typical values are at TJ = 25C. PARAMETER tSTR (1) Start-up time (1) MIN TYP MAX UNIT VOUT(nom) 3.3 V 200 600 s VOUT > 3.3 V 500 1500 s Startup time = time from EN assertion to 0.95 x VOUT(nom) and load = 47 . Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 5 TPS706 SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 www.ti.com 6.7 Typical Characteristics Over operating temperature range (TJ = -40C to 125C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 F, and VIN = VOUT(nom) + 1 V or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25C. 3.31 1.205 TJ = -40C TJ = +25C TJ = +85C TJ = +125C 1.204 3.306 1.202 Output Voltage (V) Output Voltage (V) 1.203 1.201 1.2 1.199 1.198 3.304 3.302 3.3 3.298 3.296 1.197 3.294 1.196 3.292 1.195 2.5 3 3.5 4 4.5 5 Input Voltage (V) 5.5 6 TJ = -40C TJ = +25C TJ = +85C TJ = +125C 3.308 3.29 4.25 6.5 4.5 4.75 5 TPS70612 Figure 1. 1.2-V Line Regulation vs VIN and Temperature 6.5 Figure 2. 3.3-V Line Regulation vs VIN and Temperature TJ = -40C TJ = +25C TJ = +85C TJ = +125C 1.2 1.1975 1.195 1.1925 1.19 1.1875 TJ = -40C TJ = +25C TJ = +85C TJ = +125C 3.304 3.3 Output Voltage (V) Output Voltage (V) 6.25 3.308 1.2025 3.296 3.292 3.288 3.284 1.185 3.28 1.1825 3.276 1.18 3.272 0 20 40 60 80 100 Output Current (mA) 120 140 0 20 40 TPS70612 60 80 100 Input Current (mA) 120 140 TPS70633 Figure 3. 1.2-V Load Regulation vs IOUT and Temperature Figure 4. 3.3-V Load Regulation vs IOUT and Temperature 1.205 500 480 460 440 420 400 380 360 340 320 300 280 260 240 220 200 3.5 IOUT = 10 mA IOUT = 150 mA 1.2025 1.2 1.1975 Current Limit (mA) Output Voltage (V) 6 TPS70633 1.205 1.195 1.1925 1.19 1.1875 1.185 1.1825 1.18 -40 -20 0 20 40 60 80 100 Junction Temperature (qC) 120 140 TPS70612 Figure 5. VOUT vs Temperature 6 5.25 5.5 5.75 Input Voltage (V) TJ = -40C TJ = +25C TJ = +85C TJ = +125C 4 4.5 5 5.5 Input Voltage (V) 6 6.5 TPS70612 Figure 6. 1.2-V Current Limit vs VIN and Temperature Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 TPS706 www.ti.com SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 Typical Characteristics (continued) 440 TJ = -40C 430 TJ = +25C 420 TJ = +85C 410 TJ = +125C 400 390 380 370 360 350 340 330 320 310 300 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6 6.1 6.2 6.3 6.4 6.5 Input Voltage (V) 3 Ground Pin Current (PA) Current Limit (mA) Over operating temperature range (TJ = -40C to 125C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 F, and VIN = VOUT(nom) + 1 V or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25C. TJ = +125 qC TJ = +85 qC TJ = +25 qC TJ = -40 qC 2.5 2 1.5 1 0.5 2.5 3 3.5 4 4.5 5 Input Voltage (V) TPS70633 Figure 7. 3.3-V Current Limit vs VIN and Temperature 6.5 Figure 8. GND Current vs VIN and Temperature 800 TJ = -40C TJ = +25C TJ = +85C TJ = +125C 2.6 TJ = +125 qC TJ = +85 qC TJ = +25 qC TJ = -40 qC 700 Ground Pin Current (PA) 2.8 Ground Pin Current (PA) 6 TPS70612 3 2.4 2.2 2 1.8 1.6 600 500 400 300 200 1.4 100 1.2 0 1 4 4.25 4.5 4.75 5 5.25 5.5 5.75 Input Voltage (V) 6 6.25 0 6.5 25 TPS70633, EN = open 125 150 Figure 10. GND Current vs IOUT and Temperature 90 0.6 0.5 50 75 100 Output Current (mA) TPS70612 Figure 9. GND Current vs VIN and Temperature TJ = +125 qC TJ = +85 qC TJ = +25 qC TJ = -40 qC 80 70 60 0.4 PSRR (dB) Ground Pin Current (PA) 5.5 0.3 50 40 30 0.2 20 0.1 10 0 2.5 3 3.5 4 4.5 5 Input Voltage (V) 5.5 6 6.5 0 1E+1 Shutdown current, TPS70612 1E+2 1E+3 1E+4 1E+5 Frequency (Hz) 1E+6 1E+7 VOUT = 2.8 V, VIN = 3.8 V, COUT = 2.2 F Figure 11. Shutdown Current vs VIN and Temperature Figure 12. Power-Supply Rejection Ratio vs Frequency Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 7 TPS706 SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 www.ti.com Typical Characteristics (continued) 7 6.5 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 1E+1 140 130 Time (s) Noise (PV/Hz) Over operating temperature range (TJ = -40C to 125C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 F, and VIN = VOUT(nom) + 1 V or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25C. 120 110 100 50 35 20 5 1E+2 1E+3 Frequency (Hz) 1E+4 1E+5 25 40 55 70 85 100 115 130 Temperature (C) C019 TPS70612 VOUT = 2.8 V Figure 14. Start-Up Time vs Temperature Figure 13. Noise Channel 2 (200 mV / div) Channel 2 (200 mV / div) Channel 4 (50 mA / div) Channel 4 (100 mA / div) Time (100 ms / div) Time (500 ms / div) Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V Figure 15. TPS70612 Load Transient (0 mA to 50 mA) Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V Figure 16. TPS70612 Load Transient (1 mA to 150 mA) Channel 2 (200 mV / div) Channel 2 (200 mV / div) Channel 4 (50 mA / div) Channel 4 (100 mA / div) Time (100 ms / div) Time (10 ms / div) Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V Figure 17. TPS70612 Load Transient (50 mA to 0 mA) 8 10 Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V Figure 18. TPS70612 Load Transient (50 mA to 150 mA) Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 TPS706 www.ti.com SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 Typical Characteristics (continued) Over operating temperature range (TJ = -40C to 125C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 F, and VIN = VOUT(nom) + 1 V or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25C. Channel 2 (200 mV / div) Channel 2 (200 mV / div) Channel 4 (50 mA / div) Channel 4 (100 mA / div) Time (500 ms / div) Time (100 ms / div) Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V Figure 19. TPS70633 Load Transient (0 mA to 50 mA) Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V Figure 20. TPS70633 Load Transient (1 mA to 150 mA) Channel 2 (200 mV / div) Channel 2 (200 mV / div) Channel 4 (50 mA / div) Channel 4 (50 mA / div) Time (500 ms / div) Time (10 ms / div) Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V Figure 21. TPS70633 Load Transient (50 mA to 0 mA) Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V Figure 22. TPS70633 Load Transient (50 mA to 150 mA) Channel 2 (50 mV / div) Channel 2 (50 mV / div) Channel 4 (2 V / div) Channel 4 (2 V / div) Time (50 ms / div) Time (50 ms / div) Channel 2 = VOUT, channel 4 = VIN, IOUT = 10 mA Channel 2 = VOUT, channel 4 = VIN, IOUT = 50 mA Figure 23. TPS70612 Line Transient (2.7 V to 3.7 V) Figure 24. TPS70612 Line Transient (2.7 V to 3.7 V) Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 9 TPS706 SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 www.ti.com Typical Characteristics (continued) Over operating temperature range (TJ = -40C to 125C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 F, and VIN = VOUT(nom) + 1 V or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25C. Channel 2 (50 mV / div) Channel 2 (50 mV / div) Channel 4 (2 V / div) Channel 4 (2 V / div) Time (50 ms / div) Time (50 ms / div) Channel 2 = VOUT, channel 4 = VIN, IOUT = 10 mA Channel 2 = VOUT, channel 4 = VIN, IOUT = 50 mA Figure 25. TPS70633 Line Transient (4.3 V to 5.3 V) Figure 26. TPS70633 Line Transient (4.3 V to 5.3 V) Channel 2 (1 V / div) Channel 2 (1 V / div) Channel 1 (500 mV / div) Channel 1 (1 V / div) Time (50 ms / div) Time (500 ms / div) Channel 1 = EN, channel 2 = VOUT, VIN = 4.3 V, COUT = 2.2 F, TPS70633 Figure 27. Power-Up with Enable Channel 1 = VIN, channel 2 = VOUT, IOUT = 3 mA, TPS70633 Figure 28. Power-Up and Power-Down Response Channel 2 (1 V / div) Channel 1 (1 V / div) Time (500 ms / div) Channel 1 = VIN, channel 2 = VOUT, IOUT = 150 mA, TPS70633 Figure 29. Power-Up and Power-Down Response 10 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 TPS706 www.ti.com SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 7 Detailed Description 7.1 Overview The TPS706 series are ultralow quiescent current, low-dropout (LDO) linear regulators. The TPS706 offers reverse current protection to block any discharge current from the output into the input. The TPS706 also features current limit and thermal shutdown for reliable operation. 7.2 Functional Block Diagram OUT IN Current Limit Thermal Shutdown EN Bandgap Logic Device GND 7.3 Feature Description 7.3.1 Undervoltage Lockout (UVLO) The TPS706 uses an undervoltage lockout (UVLO) circuit to keep the output shut off until the internal circuitry operates properly. 7.3.2 Shutdown The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI) (0.9 V, minimum). Turn off the device by forcing the EN pin to drop below 0.4 V. If shutdown capability is not required, connect EN to IN. 7.3.3 Reverse Current Protection The TPS706 has integrated reverse current protection. Reverse current protection prevents the flow of current from the OUT pin to the IN pin when output voltage is higher than input voltage. The reverse current protection circuitry places the power path in high impedance when the output voltage is higher than the input voltage. This setting reduces leakage current from the output to the input to 10 nA, typical. The reverse current protection is always active regardless of the enable pin logic state or if the OUT pin voltage is greater than 1.8 V. Reverse current can flow if the output voltage is less than 1.8 V and if input voltage is less than the output voltage. If voltage is applied to the input pin, then the maximum voltage that can be applied to the OUT pin is the lower of three times the nominal output voltage or 6.5 V. For example, if the 1.2-V output voltage version is used, then the maximum reverse bias voltage that can be applied to the OUT pin is 3.6 V. If the 3.3-V output voltage version is used, then the maximum reverse bias voltage that can be applied to the OUT pin is 6.5 V. Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 11 TPS706 SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 www.ti.com Feature Description (continued) 7.3.4 Internal Current Limit The TPS706 internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output voltage is not regulated, and can be measured as (VOUT = ILIMIT x RLOAD). The PMOS pass transistor dissipates [(VIN - VOUT) x ILIMIT] until a thermal shutdown is triggered and the device turns off. When cool, the device is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and thermal shutdown; see the Thermal Information section for more details. The TPS706 is characterized over the recommended operating output current range up to 150 mA. The internal current limit begins to limit the output current at a minimum of 200 mA of output current. 7.3.5 Thermal Protection Thermal protection disables the output when the junction temperature rises to approximately 158C, allowing the device to cool. When the junction temperature cools to approximately 140C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, limit junction temperature to 125C, maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection must trigger at least 35C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of 125C at the highest expected ambient temperature and worst-case load. The TPS706 internal protection circuitry is designed to protect against overload conditions. This circuitry is not intended to replace proper heatsinking. Continuously running the TPS706 into thermal shutdown degrades device reliability. 12 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 TPS706 www.ti.com SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 7.4 Device Functional Modes 7.4.1 Normal Operation The device regulates to the nominal output voltage under the following conditions: * The input voltage is at least as high as VIN(min). * The input voltage is greater than the nominal output voltage added to the dropout voltage. * The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased below the enable falling threshold. * The output current is less than the current limit. * The device junction temperature is less than the maximum specified junction temperature. 7.4.2 Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device is in the linear region and no longer controls the current through the LDO. Line or load transients in dropout can result in large output voltage deviations. 7.4.3 Disabled The device is disabled under the following conditions: * The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising threshold. * The device junction temperature is greater than the thermal shutdown temperature. Table 1 shows the conditions that lead to the different modes of operation. Table 1. Device Functional Mode Comparison PARAMETER OPERATING MODE VIN VEN IOUT TJ Normal mode VIN > VOUT(nom) + VDO and VIN > VIN(min) VEN > VEN(HI) IOUT < ILIM TJ < 125C Dropout mode VIN(min) < VIN < VOUT(nom) + VDO VEN > VEN(HI) -- TJ < 125C -- VEN < VEN(low) -- TJ > 158C Disabled mode (any true condition disables the device) Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 13 TPS706 SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS706 consumes low quiescent current and delivers excellent line and load transient performance. This performance, combined with low noise and good PSRR with little (VIN - VOUT) headroom, makes these devices ideal for RF portable applications, current limit, and thermal protection. The TPS706 devices are specified from -40C to 125C. 8.1.1 Input and Output Capacitor Considerations The TPS706 devices are stable with output capacitors with an effective capacitance of 2.0 F or greater for output voltages below 1.5 V. For output voltages equal or greater than 1.5 V, the minimum effective capacitance for stability is 1.5 F. The maximum capacitance for stability is 47 F. The equivalent series resistance (ESR) of the output capacitor must be between 0 and 0.2 for stability. The effective capacitance is the minimum capacitance value of a capacitor after taking into account variations resulting from tolerances, temperature, and dc bias effects. X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal variation in value and ESR over temperature. Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-F to 2.2-F capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple rejection, and PSRR. 8.1.2 Dropout Voltage The TPS706 uses a PMOS pass transistor to achieve low dropout. When (VIN - VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO approximately scales with the output current because the PMOS device functions like a resistor in dropout. The ground pin current of many linear voltage regulators increases substantially when the device is operated in dropout. This increase in ground pin current while operating in dropout can be several orders of magnitude larger than when the device is not in dropout. The TPS706 employs a special control loop that limits the increase in ground pin current while operating in dropout. This functionality allows for the most efficient operation while in dropout conditions that can greatly increase battery run times. 8.1.3 Transient Response As with any regulator, increasing the output capacitor size reduces over- and undershoot magnitude, but increases transient response duration. 14 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 TPS706 www.ti.com SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 8.2 Typical Application VIN IN VOUT OUT 1 mF 2.2 mF GND TPS70633 EN NC Figure 30. 3.3-V, Low-IQ Rail 8.2.1 Design Requirements Table 2 summarizes the design requirements for Figure 30. Table 2. Design Requirements for a 3.3-V, Low-IQ Rail Application PARAMETER DESIGN SPECIFICATION VIN 4.3 V VOUT 3.3 V I(IN) (no load) < 5 A IOUT (max) 150 mA 8.2.2 Detailed Design Procedure Select a 2.2-F, 10-V X7R output capacitor to satisfy the minimum output capacitance requirement with a 3.3-V dc bias. Select a 1.0-F, 6.3-V X7R input capacitor to provide input noise filtering and eliminate high-frequency voltage transients. 8.2.3 Application Curves Channel 2 (200 mV / div) Channel 2 (1 V / div) Channel 1 (500 mV / div) Channel 4 (50 mA / div) Time (500 ms / div) Time (50 ms / div) Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V Channel 1 = EN, channel 2 = VOUT, VIN = 4.3 V, COUT = 2.2 F, TPS70633 Figure 31. TPS70633 Load Transient (50 mA to 150 mA) Figure 32. Power-Up with Enable 9 Power Supply Recommendations This device is designed to operate with an input supply range of 2.7 V to 6.5 V. The input voltage range must provide adequate headroom in order for the device to have a regulated output. This input supply must be wellregulated and stable. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance. Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 15 TPS706 SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 www.ti.com 10 Layout 10.1 Layout Guidelines 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance Input and output capacitors must be placed as close to the device pins as possible. To improve ac performance (such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the device GND pin. In addition, the output capacitor ground connection must be connected directly to the device GND pin. 10.1.2 Power Dissipation The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) can be approximated by the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 1. PD = (VIN - VOUT) x IOUT (1) Figure 33 shows the maximum ambient temperature versus the power dissipation of the TPS706. This figure assumes the device is soldered on a JEDEC standard, high-K layout with no airflow over the board. Actual board thermal impedances vary widely. If the application requires high power dissipation, having a thorough understanding of the board temperature and thermal impedances is helpful to ensure the TPS706 does not operate above a junction temperature of 125C. Maximum Ambient Temperature (qC) 125 TPS706, DBV Package TPS706, DRV Package 100 75 50 0 0.2 0.4 0.6 Power Dissipation (W) 0.8 1 Figure 33. Maximum Ambient Temperature vs Device Power Dissipation 16 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 TPS706 www.ti.com SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 Layout Guidelines (continued) Estimating the junction temperature can be done by using the thermal metrics JT and JB, shown in the Thermal Information. These metrics are a more accurate representation of the heat transfer characteristics of the die and the package than RJA. The junction temperature can be estimated with Equation 2. YJT: TJ = TT + YJT * PD YJB: TJ = TB + YJB * PD where: * * * PD is the power dissipation shown by Equation 1, TT is the temperature at the center-top of the IC package, TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface. (2) NOTE Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared thermometer). For more information about measuring TT and TB, see the application note Using New Thermal Metrics (SBVA025), available for download at www.ti.com. Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 17 TPS706 SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 www.ti.com 10.2 Layout Examples Input Trace Input Capacitor Enable Trace Input Ground Plane NC IN Grounded Thermal Plane EN Thermal Pad OUT NC GND Output Trace Grounded Thermal Plane Output Ground Plane Output Capacitor Designates thermal vias. Figure 34. WSON Layout Example VOUT VIN OUT IN CIN COUT GND EN NC GND PLANE Represents via used for application-specific connections. Figure 35. SOT23-5 Layout Example 18 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 TPS706 www.ti.com SBVS245A - OCTOBER 2014 - REVISED MARCH 2015 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Spice Models Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TPS706 is available through the product folders under Simulation Models. 11.1.2 Device Nomenclature Table 3. Device Nomenclature (1) PRODUCT TPS706xx yyy z (1) VOUT xx is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V). yyy is the package designator. z is the tape and reel quantity (R = 3000, T = 250). For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. 11.2 Documentation Support 11.2.1 Related Documentation SBVU002 -- DEM-SOT23LDO Demonstration Fixture SBVA025 -- Using New Thermal Metrics 11.3 Trademarks All trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS706 19 PACKAGE OPTION ADDENDUM www.ti.com 2-Jun-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS70612DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJC TPS70612DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJC TPS70612DRVR ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJC TPS70612DRVT ACTIVE WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJC TPS70615DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIW TPS70615DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIW TPS70615DRVR ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIW TPS70615DRVT ACTIVE WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIW TPS70618DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIX TPS70618DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIX TPS70618DRVR ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIX TPS70618DRVT ACTIVE WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIX TPS70625DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIY TPS70625DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIY TPS70625DRVR ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIY TPS70625DRVT ACTIVE WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIY TPS70628DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJU Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 2-Jun-2016 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS70628DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJU TPS70628DRVR ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJU TPS70628DRVT ACTIVE WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJU TPS70630DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIZ TPS70630DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIZ TPS70630DRVR ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIZ TPS70630DRVT ACTIVE WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIZ TPS70633DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJA TPS70633DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJA TPS70633DRVR ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJA TPS70633DRVT ACTIVE WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 2-Jun-2016 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 2-Jun-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ TPS70612DBVR SOT-23 3000 178.0 9.0 DBV 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.3 3.2 1.4 4.0 8.0 Q3 TPS70612DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TPS70612DRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS70612DRVT WSON DRV 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS70615DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TPS70615DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TPS70615DRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS70615DRVT WSON DRV 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS70618DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TPS70618DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TPS70618DRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS70618DRVT WSON DRV 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS70625DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TPS70625DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TPS70625DRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS70625DRVT WSON DRV 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS70628DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TPS70628DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Jun-2016 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS70628DRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS70628DRVT WSON DRV 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS70630DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TPS70630DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TPS70630DRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS70630DRVT WSON DRV 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS70633DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TPS70633DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TPS70633DRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS70633DRVT WSON DRV 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS70612DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS70612DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS70612DRVR WSON DRV 6 3000 210.0 185.0 35.0 TPS70612DRVT WSON DRV 6 250 210.0 185.0 35.0 TPS70615DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS70615DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS70615DRVR WSON DRV 6 3000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Jun-2016 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS70615DRVT WSON DRV 6 250 210.0 185.0 35.0 TPS70618DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS70618DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS70618DRVR WSON DRV 6 3000 210.0 185.0 35.0 TPS70618DRVT WSON DRV 6 250 210.0 185.0 35.0 TPS70625DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS70625DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS70625DRVR WSON DRV 6 3000 210.0 185.0 35.0 TPS70625DRVT WSON DRV 6 250 210.0 185.0 35.0 TPS70628DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS70628DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS70628DRVR WSON DRV 6 3000 210.0 185.0 35.0 TPS70628DRVT WSON DRV 6 250 210.0 185.0 35.0 TPS70630DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS70630DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS70630DRVR WSON DRV 6 3000 210.0 185.0 35.0 TPS70630DRVT WSON DRV 6 250 210.0 185.0 35.0 TPS70633DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS70633DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS70633DRVR WSON DRV 6 3000 210.0 185.0 35.0 TPS70633DRVT WSON DRV 6 250 210.0 185.0 35.0 Pack Materials-Page 3 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com GENERIC PACKAGE VIEW DRV 6 WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4206925/F PACKAGE OUTLINE DRV0006A WSON - 0.8 mm max height SCALE 5.500 PLASTIC SMALL OUTLINE - NO LEAD 2.1 1.9 B A PIN 1 INDEX AREA 2.1 1.9 0.8 0.7 C SEATING PLANE 0.08 C (0.2) TYP 0.05 0.00 1 0.1 EXPOSED THERMAL PAD 3 2X 1.3 4 7 1.6 0.1 6 1 4X 0.65 PIN 1 ID (OPTIONAL) 6X 6X 0.3 0.2 0.35 0.25 0.1 0.05 C A C B 4222173/B 04/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT DRV0006A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.45) (1) 1 7 6 6X (0.3) (1.6) SYMM (1.1) 4X (0.65) 4 3 SYMM (R0.05) TYP ( 0.2) VIA TYP (1.95) LAND PATTERN EXAMPLE SCALE:25X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4222173/B 04/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. www.ti.com EXAMPLE STENCIL DESIGN DRV0006A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.45) 1 SYMM METAL 7 6 6X (0.3) (0.45) SYMM 4X (0.65) (0.7) 4 3 (R0.05) TYP (1) (1.95) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD #7 88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:30X 4222173/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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