Input Voltage (V)
Ground Pin Current (PA)
4 4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
TPS706
EN
IN OUT
VIN VOUT
1 Fm2.2 Fm
GND
NC
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TPS706 150-mA, 6.5-V, 1-µA I
Q
Voltage Regulators with Enable
1 Features 3 Description
The TPS706 series of linear voltage regulators are
1• Input Voltage Range: 2.7 V to 6.5 V ultralow, quiescent current devices designed for
• Ultralow IQ: 1 μApower-sensitive applications. A precision band-gap
• Reverse Current Protection and error amplifier provides 2% accuracy over
temperature. Quiescent current of only 1 µA makes
• Low ISHDN: 150 nA these devices ideal solutions for battery-powered,
• Supports 200-mA Peak Output always-on systems that require very little idle-state
• Low Dropout: 245 mV at 50 mA power dissipation. These devices have thermal-
shutdown, current-limit, and reverse-current
• 2% Accuracy Over Temperature protection for added safety.
• Available in Fixed-Output Voltages: 1.2 V to 5 V These regulators can be put into shutdown mode by
• Thermal Shutdown and Overcurrent Protection pulling the EN pin low. The shutdown current in this
• Packages: SOT-23-5, WSON-6 mode goes down to 150 nA, typical.
2 Applications The TPS706 series is available in WSON-6 and SOT-
23-5 packages.
• Smartphones and Tablets
• Portable and Battery-Powered Applications Device Information(1)
• Camera Modules PART NUMBER PACKAGE BODY SIZE (NOM)
• Set-Top Boxes SOT-23 (5) 2.90 mm × 1.60 mm
TPS706 WSON (6) 2.00 mm × 2.00 mm
• Wearables
• Solid State Drives (1) For all available packages, see the orderable addendum at
the end of the datasheet.
• Medical Equipment space
space
space
Typical Application Circuit GND Current vs VIN and Temperature
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS706
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Table of Contents
7.3 Feature Description................................................. 11
1 Features.................................................................. 17.4 Device Functional Modes........................................ 13
2 Applications ........................................................... 18 Application and Implementation ........................ 14
3 Description............................................................. 18.1 Application Information............................................ 14
4 Revision History..................................................... 28.2 Typical Application.................................................. 15
5 Pin Configuration and Functions......................... 39 Power Supply Recommendations...................... 15
6 Specifications......................................................... 410 Layout................................................................... 16
6.1 Absolute Maximum Ratings ...................................... 410.1 Layout Guidelines ................................................. 16
6.2 ESD Ratings.............................................................. 410.2 Layout Examples................................................... 18
6.3 Recommended Operating Conditions....................... 411 Device and Documentation Support................. 19
6.4 Thermal Information.................................................. 411.1 Device Support...................................................... 19
6.5 Electrical Characteristics........................................... 511.2 Documentation Support ........................................ 19
6.6 Timing Requirements................................................ 511.3 Trademarks........................................................... 19
6.7 Typical Characteristics.............................................. 611.4 Electrostatic Discharge Caution............................ 19
7 Detailed Description............................................ 11 11.5 Glossary................................................................ 19
7.1 Overview................................................................. 11 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram....................................... 11 Information........................................................... 19
4 Revision History
Changes from Original (October 2014) to Revision A Page
• Made changes to product preview data sheet; released as Production Data........................................................................ 1
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OUT
NC
IN
GND
EN
1
2
3
5
4
IN
NC
EN
6
5
4
OUT
NC
GND
1
2
3
GND
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SBVS245A –OCTOBER 2014–REVISED MARCH 2015
5 Pin Configuration and Functions
DBV Package DRV Package
SOT-23-5 WSON-6
(Top View) (Top View)
Pin Functions
PIN
NO. I/O DESCRIPTION
NAME DRV DBV
Enable pin. Driving this pin high enables the device. Driving this pin low puts the
EN 4 3 I device into low current shutdown. This pin can be left floating to enable the device.
The maximum voltage must remain below 6.5 V.
GND 3 2 — Ground
IN 6 1 I Unregulated input to the device
NC 2, 5 4 — No internal connection
Regulated output voltage. Connect a small 2.2-µF or greater ceramic capacitor
OUT 1 5 O from this pin to ground to assure stability.
The thermal pad is electrically connected to the GND node.
Thermal pad — — Connect to the GND plane for improved thermal performance.
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6 Specifications
6.1 Absolute Maximum Ratings
specified at TJ= –40°C to 125°C, unless otherwise noted; all voltages are with respect to GND(1)
MIN MAX UNIT
VIN –0.3 7 V
Voltage VEN –0.3 7 V
VOUT –0.3 7 V
Maximum output current IOUT Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation PDISS See Thermal Information
Junction temperature, TJ–55 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT
VIN Input voltage 2.7 6.5 V
VOUT Output voltage 1.2 5 V
IOUT Output current 0 150 mA
VEN Enable voltage 0 6.5 V
CIN Input capacitor 0 1 µF
COUT Output capacitor 2 2.2 47 µF
TJOperating junction temperature –40 125 °C
6.4 Thermal Information TPS706
THERMAL METRIC(1) DBV DRV UNIT
5 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 212.1 73.1
RθJC(top) Junction-to-case (top) thermal resistance 78.5 97.0
RθJB Junction-to-board thermal resistance 39.5 42.6 °C/W
ψJT Junction-to-top characterization parameter 2.86 2.9
ψJB Junction-to-board characterization parameter 38.7 42.9
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 12.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
At TJ= –40°C to 125°C, VIN = VOUT(nom) + 1 V or 2.7 V (whichever is greater), IOUT = 1 mA, VEN = 2 V, and CIN = COUT = 2.2-μF
ceramic, unless otherwise noted. Typical values are at TJ= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 2.7 6.5 V
VOUT Output voltage range 1.2 5.0 V
VOUT < 3.3 V –2% 2%
VOUT(accuracy) DC output accuracy VOUT ≥3.3 V, TJ= –40°C to 85°C –1% 1%
Line regulation (VOUT(nom) + 1 V, 2.7 V) ≤VIN ≤6.5 V 3 10 mV
ΔVOUT VIN = VOUT(nom) + 1.5 V or 3 V (whichever is
Load regulation 20 50 mV
greater), 100 µA ≤IOUT ≤150 mA
2.8 V ≤VOUT ≤3.3 V, IOUT = 50 mA 295 650 mV
VDO Dropout voltage(1)(2) 2.8 V ≤VOUT ≤3.3 V, IOUT = 150 mA 975 1540 mV
I(CL) Output current limit(3) VOUT = 0.9 × VOUT(nom) 200 320 500 mA
IOUT = 0 mA, VOUT ≤3.3 V 1.3 2.55 µA
IGND Ground pin current IOUT = 150 mA 350 µA
ISHDN Shutdown current VEN ≤0.4 V, VIN = 2.7 V 150 nA
f = 10 Hz 80 dB
PSRR Power-supply rejection ratio f = 100 Hz 62 dB
f = 1 kHz 52 dB
BW = 10 Hz to 100 kHz, IOUT = 10 mA,
VnOutput noise voltage 190 μVRMS
VIN = 2.7 V, VOUT = 1.2 V
Enable pin high (enabled) 0.9 V
VEN(HI) Enable pin high (disabled) 0 0.4 V
IEN EN pin current EN = 1.0 V, VIN = 5.5 V 300 nA
Reverse current VOUT = 3 V, VIN = VEN = 0 V 10 nA
(flowing out of IN pin)
IREV Reverse current VOUT = 3 V, VIN = VEN = 0 V 100 nA
(flowing into OUT pin) Shutdown, temperature increasing 158 °C
Thermal shutdown
TSD temperature Reset, temperature decreasing 140 °C
Operating junction
TJ–40 125 °C
temperature
(1) VDO is measured with VIN = 0.98 × VOUT(nom).
(2) Dropout is only valid when VOUT ≥2.8 V because of the minimum input voltage limits.
(3) Measured with VIN = VOUT + 3 V for VOUT ≤2.5 V. Measured with VIN = VOUT + 2.5 V for VOUT > 2.5 V.
6.6 Timing Requirements
At TJ= –40°C to 125°C, VIN = VOUT(nom) + 1 V or 2.7 V (whichever is greater), RL= 47 Ω, VEN = 2 V, and CIN = COUT = 2.2-μF
ceramic, unless otherwise noted. Typical values are at TJ= 25°C.
PARAMETER MIN TYP MAX UNIT
VOUT(nom) ≤3.3 V 200 600 µs
tSTR Start-up time(1) VOUT > 3.3 V 500 1500 µs
(1) Startup time = time from EN assertion to 0.95 × VOUT(nom) and load = 47 Ω.
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Junction Temperature (qC)
Output Voltage (V)
-40 -20 0 20 40 60 80 100 120 140
1.18
1.1825
1.185
1.1875
1.19
1.1925
1.195
1.1975
1.2
1.2025
1.205 IOUT = 10 mA
IOUT = 150 mA
Input Voltage (V)
Current Limit (mA)
3.5 4 4.5 5 5.5 6 6.5
200
220
240
260
280
300
320
340
360
380
400
420
440
460
480
500 TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
Output Current (mA)
Output Voltage (V)
0 20 40 60 80 100 120 140
1.18
1.1825
1.185
1.1875
1.19
1.1925
1.195
1.1975
1.2
1.2025
1.205 TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
Input Current (mA)
Output Voltage (V)
0 20 40 60 80 100 120 140
3.272
3.276
3.28
3.284
3.288
3.292
3.296
3.3
3.304
3.308 TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
Input Voltage (V)
Output Voltage (V)
2.5 3 3.5 4 4.5 5 5.5 6 6.5
1.195
1.196
1.197
1.198
1.199
1.2
1.201
1.202
1.203
1.204
1.205 TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
Input Voltage (V)
Output Voltage (V)
4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5
3.29
3.292
3.294
3.296
3.298
3.3
3.302
3.304
3.306
3.308
3.31 TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
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6.7 Typical Characteristics
Over operating temperature range (TJ= –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ= 25°C.
TPS70612 TPS70633
Figure 1. 1.2-V Line Regulation vs VIN and Temperature Figure 2. 3.3-V Line Regulation vs VIN and Temperature
TPS70612 TPS70633
Figure 3. 1.2-V Load Regulation vs IOUT and Temperature Figure 4. 3.3-V Load Regulation vs IOUT and Temperature
TPS70612 TPS70612
Figure 5. VOUT vs Temperature Figure 6. 1.2-V Current Limit vs VIN and Temperature
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Input Voltage (V)
Ground Pin Current (PA)
2.5 3 3.5 4 4.5 5 5.5 6 6.5
0
0.1
0.2
0.3
0.4
0.5
0.6 TJ = +125 qC
TJ = +85 qC
TJ = +25 qC
TJ = -40 qC
Frequency (Hz)
PSRR (dB)
1E+1 1E+2 1E+3 1E+4 1E+5 1E+6 1E+7
0
10
20
30
40
50
60
70
80
90
Input Voltage (V)
Ground Pin Current (PA)
4 4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
Output Current (mA)
Ground Pin Current (PA)
0 25 50 75 100 125 150
0
100
200
300
400
500
600
700
800 TJ = +125 qC
TJ = +85 qC
TJ = +25 qC
TJ = -40 qC
Input Voltage (V)
Current Limit (mA)
5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6 6.1 6.2 6.3 6.4 6.5
300
310
320
330
340
350
360
370
380
390
400
410
420
430
440 TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
Input Voltage (V)
Ground Pin Current (PA)
2.5 3 3.5 4 4.5 5 5.5 6 6.5
0.5
1
1.5
2
2.5
3TJ = +125 qC
TJ = +85 qC
TJ = +25 qC
TJ = -40 qC
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Typical Characteristics (continued)
Over operating temperature range (TJ= –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ= 25°C.
TPS70633 TPS70612
Figure 7. 3.3-V Current Limit vs VIN and Temperature Figure 8. GND Current vs VIN and Temperature
TPS70633, EN = open TPS70612
Figure 9. GND Current vs VIN and Temperature Figure 10. GND Current vs IOUT and Temperature
Shutdown current, TPS70612 VOUT = 2.8 V, VIN = 3.8 V, COUT = 2.2 µF
Figure 11. Shutdown Current vs VIN and Temperature Figure 12. Power-Supply Rejection Ratio vs Frequency
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Channel 4
(50 mA / div)
Channel 2
(200 mV / div)
Time (10 ms / div)
Channel 4
(100 mA / div)
Channel 2
(200 mV / div)
Time (100 s / div)m
Channel 4
(50 mA / div)
Channel 2
(200 mV / div)
Time (100 s / div)m
Channel 4
(100 mA / div)
Channel 2
(200 mV / div)
Time (500 s / div)m
Frequency (Hz)
Noise (PV/Hz)
1E+1 1E+2 1E+3 1E+4 1E+5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
100
110
120
130
140
±50 ±35 ±20 ±5 10 25 40 55 70 85 100 115 130
Time (s)
Temperature (C)
C019
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Typical Characteristics (continued)
Over operating temperature range (TJ= –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ= 25°C.
TPS70612
VOUT = 2.8 V
Figure 14. Start-Up Time vs Temperature
Figure 13. Noise
Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V
Figure 15. TPS70612 Load Transient (0 mA to 50 mA) Figure 16. TPS70612 Load Transient (1 mA to 150 mA)
Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V
Figure 17. TPS70612 Load Transient (50 mA to 0 mA) Figure 18. TPS70612 Load Transient (50 mA to 150 mA)
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Channel 4
(2 V / div)
Channel 2
(50 mV / div)
Time (50 s / div)m
Channel 4
(2 V / div)
Channel 2
(50 mV / div)
Time (50 s / div)m
Channel 4
(50 mA / div)
Channel 2
(200 mV / div)
Time (10 ms / div)
Channel 4
(50 mA / div)
Channel 2
(200 mV / div)
Time (500 s / div)m
Channel 4
(50 mA / div)
Channel 2
(200 mV / div)
Time (100 s / div)m
Channel 4
(100 mA / div)
Channel 2
(200 mV / div)
Time (500 s / div)m
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Typical Characteristics (continued)
Over operating temperature range (TJ= –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ= 25°C.
Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V
Figure 19. TPS70633 Load Transient (0 mA to 50 mA) Figure 20. TPS70633 Load Transient (1 mA to 150 mA)
Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V
Figure 21. TPS70633 Load Transient (50 mA to 0 mA) Figure 22. TPS70633 Load Transient (50 mA to 150 mA)
Channel 2 = VOUT, channel 4 = VIN, IOUT = 10 mA Channel 2 = VOUT, channel 4 = VIN, IOUT = 50 mA
Figure 23. TPS70612 Line Transient (2.7 V to 3.7 V) Figure 24. TPS70612 Line Transient (2.7 V to 3.7 V)
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Channel 2
(1 V / div)
Channel 1
(1 V / div)
Time (500 ms / div)
Channel 2
(1 V / div)
Channel 1
(500 mV / div)
Time (50 s / div)m
Channel 2
(1 V / div)
Channel 1
(1 V / div)
Time (500 ms / div)
Channel 4
(2 V / div)
Channel 2
(50 mV / div)
Time (50 s / div)m
Channel 4
(2 V / div)
Channel 2
(50 mV / div)
Time (50 s / div)m
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Typical Characteristics (continued)
Over operating temperature range (TJ= –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ= 25°C.
Channel 2 = VOUT, channel 4 = VIN, IOUT = 10 mA Channel 2 = VOUT, channel 4 = VIN, IOUT = 50 mA
Figure 25. TPS70633 Line Transient (4.3 V to 5.3 V) Figure 26. TPS70633 Line Transient (4.3 V to 5.3 V)
Channel 1 = EN, channel 2 = VOUT, VIN = 4.3 V, COUT = 2.2 µF, Channel 1 = VIN, channel 2 = VOUT, IOUT = 3 mA, TPS70633
TPS70633
Figure 27. Power-Up with Enable Figure 28. Power-Up and Power-Down Response
Channel 1 = VIN, channel 2 = VOUT, IOUT = 150 mA, TPS70633
Figure 29. Power-Up and Power-Down Response
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Thermal
Shutdown
Current
Limit
Bandgap
IN
EN
OUT
Logic
GND
Device
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7 Detailed Description
7.1 Overview
The TPS706 series are ultralow quiescent current, low-dropout (LDO) linear regulators. The TPS706 offers
reverse current protection to block any discharge current from the output into the input. The TPS706 also
features current limit and thermal shutdown for reliable operation.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TPS706 uses an undervoltage lockout (UVLO) circuit to keep the output shut off until the internal circuitry
operates properly.
7.3.2 Shutdown
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI) (0.9 V, minimum).
Turn off the device by forcing the EN pin to drop below 0.4 V. If shutdown capability is not required, connect EN
to IN.
7.3.3 Reverse Current Protection
The TPS706 has integrated reverse current protection. Reverse current protection prevents the flow of current
from the OUT pin to the IN pin when output voltage is higher than input voltage. The reverse current protection
circuitry places the power path in high impedance when the output voltage is higher than the input voltage. This
setting reduces leakage current from the output to the input to 10 nA, typical. The reverse current protection is
always active regardless of the enable pin logic state or if the OUT pin voltage is greater than 1.8 V. Reverse
current can flow if the output voltage is less than 1.8 V and if input voltage is less than the output voltage.
If voltage is applied to the input pin, then the maximum voltage that can be applied to the OUT pin is the lower of
three times the nominal output voltage or 6.5 V. For example, if the 1.2-V output voltage version is used, then the
maximum reverse bias voltage that can be applied to the OUT pin is 3.6 V. If the 3.3-V output voltage version is
used, then the maximum reverse bias voltage that can be applied to the OUT pin is 6.5 V.
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Feature Description (continued)
7.3.4 Internal Current Limit
The TPS706 internal current limit helps protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output
voltage is not regulated, and can be measured as (VOUT = ILIMIT × RLOAD). The PMOS pass transistor dissipates
[(VIN – VOUT) × ILIMIT] until a thermal shutdown is triggered and the device turns off. When cool, the device is
turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between
current limit and thermal shutdown; see the Thermal Information section for more details.
The TPS706 is characterized over the recommended operating output current range up to 150 mA. The internal
current limit begins to limit the output current at a minimum of 200 mA of output current.
7.3.5 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 158°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, limit junction temperature to 125°C, maximum. To estimate the margin of safety
in a complete design (including heatsink), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions. For good reliability, thermal protection must trigger at least
35°C above the maximum expected ambient condition of the particular application. This configuration produces a
worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The TPS706 internal protection circuitry is designed to protect against overload conditions. This circuitry is not
intended to replace proper heatsinking. Continuously running the TPS706 into thermal shutdown degrades
device reliability.
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7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is at least as high as VIN(min).
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
• The output current is less than the current limit.
• The device junction temperature is less than the maximum specified junction temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the
output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the
device is significantly degraded because the pass device is in the linear region and no longer controls the current
through the LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE VIN VEN IOUT TJ
VIN > VOUT(nom) + VDO and
Normal mode VEN > VEN(HI) IOUT < ILIM TJ< 125°C
VIN > VIN(min)
Dropout mode VIN(min) < VIN < VOUT(nom) + VDO VEN > VEN(HI) — TJ< 125°C
Disabled mode
(any true condition disables the — VEN < VEN(low) — TJ> 158°C
device)
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPS706
TPS706
SBVS245A –OCTOBER 2014–REVISED MARCH 2015
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS706 consumes low quiescent current and delivers excellent line and load transient performance. This
performance, combined with low noise and good PSRR with little (VIN – VOUT) headroom, makes these devices
ideal for RF portable applications, current limit, and thermal protection. The TPS706 devices are specified from
–40°C to 125°C.
8.1.1 Input and Output Capacitor Considerations
The TPS706 devices are stable with output capacitors with an effective capacitance of 2.0 μF or greater for
output voltages below 1.5 V. For output voltages equal or greater than 1.5 V, the minimum effective capacitance
for stability is 1.5 µF. The maximum capacitance for stability is 47 µF. The equivalent series resistance (ESR) of
the output capacitor must be between 0 Ωand 0.2 Ωfor stability.
The effective capacitance is the minimum capacitance value of a capacitor after taking into account variations
resulting from tolerances, temperature, and dc bias effects. X5R- and X7R-type ceramic capacitors are
recommended because these capacitors have minimal variation in value and ESR over temperature.
Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-µF to
2.2-µF capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient
response, input ripple rejection, and PSRR.
8.1.2 Dropout Voltage
The TPS706 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO approximately scales with the output current because the PMOS device
functions like a resistor in dropout.
The ground pin current of many linear voltage regulators increases substantially when the device is operated in
dropout. This increase in ground pin current while operating in dropout can be several orders of magnitude larger
than when the device is not in dropout. The TPS706 employs a special control loop that limits the increase in
ground pin current while operating in dropout. This functionality allows for the most efficient operation while in
dropout conditions that can greatly increase battery run times.
8.1.3 Transient Response
As with any regulator, increasing the output capacitor size reduces over- and undershoot magnitude, but
increases transient response duration.
14 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: TPS706
Channel 4
(50 mA / div)
Channel 2
(200 mV / div)
Time (500 s / div)m
Channel 2
(1 V / div)
Channel 1
(500 mV / div)
Time (50 s / div)m
TPS70633
EN
IN OUT
VIN VOUT
1 Fm2.2 Fm
GND
NC
TPS706
www.ti.com
SBVS245A –OCTOBER 2014–REVISED MARCH 2015
8.2 Typical Application
Figure 30. 3.3-V, Low-IQRail
8.2.1 Design Requirements
Table 2 summarizes the design requirements for Figure 30.
Table 2. Design Requirements for a 3.3-V, Low-IQRail Application
PARAMETER DESIGN SPECIFICATION
VIN 4.3 V
VOUT 3.3 V
I(IN) (no load) < 5 µA
IOUT (max) 150 mA
8.2.2 Detailed Design Procedure
Select a 2.2-µF, 10-V X7R output capacitor to satisfy the minimum output capacitance requirement with a 3.3-V
dc bias.
Select a 1.0-µF, 6.3-V X7R input capacitor to provide input noise filtering and eliminate high-frequency voltage
transients.
8.2.3 Application Curves
Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V Channel 1 = EN, channel 2 = VOUT, VIN = 4.3 V, COUT = 2.2 µF,
TPS70633
Figure 32. Power-Up with Enable
Figure 31. TPS70633 Load Transient (50 mA to 150 mA)
9 Power Supply Recommendations
This device is designed to operate with an input supply range of 2.7 V to 6.5 V. The input voltage range must
provide adequate headroom in order for the device to have a regulated output. This input supply must be well-
regulated and stable. If the input supply is noisy, additional input capacitors with low ESR can help improve the
output noise performance.
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS706
Power Dissipation (W)
Maximum Ambient Temperature (qC)
0 0.2 0.4 0.6 0.8 1
50
75
100
125 TPS706, DBV Package
TPS706, DRV Package
TPS706
SBVS245A –OCTOBER 2014–REVISED MARCH 2015
www.ti.com
10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
Input and output capacitors must be placed as close to the device pins as possible. To improve ac performance
(such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate
ground planes for VIN and VOUT, with the ground plane connected only at the device GND pin. In addition, the
output capacitor ground connection must be connected directly to the device GND pin.
10.1.2 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the
Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) can be approximated by
the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown
in Equation 1.
PD= (VIN – VOUT)×IOUT (1)
Figure 33 shows the maximum ambient temperature versus the power dissipation of the TPS706. This figure
assumes the device is soldered on a JEDEC standard, high-K layout with no airflow over the board. Actual board
thermal impedances vary widely. If the application requires high power dissipation, having a thorough
understanding of the board temperature and thermal impedances is helpful to ensure the TPS706 does not
operate above a junction temperature of 125°C.
Figure 33. Maximum Ambient Temperature vs Device Power Dissipation
16 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: TPS706
Y Y
JT J T JT D
:T =T + P·
Y Y
JB J B JB D
:T =T + P·
TPS706
www.ti.com
SBVS245A –OCTOBER 2014–REVISED MARCH 2015
Layout Guidelines (continued)
Estimating the junction temperature can be done by using the thermal metrics ΨJT and ΨJB, shown in the
Thermal Information. These metrics are a more accurate representation of the heat transfer characteristics of the
die and the package than RθJA. The junction temperature can be estimated with Equation 2.
where:
• PDis the power dissipation shown by Equation 1,
• TTis the temperature at the center-top of the IC package,
• TBis the PCB temperature measured 1 mm away from the IC package on the PCB surface. (2)
NOTE
Both TTand TBcan be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TTand TB, see the application note Using New Thermal Metrics
(SBVA025), available for download at www.ti.com.
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPS706
COUT
VOUT
VIN
GND PLANE
CIN
Represents via used for application-specific connections.
IN
GND
EN NC
OUT
Input Ground
Plane
Output Ground
Plane
Grounded
Thermal Plane
Grounded
Thermal Plane
Input
Trace
Output Trace
Enable
Trace
Input Capacitor
Output Capacitor
Designates thermal vias.
Thermal Pad
OUT GND
NC
IN NC EN
TPS706
SBVS245A –OCTOBER 2014–REVISED MARCH 2015
www.ti.com
10.2 Layout Examples
Figure 34. WSON Layout Example
Figure 35. SOT23-5 Layout Example
18 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: TPS706
TPS706
www.ti.com
SBVS245A –OCTOBER 2014–REVISED MARCH 2015
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS706 is available through the product folders under
Simulation Models.
11.1.2 Device Nomenclature
Table 3. Device Nomenclature(1)
PRODUCT VOUT
TPS706xx yyy z xx is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits
are used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V).
yyy is the package designator.
zis the tape and reel quantity (R = 3000, T = 250).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
SBVU002 — DEM-SOT23LDO Demonstration Fixture
SBVA025 —Using New Thermal Metrics
11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TPS706
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jun-2016
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS70612DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJC
TPS70612DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJC
TPS70612DRVR ACTIVE WSON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJC
TPS70612DRVT ACTIVE WSON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJC
TPS70615DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIW
TPS70615DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIW
TPS70615DRVR ACTIVE WSON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIW
TPS70615DRVT ACTIVE WSON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIW
TPS70618DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIX
TPS70618DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIX
TPS70618DRVR ACTIVE WSON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIX
TPS70618DRVT ACTIVE WSON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIX
TPS70625DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIY
TPS70625DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIY
TPS70625DRVR ACTIVE WSON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIY
TPS70625DRVT ACTIVE WSON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIY
TPS70628DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJU
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jun-2016
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS70628DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJU
TPS70628DRVR ACTIVE WSON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJU
TPS70628DRVT ACTIVE WSON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJU
TPS70630DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIZ
TPS70630DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIZ
TPS70630DRVR ACTIVE WSON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIZ
TPS70630DRVT ACTIVE WSON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIZ
TPS70633DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJA
TPS70633DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJA
TPS70633DRVR ACTIVE WSON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJA
TPS70633DRVT ACTIVE WSON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SJA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jun-2016
Addendum-Page 3
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS70612DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TPS70612DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TPS70612DRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS70612DRVT WSON DRV 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS70615DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TPS70615DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TPS70615DRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS70615DRVT WSON DRV 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS70618DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TPS70618DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TPS70618DRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS70618DRVT WSON DRV 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS70625DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TPS70625DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TPS70625DRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS70625DRVT WSON DRV 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS70628DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TPS70628DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Jun-2016
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS70628DRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS70628DRVT WSON DRV 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS70630DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TPS70630DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TPS70630DRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS70630DRVT WSON DRV 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS70633DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TPS70633DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TPS70633DRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS70633DRVT WSON DRV 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS70612DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS70612DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS70612DRVR WSON DRV 6 3000 210.0 185.0 35.0
TPS70612DRVT WSON DRV 6 250 210.0 185.0 35.0
TPS70615DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS70615DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS70615DRVR WSON DRV 6 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Jun-2016
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS70615DRVT WSON DRV 6 250 210.0 185.0 35.0
TPS70618DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS70618DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS70618DRVR WSON DRV 6 3000 210.0 185.0 35.0
TPS70618DRVT WSON DRV 6 250 210.0 185.0 35.0
TPS70625DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS70625DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS70625DRVR WSON DRV 6 3000 210.0 185.0 35.0
TPS70625DRVT WSON DRV 6 250 210.0 185.0 35.0
TPS70628DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS70628DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS70628DRVR WSON DRV 6 3000 210.0 185.0 35.0
TPS70628DRVT WSON DRV 6 250 210.0 185.0 35.0
TPS70630DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS70630DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS70630DRVR WSON DRV 6 3000 210.0 185.0 35.0
TPS70630DRVT WSON DRV 6 250 210.0 185.0 35.0
TPS70633DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS70633DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS70633DRVR WSON DRV 6 3000 210.0 185.0 35.0
TPS70633DRVT WSON DRV 6 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Jun-2016
Pack Materials-Page 3
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DRV 6 WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4206925/F
www.ti.com
PACKAGE OUTLINE
C
6X 0.35
0.25
1.6 0.1
6X 0.3
0.2
2X
1.3
1 0.1
4X 0.65
0.8
0.7
0.05
0.00
B2.1
1.9 A
2.1
1.9
(0.2) TYP
WSON - 0.8 mm max heightDRV0006A
PLASTIC SMALL OUTLINE - NO LEAD
4222173/B 04/2018
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
34
6
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
7
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 5.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
(1)
4X (0.65)
(1.95)
6X (0.3)
6X (0.45)
(1.6)
(R0.05) TYP
( 0.2) VIA
TYP
(1.1)
WSON - 0.8 mm max heightDRV0006A
PLASTIC SMALL OUTLINE - NO LEAD
4222173/B 04/2018
SYMM
1
34
6
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
7
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
www.ti.com
EXAMPLE STENCIL DESIGN
6X (0.3)
6X (0.45)
4X (0.65) (0.7)
(1)
(1.95)
(R0.05) TYP
(0.45)
WSON - 0.8 mm max heightDRV0006A
PLASTIC SMALL OUTLINE - NO LEAD
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
SYMM
1
34
6
SYMM
METAL
7
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