ISL1208IB8Z-T7A - Intersil - Datasheet.Directory

FN8085.8

ISL1208

I2C® Real Time Clock/Calendar

Low Power RTC with Battery Backed

SRAM

The ISL1208 device is a low power real time clock with

timing and crystal compensation, clock/calendar, power fail

indicator, periodic or polled alarm, intelligent battery backup

switching and ba tte ry-b a cke d user SRAM.

The oscillator uses an extern al, low-cost 32.768kHz crystal.

The real time clock tracks time with separate registers for

hours, minutes, and seconds. The device has calendar

registers for date, month, year and day of the week. The

calendar is accurate through 2099, with automatic leap year

correction.

Pinout ISL1208

(8 LD MSOP, SOIC)

TOP VIEW

ISL1208

(8 LD TDFN)

TOP VIEW

Features

• Real Time Clock/Calendar

- Tracks Time in Hours, Minutes, and Seconds

- Day of the Week, Day, Month, and Year

• 15 Selectable Frequency Outputs

• Single Alarm

- Settable to the Second, Minute, Hour, Day of the Week,

Day, or Month

- Single Event or Pulse In terrupt Mode

• Automatic Backup to Battery or Super Capacitor

• Power Failure Detection

• On-Chip Oscillator Compensation

• 2 Bytes Battery-Backed User SRAM

•I

2C Interface

- 400kHz Data Transfer Rate

• 400nA Battery Supply Current

• Same Pin Out as ST M41Txx and Maxim DS13xx Devices

• Small Package Options

- 8 Ld MSOP and SOIC Packages

- 8 Ld TDFN Package

• Pb-Free Available (RoHS Compliant)

Applications

• Utility Meters

• HVAC Equipment

• Audio/Video Components

• Set-Top Box/Television

• Modems

• Network Routers, Hubs, Switches, Bridges

• Cellular Infrastructure Equipment

• Fixed Broadband Wireless Equipment

• Pagers/PDA

• POS Equipment

• Test Meters/Fixtures

• Office Automation (Copiers, Fax)

• Home Appliances

• Computer Products

• Other Industrial/Medical/Aut o m ot ive

VBAT

VDD

IRQ/FOUT

SCL

SDA

GND 5

VBAT

GND

VDD

IRQ/FOUT

SCL

SDA

Data Sheet September 12, 2008

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

2FN8085.8

September 12, 2008

Block Diagram

Ordering Information

PART NUMBER PART MARKING VDD RANGE

(V) TEMP. RANGE

(°C) PAC KAGE PKG. DWG. #

ISL1208IU8 AGS 2.7 to 5.5 -40 to +85 8 Ld MSOP M8.118

ISL1208IU8-TK* AGS 2.7 to 5.5 -40 to +85 8 Ld MSOP Tape and

Reel M8.118

ISL1208IU8Z (Note) ANW 2.7 to 5.5 -40 to +85 8 Ld MSOP (Pb-free) M8.118

ISL1208IU8Z-TK*

(Note) ANW 2.7 to 5.5 -40 to +85 8 Ld MSOP

Tape an d Reel

(Pb-free)

M8.118

ISL1208IB8 1208 I 2.7 to 5.5 -40 to +85 8 Ld SOIC MDP0027

ISL1208IB8-TK* 1208 I 2. 7 to 5.5 -40 to +85 8 Ld SOIC Tape and Reel MDP0027

ISL1208IB8Z

(Note) 1208 ZI 2.7 to 5.5 -40 to +85 8 Ld SOIC (Pb-free) MDP0027

ISL1208IB8Z-TK*

(Note) 1208 ZI 2.7 to 5.5 -40 to +85 8 Ld SOIC

Tape an dReel (Pb-free) MDP0027

ISL1208IRT8Z

(Note) 08TZ 2.7 to 5.5 -40 to +85 8 Ld TDFN

(Pb-free) L8.3x3A

ISL1208IRT8Z-TK*

(Note) 08TZ 2.7 to 5.5 -40 to +85 8 Ld TDFN

Tape an d Reel (Pb-free) L8.3x3A

*Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

I2C

INTERFACE RTC

CONTROL

LOGIC

ALARM

FREQUENCY

OUT

RTC

DIVIDER

SDA

BUFFER

CRYSTAL

OSCILLATOR

POR

SWITCH

SCL

BUFFER

SDA

SCL

VDD

VBAT IRQ/

FOUT

INTERNAL

SUPPLY

VTRIP

SECONDS

MINUTES

HOURS

DAY OF WEEK

DATE

MONTH

YEAR

USER

SRAM

CONTROL

REGISTERS

ISL1208

3FN8085.8

September 12, 2008

Pin Descriptions

NUMBER SYMBOL DESCRIPTION

1 X1 The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz

crystal. X1 can also be driven directly from a 32.768kHz source.

2 X2 The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz

crystal.

3 VBA T This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply

fails. This pin should be tied to ground if not used.

4 GND Ground

5 SDA Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain output and

may be wire OR’ed with other open drain or open collector outputs.

6 SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device.

7IRQ

/FOUT Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. The function

is set via the configuration register.

8 VDD Power supply

ISL1208

4FN8085.8

September 12, 2008

Absolute Maximum Ratings Thermal Information

Voltage on VDD, VBAT, SCL, SDA, and IRQ Pins (Note 3)

(respect to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V

Voltage on X1 and X2 Pins

(respect to GND) . . . . . . . . . . . . .-0.5V to VDD + 0.5 (VDD Mode)

-0.5V to VBAT + 0.5 (VBAT Mode)

Latchup (Note 4) ................Class II, Level B @ +85°C

Thermal Resistance (Typical, Note 1) θJA (°C/W) θJC (°C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . 95 N/A

MSOP Package . . . . . . . . . . . . . . . . . . 128 N/A

TDFN Package (Note 2). . . . . . . . . . . . 53.7 2.8

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

3. The VDD and SDA pins should not be subjected to negative voltage while the VBAT pin is biased, otherwise latchup can result. See the

Applications section.

4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are using a negative pulse limited to -0.5V.

DC Operating Characteristics – RTC Temperature = -40°C to +85°C, unless otherwise stated.

SYMBOL PARAMETER CONDITIONS NOTES MIN

(Note 9) TYP

(Note 8) MAX

(Note 9) UNITS

VDD Main Power Supply 2.7 5.5 V

VBAT Battery Supply Voltage 1.8 5.5 V

IDD1 Supply Current VDD = 5V 5, 6 2 6 µA

VDD = 3V 1.2 4 µA

IDD2 Supply Current With I2C Active VDD = 5V 5, 6 40 120 µA

IDD3 Supply Current (Low Power Mode) VDD = 5V, LPMODE = 1 5 1.4 5 µA

IBAT Battery Supply Current VBAT = 3V 5 400 950 nA

ILI Input Leakage Current on SCL 100 nA

ILO I/O Leakage Current on SDA 100 nA

VTRIP VBAT Mode Threshold 1.6 2.2 2.6 V

VTRIPHYS VTRIP Hysteresis 10 30 75 mV

VBATHYS VBAT Hysteresis 15 50 100 mV

IRQ/FOUT

VOL Output Low Voltage VDD = 5V

IOL = 3mA 0.4 V

VDD = 2.7V

IOL = 1mA 0.4 V

Power-Down Timing Temperature = -40°C to +85°C, unless otherwise stated.

SYMBOL PARAMETER CONDITIONS NOTES MIN

(Note 9) TYP

(Note 8) MAX

(Note 9) UNITS

VDD SR- VDD Negative Slewrate 7 10 V/ms

Serial Interface Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS NOTES MIN

(Note 9) TYP

(Note 8) MAX

(Note 9) UNITS

SERIAL INTERFACE SPECS

VIL SDA and SCL Input Buffer LOW

Voltage -0.3 0.3 x

VDD V

ISL1208

5FN8085.8

September 12, 2008

VIH SDA and SCL Input Buffer HIGH

Voltage 0.7 x

VDD VDD +

0.3 V

Hysteresis SDA and SCL Input Buffer

Hysteresis 0.05 x

VDD V

VOL SDA Output Buffer LOW Voltage,

Sinking 3mA 00.4V

CPIN SDA and SCL Pin Capacitance TA = +25°C, f = 1MHz, VDD = 5V, VIN =0V,

VOUT = 0V 10, 11 10 pF

fSCL SCL Frequency 400 kHz

tIN Pulse width Suppression Time at

SDA and SCL Inputs Any pulse narrower than the max spec is

suppressed. 50 ns

tAA SCL Falling Edge to SDA Output

Data Valid SCL falling edge crossing 30% of VDD, until

SDA exits the 30% to 70% of VDD window. 900 ns

tBUF T ime the Bus Must Be Free Before

the Start of a New Transmission SDA crossing 70% of VDD during a STOP

condition, to SDA crossing 70% of VDD

during the following START condition.

1300 ns

tLOW Clock LOW Time Measured at the 30% of VDD crossing. 1300 ns

tHIGH Clock HIGH Time Measured at the 70% of VDD crossing. 600 ns

tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge. Both

crossing 70% of VDD.600 ns

tHD:STA ST ART Condition Hold Time From SDA falling edge crossing 30% of VDD

to SCL falling edge crossing 70% of VDD.600 ns

tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VDD

window , to SCL rising edge crossing 30% of

VDD

100 ns

tHD:DAT Input Data Hold T ime From SCL falling edge crossing 30% of VDD

to SDA entering the 30% to 70% of VDD

window.

20 900 ns

tSU:STO ST OP Condition Setup T ime From SCL rising edge crossing 70% of VDD,

to SDA rising edge crossing 30% of VDD.600 ns

tHD:STO STOP Condition Hold Time From SDA rising edge to SCL falling edge.

Both crossing 70% of VDD.600 ns

tDH Output Data Hold Time From SCL falling edge crossing 30% of VDD,

until SDA enters the 30% to 70% of VDD

window.

0ns

tRSDA and SCL Rise Time From 30% to 70% of VDD 10, 11 20 +

0.1 x Cb 300 ns

tFSDA and SCL Fall Time From 70% to 30% of VDD 10, 11 20 +

0.1 x Cb 300 ns

Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10, 11 10 400 pF

Rpu SDA and SCL Bus Pull-Up

Resistor Off-Chip Maximum is determined by tR and tF.

For Cb = 400pF, max is about 2kΩto~2.5kΩ.

For Cb = 40pF, max is about 15kΩ to ~20kΩ

10, 11 1 kΩ

NOTES:

5. IRQ and FOUT Inactive.

6. LPMODE = 0 (default).

7. In order to ensure proper timekeeping, the VDD SR- specification must be followed.

8. Typical values are for T = +25°C and 3.3V supply voltage.

9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. T emperature limits established by characterization

and are not production tested.

10. Parameter is not 100% tested.

11. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.

Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL PARAMETER TEST CONDITIONS NOTES MIN

(Note 9) TYP

(Note 8) MAX

(Note 9) UNITS

ISL1208

6FN8085.8

September 12, 2008

SDA vs SCL Timing

Symbol Table

tSU:STO

tDH

tHIGH

tSU:STA tHD:STA

tHD:DAT

tSU:DAT

SCL

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

tFtLOW

tBUF

tAA

WAVEFORM INPUTS OUTPUTS

Must be steady Will be steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes Allowed Changing:

State Not Known

N/A Center Line is

High Impedance

ISL1208

7FN8085.8

September 12, 2008

Typical Performance Curves Temperature is +25°C unless otherwise specified

FIGURE 1. IBAT vs VBAT FIGURE 2. IBAT vs TEMPERATURE AT VBA T = 3V

FIGURE 3. IDD1 vs TEMPERATURE FIGURE 4. IDD1 vs VCC WITH LPMODE ON AND OFF

FIGURE 5. IDD1 vs FOUT AT VDD = 3.3V FIGURE 6. IDD1 vs FOUT AT VDD = 5V

000E+0

100E-9

200E-9

300E-9

400E-9

500E-9

600E-9

700E-9

800E-9

900E-9

1E-6

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VBAT (V)

IBAT (A)

000E+0

200E-9

400E-9

600E-9

800E-9

1E-6

-40-200 20406080

TEMPERATURE (°C)

IBAT (A)

1.0E-06

1.2E-06

1.4E-06

1.6E-06

1.8E-06

2.0E-06

2.2E-06

2.4E-06

-40-200 20406080

TEMPERATURE (°C)

IDD1 (A)

VCC = 5V

VCC = 3.3V

400.0E-9

600.0E-9

800.0E-9

1.0E-6

1.2E-6

1.4E-6

1.6E-6

1.8E-6

2.0E-6

2.2E-6

2.4E-6

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VCC (V)

LPMODE = 0

LPMODE = 1

IDD1 (A)

1.2E-6

1.3E-6

1.4E-6

1.5E-6

1.6E-6

1.7E-6

1.8E-6

1.9E-6

2.0E-6

2.1E-6

FOUT (Hz)

1/8

1024

32768

1/2

1/32

1/16

1/4

4096

IDD1 (A)

1.8E-6

1.9E-6

2.0E-6

2.1E-6

2.2E-6

2.3E-6

2.4E-6

2.5E-6

2.6E-6

2.7E-6

2.8E-6

2.9E-6

3.0E-6

FOUT (Hz)

1/8

1024

32768

1/2

1/32

1/16

1/4

4096

IDD1 (A)

ISL1208

8FN8085.8

September 12, 2008

General Description

The ISL1208 device is a low power real time clock with

timing and crystal compensation, clock/calendar, power fail

indicator, periodic or polled alarm, intelligent battery backup

switching, and battery-backed user SRAM.

The oscillator uses an extern al, low-cost 32.768kHz crystal.

The real time clock tracks time with separate registers for

hours, minutes, and seconds. The device has calendar

registers for date, month, year and day of the week. The

calendar is accurate through 2099, with automatic leap year

correction.

The ISL1208's powerful alarm can be set to any

clock/calendar value for a match. For example, every

minute, every Tuesday or at 5:23 AM on March 21. The

alarm status is available by checking the Status Register, or

the device can be configured to provide a hardware interrupt

via the IRQ pin. There is a repeat mode for the alarm

allowing a periodic interrupt every minute, every hour, every

day, etc.

The device also offers a backup power input pin. This VBAT

pin allows the device to be backed up by battery or Super

Capacitor with automatic switchover from VDD to VBAT. The

entire ISL1208 device is fully operational from 2.0V to 5.5V

and the clock/calendar portion of the device remains fully

operational down to 1.8V (Standby Mode).

Pin Description

X1, X2

The X1 and X2 pins are the input and output, respectively, of

an inverting amplifie r. An external 32.768kHz quartz crystal

is used with the ISL1208 to supply a timebase for the real

time clock. Internal compensation circuitry provides high

accuracy over the operating temperature range from

-40°C to +85°C. This oscillator compensation network can

be used to calibrate the crystal timing accuracy over

temperature either during manufacturing or with an external

temperature sensor and microcontroller for active

compensation. The device can also be driven directly from a

32.768kHz source at pin X1.

VBAT

This input provides a backup supply voltage to the device.

VBAT supplies power to the device in the event that the VDD

supply fails. This pin can be connected to a battery, a Super

Cap or tied to ground if not used.

IRQ/fOUT (Interrupt Output/Frequency Output)

This dual function pin can be used as an interrupt or

frequency output pin. The IRQ/FOUT mode is selected via

the frequency out control bits of the control/status register .

•Interrupt Mode. The pin provides an in terrupt signal

output. This signal notifies a host processor that an alarm

has occurred and requests action. It is an open drain

active low output.

•Frequency Output Mode. The pin outputs a clock signal

which is related to the crystal frequency. The frequency

output is user selectable and enabled via the I2C bus. It is

an open drain active low output.

Serial Clock (SCL)

The SCL input is used to clock all serial data into and out of

the device. The input buffer on this pin is always active (not

gated). It is disabled when the backup power supply on the

VBAT pin is activated to minimize power consumption.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out

of the device. It has an open drain output and may be ORed

with other open drain or open collector outputs. The input

buffer is always active (not gated) in normal mode.

An open drain output requires the use of a pull-up resistor.

The output circuitry controls the fall time of the output signal

with the use of a slope controlled pull-down. The circuit is

designed for 400kHz I2C interface speeds. It is disabled

when the backup power supply on the VBAT pin is activated.

VDD, GND

Chip power supply and ground pins. The device will operate

with a power supply from 2.0V to 5.5VDC. A 0.1µF capacitor

is recommended on the VDD pin to ground.

Functional Description

Power Control Operation

The power control circuit accepts a VDD and a VBAT input.

Many types of batteries can be used with Intersil RTC

products. For example, 3.0V or 3.6V Lithium batteries are

appropriate, and batte ry sizes are avai lable that can power

FIGURE 7. ST ANDARD OUTPUT LOAD FOR TESTING THE

DEVICE WITH VDD = 5.0V

SDA

AND

IRQ/fOUT

1533Ω

100pF

5.0V

FOR VOL= 0.4V

AND IOL = 3mA

EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V

FIGURE 8. RECOMMENDED CRYSTAL CONNECTION

ISL1208

9FN8085.8

September 12, 2008

the ISL1208 for up to 10 years. Another option is to use a

Super Cap for applications where VDD is interrupted for up

to a month. See the “Application Section” on page 18 for

more information.

Normal Mode (VDD) to Battery Backup Mode

(VBAT)

To transition from the VDD to VBAT mode, both of the

following conditions must be met:

Condition 1:

VDD < VBAT - VBATHYS

where VBATHYS ≈ 50mV

Condition 2:

VDD < VTRIP

where VTRIP ≈ 2.2V

Battery Backup Mode (VBAT) to Normal Mode

(VDD)

The ISL1208 device will switch from the VBAT to VDD mode

when one of the following conditions occurs:

Condition 1:

VDD > VBAT + VBATHYS

where VBATHYS ≈ 50mV

Condition 2:

VDD > VTRIP + VTRIPHYS

where VTRIPHYS ≈ 30mV

These power control situations are illustrated in Figures 9

and 10.

The I2C bus i s deactivated in ba ttery backup mode to p rovide

lower power. Aside from this, all RTC functions are

operational during battery b ackup mode. Excep t for SCL and

SDA, all the inputs an d output s of the ISL1208 are active

during battery backup mode unless disabled via the control

mode down to 2V.

Power Failure Detection

The ISL1208 provides a Real Time Clock Failure Bit (RTCF)

to detect total power failure. It allows users to determine if

the device has powered up after having lost all power to the

device (both VDD and VBAT).

Low Power Mode

The normal power switching of the ISL1208 is designed to

switch into battery backup mode only if the VDD power is

lost. This will ensure that the device can accept a wide range

of backup voltages from many types of sources while reliably

switching into ba cku p mo de . An other mode, called Low

Power Mode, is available to allow direct switching from V DD

to VBAT without requiring VDD to drop below VTRIP. Since

the additional monitoring of V DD vs VTRIP is no longer

needed, that circuitry is shut down and less power is used

while operating from VDD. Power savings are typically

600nA at VDD = 5V. Low Power Mode is activated via the

LPMODE bit in the control and status registers.

Low Power Mode is useful in systems where VDD is normally

higher than VBAT at all ti mes. The device will switch from

VDD to VBAT when VDD drops bel ow VBAT, with about 50mV

of hysteresis to prevent any switchback of VDD after

switchover. In a system with a VDD = 5V and backup lithium

battery of VBAT = 3V, Low Power Mode can be used .

However, it is not recommended to use Low Power Mode in

a system with VDD = 3.3V ±10%, VBAT ≥ 3.0V, and when

there is a finite I-R voltage drop in the VDD line.

InterSeal™ Battery Saver

The ISL1208 has the InterSeal™ Battery Saver which

prevents initial battery current drain before it is first us ed. For

example, battery-backed RTCs are commo nly packaged on

a board with a battery connected. In order to preserve

battery life, the ISL1208 will not draw any power from the

battery source until after the device is first powered up from

the VDD source. Thereafter, the device will switchover to

battery backup mode whenever VDD power is lost.

Real T ime Clock Operation

The Real Time Clock (RTC) uses an external 32.768kHz quartz

crystal to mainta in an accurate internal representation of

second, minute, hour , day of week, date, month, and year . The

RTC also has leap-year correction. The clock also corrects for

months having fewer than 31 days and has a bit that controls

24-hour or AM/PM format. When the ISL1208 powers up after

the loss of both VDD and VBAT, the clock will not begin

incrementing until at least one byte is written to the clock

VBAT - VBATHYS

VBAT

VBAT + VBATHYS

BATTERY BACKUP

MODE

VDD

VTRIP 2.2V

1.8V

FIGURE 9. BATTERY SWITCHOVER WHEN VBAT < VTRIP

FIGURE 10. BATTERY SWITCHOVER WHEN VBAT > VTRIP

VTRIP

VBAT

VTRIP + VTRIPHYS

BATTERY BACKUP

MODE

VDD

VTRIP

3.0V

2.2V

ISL1208

10 FN8085.8

September 12, 2008

Accuracy of the Real Time Clock

The accuracy of the Real Time Clock depends on the

frequency of the quartz crystal that is used as the time base

for the RTC. Since the resonant frequency of a crystal is

temperature dependent, the RTC performance will also be

dependent upon temperature. The fre quency deviation of

the crystal is a function of the turnover temperature of the

crystal from the crystal’s nominal frequency. For example, a

~20ppm frequency deviation translates into an accuracy of

~1 minute per month. These parameters are ava ilable from

the crystal manufacturer. The ISL1208 provides on-chip

crystal compensation networks to adjust load capacit ance to

tune oscillator frequency from -94ppm to +140 ppm. For

more detailed information. See “Application Section” on

page 18.

Single Event and Interrupt

The alarm mode is enabled via the ALME bit. Choosing

single event or interrupt alarm mode is selected via the IM

bit. Note that when the frequency output function is enabled,

the alarm function is disabled.

The standard alarm allows for alarms of time, date, day of

the week, month, and year. When a time alarm occurs in

single event mode, an IRQ pin will be pulled low and the

alarm status bit (ALM) will be set to “1”.

The pulsed interrupt mode allows for repetitive or recurri ng

alarm functionality. Hence, once the alarm is set, the device

will continue to alarm for each occurring match of the alarm

and present time. Thus, it will alarm as often as every minute

(if only the nth second is set) or as infrequently as once a

year (if at least the nth month is set). During pulsed interrupt

mode, the IRQ pin will be pulled low for 250ms and the alarm

status bit (ALM) will be set to “1”.

NOTE: The ALM bit can be reset by the user or cleared

automatically using the auto reset mode (see ARST bit).

The alarm function can be enabled/disabled during battery

backup mode usi n g th e FO BATB bit. For more information

on the alarm, See “Alarm Registers” on page 14.

Frequency Output Mode

The ISL1208 has the option to provide a frequency output

signal using the IRQ/F OUT pin. The frequency output mode

is set by using the FO bits to select 15 possible output

frequency values from 0kHz to 32kHz. The frequency output

can be enabled/disabled during battery backup mode using

the FOBATB bit.

General Purpose User SRAM

The ISL1208 provides 2 bytes of user SRAM. The SRAM will

continue to operate in battery backup mode. However, it

should be noted that the I2C bus is disabled in battery

backup mode.

I2C Serial Interface

The ISL1208 has an I2C serial bus interface that provides

access to the control and status registers and the user

SRAM. The I2C serial interface is compatible with other

industry I2C serial bus protoco ls using a bidirectional data

signal (SDA) and a clock signal (SCL).

Oscillator Comp en sat io n

The ISL1208 provides the option of timing correction due to

temperature variation of the crystal oscillator for either

manufacturing calibration or active calibration. The total

possible compensation is typically -94ppm to +140ppm. Two

compensation mechanisms that are available are as follows:

1. An analog trimming (ATR) register that can be used to

adjust individual on-chip digital capacitors for oscillator

capacitance trimming. The individual digital capaci tor is

selectable from a range of 9pF to 40.5pF (based upon

32.758kHz). This translates to a calculated

compensation of approximately -34ppm to +80ppm. (See

ATR descri ption on page 18).

2. A digital trimming register (DTR) that can be used to

adjust the timing counter by ±60ppm. (See DTR

description on page 18).

Also provided is the ability to adjust the crystal capacitance

when the ISL1208 switches from VDD to battery backup

mode. See “Battery Backup Mode (VBAT) to Normal Mode

(VDD)” on page 9.

The battery-backed registers are accessible following a

slave byte of “1101111x” and reads or writes to addresses

[00h:13h]. The defined addre s ses and default values are

described in Table 1. Address 09h is not used. Reads or

writes to 09h will not affect operation of the device but should

be avoided.

The contents of the registers can be modified by performing

a byte or a page write operation directly to any register

address.

The registers are divided into 4 sections. These are:

1. Real Time Clock (7 bytes): Address 00h to 06h.

2. Control and Status (5 bytes): Address 07h to 0Bh .

3. Alarm (6 bytes): Address 0Ch to 11h.

4. User SRAM (2 bytes): Address 12h to 13h.

There are no addresses above 13h.

ISL1208

11 FN8085.8

September 12, 2008

Write capability is allowable into the RTC registers (00h to

06h) only when the WRTC bit (bit 4 of address 07h) is set to

“1”. A multi-byte read or write op eration is li mited to o ne

section per operation. Access to another section requires a

new operation. A read or write can begin at any address

within the se cti o n.

A register can be read by performing a random read at any

address at any time. This returns the contents of that register

location. Additional registers are read by performing a

sequential read. For the RTC and Alarm registers, the read

instruction latches all clock registers into a buffer, so an

update of the clock does not change the time being read. A

sequential read will not result in the output of data from the

memory array. At the end of a read, the master supplies a

stop condition to end the operation and free the bus. After a

read, the address remains at the previous address +1 so the

user can execute a current address read and continue

reading the next register.

It is not necessary to set the WRTC bit prior to writing into

the control and status, alarm, and user SRAM registers.

TABLE 1. REGISTER MEMORY MAP

ADDR. SECTION REG

NAME

BIT

RANGE DEFAULT 76543210

00h

RTC

SC 0 SC22 SC21 SC20 SC13 SC12 SC11 SC10 0 to 59 00h

01h MN 0 MN22 MN21 MN20 MN13 MN12 MN11 MN10 0 to 59 00h

02h HR MIL 0 HR21 HR20 HR13 HR12 HR11 HR10 0 to 23 00h

03h DT 0 0 DT21 DT20 DT13 DT12 DT11 DT10 1 to 31 00h

04h MO 0 0 0 MO20 MO13 MO12 MO11 MO10 1 to 12 00h

05h YR YR23 YR22 YR21 YR20 YR13 YR12 YR11 YR10 0 to 99 00h

06h DW00000DW2DW1DW00 to 600h

07h

Control

and

Status

SR ARST XTOSCB Reserved WRTC Reserved ALM BAT RTCF N/A 01h

08h INT IM ALME LPMODE FOBATB FO3 FO2 FO1 FO0 N/A 00h

09h Reserved N/A 00h

0Ah ATR BMATR1 BMATR0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 N/A 00h

0Bh DTR Reserved DTR2 DTR1 DTR0 N/A 00h

0Ch

Alarm

SCA ESCA ASC22 ASC21 ASC20 ASC13 ASC12 ASC11 ASC10 00 to 59 00h

0Dh MNA EMNA AMN22 AMN21 AMN20 AMN13 AMN12 AMN11 AMN10 00 to 59 00h

0Eh HRA EHRA 0 AHR21 AHR20 AHR13 AHR12 AHR11 AHR10 0 to 23 00h

0Fh DTA EDTA 0 ADT21 ADT20 ADT13 ADT12 ADT11 ADT10 1 to 31 00h

10h MOA EMOA 0 0 AMO20 AMO13 AMO12 AMO11 AMO10 1 to 12 00h

11h DWAEDWA0000ADW12ADW11ADW100 to 600h

12h User USR1 USR17 USR16 USR15 USR14 USR13 USR12 USR11 USR10 N/A 00h

13h USR2 USR27 USR26 USR25 USR24 USR23 USR22 USR21 USR20 N/A 00h

ISL1208

12 FN8085.8

September 12, 2008

Real Time Clock Registers

Addresses [00h to 06h]

RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW)

These registers depict BCD representations of the time. As

such, SC (Seconds) and MN (Minutes) range from 0 to 59,

HR (Hour) can either be a 12-hour or 24-hour mode, DT

(Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99,

and DW (Day of the Week) is 0 to 6.

The DW register provides a Day of the W eek st atus and uses

three bits DW2 to DW0 to represent the seven days of the

we ek. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-

2-… The assignment of a numerical value to a specific day

of the week is arbitrary and may be decided by the system

software designer. The default valu e is defined as “0”.

24 HOUR TIME

If the MIL bit of the HR register is “1”, the RTC uses a 24-

hour format. If the MIL bit is “0”, the RTC uses a 12-hour

format and HR21 bit functions as an AM/PM indicator with a

“1” representing PM. The clock defaults to 12-hour format

time with HR21 = “0”.

LEAP YEARS

Leap years add the day February 29 and are defined as those

years that are divisible by 4. Years divisible by 100 are not leap

years, unless they are also divisible by 400. This means that

the year 2000 is a leap year , the year 2100 is not. The ISL1208

does not correct for the leap year in the year 2100.

Control and Status Registers

Addresses [07h to 0Bh]

The Control and Status Registers consist of the Status

Digital Trimming Registers.

Status Register (SR)

The Status Register is located in the memory map at

address 07h. This is a volatile register that provides either

control or status of RTC failure, battery mode, al arm trigger,

write protection of clock counter , crystal oscillator enable and

auto reset of status bits.

REAL TIME CLOCK FAIL BIT (RTCF)

This bit is set to a “1” after a total power failure. This is a read

only bit that is set by hardware (ISL1208 internally) when the

device powers up after having lost all power to the device

(both VDD and VBAT go to 0V). The bit is set rega rd le ss of

whether VDD or VBAT is applied first. The loss of only one of

the supplies does not set the RTCF bit to “1”. On power-up

after a total power failure, all registers are set to their default

states and the clock will not increment until at least one byte

is written to the clock register . The first valid write to the RTC

section after a complete power failure resets the RTCF bit to

“0” (writing one byte is sufficient).

BATTERY BIT (BAT)

This bit is set to a “1” when the device enters battery backup

mode. This bit can be reset either manually by the user or

automatically reset by enabling the auto-reset bit (see ARST

bit). A write to this bit in the SR can only set it to “0”, not “1”.

ALARM BIT (ALM)

These bits announce if the alarm matches the real time

clock. If there i s a m atch, the re spective bit is set to “1”. This

bit can be manually reset to “0” by the user or automatically

reset by enabling the auto-reset bit (see ARST bit). A write to

this bit in the SR can only set it to “0”, not “1”.

NOTE: An alarm bit that is set by an alarm occurring during an SR

read operation will remain set after the read operation is complete.

WRITE RTC ENABLE BIT (WRTC )

The WRTC bit enables or disables write capability into the

RTC Timing Registers. The factory default setting of this bit

is “0”. Upon initialization or power-up, the WRTC must be set

to “1” to enable the RTC. Upon the completion of a valid

write (STOP), the RTC starts counting. The RTC internal

1Hz signal is synchronized to the STOP condition during a

valid write cycle.

CRYSTA L OSCILLATOR ENABLE BIT (XTOSCB)

This bit enables/disables the internal crystal oscillator . When

the XTOSCB is set to “1”, the oscillator is disabled, and the

X1 pin allows for an external 32kHz signal to drive the RTC.

The XTOSCB bit is set to “0” on power-up.

AUTO RESET ENABLE BIT (ARST)

This bit enables/disables the automatic reset of the BAT and

ALM status bits only. When ARST bit is set to “1”, these

status bits are reset to “0” after a valid read of the respective

status register (with a valid STOP condition). When the

ARST is cleared to “0”, the user must manually reset the

BAT and ALM bits.

Interrupt Control Register (INT)

TABLE 2. STATUS REGISTER (SR)

ADDR 7 6 5 4 3 2 1 0

07h ARST XTOSCB reserved WRTC reserved ALM BAT RTCF

Default00 000000

TABLE 3. INTERRUPT CONTROL REGISTER (INT)

ADDR7 6 5 4 3210

08h IM ALME LPMODE FOBATB FO3 FO2 FO1 FO0

Default0 0 0 0 0000

ISL1208

13 FN8085.8

September 12, 2008

FREQUENCY OUT CONTROL BITS (FO <3:0>)

These bits enable/disable the frequency output function and

select the output frequency at the IRQ/fOUT pin. See

Table 4 for frequency selection. When the frequency mode is

enabled, it will override the alarm mode at the IRQ/fOUT pin.

FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)

This bit enables/disables the fOUT/IRQ pin during battery

backup mode (i.e. VBAT power source active). When the

FOBATB is set to “1” the fOUT/IRQ pin is disabled during

battery backup mode. This means that both the frequency

output and alarm output functions are disabled. When the

FOBATB is cleared to “0”, the fOUT/IRQ pin is enabled

during battery backup mode.

LOW POWER MODE BIT (LPMODE)

This bit enables/disables low power mode. With

LPMODE = “0”, the device will be in normal mode and the

VBAT supply will be used when VDD < VBAT - VBATHYS and

VDD < VTRIP. With LPMODE = “1”, the device will be in low

power mode and the VBAT supply will be used when

VDD < VBAT -V

BATHYS. There is a supply current saving of

about 600nA when using LPMODE = “1” with VDD = 5V.

(See Typical Performance Curves on page 7: IDD vs VCC

with LPMODE ON and OFF.) Avoid setting the device into

low power mode with VDD < VBAT, the I2C communications

will stop permanently. The VBAT input must be lowered

below VDD to resume communications.

ALARM ENABLE BIT (ALME)

This bit enables/disables the alarm function. When the ALME

bit is set to “1”, the alarm function is enabled. When the ALME

is cleared to “0”, the alarm function is disabled. The alarm

function can operate in either a single event alarm or a periodic

interrupt alarm (see IM bit).

NOTE: When the frequency output mode is enabled, the alarm function

is disabled.

INTERRUPT/ALARM MODE BIT (IM)

This bit enables/disables the interrupt mode of the alarm

function. When the IM bit is set to “1”, the alarm will operate

in the interrupt mode, where an active low pu lse width of

250ms will appear at the IRQ/fOUT pin when the RTC is

triggered by the alarm as defined by the alarm registers (0Ch

to 11h). When the IM bit is cleared to “0”, the alarm will

operate in standard mode, where the IRQ/fOUT pin will be

tied low until the ALM status bit is cleared to “0”.

Analog Trimming Register

ANALOG TRIMMING REGISTER (ATR<5:0>)

Six analog trimming bits, ATR0 to ATR5, are provided in

order to adjust the on-chip load capacitance value for

frequency compensation of the RTC. Each bit has a different

weight for capacitance adjustment. For example, using a

Citizen CFS-206 crystal with different ATR bit combinations

provides an estimated ppm adjustment range from -34ppm

to +80ppm to the nominal frequency compensation. The

combination of analog and digital trimming can give up to

-94ppm to +140ppm of total adjustment.

The effective on-chip series load capacitance, CLOAD,

ranges from 4.5pF to 20.25pF with a mid-scale value of

12.5pF (default). CLOAD is changed via two digitally

controlled capacitors, CX1 and CX2, connected from the X1

and X2 pins to ground (see Figure 1 1). The value of CX1 and

CX2 are given in Equation 1:

TABLE 4. FREQUENCY SELECTION OF fOUT PIN

FREQUENCY,

fOUT UNITS FO3 FO2 FO1 FO0

0 Hz0 000

32768 Hz 0 0 0 1

4096 Hz 0 0 1 0

1024 Hz 0 0 1 1

64 Hz0 100

32 Hz0 101

16 Hz0 110

8 Hz0 111

4 Hz1 000

2 Hz1 001

1 Hz1 010

1/2 Hz1 011

1/4 Hz1 100

1/8 Hz1 101

1/16 Hz 1 1 1 0

1/32 Hz 1 1 1 1

IM BIT INTERRUPT/ALARM FREQUENCY

0 Single Time Event Set By Alarm

1 Repetitive/Recurring Time Event Set By Alarm

FIGURE 11. DIAGRAM OF ATR

CX1

CRYSTAL

OSCILLATOR

CX2

CX16 b5⋅8b44b32b21b10.5b09+⋅+⋅+⋅+⋅+⋅+()pF=(EQ. 1)

ISL1208

14 FN8085.8

September 12, 2008

The effective series load capacitance is the combination of

CX1 and CX2 in Equation 2.:

For exam ple , CLOAD (ATR = 00000) = 12.5pF, CLOAD (ATR =

100000) = 4.5pF, and CLOAD (ATR = 011111) = 20.25pF. The

entire range for the series combination of load capacitance

goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these

are typical values.

BATTERY MODE ATR SELECTION (BMATR <1:0>)

Since the accuracy of the crystal oscillator is dependent on

the VDD/VBAT operation, the ISL1208 provides the capability

to adjust the capacitance between VDD and VBAT when the

device switches between power sources.

DIGIT AL TRIMMING REGISTER (DTR <2:0>)

The digital trimming bits DTR0, DTR1, and DTR2 adjust the

average number of counts per second and average the ppm

error to achieve better accuracy.

• DTR2 is a sign bit. DTR2 = “0” means frequency

compensation is >0. DTR2 = “1” means frequency

compensation is <0.

• DTR1 and DTR0 are both scale bits. DTR1 gives 40ppm

adjustment and DTR0 gives 20pp m adjustment.

A range from -60ppm to +60ppm can be represented by

using these three bits (see Table 5).

Alarm Registers

Addresses [0Ch to 11h]

The alarm register bytes are set up identical to the RTC

an enable bit (enable = “1”). These enable bits specify which

alarm registers (seconds, minutes, etc.) are used to make

the comparison. Note that there is no alarm byte for year.

The alarm function works as a comparison between the

alarm registers an d the RTC registers. As the RTC

advances, the alarm will be triggered once a match occurs

between the alarm registers and the RTC registers. Any one

alarm register, multiple registers, or all registers can be

enabled for a match.

There are two alarm operation modes: Single Event and

periodic Interrupt Mode:

•Single Event Mode is enabled by setting the ALME bit to

“1”, the IM bit to “0”, and disabling the frequency output.

This mode permits a one-time match between the alarm

registers and the RTC registers. Once this match occurs,

the ALM bit is set to “1” and the IRQ output will be pulled

low and will remain low until the ALM bit is reset. This can

be done manually or by using the auto-reset feature.

•Interrupt Mode is enabled by setting the ALME bit to “1”,

the IM bit to “1”, and disabling the frequency output. The

IRQ output will now be pulsed each time an alarm occurs.

This means that once the interrupt mode alarm is set, it

will continue to alarm for each occurring ma tch of the

alarm and present time. This mode is convenient for

hourly or daily hardware interrupts in microcontroller

applications such as security camera s or utility meter

reading.

To clear an alarm, the ALM bit in the status register must be

set to “0” with a write. Note that if the ARST bit is set to 1

(address 07h, bit 7), the ALM bit will automatically be cleared

when the status register is read.

BMATR1 BMATR0

DELTA

CAPACITANCE

(CBAT TO CVDD)

0 0 0pF

0 1 -0.5pF (≈ +2ppm)

1 0 +0.5pF (≈ -2ppm)

1 1 +1pF (≈ -4ppm)

CLOAD 1

CX1

-----------1

CX2

-----------

⎝⎠

⎛⎞

-----------------------------------

CLOAD 16 b5

⋅8 b4 4 b3 2 b2 1 b1 0.5 b0 9+⋅+⋅+⋅+⋅+⋅+2

-----------------------------------------------------------------------------------------------------------------------------

⎝⎠

⎛⎞

(EQ. 2)

TABLE 5. DIGITAL TRIMMING REGISTERS

DTR REGISTER ESTIMATED

FREQUENCY

PPMDTR2 DTR1 DTR0

0 0 0 0 (default)

001 +20

010 +40

011 +60

100 0

101 -20

110 -40

111 -60

ISL1208

15 FN8085.8

September 12, 2008

Below are examples of both Single Event and periodic

Interrupt Mode alarms.

Example 1 – Alarm set with single interrupt (IM=”0”)

A single alarm will occur on January 1 at 11:30am.

A. Set Alarm registers as follows:

B. Also the ALME bit must be set as follows:

xx indicate other control bits

After these registers are set, an alarm will be generated wh en

the RTC advances to exactly 11:30am on January 1 (after

seconds changes from 59 to 00) by setting the ALM bit in the

status register to “1” an d also bringing the IRQ output low.

Example 2 – Pulsed interrupt once per minute (IM=”1”)

Interrupts at one minute intervals when the seconds register

is at 30 seconds.

A. Set Alarm registers as follows:

B. Set the Interrupt register as follows:

xx indicate other control bits

Once the registers are set, the following waveform will be

seen at IRQ-:

Note that the status register ALM bit will be set each time the

alarm is triggered, but does not need to be read or cleared.

User Registers

Addresses [12h to 13h]

These registers are 2 bytes of battery-backe d user memory

storage.

I2C Serial Interface

The ISL1208 supports a bidirectional bus oriented protocol.

The protocol defines any device that sends data onto the

bus as a transmitter and the receiving device as the receiver .

The device controlling the transfer is the ma ster and the

device being controlle d is the slave. The master always

initiates data transfers and provides the clock for both

transmit and receive operations. Therefore, the ISL1208

operates as a slave device in all applications.

All communication over the I2C interface is conducted by

sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating START and STOP conditions (See

Figure 12). On power-up of the ISL1208, the SDA pin is in

the input mode.

All I2C interface operations must begin with a START

condition, which is a HIGH to LOW transition of SDA while

SCL is HIGH. The ISL1208 continuously monitors the SDA

and SCL lines for the START condition and does not

respond to any command until this condition is met (See

Figure 12). A START condition is ignored during the

power-up sequence.

All I2C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while

SCL is HIGH (See Figure 12). A STOP condition at the end

of a read operation or at the end of a write operation to

memory only places the device in its standby mode.

An acknowledge (ACK) is a software convention us ed to

indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after

transmitting eight bits. During the ninth clock cycle, the

ALARM

BIT

DESCRIPTION76543210HEX

SCA 00000000 00hSeconds disabled

MNA 10110000B0hMinutes set to 30,

enabled

HRA 10010001 91hHours set to 11,

enabled

DTA 10000001 81hDate set to 1,

enabled

MOA 10000001 81hMonth set to 1,

enabled

DWA 00000000 00hDay of week

disabled

CONTROL

BIT

DESCRIPTION76543210HEX

INT 01xx0000 x0hEnable Alarm

ALARM

BIT

DESCRIPTION76543210HEX

SCA 10110000B0hSeconds set to 30,

enabled

MNA 0000000000hMinutes disabled

HRA 0000000000hHours disabled

DTA 0000000000hDate disabled

MOA 0000000000hMonth disabled

DWA 0000000000hDay of week disabled

CONTROL

BIT

DESCRIPTION76543210HEX

INT 11xx0000x0hEnable Alarm and Int

Mode

60s

RTC AND ALARM REGISTERS ARE BOTH “30”s

ISL1208

16 FN8085.8

September 12, 2008

receiver pulls the SDA line LOW to ackn owledge the

reception of the eight bits of data (See Figure 13).

The ISL1208 responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and

once again after successful receipt of an Address Byte. The

ISL1208 also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an

ACK after receiving a Data Byte of a read operation.

FIGURE 12. VALID DATA CHANGES, START, AND STOP CONDITIONS

FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER

FIGURE 14. BYTE WRITE SEQUENCE

SDA

SCL

START DATA DATA STOP

STABLE CHANGE DATA

STABLE

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

81 9

START ACK

SCL FROM

MASTER

HIGH IMPEDANCE

IDENTIFICATION

BYTE DATA

BYTE

SIGNALS FROM

THE MASTER

SIGNALS FROM

THE ISL1208 A

10011

WRITE

SIGNAL AT SDA 0000111

ADDRESS

BYTE

ISL1208

17 FN8085.8

September 12, 2008

Device Addressing

Following a start condition, the master must output a Slave

Address Byte. The 7 MSBs are the device identifier. These

bits are “1101111”. Slave bits “1101” access the register.

Slave bits “111” specify the device select bits.

The last bit of the Slave Address Byte defines a read or write

operation to be performed. When this R/W bit is a “1”, then a

read operation is selected. A “0” selects a write operation

(Refer to Figure 15).

After loading the entire Slave Address Byte from the SDA

bus, the ISL1208 compares the device identifier and device

select bits with “1101111”. Upon a correct compare, the

device outputs an acknowledge on the SDA line.

Following the Slave Byte is a one byte word address. The

word address is either supplied by the master device or

obtained from an internal counter. On power-up the internal

address counter is set to address 0h, so a current address

read of the CCR array starts at address 0h. When required,

as part of a random read, the master must supply the 1 Word

Address Bytes as shown in Figure 16.

In a random read operation, the slave byte in the “dummy

write” portion must match the slave byte in the “read”

section. For a random read of the Clock/Control Registers,

the slave byte must be “1101111x” in both places.

Write Operation

A Write operation requires a START condition, followed by a

valid Identification Byte, a valid Address Byte, a Data Byte,

and a STOP condition. After each of the th ree bytes, the

ISL1208 responds with an ACK. At this time, the I2C

interface enters a standby state.

Read Operation

A Read operation consists of a three byte instruction

followed by one or more Data Bytes (See Figure 16). The

master initiates the operation issuing the following

sequence: a START, the Identification byte with the R/W bit

set to “0”, an Address Byte, a second START, and a second

Identification byte with the R/W bit set to “1”. After each of

the three bytes, the ISL1208 responds with an ACK. Then

the ISL1208 transmits Data Bytes as long as the master

responds with an ACK during the SCL cycle following the

eighth bit of each byte. The master terminates the read

operation (issuing a STOP condition) following the last bit of

the last Data Byte (See Figure 16).

The Data Bytes are from the memory location indicated by

an internal pointer . This pointer initial value is determined by

the Address Byte in the Read operation instruction, and

increments by one during transmission of each Data Byte.

After reaching the memory location 13h the pointer “rolls

over” to 00h, and the device continues to output data for

each ACK received.

FIGURE 15. SLA VE ADDRESS, WORD ADDRESS, AND DAT A

BYTES

SLAVE

ADDRESS BYTE

D7 D6 D5 D2D4 D3 D1 D0

A0A7 A2A4 A3 A1

DATA BYTE

A6 A5

110 1

11R/W

WORD ADDRESS

FIGURE 16. READ SEQUENCE

SIGNALS

FROM THE

MASTER

SIGNALS FRO M

THE SLAVE

SIGNAL AT

SDA

IDENTIFICATION

BYTE WITH

R/W = 0 ADDRESS

BYTE

IDENTIFICATION

BYTE WITH

R/W = 1

LAST READ

DATA BYTE

FIRST READ

DATA BYTE

101 1111 1011111

ISL1208

18 FN8085.8

September 12, 2008

Application Section

Oscillator Crystal Requirements

The ISL1208 uses a standard 32.768kHz crystal. Either

through hole or surface mount crystals can be used. Table 6

lists some recommended surface mount crystals and the

parameters of each. This list is not exhaustive and other

surface mount devices can be used with the ISL1208 if their

specifications are very similar to the devices listed. The

crystal should have a required parallel load capacitance of

12.5pF and an equivalent series resistance of less than 50k.

The crystal’s temperature range specification should match

the application. Many crystals are rated for -10°C to +60°C

(especially through hole and tuning fork types), so an

appropriate crystal should be selected if extended

temperature range is required.

Crystal Oscillator Frequency Adjustment

The ISL1208 device contains circuitry for adjusting the

frequency of the crystal oscillator. This circu itry can be used

to trim oscillator initial accuracy as well as adjust the

frequency to compensate for temperature changes.

The Analog Trimming Register (ATR) is used to adjust the

load capacitance seen by th e crystal. There are six bits of

ATR control, with linear capacitance increments available for

adjustment. Since the A TR adjustment is essentially “pulling”

the frequency of the oscilla tor, the resulting frequency

changes will not be linear with incremental capacitance

changes. The equations which govern pulling show that

lower capacitor values of ATR adjustment will provide larger

increments. Also, the higher values of ATR adjustment will

produce smaller incremental frequency changes. These

values typically vary from 6ppm to 10 ppm/bit at the low end

to <1ppm/bit at the highest capacitance settings. The range

afforded by the ATR adjustment with a typical surface mount

crystal is typically -34ppm to +80ppm around the ATR=0

default setting because of this property. The user should

note this when using the ATR for calibration. The

temperature drift of the capacitance used in the ATR control

is extremely low , so this feature can be used for temperature

compensation with good accuracy.

In addition to the analog co mpensation afforded by the

adjustable load capacitance, a digital compensation feature

is available for the ISL1208. T here are 3 bits known as the

Digital Trimming Register (DTR). The range provided is

±60ppm in increments of 20ppm. DTR operates by adding or

skipping pulses in the clock counter. It is very useful for

coarse adjustments of frequency drift over temperature or

extending the adjustment range available with the AT R

Initial accuracy is best adjusted by enabling the frequency

output (using the INT register, address 08h), and monitoring

the ~IRQ/fOUT pin with a calibrated frequency counter. The

frequency used is unimportant, although 1Hz is the easiest

to monitor. The gating time should be set long enough to

ensure accuracy to at least 1ppm. The ATR should be set to

the center position, or 100000Bh, to begin with. Once the

initial measurement is made, then the ATR register can be

changed to adjust the frequency. Note that increasing the

ATR register for increase d capacitance will lower the

frequency, and vice-versa. If the initial measurement shows

the frequency is far off, it will be necessary to use the DTR

crystals will have tight enough initial accuracy at room

temperature so that a small ATR register adjustment sho uld

be all that is needed.

Temperature Compensation

The ATR and DTR controls can be combined to provide

crystal drift temperature compensation. The typical

32.768kHz crystal has a drift characteristic that is similar to

that shown in Figure 17. There is a turnover temperature

(T0) where the drift is very near zero. The shape is parabolic

as it varies with the square of the difference between the

actual temperature and the turnover temperature.

If full industrial temperature compensation is desired in an

ISL1208 circuit, then both the DTR and ATR registers will

need to be utilized (total correction range = -94ppm to

+140ppm).

TABLE 6. SUGGESTED SURFACE MOUNT CRYSTALS

MANUFACTURER PART NUMBER

Citizen CM200S

Epson MC-405, MC-406

Raltron RSM-200S

SaRonix 32S12

Ecliptek ECPSM29T-32.768K

ECS ECX-306

Fox FSM-327

TEMPERATURE (°C)

-160

-140

-120

-100

-80

-60

-40

-20

-40-30-20-100 1020304050607080

PPM

FIGURE 17. RTC CRYSTAL TEMPERATURE DRIFT

ISL1208

19 FN8085.8

September 12, 2008

A system to implement temperature compensation would

consist of the ISL1208, a temperature sensor, and a

microcontroller . These devices may already be in the system

so the function will just be a matter of implementing software

and performing some calculations. Fairly accurate

temperature compensation can be implemented just by

using the crystal manufacturer’s specifications for the

turnover temperature T0 and the drift coefficient (β). The

formula for ca lculating th e oscillator ad justment necessa ry is

Equation 3:

Once the temperature curve for a crystal is established, then

the designer should decide at what discrete temperatu r es

the compensation will change. Since drift is higher at

extreme temperatures, the compensation may not be

needed until the temperature is greater than +20°C from T0.

A sample curve of the ATR setting vs Frequency Adjustment

for the ISL1208 and a typical RTC crystal is given in

Figure 18. This curve may vary with different crystals, so it is

good practice to evaluate a given crystal in an ISL1208

circuit before establishing the adjustment values.

This curve is then used to figure what ATR and DTR settings

are used for compensation. The results would be placed in a

lookup table for the microcontroller to access.

Note that the ATR register affects the FOUT freque ncy

directly. Also, the DTR setting will affect the FOUT frequency

for all but the 32.768Khz setting, due to the clock correction

in the divider chain.

Layout Considerations

The crystal input at X1 has a very high impedance, and

oscillator circuits operating at low frequencies such as

32.768kHz are known to pick up noise very easily if layout

precautions are not followed. Most instances of erratic

clocking or large accuracy errors can be traced to the

susceptibility of the oscillator circuit to interference from

adjacent high speed clock or data lines. Careful layout of the

RTC circuit will avoid noise pickup and insure accurate

clocking.

Figure 19 shows a suggested layout for the ISL1208 device

using a surface mount crystal. Two main precautions should

be followed:

1. Do not run the serial bus line s or an y high speed logic

lines in the vicinity of the crystal. These logic level lines

can induce noise in the oscillator circuit to cause

misclocking.

2. Add a ground trace around th e crystal with one end

terminated at the chip ground. This will provide

termination for emitted noise in the vicinity of the RTC

device.

In addition, it is a good idea to avoid a ground plane under

the X1 and X2 pins and the crystal, as this will affect the load

capacitance and therefore the oscillator accuracy of the

circuit. If the IRQ/FOUT pin is used as a clock, it should be

routed away from the RTC device as well. The traces for the

VBAT and VCC pins can be treated as a ground, and should

be routed around the crystal.

Battery Backup Considerations

The ISL1208 device provides a VBAT pin which is used for a

battery backup input. The battery voltage can vary from 1.8V

up to 5.5V, independent of the VDD supply voltage. An

internal switch automatically connects the VBAT supply to

the to the internal power node when VDD power goes away,

and switches back to VDD when power returns.

Since this battery switch draws power from the battery, it is

very low power and not very fast. If the VDD drops too

quickly to 0V, th ere is not enough time for the switch to

connect the VBAT source to the internal power node, and the

SRAM contents can be lost or corrupted. It is a good idea to

keep power-down ramps longer than 50us to insure data

retention.

Battery drain can be minimized by using the LPMODE

option. Since normally the VBAT and VDD need to be

monitored in order to switch at the lower voltage, two

comparator function are needed during battery backup.

LPMODE shuts off one of the comparators and just

compares VDD to VBAT to activate switchover. This saves

about 500nA of VBAT current at 3.0V. Do not use LPMODE

when VBAT ≥ VDD - 0.2V, to avoid permanently placing the

device in battery backup mode.

Adjustment(ppm) T T0

–()

=∗β(EQ. 3)

-40

-30

-20

-10

0 5 10 15 20 25 30 35 40 45 50 55 60

ATR SETTING

PPM ADJUSTMENT

FIGURE 18. A TR SETTING vs OSCILLATOR FREQUENCY

ADJUSTMENT

FIGURE 19. SUGGESTED LAYOUT FOR ISL1208 AND

CRYSTAL

ISL1208

20 FN8085.8

September 12, 2008

Another consideration is systems with either ground bounce

or power supply transients that cause the VDD pin to drop

below ground for more than a few nanoseconds. This type of

power glitch can override the VBAT backup and reset or

corrupt the SRAM. If these transient glitches are present in a

system with the ISL1208, or the device is experiencing

unexplained loss of data when returning from VBAT mode, a

protection circuit should be added. Figure 20 shows a circuit

which effectively isolates the VDD input from negative

glitches. The Schottky dio de is needed to for low voltage

drop and effective protection from the negative transient.

Note that this circuit will also help if the VDD fall time is less

than 50us as CIN holds up the VDD pin during the transient.

There is also a shunt shown between the battery and the

VBAT pin. This is for quick disconnect if there is a situation

where a transient has latched the device and it will not

communicate on the I2C bus. If ground bounce is a problem,

then a second Schottky diode should be added between the

battery and the VBAT pin.

Super Capacitor Backup

A Super Capacitor can be used as an alternative to a battery

in cases where shorter backup times are required. Since the

battery backup supply current required by the ISL1208 is

extremely low, it is possible to get months of backup

operation using a Super Capacitor. Typical capacitor values

are a few µF to 1F or more depending on the applica tio n.

If backup is only needed for a few minutes, then a small

inexpensive electrolytic capacitor can be used. For extended

periods, a low leakage, high capacity Super Capacitor is the

best choice. These devices are available from such vendors

as Panasonic and Murata. The main specifications include

working voltage and leakage current. If the application is for

charging the capacitor from a +5V ±5% supply with a signal

diode, then the voltage on the capacitor can vary fr om ~4.5V

to slightly over 5.0V. A capacitor with a rated WV of 5.0V

may have a reduced lifetime if the supply voltage is slightly

high. The leakage current should be as small as possible.

For example, a Super Capacitor should be specified with

leakage of well below 1µA. A standard electrolytic capacitor

with DC leakage current in the microamps will have a

severely shortened backup time.

Below are some examples with equations to assist with

calculating backup times and required capacitance for the

ISL1208 device. The backup supply current plays a major

part in these equations, and a typical value was chosen for

example purposes. For a robust design, a margin of 30%

should be included to cover sup ply current and capacitance

tolerances over the results of the calculations. Even more

margin should be included if periods of very warm

temperature operation are expected .

Example 1. Calculating Backup Time Given

Voltages and Capacitor Value

In Figure 21, use CBAT = 0.47F and VCC = 5.0V. With

VCC = 5.0V, the voltage at VBAT will approach 4.7V as the

diode turns off completely. The ISL1208 is specified to

operate down to VBAT = 1.8V. The capacitance

charge/discharge equation (Equation 4) is used to estimate

the total backup time:

Rearranging gives:

CBAT is the backup capacitance and dV is the change in

voltage from fully charged to loss of operation. Note that

ITOT is the total of the supply current of the ISL1208 (IBAT)

plus the leakage current of the capacitor and the diode, ILKG.

In these calculations, ILKG is assumed to be extremely small

and will be ignored. If an application requires extende d

operation at temperatures over +50°C, these leakages will

increase and hence reduce backup time.

Note that IBAT changes with VBAT almost linearly (see

Typical Performance Curves on page 7). This allows us to

make an approximation of IBAT, using a value midway

between the two endpoints. The typical linear equ ation for

IBAT vs VBAT is in Equation 6:

Using this equation to solve for the average current given 2

voltage points gives Equation 7:

FIGURE 20. POWER GLITCH PROTECTION CIRCUIT

2.7V TO 5.5V

VDD VBAT

GND

BAT54

ISL1208 CBAT

CIN BT1

3.0V

3.6V

0.1µF

SHUNT

DIN FIGURE 21. SUPERCAPACITOR CHARGING CIRCUIT

2.7V TO 5.5V VDD VBAT

GND

1N4148

CBAT

I = CBAT * dV/dT (EQ. 4)

dT = CBAT * dV/ITOT to solve for backup time. (EQ. 5)

IBAT = 1.031E-7 *(VBAT) + 1.036E-7 Amps (EQ. 6)

IBATAVG = 5.155E-8*(VBAT2 + VBAT1) + 1.036E-7 Amps

(EQ. 7)

ISL1208

21 FN8085.8

September 12, 2008

Combining with Equation 5 gives the equation for backup

time in Equation 8:

where:

CBAT = 0.47F

VBAT2 = 4.7V

VBAT1 = 1.8V

ILKG = 0 (assumed minimal)

Solving Equation 7 for this example, IBATAVG = 4.387E-7 A

TBACKUP = 0.47 * (2.9) / 4.38E-7 = 3.107E6 sec

Since there are 86,400 seconds in a day , this corresponds to

35.96 days. If the 30% tolerance is included for capacitor

and supply current tolerances, then worst case backup time

would be:

CBAT = 0.70 * 35.96 = 25.2 days

Example 2. Calculating a Capacitor Value for a

Given Backup Time

Referring to Figure 21 again, the capacitor value needs to be

calculated to give 2 months (60 days) of backup time, given

VCC = 5.0V. As in Example 1, the VBAT voltage will vary from

4.7V down to 1.8V. We will need to rearrange Equation 5 to

solve for capacitance in Equation 9:

Using the terms described above, this equation becomes

Equation 10:

where:

TBACKUP = 60 days * 86,400 sec/day = 5.18 E6 seconds

IBATAVG = 4.387 E-7 A (same as Example 1)

ILKG = 0 (assumed)

VBAT2 = 4.7V

VBAT1 = 1.8VSolving gives

CBAT = 5.18 E6 * (4.387 E-7)/(2.9) = 0.784F

If the 30% tolerance is included for tolerances, then worst

case capacitor value would be:

TBACKUP = CBAT * (VBAT2 - VBAT1) / (IBATAVG + ILKG)

(EQ. 8)

seconds

CBAT = dT*I/dV (EQ. 9)

CBAT = TBACKUP * (IBATAVG + ILKG)/(VBAT2 – VBAT1)

(EQ. 10)

(EQ. 11)

CBAT 1.3 0.784 1.02F=×=

ISL1208

22 FN8085.8

September 12, 2008

ISL1208

Thin Dual Flat No-Lead Plastic Package (TDFN)

NX (b)

SECTION "C-C"

(A1)

BOTTOM VIEW

AREA

INDEX

0.10

0.08

SIDE VIEW

0.15

C0.15

TOP VIEW

AREA

INDEX

NX L

E2/2

REF.

(Nd-1)Xe

(DATUM A)

(DATUM B)

0.10

N-1

PLANE

SEATING

NX b

D2/2

NX k

FOR EVEN TERMINAL/SIDE

TERMINAL TIP

L1 10 L

L8.3x3A

8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

SYMBOL

MILLIMETERS

NOTESMIN NOMINAL MAX

A 0.70 0.75 0.80 -

A1 - 0.02 0.05 -

A3 0.20 REF -

b 0.25 0.30 0.35 5, 8

D 3.00 BSC -

D2 2.20 2.30 2.40 7, 8, 9

E 3.00 BSC -

E2 1.40 1.50 1.60 7, 8, 9

e 0.65 BSC -

k0.25 - - -

L 0.20 0.30 0.40 8

N82

Nd 4 3

Rev. 3 11/04

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.

9. Compliant to JEDEC MO-WEEC-2 except for the “L” min

dimension.

23 FN8085.8

September 12, 2008

ISL1208

Small Outline Package Family (SO)

GAUGE

PLANE

A1 L

DETAIL X 4° ±4°

SEATING

PLANE

0.010 BMCA

0.004 C

0.010 BMCA

(N/2)

NN (N/2)+1

PIN #1

I.D. MARK

h X 45°

SEE DETAIL “X”

0.010

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL

INCHES

TOLERANCE NOTESSO-8 SO-14

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28)

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

Rev. M 2/07

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Int ersi l or it s sub sidi ari es.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8085.8

September 12, 2008

ISL1208

Mini Small Outline Plastic Packages (MSOP)

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Datum Plane. Mold flash, protrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

and are measured at Datum Plane. Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only.

0.25

(0.010)

4X θ

GAUGE

PLANE

SEATING

PLANE

EE1

TOP VIEW

INDEX

AREA

-C-

-B-

0.20 (0.008) ABC

SEATING

PLANE

0.20 (0.008) C

0.10 (0.004) C

-A-

-H-

SIDE VIEW

-B-

END VIEW

0.20 (0.008) CD

- H -

-A - - B -

- H -

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.010 0.014 0.25 0.36 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.026 BSC 0.65 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N8 87

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

o15o5o15o-

α0o6o0o6o-

Rev. 2 01/03