Micrel, Inc. 5V/3.3V PROGRAMMABLE FREQUENCY SYNTHESIZER (25MHz to 400MHz) Precision Edge(R) SY89429V (R) Precision Edge SY89429V FEATURES 3.3V and 5V power supply options 25MHz to 400MHz differential PECL outputs 50ps peak-to-peak output jitter Minimal frequency over-shoot Synthesized architecture Serial 3-wire interface Parallel interface for power-on Internal quartz reference oscillator driven by quartz crystal Application Note (AN-07) for ease of design-ins Available in 28-pin PLCC and SOIC packages Precision Edge(R) DESCRIPTION The SY89429V is a general purpose, synthesized clock source targeting applications that require both serial and parallel interfaces. Its internal VCO will operate over a range of frequencies from 400MHz to 800MHz. The differential PECL output can be configured to be the VCO frequency divided by 2, 4, 8 or 16. With the output configured to divide the VCO frequency by 2, and with a 16MHz external quartz crystal used to provide the reference frequency, the output frequency can be specified in 1MHz steps. Data sheets and support documentation can be found on Micrel's web site at: www.micrel.com. APPLICATIONS Workstations Advanced communications High end consumer High-performance computing RISC CPU clock Graphics pixel clock Test equipment Other high-performance processor-based applications Precision Edge is a registered trademark of Micrel, Inc. M9999-011106 hbwhelp@micrel.com or (408) 955-1690 Rev.: J 1 Amendment: /0 Issue Date: January 2006 Precision Edge(R) SY89429V Micrel, Inc. Ordering Information(1) TEST GND (TTL) GND VCC (TTL) FOUT /FOUT VCC_OUT PACKAGE/ORDERING INFORMATION 25 24 23 22 21 20 19 26 18 27 17 28 16 PLCC TOP VIEW 1 15 2 14 3 13 4 12 9 10 11 M[2] 8 N[1] N[0] M[8] M[7] M[6] M[5] M[4] M[3] 7 M[1] 6 M[0] XTAL2 5 VCC1 /P_LOAD S_CLOCK S_DATA S_LOAD VCC_QUIET LOOP_FILTER LOOP_REF XTAL1 28-PinPLCC (J28-1) $ !%& ! ' ( $ ! " ! # Part Number Package Type Operating Range Package Marking Lead Finish SY89429VJC J28-1 Commercial SY89429VJC Sn-Pb SY89429VJCTR(2) J28-1 Commercial SY89429VJC Sn-Pb SY89429VZC Z28-1 Commercial SY89429VZC Sn-Pb SY89429VZCTR(2) Z28-1 Commercial SY89429VZC Sn-Pb SY89429VJZ(3) J28-1 Commercial SY89429VJZ with Matte-Sn Pb-Free bar line indicator Pb-Free SY89429VJZTR(2, 3) J28-1 Commercial SY89429VJZ with Matte-Sn Pb-Free bar line indicator Pb-Free SY89429VZH(3) Z28-1 Commercial SY89429VZH with NiPdAu Pb-Free bar line indicator Pb-Free SY89429VZHTR(2, 3) Z28-1 Commercial SY89429VZH with NiPdAu Pb-Free bar line indicator Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. 28-PinSOIC (Z28-1) M9999-011106 hbwhelp@micrel.com or (408) 955-1690 2 Precision Edge(R) SY89429V Micrel, Inc. BLOCK DIAGRAM +3.3V or +5.0V PLL FREF /8 PHASE DETECTOR VCO 10-25MHz Fundamental Crystal OSC 3 WIRE INTERFACE /M PECL FOUT /N 400 - 800MHz INTERFACE LOGIC SERIAL TEST PARALLEL CONFIG INFO DETAILED BLOCK DIAGRAM % $ %1$" 2345673859 :;859 10pF % % & % ! " $ %% ,!( / 0 /0 <$** *%)= $ $ & $ ? ? 53;>5738 $ $ % % $ % ,!( $!( !( $) !+ %) % *% , - ./ NOTE: Pin numbers reference PLCC pinout. M9999-011106 hbwhelp@micrel.com or (408) 955-1690 ' ) ' )* $% # % / > 3 $ 0-%./ %,*$$ $ Precision Edge(R) SY89429V Micrel, Inc. PIN DESCRIPTIONS INPUTS OUTPUTS XTAL1, XTAL2 These pins form an oscillator when connected to an external crystal. The crystal is series resonant. See "AN-07" for Crystal Interface Guideline. FOUT, /FOUT These differential positive-referenced ECL signals (PECL) are the output of the synthesizer. TEST The function of this TTL output is determined by the serial configuration bits T[2:0]. S_LOAD This TTL pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this signal is HIGH; thus, the register data must be stable on the HIGH-to-LOW transition of S_LOAD for proper operation. POWER VCC1 This is the positive supply for the chip and is normally connected to +3.3V or +5.0V. S_DATA This TTL pin is the input to the serial configuration shift registers. VCC_OUT This is the positive reference for the PECL outputs, FOUT and /FOUT. It is constrained to be less than or equal to VCC1. S_CLOCK This TTL pin clocks the serial configuration shift registers. On the rising edge of this signal, data from S_DATA is sampled. VCC_QUIET This is the positive supply for the PLL and should be as noisefree as possible for low-jitter operation. /P_LOAD This TTL pin loads the configuration latches with the contents of the parallel inputs. The latches will be transparent when this signal is LOW: Thus, the parallel data must be stable on the LOW-to-HIGH transition of /P_LOAD for proper operation. During power up, hold /P_LOAD low with a valid M count on M[0] - M[8] until supplies have stabilized. GND These pins are the negative supply for the chip and are normally all connected to ground. OTHER M[8:0] These TTL pins are used to configure the PLL loop divider. They are sampled on the LOW-to-HIGH transition of /P_LOAD. M[8] is the MSB, M[0] is the LSB. The binary count on the M pins equates to the divide-by value for the PLL. LOOP_FILTER This is an analog I/O pin that provides the loop filter for the PLL. LOOP_REF This is an analog I/O pin that provides a reference voltage for the PLL. N[1:0] These TTL pins are used to configure the output divider modulus. They are sampled on the LOW-to-HIGH transition of /P_LOAD. N[1:0] Output Division 00 2 01 4 10 8 11 16 M9999-011106 hbwhelp@micrel.com or (408) 955-1690 4 Precision Edge(R) SY89429V Micrel, Inc. WITH 16MHZ INPUT VCO Frequency 256 128 64 32 16 8 4 2 1 (MHz) M Count M8 M7 M6 M5 M4 M3 M2 M1 M0 400 402 404 406 * * * 794 796 798 800 200 201 202 203 * * * 397 398 399 400 0 0 0 0 * * * 1 1 1 1 1 1 1 1 * * * 1 1 1 1 1 1 1 1 * * * 0 0 0 0 0 0 0 0 * * * 0 0 0 0 0 0 0 0 * * * 0 0 0 1 1 1 1 1 * * * 1 1 1 0 0 0 0 0 * * * 1 1 1 0 0 0 1 1 * * * 0 1 1 0 0 1 0 1 * * * 1 0 1 0 FUNCTIONAL DESCRIPTION The internal oscillator uses the external quartz crystal as the basis of its frequency reference. The output of the reference oscillator is divided by eight before being sent to the phase detector. With a 16MHz crystal, this provides a reference frequency of 2MHz. The VCO, within the PLL, operates over a range of 400- 800MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The output of this loop divider is also applied to the phase detector. The phase detector and loop filter force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock. External loop filter components are utilized to allow for optimal phase jitter performance. The output of the VCO is also passed through an output divider before being sent to the PECL output driver. The output divider is configured through either the serial or the parallel interfaces and can provide one of four divider ratios (2, 4, 8 or 16). This divider extends the performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider and is capable of driving a pair of transmission lines terminated M9999-011106 hbwhelp@micrel.com or (408) 955-1690 in 50 to VCC -2 volts. The positive reference for the output driver is provided by a dedicated power pin (VCC_OUT) to reduce noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. Normally, upon system reset, the /P_LOAD input is held LOW until some time after power becomes valid. With S_LOAD held LOW, on the LOW-to-HIGH transition of /P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pull-up resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count. The serial interface logic is implemented with a 14-bit shift register scheme. The register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet set-up and hold timing as specified in the AC parameters section of this datasheet. With /P_LOAD held HIGH, the configuration latches will capture the value in the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values and is controlled by the T[2:0] bits in the serial data stream. See the programming subsection of this data sheet for more information. 5 Precision Edge(R) SY89429V Micrel, Inc. PROGRAMMING INTERFACE Programming the device is accomplished by properly configuring the internal dividers to produce the desired frequency at the outputs. The output frequency can be represented by this formula: FOUT = ( The TEST output provides visibility for one of several internal nodes (as determined by the T[1:0] bits in the serial configuration stream). It is not configurable through the parallel interface. Although it is possible to select the node that represents FOUT, the TTL output may not be able to toggle fast enough for some of the higher output frequencies. The T2, T1, T0 configuration latches are preset to 000 when /P_LOAD is low, so that the FOUT outputs are as jitter-free as possible. The serial configuration port can be used to select one of the alternate functions for this pin. The Test register is loaded with the first three bits, the N register with the next two and the M register with the final eight bits of the data stream on the S_DATA input. For each register, the most significant bit is loaded first (T2, N1 and M8). When T[2:0] is set to 100 the SY89429V is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clock tree (See detailed Block Diagram). Because the S_CLOCK is a TTL level the input frequency is limited to 250MHz or less. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 125MHz as the minimum divide ratio of the N counter is 2. Note that the M counter output on the TEST output will not be a 50% duty cycle due to the way the divider is implemented. M FXTAL 8 )x N Where FXTAL is the crystal frequency, M is the loop divider modulus, and N is the output divider modulus. Note that it is possible to select values of M such that the PLL is unable to achieve loop lock. To avoid this, always ensure that M is selected to be 200 M 400 for a 16MHz input reference. M[8:0] and N[1:0] are normally specified once at power-on, through the parallel interface, and then possibly again through the serial interface. This approach allows the designer to bring up the application at one frequency and then change or finetune the clock, as the ability to control the serial interface becomes available. To minimize transients in the frequency domain, the output should be varied in the smallest step size possible. T2 T1 T0 TEST 0 0 0 Data Out - Last Bit SR FVCO / N 0 0 1 HIGH FVCO / N 0 1 0 FREF FVCO / N 0 1 1 M Counter Output FVCO / N 1 0 0 FOUT FVCO / N 1 0 1 LOW FVCO / N 1 1 0 S_CLOCK / M S_CLOCK / N 1 1 1 FOUT / 4 FVCO / N FOUT / /FOUT M9999-011106 hbwhelp@micrel.com or (408) 955-1690 6 Precision Edge(R) SY89429V Micrel, Inc. ABSOLUTE MAXIMUM RATINGS(1) Symbol Value Unit VCC Power Supply Voltage Parameter -0.5 to +7.0 V VI Input Voltage -0.5 to +7.0 V IOUT Output Source 50 100 mA TLEAD Lead Temperature (soldering 20sec.) +260 C Tstore Storage Temperature -65 to +150 C TA Operating Temperature -0 to +75 C Continuous Surge NOTE: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended periods may affect device reliability. 100H ECL DC ELECTRICAL CHARACTERISTICS VCC1 = VCC_QUIET = VCC_TTL = VCC_OUT = +3.3V to +5.0V 5%; TA = 0C to +75C Symbol Parameter Min. Max. Unit Condition VOH Output HIGH Voltage VCC_OUT -1.075 VCC_OUT -0.830 V 50 to VCC_OUT -2V VOL Output LOW Voltage VCC_OUT -1.860 VCC_OUT -1.570 V 50 to VCC_OUT -2V TTL DC ELECTRICAL CHARACTERISTICS VCC1 = VCC_QUIET = VCC_TTL = VCC_OUT = +3.3V to +5.0V 5%; TA = 0C to +75C TA = 0C Symbol Parameter TA = +25C TA = +75C Min. Max. Min. Max. Min. Max. Unit Condition VIH Input HIGH Voltage 2.0 -- 2.0 -- 2.0 -- V -- VIL Input LOW Voltage -- 0.8 -- 0.8 -- 0.8 V -- IIH Input HIGH Current -- 50 -- 50 -- 50 A IIL Input LOW Current -- -0.6 -- -0.6 -- -0.6 mA VIK Input Clamp Voltage -- -1.2 -- -1.2 -- -1.2 V IIN = -12mA VOH Output HIGH Voltage -- 2.0 -- 2.0 -- 2.0 V IOH = -2.0mA VOL Output LOW Voltage -- 0.5 -- 0.5 -- 0.5 V IOL = 8mA IOS Output Short Circuit Current mA VOUT = 0V ICC1 Supply Current mA 5.0V 5% mA 3.3V 5% -100 (Typ.) -- -100 (Typ.) 190 -- 190 -100 (Typ.) -- 190 0.89X of 5V Val. 0.89X of 5V Val. 0.89X of 5V Val. Typical % of ICC1 VCC1 VCC_OUT VCC_QUIET VCC_TTL M9999-011106 hbwhelp@micrel.com or (408) 955-1690 33% 9% 14% 44% 33% 9% 14% 44% 7 33% 9% 14% 44% VIN = 2.7V VIN = 0.5V Precision Edge(R) SY89429V Micrel, Inc. AC ELECTRICAL CHARACTERISTICS VCC1 = VCC_QUIET = VCC_TTL = VCC_OUT = +3.3V to +5.0V 5%; TA = 0C to +75C TA = 0C Symbol Parameter TA = +25C TA = +75C Min. Max. Min. Max. Min. Max. Unit Condition Fundamental Cyrstal fMAXI Maximum Input Frequency Note 1 S_CLOCK Xtal Oscillator -- 10 10 25 -- 10 10 25 -- 10 10 25 MHz fMAXO Maximum Output Frequency VCO (Internal) FOUT 400 25 800 400 400 25 800 400 400 25 800 400 MHz tLOCK Maximum PLL Lock Time -- 10 -- 10 -- 10 ms tjitter Cycle-to-Cycle Jitter (Peak-to-Peak) -- 50 -- 50 -- 50 ps tS Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to /P_LOAD 20 20 20 -- -- -- 20 20 20 -- -- -- 20 20 20 -- -- -- ns tH Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to /P_LOAD 20 20 20 -- -- -- 20 20 20 -- -- -- 20 20 20 -- -- -- ns tpw(MIN) Minimum Pulse Width S_LOAD /P_LOAD 50 50 -- -- 50 50 -- -- 50 50 -- -- ns tDC FOUT Duty Cycle 45 55 45 55 45 55 % tr tf Output Rise/Fall 20% to 80% FOUT 300 800 300 800 300 800 ps Test output static NOTE: 1. 10MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at high frequencies when used as a test clock in TEST_MODE 6. TIMING DIAGRAM S_DATA S_CLOCK tSET-UP S_LOAD tHOLD tSET-UP M[8:0] N[1:0] /P_LOAD tHOLD tSET-UP M9999-011106 hbwhelp@micrel.com or (408) 955-1690 8 Precision Edge(R) SY89429V Micrel, Inc. 28-PIN SOIC .300" WIDE (Z28-1) M9999-011106 hbwhelp@micrel.com or (408) 955-1690 9 Precision Edge(R) SY89429V Micrel, Inc. 28-PIN PLCC (J28-1) Rev. 03 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated. M9999-011106 hbwhelp@micrel.com or (408) 955-1690 10