1
Precision Edge®
SY89429V
Micrel, Inc.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
The SY89429V is a general purpose, synthesized clock
source targeting applications that require both serial and
parallel interfaces. Its internal VCO will operate over a
range of frequencies from 400MHz to 800MHz. The
differential PECL output can be configured to be the VCO
frequency divided by 2, 4, 8 or 16. With the output configured
to divide the VCO frequency by 2, and with a 16MHz
external quartz crystal used to provide the reference
frequency, the output frequency can be specified in 1MHz
steps.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
FEATURES
DESCRIPTION
Precision Edge®
SY89429V
5V/3.3V PROGRAMMABLE
FREQUENCY SYNTHESIZER
(25MHz to 400MHz)
■3.3V and 5V power supply options
■25MHz to 400MHz differential PECL outputs
■50ps peak-to-peak output jitter
■Minimal frequency over-shoot
■Synthesized architecture
■Serial 3-wire interface
■Parallel interface for power-on
■Internal quartz reference oscillator driven by quartz
crystal
■Application Note (AN-07) for ease of design-ins
■Available in 28-pin PLCC and SOIC packages
APPLICATIONS
■Workstations
■Advanced communications
■High end consumer
■High-performance computing
■RISC CPU clock
■Graphics pixel clock
■Test equipment
■Other high-performance processor-based
applications
Rev.: J Amendment: /0
Issue Date: January 2006
Precision Edge is a registered trademark of Micrel, Inc.
Precision Edge®
2
Precision Edge®
SY89429V
Micrel, Inc.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
567891011
VCC_QUIET
XTAL1
S_CLOCK
S_DATA
LOOP_REF
S_LOAD
LOOP_FILTER
VCC1
M[3]
M[0]
M[1]
M[2]
XTAL2
/P_LOAD
M[8]
M[4]
M[7]
M[5]
N[1]
M[6]
N[0]
FOUT
VCC_OUT
TEST
GND
VCC (TTL)
GND (TTL)
/FOUT
PLCC
TOP VIEW
PACKAGE/ORDERING INFORMATION
28-PinPLCC (J28-1)
Ordering Information(1)
Package Operating Package Lead
Part Number Type Range Marking Finish
SY89429VJC J28-1 Commercial SY89429VJC Sn-Pb
SY89429VJCTR(2) J28-1 Commercial SY89429VJC Sn-Pb
SY89429VZC Z28-1 Commercial SY89429VZC Sn-Pb
SY89429VZCTR(2) Z28-1 Commercial SY89429VZC Sn-Pb
SY89429VJZ(3) J28-1 Commercial SY89429VJZ with Matte-Sn
Pb-Free bar line indicator Pb-Free
SY89429VJZTR(2, 3) J28-1 Commercial SY89429VJZ with Matte-Sn
Pb-Free bar line indicator Pb-Free
SY89429VZH(3) Z28-1 Commercial SY89429VZH with NiPdAu
Pb-Free bar line indicator Pb-Free
SY89429VZHTR(2, 3) Z28-1 Commercial SY89429VZH with NiPdAu
Pb-Free bar line indicator Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
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3
Precision Edge®
SY89429V
Micrel, Inc.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
BLOCK DIAGRAM
DETAILED BLOCK DIAGRAM
NOTE:
Pin numbers reference PLCC pinout.
+3.3V
or
+5.0V
PHASE DETECTOR
PLL
÷ M
÷ 8
OSC
INTERFACE
LOGIC
SERIAL
PARALLEL
÷ N
FREF
PECL
FOUT
400 – 800MHz
TEST
CONFIG INFO
3 WIRE
INTERFACE
10-25MHz
Fundamental
Crystal
VCO
÷
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4
Precision Edge®
SY89429V
Micrel, Inc.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
PIN DESCRIPTIONS
INPUTS
XTAL1, XTAL2
These pins form an oscillator when connected to an external
crystal. The crystal is series resonant. See “AN-07” for Crystal
Interface Guideline.
S_LOAD
This TTL pin loads the configuration latches with the contents
of the shift registers. The latches will be transparent when this
signal is HIGH; thus, the register data must be stable on the
HIGH-to-LOW transition of S_LOAD for proper operation.
S_DATA
This TTL pin is the input to the serial configuration shift
registers.
S_CLOCK
This TTL pin clocks the serial configuration shift registers. On
the rising edge of this signal, data from S_DATA is sampled.
/P_LOAD
This TTL pin loads the configuration latches with the contents
of the parallel inputs. The latches will be transparent when this
signal is LOW: Thus, the parallel data must be stable on the
LOW-to-HIGH transition of /P_LOAD for proper operation.
During power up, hold /P_LOAD low with a valid M count on
M[0] - M[8] until supplies have stabilized.
M[8:0]
These TTL pins are used to configure the PLL loop divider.
They are sampled on the LOW-to-HIGH transition of /P_LOAD.
M[8] is the MSB, M[0] is the LSB. The binary count on the M
pins equates to the divide-by value for the PLL.
N[1:0]
These TTL pins are used to configure the output divider
modulus. They are sampled on the LOW-to-HIGH transition
of /P_LOAD.
OUTPUTS
FOUT, /FOUT
These differential positive-referenced ECL signals (PECL)
are the output of the synthesizer.
TEST
The function of this TTL output is determined by the serial
configuration bits T[2:0].
POWER
VCC1
This is the positive supply for the chip and is normally
connected to +3.3V or +5.0V.
VCC_OUT
This is the positive reference for the PECL outputs, FOUT and
/FOUT. It is constrained to be less than or equal to VCC1.
VCC_QUIET
This is the positive supply for the PLL and should be as noise-
free as possible for low-jitter operation.
GND
These pins are the negative supply for the chip and are
normally all connected to ground.
OTHER
LOOP_FILTER
This is an analog I/O pin that provides the loop filter for the
PLL.
LOOP_REF
This is an analog I/O pin that provides a reference voltage for
the PLL.
N[1:0] Output Division
0 0 2
0 1 4
1 0 8
1 1 16
5
Precision Edge®
SY89429V
Micrel, Inc.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
WITH 16MHZ INPUT
VCO Frequency 256 128 64 32 16 8421
(MHz) M Count M8 M7 M6 M5 M4 M3 M2 M1 M0
400 200 011001000
402 201 011001001
404 202 011001010
406 203 011001011
•••••••••••
•••••••••••
•••••••••••
794 397 110001101
796 398 110001110
798 399 110001111
800 400 110010000
The internal oscillator uses the external quartz crystal as the
basis of its frequency reference. The output of the reference
oscillator is divided by eight before being sent to the phase
detector. With a 16MHz crystal, this provides a reference frequency
of 2MHz.
The VCO, within the PLL, operates over a range of 400–
800MHz. Its output is scaled by a divider that is configured by
either the serial or parallel interfaces. The output of this loop
divider is also applied to the phase detector.
The phase detector and loop filter force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low) the PLL will not achieve loop lock. External loop
filter components are utilized to allow for optimal phase jitter
performance.
The output of the VCO is also passed through an output
divider before being sent to the PECL output driver. The output
divider is configured through either the serial or the parallel
interfaces and can provide one of four divider ratios (2, 4, 8 or 16).
This divider extends the performance of the part while providing
a 50% duty cycle.
The output driver is driven differentially from the output divider
and is capable of driving a pair of transmission lines terminated
FUNCTIONAL DESCRIPTION
in 50Ω to VCC –2 volts. The positive reference for the output driver
is provided by a dedicated power pin (VCC_OUT) to reduce noise
induced jitter.
The configuration logic has two sections: serial and parallel.
The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. Normally, upon
system reset, the /P_LOAD input is held LOW until some time
after power becomes valid. With S_LOAD held LOW, on the
LOW-to-HIGH transition of /P_LOAD, the parallel inputs are
captured. The parallel interface has priority over the serial
interface. Internal pull-up resistors are provided on the M[8:0]
and N[1:0] inputs to reduce component count.
The serial interface logic is implemented with a 14-bit shift
register scheme. The register shifts once per rising edge of the
S_CLOCK input. The serial input S_DATA must meet set-up and
hold timing as specified in the AC parameters section of this data-
sheet. With /P_LOAD held HIGH, the configuration latches will
capture the value in the shift register on the HIGH-to-LOW edge
of the S_LOAD input. See the programming section for more
information.
The TEST output reflects various internal node values and is
controlled by the T[2:0] bits in the serial data stream. See the
programming subsection of this data sheet for more information.
6
Precision Edge®
SY89429V
Micrel, Inc.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
PROGRAMMING INTERFACE
Programming the device is accomplished by properly
configuring the internal dividers to produce the desired
frequency at the outputs. The output frequency can be
represented by this formula:
Where FXTAL is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it is
possible to select values of M such that the PLL is unable to
achieve loop lock. To avoid this, always ensure that M is
selected to be 200 ≤ M ≤ 400 for a 16MHz input reference.
M[8:0] and N[1:0] are normally specified once at power-on,
through the parallel interface, and then possibly again through
the serial interface. This approach allows the designer to bring
up the application at one frequency and then change or fine-
tune the clock, as the ability to control the serial interface
becomes available. To minimize transients in the frequency
domain, the output should be varied in the smallest step size
possible.
The TEST output provides visibility for one of several
internal nodes (as determined by the T[1:0] bits in the serial
configuration stream). It is not configurable through the parallel
interface. Although it is possible to select the node that
represents FOUT, the TTL output may not be able to toggle
fast enough for some of the higher output frequencies. The T2,
T1, T0 configuration latches are preset to 000 when /P_LOAD
is low, so that the FOUT outputs are as jitter-free as possible.
The serial configuration port can be used to select one of the
alternate functions for this pin.
The Test register is loaded with the first three bits, the N
register with the next two and the M register with the final eight
bits of the data stream on the S_DATA input. For each register,
the most significant bit is loaded first (T2, N1 and M8).
When T[2:0] is set to 100 the SY89429V is placed in PLL
bypass mode. In this mode the S_CLOCK input is fed directly
into the M and N dividers. The N divider drives the FOUT
differential pair and the M counter drives the TEST output pin.
In this mode the S_CLOCK input could be used for low speed
board level functional test or debug. Bypassing the PLL and
driving FOUT directly gives the user more control on the test
clocks sent through the clock tree (See detailed Block Diagram).
Because the S_CLOCK is a TTL level the input frequency is
limited to 250MHz or less. This means the fastest the FOUT
pin can be toggled via the S_CLOCK is 125MHz as the minimum
divide ratio of the N counter is 2. Note that the M counter output
on the TEST output will not be a 50% duty cycle due to the way
the divider is implemented.
T2 T1 T0 TEST FOUT / /FOUT
000Data Out – Last Bit SR FVCO ÷ N
001HIGH FVCO ÷ N
010FREF FVCO ÷ N
011M Counter Output FVCO ÷ N
100FOUT FVCO ÷ N
101LOW FVCO ÷ N
110S
_CLOCK ÷ MS
_CLOCK ÷ N
111FOUT ÷ 4 FVCO ÷ N
FOUT =
(
)
x
FXTAL
8
M
N
7
Precision Edge®
SY89429V
Micrel, Inc.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
100H ECL DC ELECTRICAL CHARACTERISTICS
VCC1 = VCC_QUIET = VCC_TTL = VCC_OUT = +3.3V to +5.0V ±5%; TA = 0°C to +75°C
Symbol Parameter Min. Max. Unit Condition
VOH Output HIGH Voltage VCC_OUT –1.075 VCC_OUT –0.830 V 50Ω to VCC_OUT –2V
VOL Output LOW Voltage VCC_OUT –1.860 VCC_OUT –1.570 V 50Ω to VCC_OUT –2V
TA = 0°CT
A = +25°CT
A = +75°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
VIH Input HIGH Voltage 2.0 — 2.0 — 2.0 — V —
VIL Input LOW Voltage — 0.8 — 0.8 — 0.8 V —
IIH Input HIGH Current — 50 — 50 — 50 µAV
IN = 2.7V
IIL Input LOW Current — –0.6 — –0.6 — –0.6 mA VIN = 0.5V
VIK Input Clamp Voltage — –1.2 — –1.2 — –1.2 V IIN = –12mA
VOH Output HIGH Voltage — 2.0 — 2.0 — 2.0 V IOH = –2.0mA
VOL Output LOW Voltage — 0.5 — 0.5 — 0.5 V IOL = 8mA
IOS Output Short Circuit Current –100 (Typ.) –100 (Typ.) –100 (Typ.) mA VOUT = 0V
ICC1 Supply Current — 190 — 190 — 190 mA 5.0V ±5%
0.89X of 5V Val. 0.89X of 5V Val. 0.89X of 5V Val. mA 3.3V ±5%
Typical % of ICC1 VCC1 33% 33% 33%
VCC_OUT 9% 9% 9%
VCC_QUIET 14% 14% 14%
VCC_TTL 44% 44% 44%
TTL DC ELECTRICAL CHARACTERISTICS
VCC1 = VCC_QUIET = VCC_TTL = VCC_OUT = +3.3V to +5.0V ±5%; TA = 0°C to +75°C
Symbol Parameter Value Unit
VCC Power Supply Voltage –0.5 to +7.0 V
VIInput Voltage –0.5 to +7.0 V
IOUT Output Source Continuous 50 mA
Surge 100
TLEAD Lead Temperature (soldering 20sec.) +260 °C
Tstore Storage Temperature –65 to +150 °C
TAOperating Temperature –0 to +75 °C
NOTE:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions
other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS(1)
8
Precision Edge®
SY89429V
Micrel, Inc.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
TA = 0°CT
A = +25°CT
A = +75°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
fMAXI Maximum Input Frequency S_CLOCK —10—10 — 10 MHz Fundamental
Note 1 Xtal Oscillator 10 25 10 25 10 25 Cyrstal
fMAXO Maximum Output Frequency VCO (Internal) 400 800 400 800 400 800 MHz
FOUT 25 400 25 400 25 400
tLOCK Maximum PLL Lock Time — 10 — 10 — 10 ms
tjitter Cycle-to-Cycle Jitter (Peak-to-Peak) — 50 — 50 — 50 ps Test output static
tSSetup Time S_DATA to S_CLOCK 20 — 20 — 20 — ns
S_CLOCK to S_LOAD 20 — 20 — 20 —
M, N to /P_LOAD 20 — 20 — 20 —
tHHold Time S_DATA to S_CLOCK 20 — 20 — 20 — ns
S_CLOCK to S_LOAD 20 — 20 — 20 —
M, N to /P_LOAD 20 — 20 — 20 —
tpw(MIN) Minimum Pulse Width S_LOAD 50 — 50 — 50 — ns
/P_LOAD 50 — 50 — 50 —
tDC FOUT Duty Cycle 45 55 45 55 45 55 %
trOutput Rise/Fall FOUT 300 800 300 800 300 800 ps
tf20% to 80%
AC ELECTRICAL CHARACTERISTICS
VCC1 = VCC_QUIET = VCC_TTL = VCC_OUT = +3.3V to +5.0V ±5%; TA = 0°C to +75°C
NOTE:
1. 10MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at high frequencies when used as a test clock in
TEST_MODE 6.
TIMING DIAGRAM
S_DATA
S_CLOCK
S_LOAD
M[8:0]
N[1:0]
/P_LOAD
tHOLD
tSET-UP
tHOLD
tSET-UP
tSET-UP
9
Precision Edge®
SY89429V
Micrel, Inc.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
28-PIN SOIC .300" WIDE (Z28-1)
10
Precision Edge®
SY89429V
Micrel, Inc.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
28-PIN PLCC (J28-1)
Rev. 03
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
