BSS138_F085 - ON SEMICONDUCTOR - Datasheet.Directory

Publication Order Number:

BSS138-F085/D

BSS138-F085 — N-Channel Logic Level Enhancement Mode Field Effect Transistor

August-2017, Rev. 2

BSS138-F085

N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description

These N-Channel enhancement mode field effect tran-

sistors are produced using Fairchild’s proprietary, high

cell density, DMOS technology. These products have

been designed to minimize on-state resistance while pro-

vide rugged, reliable, and fast switching perfor-

mance.These products are particularly suited for low

voltage, low current applications such as small servo

motor control, power MOSFET gate drivers, and other

switching applications.

Features

• Automotive Qualified

• 0.22 A, 50 V. RDS(ON) = 3.5Ω @ VGS = 10 V

RDS(ON) = 6.0Ω @ VGS = 4.5 V

• High density cell design for extremely low RDS(ON)

• Rugged and Reliable

• Compact industry standard SOT-23 surface mount

package

Absolute Maximum Rations TA = 25°C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Units Symbol

VDSS Drain-Source Voltage 50 V

VGSS Gate-Source Voltage 20 V

Drain Current – Continuous (Note 1) 0.22 A

– Pulsed 0.88

Maximum Power Dissipation (Note 1) 0.36 W

Derate Above 25C2.8mW/C

TJ, TSTG Operating and Storage Junction Temperature Range −55 to +150 C

Maximum Lead Temperature for Soldering Purposes,

1/16” from Case for 10 Seconds 300 C

RJA Thermal Resistance, Junction-to-Ambient (Note 1) 350 C/W

Device Marking Device Reel Size Tape width Quantity

SS BSS138-F085 7’’ 8mm 3000 units

SOT-23

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BSS138-F085 — N-Channel Logic Level Enhancement Mode Field Effect Transistor

Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Unit

Off Characteristics

BVDSS Drain–Source Breakdown Voltage VGS = 0 V, ID = 250 μA50 V

BVDSS

/ TJ

Breakdown Voltage Temperature

Coefficient ID = 250 μA, Referenced to 25°C 72 mV/C

IDSS Zero Gate Voltage Drain Current

VDS = 50V, VGS = 0 V 0.5 μA

VDS = 50V, VGS = 0 V, TJ = 125°C 5 μA

VDS = 30V, VGS = 0 V 100 nA

IGSS Gate–Body Leakage VGS = 20V, VDS = 0 V 100 nA

On Characteristics (Note2)

VGS(th) Gate Threshold Voltage VDS = VGS, ID = 1 mA 0.8 1.3 1.5 V

VGS(th)

/ TJ

Gate Threshold Voltage

Temperature Coefficient ID = 1 mA, Referenced to 25°C -2 mV/C

RDS(on) Static Drain–Source On–Resistance

VGS = 10 V, ID = 0.22 A 0.7 3.5

Ω

VGS = 4.5 V, ID = 0.22 A 1.0 6.0

VGS = 10 V, ID = 0.22 A, TJ = 125°C 1.1 5.8

ID(on) On–State Drain Current VGS = 10 V, VDS = 5 V 0.2 A

gFS Forward Transconductance VDS = 10 V, ID = 0.22 A 0.12 0.5 S

Dynamic Characteristics

Ciss Input Capacitance

VDS = 25 V, VGS = 0 V,

f = 1.0 MHz

27 pF

Coss Output Capacitance 13 pF

Crss Reverse Transfer Capacitance 6 pF

RGGate Resistance VGS = 15 mV, f = 1.0 MHz 9Ω

Switching Characteristics (Note2)

td(on) Turn-On Delay Time

VDD = 30 V, ID = 0.29 A,

VGS = 10 V, RGEN = 6 Ω

2.8 5.8 ns

trTurn-On Rise Time 2.1 4.4 ns

td(off) Turn-Off Delay Time 9.6 19.2 ns

tfTurn-Off Fall Time 8.4 16.8 ns

QgTotal Gate Charge

VDS = 25 V, ID = 0.22 A,

VGS = 10 V

1.7 2.4 nC

Qgs Gate-Source Charge 0.1 nC

Qgd Gate-Drain Charge 0.4 nC

Drain–Source Diode Characteristics and Maximum Ratings

ISMaximum Continuous Drain–Source Diode Forward Current 0.22 A

VSD Drain–Source Diode Forward

Voltage VGS = 0 V, IS = 0.44 A (Note 2) 0.8 1.4 V

Notes:

1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain

pins. RJC is guaranteed by design while RJA is determined by the user's board design.

a) 350°C/W when mounted on a

minimum pad.

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width ≤300 μs, Duty Cycle ≤ 2.0%.

BSS138_F085 — N-Channel Logic Level Enhancement Mode Field Effect Transistor

Typical Performance Characteristics

Figure 1. On-Region Characteristics Figure 2. On-Resistance Variation with

Drain Current and Gate Voltage

Figure 3. On-Resistance Variation with Figure 4. On-Resistance Variation with

Temperature Gate-to-Source Voltage

Figure 5. Transfer Characteristics Figure 5. Body Diode Forward Voltage Variation

with Source Current and Temperature

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BSS138_F085 — N-Channel Logic Level Enhancement Mode Field Effect Transistor

Typical Performance Characteristics

Figure 7. Gate Charge Characteristics Figure 8. Capacitance Characteristics

Figure 9. Maximum Safe Operating Area Figure 10. Single Pulse Maximum

Power Dissipation

Figure 11. Transient Thermal Response Curve

Thermal characterization performed using the conditions described in Note 1a

Transient thermal response will change depending on the circuit board design

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