2015-2016 Microchip Technology Inc. DS20005396B-page 1
MCP37220-200
MCP37D20-200
Features
• Sample Rates: 200 Msps
• Signal-to-Noise Ratio (SNR) with fIN =15MHz
and -1 dBFS:
- 67.8 dBFS (typical) at 200 Msps
• Spurious-Free Dynamic Range (SFDR) with
fIN = 15 MHz and -1 dBFS:
- 96 dBc (typical) at 200 Msps
• Power Dissipation with LVDS Digital I/O:
- 346 mW at 200 Msps
• Power Dissipation with CMOS Digital I/O:
- 304 mW at 200 Msps, output clock = 100 MHz
• Power Dissipation Excluding Digital I/O:
- 256 mW at 200 Msps
• Power-Saving Modes:
- 89 mW during Standby
- 24 mW during Shutdown
• Supply Voltage:
- Digital Section: 1.2V, 1.8V
- Analog Section: 1.2V, 1.8V
• Selectable Full-Scale Input Range: up to 1.8 VP-P
• Analog Input Bandwidth: 650 MHz
• Output Interface:
- Parallel CMOS, DDR LVDS
• Output Data Format:
- Two's complement or offset binary
• Optional Output Data Randomizer
• Digital Signal Post-Processing (DSPP) Options:
- Decimation filters for improved SNR
- Offset and Gain adjustment
- Digital Down-Conversion (DDC) with I/Q or
fS/8 output (MCP37D20-200)
• Built-In ADC Linearity Calibration Algorithms:
- Harmonic Distortion Correction (HDC)
- DAC Noise Cancellation (DNC)
- Dynamic Element Matching (DEM)
- Flash Error Calibration
• Serial Peripheral Interface (SPI)
• Package Options:
- VTLA-124 (9 mm x 9 mm x 0.9 mm)
- TFBGA-121 (8 mm x 8 mm)
• No external reference decoupling capacitor
required for TFBGA Package
• Industrial Temperature Range: -40°C to +85°C
Typical Applications
• Communication Instruments
• Microwave Digital Radio
• Cellular Base Stations
• Radar
• Scanners and Low-Power Portable Instruments
• Industrial and Consumer Data Acquisition System
Device Offering(1)
Part Number Sample Rate Resolution Digital Decimation
(FIR Filters)
Digital
Down-Conversion
Noise-Shaping
Requantizer
MCP37220-200 200 Msps 14 Yes No No
MCP37D20-200 200 Msps 14 Ye s Yes No
MCP37210-200 200 Msps 12 Yes No Yes
MCP37D10-200 200 Msps 12 Ye s Yes Yes
1: Devices in the same package type are pin-compatible.
200 Msps, 14-Bit Low-Power Single-Channel ADC
MCP37220-200 AND MCP37D20-200
DS20005396B-page 2 2015-2016 Microchip Technology Inc.
Functional Block Diagram
Output Control:
Reference
SENSE
VCM
AIN+
AIN-
CLK+
CLK-
Q[13:0]
OVR
SCLK CS
SDIO
DCLK+
DCLK-
VREF+ VREF-
WCK
Pipelined
PLL
Clock
Output Clock Control
Internal Registers
ADC
Digital Signal Post-Processing:
- Decimation
- CMOS
AVDD12 AVDD18 DVDD18
DVDD12
REF-REF+
DLL
Duty Cycle
Correction
Selection
- Offset/Gain Adjustment
GND
Generator
VBG
- Digital Down-Conversion
- DDR LVDS
MCP37D20-200:
2015-2016 Microchip Technology Inc. DS20005396B-page 3
MCP37220-200 AND MCP37D20-200
Description
The MCP37220-200 is a single-channel 200 Msps
14-bit pipelined ADC, with built-in high-order digital
decimation filters, gain and offset adjustment.
The MCP37D20-200 is also a single-channel 200 Msps
14-bit pipelined ADC, with built-in digital
down-conversion in addition to the features offered by
the MCP37220-200.
Both devices feature harmonic distortion correction
and DAC noise cancellation that enables high-
performance specifications with SNR of 67.8 dBFS
(typical) and SFDR of 96 dBc (typical).
The output decimation filter option improves SNR
performance up to 83.9 dBFS with the 512x decimation
setting.
The digital down-conversion option in the MCP37D20-200
can be utilized with the decimation and quadrature output
(I and Q data) options and offers great flexibility in digital
communication system design, including cellular
base-stations and narrow-band communication systems.
These A/D converters exhibit industry-leading
low-power performance with only 348 mW operation
while using the LVDS output interface at 200 Msps.
This superior low-power operation, coupled with high
dynamic performance, makes these devices ideal for
portable communication devices, sonar, radar and
high-speed data acquisition systems.
These devices also include various features designed
to maximize flexibility in the user’s applications and
minimize system cost, such as a programmable PLL
clock, output data rate control and phase alignment,
and programmable digital pattern generation. The
device’s operational modes and feature sets are
configured by setting up the user-programmable
internal registers.
The device samples the analog input on the rising edge
of the clock. The digital output code is available after
23 clock cycles of data latency. Latency will increase if
any of the digital signal post-processing (DSPP)
options are enabled.
The differential full-scale analog input range is
programmable up to 1.8 VP-P
. The ADC output data
can be coded in two's complement or offset binary
representation, with or without the data randomizer
option. The output data is available with a full-rate
CMOS or Double-Data-Rate (DDR) LVDS interface.
The device is available in Pb-free VTLA-124 and
TFBGA-121 packages. The device operates over the
commercial temperature range of -40°C to +85°C.
Package Types
(a) VTLA-124 Package.
(b) TFBGA-121 Package.
Bottom View
Dimension: 9 mm x 9 mm x 0.9 mm
Bottom View
Dimension: 8 mm x 8 mm x 1.08 mm
Ball Pitch: 0.65 mm
Ball Diameter: 0.4 mm
MCP37220-200 AND MCP37D20-200
DS20005396B-page 4 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS20005396B-page 5
MCP37220-200 AND MCP37D20-200
1.0 PACKAGE PIN CONFIGURATIONS
AND FUNCTION DESCRIPTIONS
FIGURE 1-1: VTLA-124 Package.
A17 A19 A20
A13
A14
A15
A16
AV
DD18
A
IN
+
CLK-
CLK+
RESET DCLK+
DCLK-
VTLA-124
(9 mm x 9 mm x 0.9 mm)
A67
A
IN
-
SLAVE
SYNC
CAL
Q0/Q0-
Q1/Q0+
Q2/Q1-
Q4/Q2-
Q5/Q2+
Q6/Q3-
Q7/Q3+
Q8/Q4-
Q9/Q4+
Q10/Q5-
Q11/Q5+
Q12/Q6-
Q13/Q6+
WCK/OVR+
SENSE
REF-
REF-
V
CM
REF+
REF+
SDIO
SCLK
CS
NC
GND
WCK/OVR-
DV
DD18
DV
DD18
AV
DD12
EP
Note 1: Tie to GND or DVDD18. ADR1 is internally bonded to GND.
2: NC – Not connected pin. This pin can float or be tied to ground.
3: TP – Test pin. Leave this pin floating and do not tie to ground or supply.
4: Exposed pad (EP – back pad of the package) is the common ground (GND) for analog and digital
supplies. Connect this pad to a clean ground reference on the PCB.
V
BG
Note 2
Note 2
A68 A65
A66 A63
A64 A61
A62 A59
A60 A57
A58 A55
A56 A53
A54 A52
A1 B55
B56 B53
B54 B51
B52 B49
B50 B47
B48 B45
B46 B43
B44 B42
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
A18 A21 A23
A22 A25
A24 A27
A26 A29
A28 A31
A30 A33
A32
B15
B14 B17
B16 B19
B18 B21
B20 B23
B22 B25
B24 B27
B26 B28
A34
A50
A49
A48
A47
A46
A45
A44
A43
A42
A41
A40
A39
A38
A37
A36
A35
A51
B41
B40
B39
B38
B37
B36
B35
B34
B33
B32
B31
B30
B29
AV
DD12
ADR0 DV
DD18
AV
DD18
Q3/Q1+
NC
NC
AV
DD18
AV
DD18
AV
DD12
AV
DD12
AV
DD12
DV
DD12
DV
DD12
DV
DD12
DV
DD18
DV
DD18
(OVR)
(WCK)
DV
DD18
NC
Note 2
Note 2
Note 1
Top View
(Not to Scale)
(GND)
Note 4
NC
NC
NC
TP
Note 2
Note 3
Note 2
MCP37220-200 AND MCP37D20-200
DS20005396B-page 6 2015-2016 Microchip Technology Inc.
TABLE 1-1: PIN FUNCTION TABLE FOR VTLA-124
Pin No. Name I/O Type Description
Power Supply Pins
A2, A22, A65, B1,
B52
AVDD18 Supply Supply voltage input (1.8V) for analog section
A12, A56, A60,
A63, B10, B11,
B12, B13, B15,
B16, B45, B49,
B53
AVDD12 Supply voltage input (1.2V) for analog section
A25, A30, B39 DVDD12 Supply voltage input (1.2V) for digital section
A41, B24, B27,
B31, B36, B43
DVDD18 Supply voltage input (1.8V) for digital section and all digital I/O
EP GND Exposed pad: Common ground pin for digital and analog sections
ADC Analog Input Pins
B54 AIN+ Analog
Input
Differential analog input (+)
A64 AIN- Differential analog input (-)
A21 CLK+ Differential clock input (+)
B17 CLK- Differential clock input (-)
Reference Pins (1)
A57, B46 REF+ Analog
Output
Differential reference voltage (+)
A58, B47 REF- Differential reference voltage (-)
SENSE, Bandgap and Common-Mode Voltage Pins
B48 SENSE Analog Input Analog input full-scale range selection. See Table 4-2 for SENSE
voltage settings.
A59 VBG Analog
Output
Internal bandgap output voltage.
Connect a decoupling capacitor (2.2 µF)
A55 VCM Common-mode output voltage for analog input signal.
Connect a decoupling capacitor (0.1 µF)(2)
Digital I/O Pins
B18 ADR0 Digital Input SPI address selection pin (A0 bit). Tie to GND or DVDD18(3)
A23 SLAVE Not used. Tie to GND(9)
B19 SYNC Digital
Input/Output
Not used. Leave this pin floating(9)
B21 RESET Digital Input Reset control input:
High: Normal operating mode
Low: Reset mode(4)
A26 CAL Digital Output Calibration status flag digital output:
High: Calibration is complete
Low: Calibration is not complete(5)
B22 DCLK+ LVDS: Differential digital clock output (+)
CMOS: Digital clock output(6)
A27 DCLK- LVDS: Differential digital clock output (-)
CMOS: Unused (leave floating)
2015-2016 Microchip Technology Inc. DS20005396B-page 7
MCP37220-200 AND MCP37D20-200
ADC Output Pins (7)
B26 Q0/Q0- Digital
Output
Digital data output: CMOS = Q0
DDR LVDS = Q0-
A31 Q1/Q0+ Digital data output: CMOS = Q1
DDR LVDS = Q0+
B30 Q2/Q1- Digital data output: CMOS = Q2
DDR LVDS = Q1-
A38 Q3/Q1+ Digital data output: CMOS = Q3
DDR LVDS = Q1+
A39 Q4/Q2- Digital data output: CMOS = Q4
DDR LVDS = Q2-
B32 Q5/Q2+ Digital data output: CMOS = Q5
DDR LVDS = Q2+
A40 Q6/Q3- Digital data output: CMOS = Q6
DDR LVDS = Q3-
B33 Q7/Q3+ Digital data output: CMOS = Q7
DDR LVDS = Q3+
B34 Q8/Q4- Digital data output: CMOS = Q8
DDR LVDS = Q4-
A42 Q9/Q4+ Digital data output: CMOS = Q9
DDR LVDS = Q4+
B35 Q10/Q5- Digital data output: CMOS = Q10
DDR LVDS = Q5-
A43 Q11/Q5+ Digital data output: CMOS = Q11
DDR LVDS = Q5+
A44 Q12/Q6- Digital data output: CMOS = Q12
DDR LVDS = Q6-
B37 Q13/Q6+ Digital data output: CMOS = Q13
DDR LVDS = Q6+
B38 WCK/
OVR+
(OVR)
OVR: Input overrange indication digital output(8)
WCK:
- MCP37220: No output
-MCP37D20: Word clock synchronizes with digital output in
I/Q data mode
A45 WCK/OVR-
(WCK)
SPI Interface Pins
A53 SDIO Digital Input/
Output
SPI data input/output
A54 SCLK Digital Input SPI serial clock input
B44 CS SPI Chip Select input
TABLE 1-1: PIN FUNCTION TABLE FOR VTLA-124 (CONTINUED)
Pin No. Name I/O Type Description
MCP37220-200 AND MCP37D20-200
DS20005396B-page 8 2015-2016 Microchip Technology Inc.
Notes:
1. These pins are for the internal reference voltage output. They should not be driven. External decoupling circuit
is required. See Section 4.3.3 “Decoupling Circuits for Internal Voltage Reference and Bandgap Output”
for details.
2. When VCM output is used for the common-mode voltage of analog inputs (i.e. by connecting to the center-tap of
a balun), VCM pin should be decoupled with a 0.1 µF capacitor.
3. ADR1 (for A1 bit) is internally bonded to GND (‘0’). If ADR0 is dynamically controlled, ADR0 must be held
constant while CS is “Low”.
4. The device is in Reset mode while this pin stays “Low”. On the rising edge of RESET, the device exits the Reset
mode, initializes all internal user registers to default values and begins power-up calibration.
5. CAL pin stays “Low” at power-up until the first power-up calibration is completed. When the first calibration has
completed, this pin has “High” output. It stays “High” until the internal calibration is restarted by hardware or a
Soft Reset command. In Reset mode, this pin is “Low”. In Standby and Shutdown modes, this pin will maintain
the prior condition.
6. The phase of DCLK relative to the data output bits may be adjusted depending on the operating mode. This is
controlled differently depending on the configuration of the digital signal post-processing (DSPP) and PLL
(or DLL). See also Addresses 0x52, 0x64 and 0x6D (Registers 5-7,5-22 and 5-28) for more details.
7. DDR LVDS: Two data bits are multiplexed onto each differential output pair. The output pins shown here are for
the “Even bit first” setting, which is the default setting of OUTPUT_MODE<1:0> in Address 0x62 (Register 5-20).
The even data bits (Q0, Q2, Q4, Q6, Q8, Q10, Q12) appear when DCLK+ is “High”. The odd data bits (Q1, Q3,
Q5, Q7, Q9, Q11, Q13) appear when DCLK+ is “Low”. See Addresses 0x65 (Register 5-23) and 0x68 (Register 5-
26) for output polarity control. See Figure 2-2 for LVDS output timing diagrams.
8. OVR: OVR will be held “High”’ when analog input overrange is detected. Digital signal post-processing (DSPP)
will cause OVR to assert early relative to the output data. See Figure 2-2 for LVDS timing of these bits.
WCK: Available for the I/Q output mode only in the MCP37D20. WCK is normally “Low” in I/Q output mode, and
“High” when it outputs in-phase (I) data.
(a) MCP37220 and MCP37D20 operating outside I/Q output mode: WCK/OVR+ is OVR and WCK/OVR- is
logic ‘0’ (not used). In DDR LVDS output mode, the rising edge of DCLK+ is OVR.
(b) I/Q output mode in the MCP37D20: In CMOS output mode, WCK/OVR+ is OVR and WCK/OVR- is WCK.
WCK is synchronized to in-phase (I) data. In DDR LVDS output mode, WCK/OVR+ and WCK/OVR- are
multiplexed. The rising edge of DCLK+ is OVR and the falling edge is WCK.
9. This pin function is not released yet.
Not Connected Pins
A1, A3 - A7,
A8 - A11,
A13 - A20,
A32 - A37,
A46 - A52,
A61 - A62,
A66 - A68,
B2 - B9, B14,
B28, B29, B40,
B41, B42,
B50 - B51, B55,
B56
NC These pins can be tied to ground or left floating.
Pins that need to be grounded
A24, A64,
B20, B54
GND These pins are not supply pins, but need to be tied to ground.
Output Test Pins
A28 - A29, B23,
B25
TP Digital
Output
Output test pins. Do not use. Always leave these pins floating.
Do not tie to ground or supply.
TABLE 1-1: PIN FUNCTION TABLE FOR VTLA-124 (CONTINUED)
Pin No. Name I/O Type Description
2015-2016 Microchip Technology Inc. DS20005396B-page 9
MCP37220-200 AND MCP37D20-200
FIGURE 1-2: TFBGA-121 Package. Decoupling capacitors for reference pins and VBG are
embedded in the package.
Top View
1 2 3 4 5 6 7 8 9 10 11
SDIO V
CM
REF+ REF-
SCLK
WCK/
Q12/Q6-
Q8/Q4-
Q6/Q3-
Q2/Q1-
Q4/Q2-
Q10/Q5-
OVR-
CS
WCK/
Q13/Q6
+
Q11/Q5
+
Q7/Q3+
Q3/Q1+
Q9/Q4+
Q5/Q2+
OVR+
GND
GND
GND
GND
DV
DD18
DV
DD12
DV
DD12
DV
DD18
GND
GND
GND
GND
DV
DD18
DV
DD12
DV
DD12
DV
DD18
DCLK-
SENSE
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD12
AV
DD18
AV
DD18
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGND
CAL GND SLAVE ADR0
GND
GND
GND
GND
GND
GND
GND
ADR1 GND GND
Q0/Q0- Q1/Q0+
DCLK+ RESET SYNC GND CLK+ CLK- GND AV
DD18
A
B
C
D
E
F
G
H
J
K
L
(Not to Scale)
Analog
Digital
All others: Supply Voltage
Notes:
V
BG
(WCK) (OVR)
TP1 TP1 A
IN-
A
IN+
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
TP2
TP2
TP2 TP2
Ball dimension: (a) Ball Pitch = 0.65 mm, (b) Ball Diameter = 0.4 mm.
Solder sphere composition (SnAgCu).
Die dimension: 8 mm x 8 mm x 1.08 mm.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 10 2015-2016 Microchip Technology Inc.
TABLE 1-2: PIN FUNCTION TABLE FOR TFBGA-121
Ball No. Name I/O Type Description
A1 SDIO Digital
Input/Output
SPI data input/output
A2 VCM Analog
Output
Common-mode output voltage for analog input signal
Connect a decoupling capacitor (0.1 µF)(1)
A3 REF+ Differential reference voltage (+/-). Decoupling capacitors are embedded in
the TFBGA package. Leave these pins floating.
A4 REF-
A5 VBG Internal bandgap output voltage
A decoupling capacitor (2.2 μF) is embedded in the TFBGA package. Leave
this pin floating.
A6 TP1 Analog
Output
Analog test pins. Leave these pins floating.
A7
A8 AIN- Analog Input Differential analog input (-)
A9 AIN+ Differential analog input (+)
A10 GND Supply Common ground for analog and digital sections
A11
B1 SCLK Digital Input SPI serial clock input
B2 CS SPI chip select input
B3 GND Supply Common ground for analog and digital sections
B4
B5 SENSE Analog Input Analog input range selection. See Table 4-2 for SENSE voltage settings.
B6 AVDD12 Supply Supply voltage input (1.2V) for analog section
B7
B8 AVDD18 Supply voltage input (1.8V) for analog section
B9
B10 GND Supply Common ground for analog and digital sections
B11
C1 WCK/OVR-
(WCK)
Digital
Output
OVR: Input overrange indication digital output(2)
WCK:
- MCP37220: No output
-MCP37D20: Word clock synchronizes with digital output in I/Q data
mode
C2
WCK/OVR+
(OVR)
C3 GND Supply Common ground for analog and digital sections
C4
C5 AVDD12 Supply voltage input (1.2V) for analog section
C6
C7
C8 GND Common ground pin for analog and digital sections
C9
C10
C11
2015-2016 Microchip Technology Inc. DS20005396B-page 11
MCP37220-200 AND MCP37D20-200
D1 Q12/Q6- Digital
Output
Digital data output(3)
CMOS = Q12
DDR LVDS = Q6-
D2 Q13/Q6+ Digital data output(3)
CMOS = Q13
DDR LVDS = Q6+
D3 GND Supply Common ground for analog and digital sections
D4
D5 AVDD12 Supply Supply voltage input (1.2V) for analog section
D6
D7
D8 GND Supply Common ground for analog and digital sections
D9
D10
D11
E1 Q10/Q5- Digital
Output
Digital data output(3)
CMOS = Q10
DDR LVDS = Q5-
E2 Q11/Q5+ Digital data output(3)
CMOS = Q11
DDR LVDS = Q5+
E3 GND Supply Common ground for analog and digital sections
E4
E5 AVDD12 Supply voltage input (1.2V) for analog section
E6
E7
E8 GND Common ground for analog and digital sections
E9
E10
E11
F1 Q8/Q4- Digital
Output
Digital data output(3)
CMOS = Q8
DDR LVDS = Q4-
F2 Q9/Q4+ Digital data output(3)
CMOS = Q9
DDR LVDS = Q4+
F3 DVDD18 Supply Supply voltage input (1.8V) for digital section.
All digital input pins are driven by the same DVDD18 potential.
F4
F5 AVDD12 Supply voltage input (1.2V) for analog section
F6
F7
F8 GND Common ground for analog and digital sections
F9
F10
F11
TABLE 1-2: PIN FUNCTION TABLE FOR TFBGA-121 (CONTINUED)
Ball No. Name I/O Type Description
MCP37220-200 AND MCP37D20-200
DS20005396B-page 12 2015-2016 Microchip Technology Inc.
G1 Q6/Q3- Digital
Output
Digital data output(3)
CMOS = Q6
DDR LVDS = Q3-
G2 Q7/Q3+ Digital data output(3)
CMOS = Q7
DDR LVDS = Q3+
G3 DVDD18 Supply Supply voltage input (1.8V) for digital section.
All digital input pins are driven by the same DVDD18 potential
G4
G5 GND Common ground for analog and digital sections
G6
G7 AVDD12 Supply Supply voltage input (1.2V) for analog section
G8
G9 GND Common ground for analog and digital sections
G10
G11
H1 Q4/Q2- Digital
Output
Digital data output(3)
CMOS = Q4
DDR LVDS = Q2-
H2 Q5/Q2+ Digital data output(3)
CMOS = Q5
DDR LVDS = Q2+
H3 DVDD12 Supply Supply voltage input (1.2V) for digital section
H4
H5 GND Common ground for analog and digital sections
H6
H7
H8
H9
H10
H11
J1 Q2/Q1- Digital
Output
Digital data output(3)
CMOS = Q2
DDR LVDS = Q1-
J2 Q3/Q1+ Digital data output(3)
CMOS = Q3
DDR LVDS = Q1+
J3 DVDD12 Supply DC supply voltage input pin for digital section (1.2V)
J4
J5 GND Common ground for analog and digital sections
J6
J7
J8
J9
J10
J11
TABLE 1-2: PIN FUNCTION TABLE FOR TFBGA-121 (CONTINUED)
Ball No. Name I/O Type Description
2015-2016 Microchip Technology Inc. DS20005396B-page 13
MCP37220-200 AND MCP37D20-200
K1 Q0/Q0- Digital
Output
Digital data output(3)
CMOS = Q0
DDR LVDS = Q0-
K2 Q1/Q0+ Digital data output(3)
CMOS = Q1
DDR LVDS = Q0+
K3 TP2 Output test pin.
Do not use. Do not tie to ground or supply. Always leave this pin floating.
K4 DCLK- LVDS: Differential digital clock output (-)
CMOS: Unused (leave floating)
K5 CAL Calibration status flag digital output(4)
High: Calibration is complete
Low: Calibration is not complete
K6 GND Supply Common ground pin for analog and digital sections
K7 SLAVE Digital Input Not used. Tie this pin to GND(8)
K8 ADR0 SPI address selection pin (A0 bit). Tie to GND or DVDD18(5)
K9 ADR1 SPI address selection pin (A1 bit). Tie to GND or DVDD18(5)
K10 GND Supply Common ground for analog and digital sections
K11
L1 TP2 Digital
Output
Output test pins. Do not use.
Do not tie to ground or supply. Always leave these pins floating.
L2
L3
L4 DCLK+ LVDS: Differential digital clock output (+)
CMOS: Digital clock output(6)
L5 RESET Digital Input Reset control input:
High: Normal operating mode
Low: Reset mode(7)
L6 SYNC Digital Input/
Output
Not used. Leave this pin floating(8)
L7 GND Supply Common ground for analog and digital sections
L8 CLK+ Analog Input Differential clock input (+)
L9 CLK- Differential clock input (-)
L10 GND Supply Common ground for analog and digital sections
L11 AVDD18 Analog Input Supply voltage input (1.8V) for analog section
TABLE 1-2: PIN FUNCTION TABLE FOR TFBGA-121 (CONTINUED)
Ball No. Name I/O Type Description
MCP37220-200 AND MCP37D20-200
DS20005396B-page 14 2015-2016 Microchip Technology Inc.
Notes:
1. When VCM output is used for the common-mode voltage of analog inputs (i.e. by connecting to the center-tap of
a balun), the VCM pin should be decoupled with a 0.1 µF capacitor.
2. OVR: OVR will be held “High”’ when analog input overrange is detected. Digital signal post-processing (DSPP)
will cause OVR to assert early relative to the output data. See Figure 2-2 for LVDS timing of these bits.
WCK: Available for the I/Q output mode only in the MCP37D20. In the I/Q output mode, WCK is normally “Low”,
and “High” when it outputs in-phase (I) data.
(a) MCP37220 and MCP37D20 operating outside I/Q output mode: WCK/OVR+ is OVR and WCK/OVR- is
logic ‘0’ (not used). In DDR LVDS output mode, the rising edge of DCLK+ is OVR.
(b) I/Q output mode in the MCP37D20: In CMOS output mode, WCK/OVR+ is OVR and WCK/OVR- is WCK.
WCK is synchronized to in-phase (I) data. In DDR LVDS output mode, WCK/OVR+ and WCK/OVR- are
multiplexed. The rising edge of DCLK+ is OVR and the falling edge is WCK.
3. DDR LVDS: Two data bits are multiplexed onto each differential output pair. The output pins shown here are for
the “Even bit first” setting, which is the default setting of OUTPUT_MODE<1:0> in Address 0x62 (Register 5-20).
The even data bits (Q0, Q2, Q4, Q6, Q8, Q10, Q12) appear when DCLK+ is “High”. The odd data bits (Q1, Q3,
Q5, Q7, Q9, Q11, Q13) appear when DCLK+ is “Low”. See Addresses 0x65 (Register 5-23) and 0x68
(Register 5-26) for output polarity control.
See Figure 2-2 for LVDS output timing diagram.
4. CAL pin stays “Low” at power-up until the first power-up calibration is completed. When the first calibration has
completed, this pin has “High” output. It stays “High” until the internal calibration is restarted by hardware or a
Soft Reset command. In Reset mode, this pin is “Low”. In Standby and Shutdown modes this pin will maintain
the prior condition.
5. If the SPI address is dynamically controlled, the Address pin must be held constant while CS is “Low”.
6. The phase of DCLK relative to the data output bits may be adjusted depending on the operating mode. This is
controlled differently depending on the configuration of the digital signal post-processing (DSPP) and PLL
(or DLL). See also Addresses 0x52, 0x64 and 0x6D (Registers 5-7,5-22 and 5-28) for more details.
7. The device is in Reset mode while this pin stays “Low”. On the rising edge of RESET
, the device exits the
Reset mode, initializes all internal user registers to default values, and begins power-up calibration.
8. This pin function is not released yet.
2015-2016 Microchip Technology Inc. DS20005396B-page 15
MCP37220-200 AND MCP37D20-200
2.0 ELECTRICAL CHARACTERISTICS
2.1 Absolute Maximum Ratings †
Analog and Digital Supply Voltage (AVDD12, DVDD12)....................................................................................................... -0.3V to 1.32V
Analog and Digital Supply Voltage (AVDD18, DVDD18)....................................................................................................... -0.3V to 1.98V
All Inputs and Outputs with respect to GND ........................................................................................................-0.3V to AVDD18 +0.3V
Differential Input Voltage ..................................................................................................................................................|AVDD18 -GND|
Current at Input Pins ...................................................................................................................................................................... ±2 mA
Current at Output and Supply Pins ........................................................................................................................................... ±250 mA
Storage Temperature ..................................................................................................................................................... -65°C to +150°C
Ambient Temperature with Power Applied (TA).............................................................................................................. -55°C to +125°C
Maximum Junction Temperature (TJ)........................................................................................................................................... +150°C
ESD Protection on all Pins....................................................................................................................................................... 2 kV HBM
Solder Reflow Profile ............................................................................................... See Microchip Application Note AN233 (DS00233)
2.2 Electrical Specifications
†Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
TABLE 2-1: ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Differential Analog Input (AIN) = Sine wave with amplitude of -1 dBFS,
fIN = 70 MHz, Clock Input = 200 MHz, fS= 200 Msps, PLL and decimation filters are disabled, Output load: CMOS data pin = 10 pF,
LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is applied for typical value.
Parameters Sym. Min. Typ. Max. Units Conditions
Power Supply Requirements
Analog Supply Voltage AVDD18 1.71 1.8 1.89 V
AVDD12 1.14 1.2 1.26 V
Digital Supply Voltage DVDD18 1.71 1.8 1.89 V Note 1
DVDD12 1.14 1.2 1.26 V
Analog Supply Current
Analog Supply Current
during Conversion
IDD_A18 — 0.03 0.1 mA at AVDD18 Pin
IDD_A12 — 141 159 mA at AVDD12 Pin
Digital Supply Current
Digital Supply Current
during Conversion
IDD_D12 — 72 109 mA at DVDD12 Pin
Digital I/O Current in
CMOS Output Mode
IDD_D18 —27—mAat DV
DD18 Pin
DCLK = 100 MHz
Digital I/O Current in
LVDS Mode
IDD_D18
Measured at DVDD18 Pin
—
50 75 mA 3.5 mA mode
35 —mA
1.8 mA mode
62 5.4 mA mode
Supply Current during Power-Saving Modes
During Standby Mode ISTANDBY_AN —45—mA
Address 0x00<4:3> = 1,1(2)
ISTANDBY_DIG —29—
During Shutdown Mode IDD_SHDN — 20 — mA Address
0x00<7,0> = 1,1(3)
MCP37220-200 AND MCP37D20-200
DS20005396B-page 16 2015-2016 Microchip Technology Inc.
PLL Circuit
PLL Circuit Current IDD_PLL — 17 — mA PLL enabled. Included in
analog supply current
specification.
Total Power Dissipation(4)
Power Dissipation
during Conversion,
excluding Digital I/O
PDISS_ADC —256—mW
Total Power Dissipation
during Conversion with
CMOS Output Mode
PDISS_CMOS —304—mWf
S=200Msps,
DCLK = 100 MHz
Total Power Dissipation
during Conversion with
LVDS Output Mode
PDISS_LVDS —346— mW 3.5 mA mode
319 1.8 mA mode
367 5.4 mA mode
During Standby Mode PDISS_STAND
BY
— 89 — mW Address
0x00<4:3> = 1,1(2)
During Shutdown Mode PDISS_SHDN — 24 — mW Address
0x00<7,0> = 1,1(3)
Power-On Reset (POR) Voltage
Threshold Voltage VPOR — 800 — mV Applicable to AVDD12 only
(POR tracks AVDD12)
Hysteresis VPOR_HYST —40—mV
SENSE Input(5,7,13)
SENSE Input Voltage VSENSE GND — AVDD12 V V
SENSE selects reference
SENSE Pin Input
Resistance
RIN_SENSE — 694 —
V
SENSE
=0.8V
—154.8—k
V
SENSE
=1.2V
Current Sink into
SENSE Pin
ISENSE — 360 — µA
V
SENSE
=0.8V
—4.2—µA
V
SENSE
=1.2V
Reference and Common-Mode Voltages
Internal Reference
Voltage(7,8)
VREF —0.4—VV
SENSE =GND
—0.8— V
SENSE =AV
DD12
— VSENSE — 400 mV < VSENSE <800mV
Common-Mode
Voltage Output
VCM —0.55—VAvailable at V
CM pin
Bandgap Voltage
Output
VBG —0.55—VAvailable at V
BG pin
TABLE 2-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Differential Analog Input (AIN) = Sine wave with amplitude of -1 dBFS,
fIN = 70 MHz, Clock Input = 200 MHz, fS= 200 Msps, PLL and decimation filters are disabled, Output load: CMOS data pin = 10 pF,
LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is applied for typical value.
Parameters Sym. Min. Typ. Max. Units Conditions
2015-2016 Microchip Technology Inc. DS20005396B-page 17
MCP37220-200 AND MCP37D20-200
Analog Inputs
Full-Scale Differential
Analog Input Range(5,7)
AFS —0.9—V
P-P VSENSE =GND
—1.8— V
SENSE =AV
DD12
—2.25x
VSENSE
— 400 mV < VSENSE <800mV
Analog Input
Bandwidth
fIN_3dB — 650 — MHz AIN =-3 dBFS
Differential Input
Capacitance
CIN —1.6—pFNote 5, Note 9
Analog Input Leakage
Current (AIN+, AIN- pins)
ILI_AH ——+50µA
VIH =AV
DD12
ILI_AL -50 — — µA VIL =GND
ADC Conversion Rate
Conversion Rate fS— 200 Msps Tested at 200 Msps
Clock Inputs (CLK+, CLK-)(10)
Clock Input Frequency fCLK — — 250 MHz Note 5
Differential Input
Voltage
VCLK_IN 300 — 800 mVP-P Note 5
Clock Jitter CLKJITTER — 175 — fSRMS Note 5
Clock Input Duty
Cycle(5)
49 50 51 % Duty cycle correction
disabled
30 50 70 % Duty cycle correction
enabled
Input Leakage Current
at CLK input pin
ILI_CLKH ——+110µA
VIH =AV
DD12
ILI_CLKL -20 — — µA VIL =GND
Converter Accuracy(6)
ADC Resolution
(with no missing code)
— — 14 bits
Offset Error — ±15 ±45 LSb
Gain Error GER — ±0.5 — % of
FS
Integral Nonlinearity INL — ±1.5 — LSb
Differential Nonlinearity DNL — ±0.4 — LSb
Analog Input
Common-Mode
Rejection Ratio
CMRRDC — 70 — dB DC measurement
TABLE 2-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Differential Analog Input (AIN) = Sine wave with amplitude of -1 dBFS,
fIN = 70 MHz, Clock Input = 200 MHz, fS= 200 Msps, PLL and decimation filters are disabled, Output load: CMOS data pin = 10 pF,
LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is applied for typical value.
Parameters Sym. Min. Typ. Max. Units Conditions
MCP37220-200 AND MCP37D20-200
DS20005396B-page 18 2015-2016 Microchip Technology Inc.
Dynamic Accuracy(6,14)
Spurious Free Dynamic
Range
SFDR 82 96 — dBc fIN =15MHz
—80—dBcf
IN =70MHz
Signal-to-Noise Ratio
(for all resolutions)
SNR 66.1 67.8 — dBFS fIN =15MHz
—67.2— f
IN =70MHz
Effective Number of
Bits (ENOB)(11)
ENOB — 10.9 — bits fIN =15MHz
—10.9— f
IN =70MHz
Total Harmonic
Distortion
(first 13 harmonics)
THD 83 89 — dBc fIN =15MHz
81 — dBc fIN =70MHz
Worst Second or
Third Harmonic
Distortion
HD2 or HD3 — 95.8 — dBc fIN =15MHz
—82—dBcf
IN =70MHz
Two-Tone
Intermodulation
Distortion
fIN1 =15MHz,
fIN2 =17MHz
IMD — 92.7 — dBc AIN = -7 dBFS,
with two input frequencies
Digital Logic Input and Output (Except LVDS Output)
Schmitt Trigger High-
Level Input Voltage
VIH 0.7 DVDD18 —DV
DD18 V
Schmitt Trigger Low-
Level Input Voltage
VIL GND — 0.3 DVDD18 V
Hysteresis of Schmitt
Trigger Inputs
(All digital inputs)
VHYST — 0.05
DVDD18
—V
Low-Level Output
Voltage
VOL ——0.3VI
OL =-3mA,
all digital I/O pins
High-Level Output
Voltage
VOH DVDD18 –0.5 1.8 — V I
OL =+3mA,
all digital I/O pins
Digital Data Output (CMOS Mode)
Maximum External
Load
Capacitance
CLoad —10 —pF From output pin to GND
Internal I/O
Capacitance
CINT —4—pFNote 5
Digital Data Output (LVDS Mode)(5)
LVDS High-Level
Differential Output
Voltage
VH_LVDS 200 300 400 mV 100 differential
termination,
LVDS bias = 3.5 mA
LVDS Low-Level
Differential Output
Voltage
VL_LVDS -400 -300 -200 mV 100 differential
termination,
LVDS bias = 3.5 mA
TABLE 2-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Differential Analog Input (AIN) = Sine wave with amplitude of -1 dBFS,
fIN = 70 MHz, Clock Input = 200 MHz, fS= 200 Msps, PLL and decimation filters are disabled, Output load: CMOS data pin = 10 pF,
LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is applied for typical value.
Parameters Sym. Min. Typ. Max. Units Conditions
2015-2016 Microchip Technology Inc. DS20005396B-page 19
MCP37220-200 AND MCP37D20-200
Notes:
1. This 1.8V digital supply voltage is used for the digital I/O circuit, including SPI, CMOS and LVDS data output drivers.
2. Standby mode: Most of the internal circuits are turned-off except internal reference, clock, bias circuits and SPI
interface.
3. Shutdown mode: All circuits, including reference and clock, are turned-off except the SPI interface.
4. Power dissipation is calculated by using the following equation.
(a) During operation:
PDISS =V
DD18 x(I
DD_A18 +I
DD_D18)+V
DD12 x(I
DD_A12 +I
DD_D12), where IDD_D18 is the digital I/O current for
LVDS or CMOS output. VDD18 = 1.8V and VDD12 = 1.2V are used for typical value calculation.
(b) During Standby mode:
PDISS_STANDBY =(I
STANDBY_AN + ISTANDBY_DIG) x 1.2V
(c) During Shutdown mode:
PDISS_SHDN =I
DD_SHDN x 1.2 V
5. This parameter is ensured by design, but not 100% tested in production.
6. This parameter is ensured by characterization, but not 100% tested in production.
7. See Table 4-1 for details.
8. Differential reference voltage output at REF+/REF- pins: VREF =V
REF+–V
REF-.
9. Input capacitance refers to the effective capacitance between differential input pin pair.
10. See Figure 4-8 for details of clock input circuit.
11. ENOB = (SINAD - 1.76)/6.02.
12. This leakage current is due to internal pull-up resistor.
13. RIN_SENSE is calculated from SENSE pin to virtual ground at 0.55V for 400 mV < VSENSE <800 mV.
RSENSE =(V
SENSE - 0.55V)/ISENSE.
14. Dynamic performance is characterized with DIG_GAIN<7:0> = 0011-1000.
LVDS Common-Mode
Voltage
VCM_LVDS 11.151.4V
Output Capacitance CINT_LVDS — 4 — pF Internal capacitance from
output pin to GND
Differential Load
Resistance (LVDS)
RLVDS — 100 — Across LVDS output pairs
Input Leakage Current on Digital I/O Pins
Data Output Pins ILI_DH ——+1µAV
IH =DV
DD18
ILI_DL -1 — — µA VIL =GND
I/O Pins except Data
Output Pins
ILI_DH ——+6µAV
IH =DV
DD18
ILI_DL -35 — — µA VIL =GND
(12)
TABLE 2-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Differential Analog Input (AIN) = Sine wave with amplitude of -1 dBFS,
fIN = 70 MHz, Clock Input = 200 MHz, fS= 200 Msps, PLL and decimation filters are disabled, Output load: CMOS data pin = 10 pF,
LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is applied for typical value.
Parameters Sym. Min. Typ. Max. Units Conditions
MCP37220-200 AND MCP37D20-200
DS20005396B-page 20 2015-2016 Microchip Technology Inc.
TABLE 2-2: TIMING REQUIREMENTS – LVDS AND CMOS OUTPUTS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Differential analog input (AIN) = -1 dBFS sine wave, fIN = 70 MHz, Clock
input = 200 MHz, fS= 200 Msps, PLL and decimation filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100
termination, LVDS driver current setting = 3.5 mA, DCLK_PHDLY_DLL<2:0> = 000, +25°C is applied for typical value.
Parameters Symbol Min. Typ. Max. Units Conditions
Aperture Delay tA—1 — nsNote 1
Out-of-Range Recovery Time tOVR —1 —ClocksNote 1
Output Clock Duty Cycle — 50 — % Note 1
Pipeline Latency TLATENCY — 23 — Clocks Note 2, Note 4
System Calibration(1)
Power-Up Calibration Time TPCAL —3×2
26 — Clocks First 3×226 sample
clocks after power-up
Background Calibration
Update Rate
TBCAL —2
30 —ClocksPer 2
30 sample clocks
after TPCAL
RESET Low Time TRESET 5—— nsSee Figure 2-6 for
details(1)
LVDS Data Output Mode(1,5)
Input Clock to
Output Clock Propagation Delay
tCPD —5.7 — ns
Output Clock to
Data Propagation Delay
tDC —0.5 — ns
Input Clock to
Output Data Propagation Delay
tPD —5.8 — ns
CMOS Data Output Mode(1)
Input Clock to
Output Clock Propagation Delay
tCPD —3.8 — ns
Output Clock to
Data Propagation Delay
tDC —0.7 — ns
Input Clock to
Output Data Propagation Delay
tPD —4.5 — ns
Note 1: This parameter is ensured by design, but not 100% tested in production.
2: This parameter is ensured by characterization, but not 100% tested in production.
3: tRISE = approximately less than 10% of duty cycle.
4: Output latency is measured without using decimation filter and digital down-converter options.
5: The time delay can be adjusted with the DCLK_PHDLY_DLL<2:0> setting.
2015-2016 Microchip Technology Inc. DS20005396B-page 21
MCP37220-200 AND MCP37D20-200
FIGURE 2-1: Timing Diagram – CMOS Output.
FIGURE 2-2: Timing Diagram – LVDS Output with Even Bit First.
CLK-
CLK+
Input Clock:
DCLK
Digital Clock Output:
Q<N:0>
Output Data:
OVR
Over-Range Output:
S-L-1 S-L S-L+1 S-1 S
S-L-1 S-L S-L+1 S-1 S
S-1
SS+1 S+L
S+L-1
tA
Latency = L Cycles
tCPD
tDC
tPD
Input Signal:
*S = Sample Point
CLK-
CLK+
Input Clock:
Digital Clock Output:
Output Data:
Word-CLK/
Over-Range Output:
S-1
S
S+1 S+L
S+L-1
tA
Latency = L Cycles
tCPD
tDC
tPD
DCLK-
DCLK+
Q-[N:0]
Q+[N:0]
WCK/OVR-
WCK/OVR+
EVEN
S-L
ODD
S-L
EVEN
S-L-1
ODD
S-L-1
EVEN
S-L+1
EVEN
S
EVEN
S-1
ODD
S-1
WCK
S-L
OVR
S-L
WCK
S-L-1
OVR
S-L-1
WCK
S-L+1
WCK
S
WCK
S-1
OVR
S-1
Input Signal:
Note 1: (a) MCP37220: WCK has no output.
(b) MCP37D20: WCK has output in I and Q output mode only.
(Note 1)
*S = Sample Point
MCP37220-200 AND MCP37D20-200
DS20005396B-page 22 2015-2016 Microchip Technology Inc.
FIGURE 2-3: SPI Serial Input Timing Diagram.
FIGURE 2-4: SPI Serial Output Timing Diagram.
TABLE 2-3: SPI SERIAL INTERFACE TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Differential analog input (AIN) = -1 dBFS sine wave, fIN = 70 MHz, Clock
input = 200 MHz, fS= 200 Msps (ADC core), PLL and decimation filters are disabled, Output load: CMOS data pin = 10 pF,
LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is applied for typical value. All timings are measured at
50%.
Parameters Symbol Min. Typ. Max. Units Conditions
Serial Clock Frequency, fSCK =50MHz
CS Setup Time tCSS 10 — — ns
CS Hold Time tCSH 20 — — ns
CS Disable Time tCSD 20 — — ns
Data Setup Time tSU 2——ns
Data Hold Time tHD 4——ns
Serial Clock High Time tHI 8——ns
Serial Clock Low Time tLO 8——nsNote 1
Serial Clock Delay Time tCLD 20 — — ns
Serial Clock Enable Time tCLE 20 — — ns
Output Valid from SCK Low tDO — — 20 ns
Output Disable Time tDIS — — 10 ns Note 1
Note 1: This parameter is ensured by design, but not 100% tested in production.
CS
SCLK
SDIO LSb in
MSb in
tCSS
tSU tHD
tCSD
tCSH tCLD
tCLE
tHI tLO
tSCK
(SDI)
tCSH
tDIS
tHI tLO
tSCK
CS
SCLK
SDIO MSb out LSb out
tDO
(SDO)
2015-2016 Microchip Technology Inc. DS20005396B-page 23
MCP37220-200 AND MCP37D20-200
FIGURE 2-5: POR-Related Events: Register Initialization and Power-Up Calibration.
FIGURE 2-6: RESET Pin Timing Diagram.
TABLE 2-4: TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +85°C, AVDD18 =DV
DD18 =1.8V,
AVDD12 =DV
DD12 = 1.2V, GND = 0V, SENSE = AVDD12, Differential analog input (AIN) = -1 dBFS sine wave, fIN = 70 MHz, Clock
input = 200 MHz, fS= 200 Msps, PLL and decimation filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100
termination, LVDS driver current setting = 3.5 mA, +25°C is applied for typical value.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges(1)
Operating Temperature Range TA-40 — +85 °C
Thermal Package Resistances(2)
121L Ball-TFBGA
(8 mm x 8 mm)
Junction-to-Ambient Thermal Resistance JA —40.2—°C/W
Junction-to-Case Thermal Resistance JC —8.4—°C/W
124L VTLA
(9 mm x 9 mm)
Junction-to-Ambient Thermal Resistance JA —21—°C/W
Junction-to-Case (top) Thermal Resistance JC —8.7—°C/W
Note 1: Maximum allowed power dissipation (PDMAX)=(T
JMAX –T
A)/JA.
2: This parameter value is achieved by package simulations.
AVDD12
Power-on Reset (POR)
3×226 cycles
(TPCAL)
Power-up calibration complete:
• Registers are initialized
• Device is ready for correct conversion
RESET Pin
tRESET
Stop ADC conversion
and ADC recalibration
Power-Up Calibration Time
Start register initialization Recalibration complete:
• CAL Pin: High
• ADC_CAL_STAT = 1
MCP37220-200 AND MCP37D20-200
DS20005396B-page 24 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS20005396B-page 25
MCP37220-200 AND MCP37D20-200
3.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise specified, all parameters apply for TA= -40°C to +85°C, AVDD18 =DV
DD18 =1.8V, AV
DD12 =DV
DD12 =1.2V,
GND = 0V, SENSE = AVDD12, Differential Analog Input (AIN) = sine wave with amplitude of -1 dBFS, fIN = 70 MHz, Clock
Input = 200 MHz, fS= 200 Msps, PLL and decimation filters are disabled, DIG_GAIN<7:0> = 0011-1000.
FIGURE 3-1: FFT for 14.9 MHz Input
Signal: fS=200 Msps, AIN = -1 dBFS.
FIGURE 3-2: FFT for 69.9 MHz Input
Signal: fS=200 Msps, AIN = -1 dBFS.
FIGURE 3-3: FFT for 151 MHz Input
Signal: fS=200 Msps, AIN = -1 dBFS.
FIGURE 3-4: FFT for 14.9 MHz Input
Signal: fS=200 Msps, AIN = -4 dBFS.
FIGURE 3-5: FFT for 69.9 MHz Input
Signal: fS=200 Msps, AIN = -4 dBFS.
FIGURE 3-6: FFT for 151 MHz Input
Signal: fS=200 Msps, AIN = -4 dBFS.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
020 40 60 80 100
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
Frequency (MHz)
234567
I
CLK
= 200MHz
f
IN
= 14.9MHz @ -1.0dBFS
SNR = 66.4dB (67.4dBFS)
SFDR = 98.1dBc
THD = -92.3dBc
+' = -104.3dBc
+'= -99.1dBc
020 40 60 80 100
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
Frequency (MHz)
2
3
4
5
6
7
f
CLK
= 200MHz
f
IN
= 69.9MHz @ -1.0dBFS
SNR = 66.2dB (67.2dBFS)
SFDR = 81.3dBc
THD = -80.8dBc
HD2 = -99.4dBc
HD3 = -81.4dBc
020 40 60 80 100
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
Frequency (MHz)
2
3
456
7
f
CLK
= 200MHz
f
IN
= 151.0MHz @ -1.0dBFS
SNR = 65.6dB (66.6dBFS)
SFDR = 75.8dBc
THD = -75.2dBc
HD2 = -86.5dBc
HD3 = -75.8dBc
020 40 60 80 100
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
Frequency (MHz)
234567
f
CLK
= 200MHz
f
IN
= 14.9MHz @ -4.0dBFS
SNR = 63.3dB (67.3dBFS)
SFDR = 95.6dBc
THD = -91.6dBc
+' = -106.7dBc
+'= -99.4dBc
020 40 60 80 100
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
Frequency (MHz)
2
3
4
5
67
f
CLK
= 200MHz
f
IN
= 69.9MHz @ -4.0dBFS
SNR = 63.3dB (67.3dBFS)
SFDR = 88.3dBc
THD = -86.2dBc
HD2 = -97.3dBc
HD3 = -88.6dBc
020 40 60 80 100
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
Frequency (MHz)
2
3
45
6
7
f
CLK
= 200MHz
f
IN
= 151.0MHz @ -4.0dBFS
SNR = 62.9dB (66.9dBFS)
SFDR = 82.6dBc
THD = -81.1dBc
HD2 = -90.2dBc
HD3 = -82.6dBc
MCP37220-200 AND MCP37D20-200
DS20005396B-page 26 2015-2016 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA= -40°C to +85°C, AVDD18 =DV
DD18 =1.8V, AV
DD12 =DV
DD12 =1.2V,
GND = 0V, SENSE = AVDD12, Differential Analog Input (AIN) = sine wave with amplitude of -1 dBFS, fIN = 70 MHz, Clock
Input = 200 MHz, fS= 200 Msps, PLL and decimation filters are disabled, DIG_GAIN<7:0> = 0011-1000.
FIGURE 3-7: Two-Tone FFT:
fIN1 = 17.6 MHz and fIN2 =20.4MHz,
AIN = -7 dBFS per Tone, fS=200Msps.
FIGURE 3-8: SNR/SFDR vs. Input
Frequency.
FIGURE 3-9: SNR/SFDR vs. VCM Voltage
(Externally Applied): fS= 200 Msps,
fIN =15MHz.
FIGURE 3-10: SNR/SFDR vs.Temperature:
fS=200Msps, f
IN =15MHz.
FIGURE 3-11: SNR/SFDR vs. Supply
Voltage: fS=200Msps, f
IN =15MHz.
FIGURE 3-12: HD2/HD3 vs. Supply
Voltage: fS=200Msps, f
IN =15MHz.
020 40 60 80 100
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
Frequency (MHz)
F
1
F
2
F
1
+F
2
F
2
-F
1
2F
1
-F
2
2F
1
+F
2
2F
2
-F
1
2F
2
+F
1
Mode = Single
f
CLK
= 200MHz
f
1
= 17.6MHz @G%)6
f
2
= 20.4MHz @G%)6
2f
1
-f
2
= -97.4dBc
2f
2
-f
1
= -92.7dBc
SFDR = 90.2dBc
025 50 75 100 125
67
68
69
SNR (dBFS)
Input Frequency (MHz)
66
SFDR (dBFS)
SNR (dBFS)
050 100
150
60
80
100
SFDR (dBFS)
Input Frequency (MHz)
0
00.2 0.4 0.6 0.8 1
57
58
59
60
61
62
63
64
65
66
67
68
69
SNR (dBFS)
External VCM (V)
SNR (dBFS)
SFDR (dBFS)
00.2 0.4 0.6 0.8 1
.2
0
75
80
85
90
95
100
105
110
SFDR (dBFS)
External VCM (V)
-40 -20 020 40 60 80 100
65
66
67
68
69
SNR (dBFS)
f
S
=0VSV
f
IN
= 15 MHz
A
IN
= -1 dBFS
SNR (dBFS)
SFDR (dBFS)
-40 -20 020 40 60 80 100
80
85
90
95
100
SFDR (dBFS)
7HPSHUDWXUH&
66.5
67
67.5
68
68.5
69
SNR (dBFS)
66
1.14 1.26
1.
75
80
85
90
95
100
SFDR (dBFS)
Supply Voltage (V)
f
S
= 200 MVSV
f
IN
= 15 MHz
A
IN
= -1 dBFS
SNR (dBFS)
SFDR (dBFS)
1.2
7
1.
1.08 1.14 1.26 1.32
-105
-100
-95
-90
-85
-80
-75
-70
HDN (dBFS)
Supply Voltage (V)
f
S
= 200 MVSV
f
IN
= 15 MHz
A
IN
= -1 dBFS
HD2 (dBFS)
HD3 (dBFS)
1.2
2015-2016 Microchip Technology Inc. DS20005396B-page 27
MCP37220-200 AND MCP37D20-200
Note: Unless otherwise specified, all parameters apply for TA= -40°C to +85°C, AVDD18 =DV
DD18 =1.8V, AV
DD12 =DV
DD12 =1.2V,
GND = 0V, SENSE = AVDD12, Differential Analog Input (AIN) = sine wave with amplitude of -1 dBFS, fIN = 70 MHz, Clock
Input = 200 MHz, fS= 200 Msps, PLL and decimation filters are disabled, DIG_GAIN<7:0> = 0011-1000.
FIGURE 3-13: SNR/SFDR vs. Analog Input
Amplitude: fS=200Msps, f
IN =15MHz.
FIGURE 3-14: SNR/SFDR vs. Sample
Rate (Msps): fIN =15MHz.
FIGURE 3-15: SNR/SFDR vs. SENSE Pin
Voltage: fS= 200 Msps, fIN =15MHz.
FIGURE 3-16: SNR/SFDR vs. Analog Input
Amplitude: fS=200Msps, f
IN =70MHz.
FIGURE 3-17: SNR/SFDR vs. Sample
Rate (Msps): fIN =70MHz.
FIGURE 3-18: SNR/SFDR vs. SENSE Pin
Voltage: fS=200Msps, f
IN =70MHz.
-100 -80 -20 0
65
66
67
68
69
SNR (dBFS)
SFDR (dBFS)
SFDR (dBc)
SNR (dBFS)
SNR (dB)
-100 -80 -20 0
0
20
40
60
80
100
120
SNR (dB), SFDR (dBc, dBFS)
,QSXW$PSOLWXGH( (dBFS)
-0-40
50 100 150 200 250
60
62
64
66
68
70
72
74
76
78
SNR/dBFS
50 100 150 200 250
75
80
85
90
95
100
105
SFDR/dBFS
SDPSOH5DWH (MVSV)
f
IN
= 15 MHz
A
IN
= -1 dBFS
SNR (dBFS)
SFDR (dBFS)
0.4 0.6 0.8
59
60
61
62
63
64
65
66
67
68
69
70
SNR (dBFS)
SENSE Pin Voltage
BG-
LOW0.2
0.4 0.6 0.8
1.0BG-+,*+
75
80
85
90
95
100
105
110
SFDR (dBFS)
SENSE Pin Voltage
57
-80 -20 0
66
67
68
69
SNR (dBFS)
SFDR (dBFS)
SFDR (dBc)
SNR (dBFS)
SNR (dB)
-1
00
-80 -20 0
0
20
40
60
80
100
120
SNR (dB), SFDR (dBc, dBFS)
,QSXW$PSOLWXGH( (dBFS)
6
-60 
50 100 150 200
56
58
60
62
64
66
68
70
72
74
SNR/dBFS
50 100 150 200
250
55
60
65
70
75
80
SFDR/dBFS
6DPSOH5DWH (MVSV)
f
IN
= 70 MHz
A
IN
= -1 dBFS
SNR (dBFS)
SFDR (dBFS)
5
0.4 0.6 0.8
59
60
61
62
63
64
65
66
67
68
69
70
SNR (dBFS)
SENSE Pin Voltage
BG-
LOW0.2
0.4 0.6 0.8
1.0BG-+IGH
75
80
85
90
95
100
105
110
SFDR (dBFS)
SENSE Pin Voltage
57
MCP37220-200 AND MCP37D20-200
DS20005396B-page 28 2015-2016 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA= -40°C to +85°C, AVDD18 =DV
DD18 =1.8V, AV
DD12 =DV
DD12 =1.2V,
GND = 0V, SENSE = AVDD12, Differential Analog Input (AIN) = sine wave with amplitude of -1 dBFS, fIN = 70 MHz, Clock
Input = 200 MHz, fS= 200 Msps, PLL and decimation filters are disabled, DIG_GAIN<7:0> = 0011-1000.
FIGURE 3-19: VREF vs. Temperature.
FIGURE 3-20: INL Error vs. Output Code:
fS= 200 Msps, fIN =4MHz.
FIGURE 3-21: Shorted Input Histogram:
fS= 200 Msps.
FIGURE 3-22: Gain and Offset Error Drifts
vs. Temperature using Internal Reference, with
Respect to 25 °C: fS=200Msps.
FIGURE 3-23: DNL Error vs. Output Code:
fS=200Msps, f
IN =4MHz.
-40 -20 020 40 60 80 100 120
0.784
0.786
0.788
0.79
0.792
0.794
0.796
0.798
0.8
0.802
TemperatureC)
Reference Voltage (V)
AV
DD12
= 1.2V
AV
DD12
= 1.26V
AV
DD12
= 1.14V
04096 12288 16384
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
8192
INL Error (LSB)
f
CLK
= 200MHz,
INL = 1.313LSB,
14-Bit Mode (16384 Codes)
f
IN
= 4.0MHz
A
IN
= 88.9%FS
Output Code
Temperature (oC)
020 40 60
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Gain Error (dB)
-0
020
020 40 60
-
80100
-8
-6
-4
-2
0
2
4
6
8
10
Offset Error (LSB)
Offset Error
Gain Error
Resolution =%LW
V
SENSE
= AV
DD12
f
S
= 200 MVSV
I
,1
 15 MHz
A
IN
= -1 dBFS
04096 12288 16384
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
8192
DNL Error (LSB)
14-Bit Mode (16384 Codes)
f
CLK
= 200MHz,
DNL = 0.308LSB,
f
IN
= 4.0MHz
A
IN
= 88.9%FS
Output Code
2015-2016 Microchip Technology Inc. DS20005396B-page 29
MCP37220-200 AND MCP37D20-200
Note: Unless otherwise specified, all parameters apply for TA= -40°C to +85°C, AVDD18 =DV
DD18 =1.8V, AV
DD12 =DV
DD12 =1.2V,
GND = 0V, SENSE = AVDD12, Differential Analog Input (AIN) = sine wave with amplitude of -1 dBFS, fIN = 70 MHz, Clock
Input = 200 MHz, fS= 200 Msps, PLL and decimation filters are disabled, DIG_GAIN<7:0> = 0011-1000.
FIGURE 3-24: Input Bandwidth. FIGURE 3-25: Power Consumption vs.
Sampling Frequency (LVDS Mode).
0200 400 600 800 1000 1200
-14
-12
-10
-8
-6
-4
-2
0
Frequency (MHz)
Attenuation (dB)
050 100 150 200 250
0
20
40
60
80
100
120
140
160
Current (mA)
Sampling Frequency (MHz)
IDD_A12
IDD_D12
IDD_D18
Total Power for ADC Core
(except LVDS I/O)
A
IN
= -1 dBFS
050 100 150 200 250
300
180
200
220
240
260
280
300
320
Power (mW)
10
MCP37220-200 AND MCP37D20-200
DS20005396B-page 30 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS20005396B-page 31
MCP37220-200 AND MCP37D20-200
4.0 THEORY OF OPERATION
The MCP37220-200 and MCP37D20-200 devices are
single-channel, low-power, 14-bit, 200 Msps
Analog-to-Digital Converters (ADC) with built-in
patented features that maximize performance. The
features include Harmonic Distortion Correction
(HDC), DAC Noise Cancellation (DNC), Dynamic
Element Matching (DEM) and flash error calibration.
These devices include various built-in digital signal
post-processing features. The MCP37220-200
includes FIR decimation filters and the MCP37D20-200
includes both FIR decimation filters and Digital
Down-Conversion (DDC). Digital gain and offset
correction features are also offered in both devices.
These built-in advanced digital signal post-processing
sub-blocks, which are individually enabled and
controlled, can be used for various special applications
such as I/Q demodulation, digital down-conversion,
and imaging.
When the device is first powered-up, it performs
internal calibrations by itself and is running with default
settings. From this point, the user can configure the
device registers using the SPI command.
The device samples the analog input on the rising edge
of the clock. The digital output code is available after
23 clock cycles of data latency. Latency will increase if
any of the digital signal post-processing (DSPP)
options are enabled.
The output data can be coded in two’s complement or
offset binary format and can be randomized using the
user option. The output data is available through the
CMOS or LVDS (Low-Voltage Differential Signaling)
interface.
4.1 ADC Core Architecture
Figure 4-1 shows the simplified block diagram of the
ADC core. The ADC core consists of six stages. All
stages consist of a multi-level flash ADC and DAC.
Except the last stage, all have a residue amplifier with
a gain of 4. Dither is added in each of the first
two stages. The digital outputs from all six stages are
combined in a digital error correction logic block and
digitally processed for the final 14-bit output.
The first two stages include patented digital calibration
features:
• Harmonic Distortion Correction (HDC) algorithm
that digitally measures and cancels ADC errors
arising from distortions introduced by the residue
amplifiers
• DAC Noise Cancellation (DNC) algorithm that
corrects DAC’s nonlinearity errors
• Dynamic Element Matching (DEM) which
randomizes DAC errors, thereby converting
harmonic distortion to white noise
These digital correction algorithms are first applied
during the Power-on Reset sequence and then operate
in the background during normal operation of the
pipelined ADC. These algorithms automatically track
and correct any environmental changes in the ADC.
More details of the system correction algorithms are
shown in Section 4.10 “System Calibration”.
FIGURE 4-1: ADC Core Block Diagram.
Clock Generation
Pipeline
Stage 1
Pipeline
Stage 2 Pipeline
Stage 3
Pipeline
Stage 4
Pipeline
Stage 5
Flash
Stage 6
Digital Error Correction
14-Bit Digital Output
AIN+
AIN-
HDC1, DNC1 HDC2, DNC2
User-Programmable Options Programmable Digital Signal Post-Processing (DSPP)
Reference Generator
REF REF REF REF REF REF
REF
Analog Input
MCP37220-200 AND MCP37D20-200
DS20005396B-page 32 2015-2016 Microchip Technology Inc.
4.2 Supply Voltage (DVDD, AVDD, GND)
The device operates from two sets of supplies and a
common ground:
• Digital Supplies (DVDD) for the digital section:
1.8V and 1.2V
• Analog Supplies (AVDD) for the analog section:
1.8V and 1.2V
• Ground (GND): Common ground for both digital
and analog sections.
The supply pins require an appropriate bypass
capacitor (ceramic) to attenuate high-frequency noise
present in most application environments. The ground
pins provide the current return path. These ground pins
must connect to the ground plane of the PCB through
a low-impedance connection. A ferrite bead can be
used to separate analog and digital supply lines if a
common power supply is used for both analog and
digital sections.
The voltage regulators for each supply need to have
sufficient output current capabilities to support a stable
ADC operation.
4.3 Analog Input Circuit
The analog inputs (AIN) of all MCP37XXX devices are
a differential CMOS switched capacitor
sample-and-hold circuit. Figure 4-2 shows the
equivalent input structure of the device.
The input impedance of the device is mostly governed
by the input sampling capacitor (CS= 1.6 pF) and input
sampling frequency (fS). The performance of the
device can be affected by the input signal conditioning
network (see Figure 4-3). The analog input signal
source must have sufficiently low output impedance to
charge the sampling capacitors (CS= 1.6 pF) within
one clock cycle. A small external resistor (e.g. 5Ω) in
series with each input is recommended as it helps
reduce transient currents and dampens ringing
behavior. A small differential shunt capacitor at the chip
side of the resistors may be used to provide dynamic
charging currents and may improve performance. The
resistors form a low-pass filter with the capacitor and
their values must be determined by application
requirements and input frequency.
The VCM pin provides a common-mode voltage
reference (0.55V), which can be used for a center-tap
voltage of an RF transformer or balun. If the VCM pin
voltage is not used, the user may provide a common-
mode voltage (0.55V) from another supply.
FIGURE 4-2: Equivalent Input Circuit.
AIN+
AIN-
VCM
CS=1.6pF
40
5pF
AVDD12
AVDD12
Sample Hold
Hold
CS=1.6pF
Sample
40
5pF
MCP37XXX
2015-2016 Microchip Technology Inc. DS20005396B-page 33
MCP37220-200 AND MCP37D20-200
4.3.1 ANALOG INPUT DRIVING CIRCUIT
4.3.1.1 Differential Input Configuration
The device achieves optimum performance when the
input is driven differentially, where common-mode
noise immunity and even-order harmonic rejection are
significantly improved. If the input is single-ended, it
must be converted to a differential signal in order to
properly drive the ADC input. The differential
conversion and common-mode application can be
accomplished by using an RF transformer or balun with
a center-tap. Additionally, one or more anti-aliasing
filters may be added for optimal noise performance and
should be tuned such that the corner frequency is
appropriate for the system.
Figure 4-3 shows an example of the differential input
circuit with transformer. Note that the input driving circuits
are terminated by 50 near the ADC side through a pair
of 25 resistors from each input to the common-mode
(VCM) from the device. The RF transformer must be
carefully selected to avoid artificially high harmonic
distortion. The transformer can be damaged if a strong
RF input is applied or an RF input is applied while the
MCP37XXX is powered off. The transformer has to be
selected to handle sufficient RF input power.
Figure 4-4 shows an input configuration example when
a differential output amplifier is used.
FIGURE 4-3: Transformer Coupled Input
Configuration.
FIGURE 4-4: DC-Coupled Input
Configuration with Preamplifier: the external
signal conditioning circuit and associated
component values are for reference only.
Typically, the amplifier manufacturer provides
reference circuits and component values.
4.3.1.2 Single-Ended Input Configuration
Figure 4-5 shows an example of a single-ended input
configuration. SNR and SFDR performance degrades
significantly when the device is operated in a
single-ended configuration. The unused negative side
of the input should be AC-coupled to ground using a
capacitor.
FIGURE 4-5: Singled-Ended Input
Configuration.
4.3.2 SENSE VOLTAGE AND INPUT
FULL-SCALE RANGE
The device has a bandgap-based differential internal
reference voltage. The SENSE pin voltage is used to
select the reference voltage source and configures the
input full-scale range. A comparator detects the
SENSE pin voltage and configures the full-scale input
range into one of the three possible modes which are
summarized in Tab le 4-1 . Figure 4-6 shows an
example of how the SENSE pin should be driven.
The SENSE pin can sink or source currents as high as
360 µA across all operational conditions. Therefore, it
may require a driver circuit, unless the SENSE
reference source provides sufficient output current.
FIGURE 4-6: SENSE Pin Voltage Setup.
AIN+
AIN-
VCM
3.3 pF
50
50
5
5
0.1 µF
25
25
Analog
0.1 µF
1
1
3
6
41
6
43
MABAES0060
Input
MCP37XXX
MABAES0060
AIN+
AIN-
Analog 6.8 pF
High-Speed 100
100
VCM
50
Differential
Amplifier
0.1 µF
CM
+
-
MCP37XXX
Input
A
IN
+
A
IN
-
R
VCM
1k
Analog
50
10 µF
0.1 µF
0.1 µF
10 µF 0.1 µF
1k
VCM
R
C
MCP37XXX
Input
Note 1: This voltage buffer can be removed if SENSE
reference is coming from a stable source (such as
MCP1700) which can provide a sufficient output
current to the SENSE pin.
SENSE
0.1 µF
R1
R2
MCP1700
0.1 µF
MCP37XXX
(Note 1)
MCP37220-200 AND MCP37D20-200
DS20005396B-page 34 2015-2016 Microchip Technology Inc.
4.3.2.1 SENSE Selection Vs. SNR/SFDR
Performance
The SENSE pin is used to configure the full-scale input
range of the ADC. Depending on the application
conditions, the SNR, SFDR and dynamic range
performance are affected by the SENSE pin
configuration. Tab l e 4-2 summarizes these settings.
• High-Reference Mode
This mode is enabled by setting the SENSE pin to AVDD12
(1.2V). This mode provides the highest input full-scale
range (1.8 VP-P) and the highest SNR performance.
Figures 3-15 and Figure 3-18 show SNR/SFDR versus
input amplitude in High-Reference mode.
• Low-Reference Mode
This mode is enabled by setting the SENSE pin to
ground. This mode is suitable for applications which
have a smaller input full-scale range.
This mode provides improved SFDR characteristics,
but SNR is reduced by -6 dB compared to the High-
Reference mode.
• SENSE Mode
This mode is enabled by driving the SENSE pin with an
external voltage source between 0.4V and 0.8V.
This mode allows the user to adjust the input full-scale
range such that SNR and dynamic range are optimized
in a given application system environment.
TABLE 4-1: SENSE PIN VOLTAGE AND INPUT FULL-SCALE RANGE
SENSE Pin
Voltage
(VSENSE)
Selected
Reference Voltage
(VREF)
Full-Scale Input Voltage
Range (AFS)
LSb Size
(AFS/214)Condition
Tied to GND 0.4V 0.9 VP-P 54.93 µV Low-Reference
Mode(2)
0.4V – 0.8V 0.4V – 0.8V 0.9 VP-P to 1.8 VP-P(1)Adjustable Sense Mode(3)
Tied to AVDD12 0.8V 1.8 VP-P 109.86 µV High-Reference
Mode(2)
Note 1: AFS =2.25V
P-P x(V
SENSE)=0.9V
P-P to 1.8 VP-P
2: Based on internal bandgap voltage
3: Based on VSENSE
TABLE 4-2: SENSE VS. SNR/SFDR PERFORMANCE
SENSE Descriptions
High-Reference Mode
(SENSE pin = AVDD12)
High-input full-scale range (1.8 VP-P) and optimized SNR
Low-Reference Mode
(SENSE pin = ground)
Low-input full-scale range (0.9 VP-P) and reduced SNR, but optimized SFDR
Sense Mode
(SENSE pin = 0.4V to 0.8V)
Adjustable-input full-scale range (0.9 VP-P - 1.8 VP-P). Dynamic trade-off between
High-Reference and Low-Reference modes can be used.
2015-2016 Microchip Technology Inc. DS20005396B-page 35
MCP37220-200 AND MCP37D20-200
4.3.3 DECOUPLING CIRCUITS FOR
INTERNAL VOLTAGE REFERENCE
AND BANDGAP OUTPUT
4.3.3.1 Decoupling Circuits for REF Pins
The internal reference is available at REF pins. This
internal reference requires external capacitors for
stable operation.
VTLA-124 Package Device: Figure 4-7 shows the
recommended circuit for the REF pins. A 2.2 µF
ceramic capacitor with two optional capacitors (22 nF
and 220 nF) is recommended between the positive and
negative reference pins. The negative reference pin
(REF-) is then grounded through a 220 nF capacitor.
The capacitors should be placed as close to the ADC
as possible with short and thick traces. Vias on the PCB
are not recommended for this reference pin circuit.
TFBGA-121 Package Device: The decoupling
capacitor is embedded in the package. Therefore, no
external circuit is required on the PCB.
4.3.3.2 Decoupling Circuit for VBG Pin
The bandgap circuit is a part of the reference circuit and
the output is available at the VBG pin.
VTLA-124 Package Device: V
BG pin needs an
external decoupling capacitor (2.2 µF) as shown in
Figure 4-7.
TFBGA-121 Package Device: The decoupling
capacitor is embedded in the package. Therefore, no
external circuit is required on the PCB.
FIGURE 4-7: External Circuit for Voltage
Reference and VBG pins for the VTLA-124
Package. Note that this external circuit is not
required for the TFBGA-121 package.
4.4 External Clock Input
For optimum performance, the MCP37XXX requires a
low-jitter differential clock input at the CLK+ and CLK−
pins. Figure 4-8 shows the equivalent clock input
circuit.
FIGURE 4-8: Equivalent Clock Input
Circuit.
The clock input amplitude range is between 300 mVP-P
and 800 mVP-P
. When a single-ended clock source is
used, an RF transformer or balun can be used to
convert the clock into a differential signal for the best
ADC performance. Figure 4-9 shows an example clock
input circuit. The common-mode voltage is internally
generated and a center-tap is not required. The
back-to-back Schottky diodes across the transformer’s
secondary current limit the clock amplitude to
approximately 0.8 VP-P differential. This limiter helps
prevent large voltage swings of the input clock while
preserving the high slew rate that is critical for low jitter.
FIGURE 4-9: Transformer-Coupled
Differential Clock Input Configuration.
Note: The internal reference output (REF+/REF-)
and bandgap voltage output (VBG) should
not be driven.
REF+ REF-
2.2 µF
22 nF
220 nF
220 nF
2.2 µF
VBG
(optional)
CLK+
CLK-
2pF
300
AVDD12
AVDD12
300
12 kClock
Buffer
100 fF
100 fF
~300 fF
AVDD12
MCP37XXX
~300 fF
CLK+
CLK-
0.1 µF
Clock
50Schottky
(HSMS-2812)
61
43
WBC1-1TL
Coilcraft
MCP37XXX
Diodes
Source
MCP37220-200 AND MCP37D20-200
DS20005396B-page 36 2015-2016 Microchip Technology Inc.
4.4.1 CLOCK JITTER AND SNR
PERFORMANCE
In a high-speed pipelined ADC, the SNR performance
is directly limited by thermal noise and clock jitter.
Thermal noise is independent of input clock and a
dominant term at low input frequency. On the other
hand, the clock jitter becomes a dominant term as input
frequency increases. Equation 4-1 shows the SNR
jitter component, which is expressed in terms of the
input frequency (fIN) and the total amount of clock jitter
(TJitter), where TJitter is a sum of the following two
components:
• Input clock jitter (phase noise)
• Internal aperture jitter (due to noise of the clock
input buffer).
EQUATION 4-1: SNR VS.CLOCK JITTER
The clock jitter can be minimized by using a
high-quality clock source and jitter cleaners as well as
a band-pass filter at the external clock input, while a
faster clock slew rate improves the ADC aperture jitter.
With a fixed amount of clock jitter, the SNR degrades
as the input frequency increases. This is illustrated in
Figure 4-10. If the input frequency increases from
10 MHz to 20 MHz, the maximum achievable SNR
degrades about 6 dB. For every decade (e.g. 10 MHz
to 100 MHz), the maximum achievable SNR due to
clock jitter is reduced by 20 dB.
FIGURE 4-10: SNR vs. Clock Jitter.
SNRJitter dBc 20 log10
–2
f
IN T
Jitter
=
where the total jitter term (Tjitter) is given by:
TJitter tJitter Clock Input,

2tAperture ADC,

2
+=
0
20
40
60
80
100
120
140
160
1 10 100 1000
SNR (dBc)
Input Frequency (fIN, MHz)
Jitter = 1
p
s
Jitter = 0.5 ps
Jitter = 0.25 ps
Jitter = 0.125 ps
Jitter = 0.0625 ps
2015-2016 Microchip Technology Inc. DS20005396B-page 37
MCP37220-200 AND MCP37D20-200
4.5 ADC Clock Selection
This section describes the ADC clock selection and
how to use the built-in Delay-Locked Loop (DLL) and
Phase-Locked Loop (PLL) blocks.
When the device is first powered-up, the external clock
input (CLK+/-) is directly used for the ADC timing as
default. After this point, the user can enable the DLL or
PLL circuit by setting the register bits. Figure 4-11
shows the clock control blocks. Tabl e 4-3 shows an
example of how to select the ADC clock depending on
the operating conditions.
TABLE 4-3: ADC CLOCK SELECTION (EXAMPLE)
Operating Conditions Control Bit Settings(1)
Features
Input Clock Duty
Cycle Correction
DCLK Output Phase
Delay Control
CLK_SOURCE = 0 (Default)(2)
• DLL output is not used
• Decimation is not used
(Default)(3)
EN_DLL = 0
EN_DLL_DCLK = 0
EN_PHDLY = 0
Not Available Not Available
EN_DLL = 1
EN_DLL_DCLK = 0
EN_PHDLY = 0
Available
• DLL output is used
• Decimation is not used
EN_DLL = 1
EN_DLL_DCLK = 1
EN_PHDLY = 1
Available Available
• DLL output is not used
• Decimation is used(4)
EN_DLL = 0
EN_DLL_DCLK = X
EN_PHDLY = 1
Not Available
EN_DLL = 1
EN_DLL_DCLK = 0
EN_PHDLY = 1
Available
CLK_SOURCE = 1(5)
• Decimation is not used EN_DLL = X
EN_DLL_DCLK = X
EN_PHDLY = 0
Not Available Available
• Decimation is used(4)EN_DLL = X
EN_DLL_DCLK = X
EN_PHDLY = 1
Note 1: See Addresses 0x52, 0x53, and 0x64 for bit settings.
2: The sampling frequency (fS) of the ADC core comes directly from the input clock buffer
3: Output data is synchronized with the output data clock (DCLK), which comes directly from the input clock buffer.
4: While using decimation, output clock rate and phase delay are controlled by the digital clock output control block
5: The sampling frequency (fS) is generated by the PLL circuit. The external clock input is used as the reference input
clock for the PLL block.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 38 2015-2016 Microchip Technology Inc.
FIGURE 4-11: Timing Clock Control Blocks.
VCO
Phase/Freq.
Detector (3rd Order) Output/Div
PLL_PRE<11:0>
PLL_REFDIV<9:0>
Current
PLL_OUTDIV<3:0>
PLL Block
Input Clock Buffer
EN_DUTY
C1: PLL_CAP1<4:0>
PLL_CHAGPUMP<3:0>
Loop Filter Control
C2: PLL_CAP2<4:0>
C3: PLL_CAP3<4:0>
R1: PLL_RES<4:0>
Loop Filter
(80 MHz - 250 MHz)
PLL Output Control Block
Pump
C3C2
R1
C1
Loop Filter Control Parameters:
fVCO
See Addresses 0x54 - 0x5D for Control Parameters
See Addresses 0x55 and 0x6D
÷N
÷R
if CLK_SOURCE = 1
Charge
Clock Input (fCLK): < 250 MHz
fREF
Duty Cycle Correction (DCC)
fS
EN_DLL
Phase Delay
DCLK_PHDLY_DLL<2:0>
DCLK
fS
EN_CLK
DLL Block
fQ
EN_PLL_CLK
DCLK Delay
DCLK_DLY_PLL<2:0>
for control parameters
if CLK_SOURCE = 0
Note: VCO output range is 1.075 GHz – 1.325 GHz by setting PLL_REFDIV<10:0> and PLL_PRE<11:0>, with fREF = 5 MHz - 250 MHz range.
fVCO
N
R
----f
REF
1.075 1.325–GHz==
EN_PLL_REFDIV
Digital Output
Clock Phase Delay Control
Clock Rate Control
Digital Output
Digital Clock Output Control Block
DCLK
if digital decimation is used
OUT_CLKRATE<3:0>
RESET_DLL
EN_DLL_DCLK
DCLK_PHDLY_DEC<2:0>
EN_PHDLY
DCLK
See Addresses 0x64 and 0x02
for control parameters
See Addresses 0x52 and 0x64<7> for details
if digital decimation is used
See Addresses 0x7A, 0x7B, 0x7C, and 0x81
(5 MHz to 250 MHz)
(when decimation filter is used)
EN_PLL EN_PLL_BIAS
EN_PLL_OUT
EN_DLL = 0
EN_DLL_DCLK = 0
See Addresses 0x7A, 0x7B, 0x7C, and 0x81
EN_PHDLY
DLL Circuit
2015-2016 Microchip Technology Inc. DS20005396B-page 39
MCP37220-200 AND MCP37D20-200
4.5.1 USING DLL MODE
Using the DLL block is the best option when output
clock phase control is needed while the clock
multiplication and the digital decimation are not
required. When the DLL block is enabled, the user can
control the input clock Duty Cycle Correction (DCC)
and the output clock phase delay.
See the DLL block in Figure 4-11 for details. Table 4-4
summarizes the DLL control register bits. See also
Table 4-15 for the output clock phase control.
4.5.1.1 Input Clock Duty Cycle Correction
The ADC performance is sensitive to the clock duty
cycle. The ADC achieves optimum performance with
50% duty cycle, and all performance characteristics are
ensured when the duty cycle is 50% with ±1% tolerance.
When CLK_SOURCE = 0, the external clock is used
as the sampling frequency (fS) of the ADC core. When
the external input clock is not high-quality (for example,
duty cycle is not 50%), the user can enable the internal
clock duty cycle correction circuit by setting the
EN_DUTY bit in Address 0x52 (Register 5-7). When
duty cycle correction is enabled (EN_DUTY = 1), only
the falling edge of the clock signal is modified (rising
edge is unaffected).
The duty cycle correction process adds additional jitter
noise to the clock signal. Therefore, using this option is
only recommended when an asymmetrical input clock
source causes significant performance degradation or
when the input clock source is not stable.
4.5.1.2 DLL Block Reset Event
The DLL must be reset if the clock is removed or the
clock frequency is changed. The DLL reset is controlled
by using the RESET_DLL bit in Address 0x52
(Register 5-7). The DLL has an automatic reset with
the following events:
• During power-up: Stay in reset until the
RESET_DLL bit is cleared.
• When the SOFT_RESET command is issued
while the DLL is enabled: the RESET_DLL bit is
automatically cleared after reset.
4.5.2 USING PLL MODE
The PLL block is mainly used when clock multiplication
is needed. When CLK_SOURCE = 1, the sampling
frequency (fS) of the ADC core is coming from the
internal PLL block.
The recommended PLL output clock range is from
80 MHz to 250 MHz. The external clock input is used
as the PLL reference frequency. The range of the clock
input frequency is from 5 MHz to 250 MHz.
TABLE 4-4: DLL CONTROL REGISTER BITS
Control Parameter Register Descriptions
CLK_SOURCE 0x53 CLK_SOURCE = 0: External clock input becomes input of the DLL block
EN_DLL 0x52 EN_DLL = 1: Enable DLL block
EN_DUTY 0x52 Input clock duty cycle correction control bit(1)
EN_DLL_DCLK 0x52 DLL output clock enable bit
EN_PHDLY 0x64 Enable digital output clock phase delay control.
DCLK_PHDLY_DLL<2:0> 0x52 Phase Delay control bits of digital output clock (DCLK) when DLL is used(2)
RESET_DLL 0x52 Reset control bit for the DLL block
Note 1: Duty cycle correction is not recommended when a high-quality external clock is used.
2: If decimation is used, the output clock phase delay is controlled using DCLK_PHDLY_DEC<2:0> in
Address 0x64.
Note: The clock duty cycle correction is only
applicable when the DLL block is enabled
(EN_DLL = 1). It is not applicable for the
PLL output. Note: The PLL mode is only supported for
sampling frequencies between 80 MHz
and 250 MHz.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 40 2015-2016 Microchip Technology Inc.
4.5.2.1 PLL Output Frequency and Output
Control Parameters
The internal PLL can provide a stable timing output
ranging from 80 MHz to 250 MHz. Figure 4-11 shows
the PLL block using a charge-pump-based integer N
PLL and the PLL output control block. The PLL block
includes various user control parameters for the
desired output frequency. Ta b l e 4 - 5 summarizes the
PLL control register bits and Ta b l e 4 - 6 shows an
example of register bit settings for the PLL charge
pump and loop filter.
The PLL block consists of:
• Reference Frequency Divider (R)
• Prescaler – which is a feedback divider (N)
• Phase/Frequency Detector (PFD)
• Current Charge Pump
• Loop Filter – a 3rd order RC low-pass filter
• Voltage-Controlled Oscillator (VCO)
The external clock at the CLK+ and CLK- pins is the
input frequency to the PLL. The range of input
frequency (fREF) is from 5 MHz to 250 MHz. This input
frequency is divided by the reference frequency
divider (R) which is controlled by the 10-bit-wide
PLL_REFDIV<9:0> setting. In the feedback loop, the
VCO frequency is divided by the prescaler (N) using
PLL_PRE<11:0>.
The ADC core sampling frequency (fS), ranging from
80 MHz to 250 MHz, is obtained after the output
frequency divider (PLL_OUTDIV<3:0>). For stable
operation, the user needs to configure the PLL with the
following limits:
The charge pump is controlled by the PFD and forces
sink (DOWN) or source (UP) current pulses onto the
loop filter. The charge pump bias current is controlled
by the PLL_CHAGPUMP<3:0> bits, approximately
25 µA per step. The loop filter consists of a 3rd order
passive RC filter. Table 4-6 shows the recommended
settings of the charge pump and loop filter parameters,
depending on the charge pump input frequency range
(output of the reference frequency divider).
When the PLL is locked, it tracks the input
frequency (fREF) with the ratio of dividers (N/R). The
PLL operating status is monitored by the PLL status
indication bits: <PLL_VCOL_STAT> and
<PLL_VCOH_STAT> in Address 0xD1 (Register 5-68).
Equation 4-2 shows the VCO output frequency (fVCO)
as a function of the two dividers and reference
frequency:
EQUATION 4-2: VCO OUTPUT
FREQUENCY
See Addresses 0x54 to 0x57 (Registers 5-9 to 5-12) for
these bits settings.
The tuning range of the VCO is 1.075 GHz to
1.325 GHz. N and R values must be chosen such that
the VCO is within this range. In general, lower values of
the VCO frequency (fVCO) and higher values of the
charge pump frequency (fQ) should be chosen to
optimize the clock jitter. Once the VCO output
frequency is determined to be within this range, the
user needs to set the final ADC sampling frequency (fS)
with the PLL output divider using PLL_OUTDIV<3:0>.
Equation 4-3 shows how to obtain the ADC core
sampling frequency:
EQUATION 4-3: SAMPLING FREQUENCY
Table 4-7 shows an example of generating
fS= 200 MHz output using the PLL control parameters.
4.5.2.2 PLL Calibration
The PLL should be recalibrated following a change in
the clock input frequency or in the PLL configuration
register bit settings (Addresses 0x54 - 0x57;
Registers 5-9 – 5-12).
The PLL can be calibrated by toggling the
PLL_CAL_TRIG bit in Address 0x6B (Register 5-27) or
by sending a SOFT_RESET command (See Address
0x00, Register 5-1). The PLL calibration status is
observed by the PLL_CAL_STAT bit in Address 0xD1
(Register 5-68).
4.5.2.3 Monitoring of PLL Drifts
The PLL drifts can be monitored using the status
monitoring bits in Address 0xD1 (Register 5-68). Under
normal operation, the PLL maintains lock across all
temperature ranges. It is not necessary to actively
monitor the PLL, unless extreme variations in the
supply voltage are expected or if the input reference
clock frequency has been changed.
• Input clock frequency (fREF) = 5 MHz to 250 MHz
• Charge pump input frequency
(after PLL reference divider)
= 4 MHz to 50 MHz
• VCO output frequency = 1.075 to 1.325 GHz
• PLL output frequency after
output divider
= 80 MHz to 250 MHz
fVCO
N
R
----


fREF 1.075 GHz to 1.325 GHz==
Where:
N = 1 to 4095 controlled by PLL_PRE<11:0>
R = 1 to 1023 controlled by PLL_REFDIV<9:0>
fS
fVCO
PLL_OUTDIV
--------------------------------------


80 MHz to 250 MHz==
2015-2016 Microchip Technology Inc. DS20005396B-page 41
MCP37220-200 AND MCP37D20-200
TABLE 4-5: PLL CONTROL REGISTER BITS
Control Parameter Register Descriptions
PLL Calibration and Status Indication Bits
PLL Global Control Bits
EN_PLL 0x59 Master enable bit for the PLL circuit
EN_PLL_OUT 0x5F Master enable bit for the PLL output
EN_PLL_BIAS 0x5F Master enable bit for the PLL bias
EN_PLL_REFDIV 0x59 Master enable bit for the PLL reference divider
PLL Block Setting Bits
PLL_REFDIV<9:0> 0x54-0x55 PLL reference divider (R) (See Tabl e 4 -7)
PLL_PRE<11:0> 0x56-0x57 PLL prescaler (N) (See Table 4-7 )
PLL_CHAGPUMP<3:0> 0x58 PLL charge pump bias current control: from 25 µA to 375 µA, 25 µA per step
PLL_RES<4:0> 0x5A PLL loop filter resistor value selection (See Table 4-6)
PLL_CAP3<4:0> 0x5B PLL loop filter capacitor 3 value selection (See Ta b l e 4 - 6 )
PLL_CAP2<4:0> 0x5D PLL loop filter capacitor 2 value selection (See Ta b l e 4 - 6 )
PLL_CAP1<4:0> 0x5C PLL loop filter capacitor 1 value selection (See Ta b l e 4 - 6 )
PLL Output Control Bits
PLL_OUTDIV<3:0> 0x55 PLL output divider (See Tabl e 4-7)
DCLK_DLY_PLL<2:0> 0x6D Delay DCLK output up to 15 cycles of VCO clocks
EN_PLL_CLK 0x6D EN_PLL_CLK = 1 enable PLL output clock to the ADC circuits
PLL Drift Monitoring Bits
PLL_VCOL_STAT 0xD1 PLL drift status monitoring bit
PLL_VCOH_STAT 0xD1 PLL drift status monitoring bit
PLL Block Calibration Bits
PLL_CAL_TRIG 0x6B Forcing recalibration of the PLL
SOFT_RESET 0x00 PLL is calibrated when exiting soft reset mode
PLL_CAL_STAT 0xD1 PLL auto-calibration status indication
MCP37220-200 AND MCP37D20-200
DS20005396B-page 42 2015-2016 Microchip Technology Inc.
TABLE 4-6: RECOMMENDED PLL CHARGE PUMP AND LOOP FILTER BIT SETTINGS
PLL Charge Pump and Loop Filter
Parameter
fQ=f
REF/PLL_REFDIV
fQ< 5 MHz 5 MHz ≤fQ<25MHz f
Q≥25 MHz
PLL_CHAGPUMP<3:0> 0x04 0x04 0x04
PLL_RES<4:0> 0x1F 0x1F 0x07
PLL_CAP3<4:0> 0x07 0x02 0x07
PLL_CAP2<4:0> 0x07 0x01 0x08
PLL_CAP1<4:0> 0x07 0x01 0x08
TABLE 4-7: EXAMPLE OF PLL CONTROL BIT SETTINGS FOR fS = 200 MHz WITH fREF = 100 MHz
PLL Control Parameter Value Descriptions
fREF 100 MHz fREF is coming from the external clock input
Ta r get fS(1)200 MHz ADC sampling frequency
Ta r get fVCO(2)1.2 GHz Range of fVCO = 1.0375 GHz – 1.325 GHz
Ta r get fQ(3)10 MHz fQ=f
REF/PLL_REFDIV (See Tab le 4-6)
PLL Reference Divider (R) 10 PLL_REFDIV<9:0> = 0x0A
PLL Prescaler (N) 120 PLL_PRE<11:0> = 0x78
PLL Output Divider 6 PLL_OUTDIV<3:0> = 0x06
Note 1: fS=f
VCO/PLL_OUTDIV = 1.2 GHz/6 = 200 MHz
2: fVCO = (N/R) x fREF =(12)x100MHz=1.2GHz
3: fQ should be maximized for the best noise performance.
2015-2016 Microchip Technology Inc. DS20005396B-page 43
MCP37220-200 AND MCP37D20-200
4.6 Digital Signal Post-Processing
(DSPP) Options
While the device converts the analog input signals to
digital output codes, the user can enable various digital
signal post-processing (DSPP) options for special
applications. These options are individually enabled or
disabled by setting the configuration bits. Ta b l e 4 - 8
summarizes the DSPP options that are available for
each device.
4.6.1 DECIMATION FILTERS
Figure 4-12 shows a simplified decimation filter block
diagram and Tab le 4-10 summarizes the related
control parameters for using decimation filters.
•MCP37220-200: Decimation rate is controlled by
FIR_A<8:0> in Addresses 0x7A and 0x7B
(Registers 5-34 – 5-35). The FIR_A<8:0> provides
a maximum programmable decimation rate up to
512x using nine cascaded decimation stages.
•MCP37D20-200: (a) When DDC mode is not
required, only FIR A is used. (b) When digital
down-conversion (DDC) is used for I and Q data
filtering, both FIR A and FIR B filters are used
(see Figure 4-12). In this case, both are set to the
same decimation rate. Note that stage 1A in
FIR A is unused: the user must clear FIR_A<0> in
Address 0x7A (Register 5-34).
The overall SNR performance can be improved with
higher decimation rate. In theory, 3 dB improvement is
expected with each successive stage of decimation (2x
per stage), but the actual improvement is
approximately 2.5 dB per stage due to finite attenuation
in the FIR filters.
4.6.1.1 Output Data Rate and Clock Phase
Control when Decimation is Used
When decimation is used, it also reduces the output
clock rate and output bandwidth by a factor equal to the
decimation rate applied: the output clock rate is
therefore no longer equal to the ADC sampling clock.
The user needs to adjust the output clock and data
rates in Address 0x02 (Register 5-3) based on the
decimation applied. This allows the output data to be
synchronized to the output data clock.
Phase shifts in the output clock can be achieved using
DCLK_PHDLY_DEC<2:0> in Address 0x64
(Register 5-22). Only four output sampling phases are
available when decimation of 2x is used, while all eight
clock phases are available for other decimation rates.
See Section 4.9.8 “Output Data And Clock Rates”
for more details.
4.6.1.2 Using Decimation with Digital
Down-Conversion (MCP37D20-200)
In the MCP37D20, the decimation feature can be used
in conjunction with DDC. When DDC is enabled, the
I and Q outputs can be decimated using
I and Q channels. Since the half-band filter already
includes a 2x decimation, the maximum possible
decimation rate is 256x for each I and Q data using
FIR A and FIR B filters (128x each from FIR A and B).
TABLE 4-8: DIGITAL SIGNAL POST-
PROCESSING (DSPP)
OPTIONS
Digital Signal Post-Processing
Option
Offering
Device
FIR Decimation Filters MCP37220-200
MCP37D20-200
Digital Gain and Offset correction
Digital Down-Conversion (DDC) MCP37D20-200
Note: Digital Gain/Offset adjustment and DDC
for I/Q data options occur prior to the
decimation filters if they are enabled.
TABLE 4-9: DECIMATION RATE VS. SNR
PERFORMANCE
Decimation Rate SNR (dBFS)
1x 67.8
2x 68.9
4x 71.8
8x 74.3
16x 76.8
32x 79
64x 81
128x 82.1
256x 82.7
512x 83.9
Note: The above data is valid with
fS= 200 Msps, fIN =1MHz,
AIN = -1dBFS. The data may vary in other
conditions.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 44 2015-2016 Microchip Technology Inc.
FIGURE 4-12: Simplified Block Diagram of Decimation Filters.
TABLE 4-10: REGISTER CONTROL PARAMETERS FOR USING DECIMATION FILTERS
Control Parameter Register Descriptions
Decimation Filter Settings
FIR_A<8:0> 0x7A, 0x7B FIR A configuration
FIR_B<7:0> 0x7C FIR B configuration for Q-channel
Output Data Rate and Clock Rate Settings(1)
OUT_DATARATE<3:0> 0x02 Output data rate: Equal to decimation rate
OUT_CLKRATE<3:0> 0x02 Output clock rate: Equal to decimation rate
Output Clock Phase Control Settings(2)
EN_PHDLY 0x64 Enable digital output phase delay when decimation filter is used
DCLK_PHDLY_DEC<2:0> 0x64 Digital output clock phase delay control
Note 1: The output data and clock rates must be updated when decimation rates are changed.
2: Output clock (DCLK) phase control is used when the output clock is divided by OUT_CLKRATE<3:0> bit
settings.
Stage 1A
FIR A
Stage 2A
FIR A
Stage 3A
FIR A
Stage 3B
FIR B
D2
Single
Output D2
I/Q
Stage 9A
FIR A
Stage 9B
FIR B
Output
D128
I/Q
D4
Single
D8
Single
D512
Single
2
222
2
2
(Note 1)
(Note 2)
(Note 3)
Decimation
Input
DeMUX
I-Channel
Q - Channel
MUX
MUX
Note 1: Stage 1A FIR is the first stage of the FIR A filter
2: (a) Decimation Input (Not in DDC mode): Only FIR_A<8:0> is used
(b) DDC Input for I/Q filtering in DDC mode: FIR_A<8:1> for I data and FIR_B<7:0> for Q data are used
3: Maximum Decimation Rate:
(a) When DDC is not used: 512x
(b) When DDC is used: 128x each for FIR A and FIR B
I and Q Data
Input
in DDC Mode
(MCP37D20 only)
2015-2016 Microchip Technology Inc. DS20005396B-page 45
MCP37220-200 AND MCP37D20-200
4.6.2 DIGITAL DOWN-CONVERSION
(MCP37D20-200 ONLY)
The Digital Down-Conversion (DDC) feature is available
in MCP37D20-200. This feature can be optionally
combined with the decimation filter and used to:
• translate the input frequency spectrum to lower
frequency band
• remove the unwanted out-of-band portion
• output the resulting signal as either I/Q data or a
real signal centered at ¼ of the output data rate.
Figure 4-13 shows the DDC configuration. The DDC
includes a 32-bit complex numerically controlled
oscillator (NCO), a selectable (high/low) half-band filter,
optional decimation and two output modes (I/Q or fS/8).
Frequency translation is accomplished with the NCO.
The NCO frequency is programmable from 0 Hz to fs.
Phase and amplitude dither can be enabled to improve
spurious performance of the NCO.
Each of the processing sub-blocks are individually
controlled. Examples of setting registers for selected
output type are shown in Tables 4-11 and 4-12 in
Section 4.6.3 “Examples of Register Settings for
DDC and Decimation”.
This DDC feature can be used in a variety of
high-speed signal-processing applications, including
digital radio, wireless base stations, radar, cable
modems, digital video, MRI imaging, etc.
Example:
If the ADC is sampling an input at 200 Msps but the
user is only interested in a 5 MHz span centered at
67 MHz, the digital down-conversion may be used to
mix the sampled ADC data with 67 MHz to convert it to
DC. The resulting signal can then be decimated by 16x
such that the bandwidth of the ADC output is 6.25 MHz
(200 Msps/16x decimation gives 12.5 Msps with
6.25 MHz Nyquist bandwidth). If fS/8 mode is selected,
then a single 25 Msps channel is output, where
6.25 MHz in the output data corresponds to 67 MHz at
the ADC input. If I/Q mode is selected, then two
12.5 Msps channels are output, where DC corresponds
to 67 MHz and the channels represents In-Phase (I)
and Quadrature (Q) components of the down-
conversion.
FIGURE 4-13: Simplified DDC Block Diagram. See Tables 4-11 and 4-12 for using this DDC Block.
Half-Band Filter A
LP/HP
NCO (32-bit)
I
Q
HBFILTER_A
Decimation and Output Frequency Translation
FIR A
Decimation Filter
(Note 2)
(
Note 1
)
(Note 1)
Real
(Note 3)
EN_DDC2
EN_DDC_FS/8
NCO (
)
EN_DDC1
f
S
/8
DER
EN_NCO
(Note 4)
(Note 5)
ADC DATA
COS SIN
FIR_A<8:1>
FIR_B<7:0>
FIR B
Decimation Filter
I or IDEC
Q or QDEC
RealDEC
or
Note 1: See Addresses 0x80 - 0x81 (Registers 5-37 – 5-38) for the Control Parameters.
2: See Figure 4-14 for details of NCO control block.
3: Half-band Filter A includes a single- stage decimation filter.
4: See Figure 4-12 for details.
5: Switches are closed if decimation filter is not used, and open if decimation filter is used.
Down-Converting and Decimation
MCP37220-200 AND MCP37D20-200
DS20005396B-page 46 2015-2016 Microchip Technology Inc.
4.6.2.1 Numerically Controlled Oscillator
(NCO)
The on-board Numerically Controlled Oscillator (NCO)
provides the frequency reference for the In-Phase and
Quadrature mixers in the digital down-converter (DDC).
The NCO serves as a quadrature local oscillator capable
of producing an NCO frequency of between 0 Hz and f
S
with a resolution of f
S
/2
32
, where f
S
is the ADC core
sampling frequency.
Figure 4-14 shows the control signals associated with
the NCO.
FIGURE 4-14: NCO Block Diagram.
• NCO Frequency Control:
The NCO frequency is programmed from 0 Hz to fS,
using the 32-bit wide unsigned register variable
NCO_TUNE<31:0> in Addresses 0x82 – 0x85
(Registers 5-39 – 5-42).
The following equation is used to set the
NCO_TUNE<31:0> register:
EQUATION 4-4: NCO FREQUENCY
Mod() is a remainder function. For example,
Mod(5, 2) = 1 and Mod(1.999, 2) = 1.999.
Example 1:
If fNCO is 100 MHz and fS is 200 MHz:
Example 2:
If fNCO is 199.99999994 MHz and fS is 200 MHz:
4.6.2.2 NCO Amplitude and Phase Dither
The EN_AMPDITH and EN_PHSDITH parameters in
Address 0x80 (Register 5-37) can be used for
amplitude and phase dithering, respectively.
In principle, these will dither the quantization error
created by the use of digital circuits in the mixer and
local oscillator, thus reducing spurs at the expense of
noise. In practice, the DDC circuitry has been designed
with sufficient noise and spurious performance for most
applications. In the worst case scenario, the NCO has
an SFDR of greater than 116 dB when the amplitude
dither is enabled and 112 dB when disabled.
Although the SNR (93 dB) of the DDC is not
significantly affected by the dithering option, using the
NCO with dithering options enabled is always
recommended for the best performance.
4.6.2.3 NCO for fS/8 and fS/(8xDER)
The output of the first down-conversion block (DDC1)
is a complex signal (comprising I and Q data) which can
then be optionally decimated further up to 128x to
provide both a lower output data rate and input channel
filtering. If fS/8 mode is enabled, a second mixer stage
(DDC2) will convert the I/Q signals from the DDC1 to a
real signal centered at half of the current Nyquist
frequency; i.e., if the current output data rate for I and Q
is 25 Msps each (12.5 MHz Nyquist), then in fS/8 mode
the output data rate would be 50 Msps (25 Msps x2 for
I and Q) and the resulting real signal after combining
the two would be re-centered around 12.5 MHz.
This second frequency translation by DDC2 is
accomplished after the decimation filters (if used) as
shown in Figure 4-13.
When decimation is enabled, the I/Q outputs are
up-converted by fS/(8xDER), where DER is the
additional decimation rate added by the FIR decimation
filters. This provides a decimated output signal
centered at fS/8 or fS/(8xDER) in the frequency domain.
Note: The NCO is only used for DDC. It should be
disabled when not in use.
NCO_PHASE<15:0>
Amplitude Dither EN_AMPDITH
EN_PHSDITH
EN_LFSR
NCO_TUNE<31:0>
Phase Offset Control
NCO Tuning Sine/Cosine
Signal Generator NCO Output
EN_NCO
Phase Dither EN_LFSR
NCO _TUNE<31:0> round 232 Mod fNCO fS

fS
----------------------------------------



=
Where:
fS= sampling frequency (Hz)
fNCO = desired NCO frequency (Hz)
Mod (fNCO, fS) = gives the remainder of fNCO/fS
Mod fNCO fS
Mod 100 200
100==
NCO_TUNE<31:0> round 232 Mod 100 200

200
--------------------------------------


=
0x8000 0000=
Mod fNCO fS
Mod 199.99999994 200
199.99999994==
NCO_TUNE<31:0> round 232 Mod 199.99999994 200

200
---------------------------------------------------------------


=
0xFFFF FFFF=
2015-2016 Microchip Technology Inc. DS20005396B-page 47
MCP37220-200 AND MCP37D20-200
4.6.2.4 NCO Phase Offset Control
The user can add phase offset to the NCO frequency
using the NCO phase offset control registers
(Addresses 0x86 to 0x87 – Registers 5-43 – 5-44).
NCO_PHASE<15:0> is the 16-bit-wide NCO phase
offset control parameter. The phase offset can be
controlled from 0° to 359.995° with 0.005° per step. The
following equation is used to program the NCO phase
offset register:
EQUATION 4-5: NCO PHASE OFFSET
A decimal number is used for the binary contents of the
NCO_PHASE<15:0>.
4.6.2.5 In-Phase and Quadrature Signals
When the first down-conversion is enabled, it produces
In-phase (I) and Quadrature (Q) components given by:
EQUATION 4-6: I AND Q SIGNALS
I and Q data are output in an interleaved fashion where
I data is output on the rising edge of the WCK.
4.6.2.6 Half-Band Filter
The frequency translation is followed by a half-band
digital filter, which is used to reduce the sample rate by
a factor of two while rejecting aliases that fall into the
band of interest.
The user can select a high- or low-pass half-band filter
using the HBFILTER_A bit in Address 0x80
(Register 5-37). Figures 4-15 and 4-16 show the
transfer functions of the filters. These filters provide
greater than 90 dB of attenuation in the attenuation
band, and less than 1 mdB (10-3 dB) of ripple in the
passband region of 20% of the input sampling rate.
For example, for an ADC sample rate of 200 Msps,
these filters provide less than 1 mdB of ripple over a
bandwidth of 40 MHz.
The filter responses shown in Figures 4-15 and 4-16
indicate a ripple of 0.5 mdB and an alias rejection of
90 dB. The output of the half-band filter is a
DC-centered complex signal (I and Q). This I and Q
signal is then carried to the next down-conversion
stage (DDC2) for frequency translation
(up-conversion), if the DDC is enabled.
FIGURE 4-15: High-Pass (HP) Response
of Half-Band Filter.
FIGURE 4-16: Low-Pass (LP) Response of
Half-Band Filter.
NCO_PHASE<15:0> 216 Offset Value (
360
---------------------------------------
=
where:
Offset Value () = desired phase offset value in degrees
where:
IADCCOS2
fNCOt
+
=
QADCSIN2
fNCOt
+
=
360 NCO_PHASE<15:0>
216
----------------------------------------------------
=
0.005493164
NCO_PHASE<15:0>
=
where:
ADC = output of the ADC block
= NCO phase offset defined by
NCO_PHASE<15:0> in Address 0x86
t = k/fS, with k =1, 2, 3,..., n
fNCO = NCO frequency
Note:
The half-band filter delays the data output by
80 clock cycles: 2 (due to decimation) x 40
cycles (due to filter group delay)
In-Band Ripple
0.0005
0
-0.0005
0
-30
-60
-90
-120
Amplitude (dBc)
0 0.1 0.2 0.3 0.4 0.5
Half-Band Filter Frequency Response
0 0.1 0.2 0.3 0.4 0.5
Fraction of Input Sample Rate
In-Band Ripple
0.0005
0
-0.0005
0
-30
-60
-90
-120
Amplitude (dBc)
0 0.1 0.2 0.3 0.4 0.5
Half-Band Filter Frequency Response
0 0.1 0.2 0.3 0.4 0.5
Fraction of Input Sample Rate
MCP37220-200 AND MCP37D20-200
DS20005396B-page 48 2015-2016 Microchip Technology Inc.
4.6.3 EXAMPLES OF REGISTER
SETTINGS FOR DDC AND
DECIMATION
The following tables show examples of setting registers
for using digital down-conversion (DDC) with
decimation depending on the output type selection. This
feature is available in the MCP37D20-200 device only.
TABLE 4-11: REGISTER SETTINGS FOR DDC AND DECIMATION OPTIONS – EXAMPLE
Decimation Rate
(by FIR A and FIR B)(1)
DDC
Mode
Address
0x02(2)
FIR A Filter FIR B Filter DDC1 DDC2
Output
0x7A<6>
(FIR_A<0>)
0x7B
(FIR_A<8:1>)
0x7C
(FIR_B<7:0>)
0x80<5,1,0>(3)
0x81<6>(4)
0 Disabled 0x00 00x00 0x00 0,0,00ADC
8 Disabled 0x33 10x03 0x00 0,0,00ADC with decimation (÷8)
512 Disabled 0x99 10xFF 0x00 0,0,00ADC with decimation (÷512)
0I/Q0x00
(5)00x00 0x00 1,0,10I/Q Data
8 I/Q 0x33 00x07 0x07 1,0,10Decimated I/Q (÷8)
0f
S/8 0x11(6)00x00 0x00 1,1,10Real without additional
decimation
8f
S/8 0x44 00x07 0x07 1,0,11Real with decimation (÷16)
Note 1: When DDC is used, the actual total decimation is 2x larger since 2x is included from the DDC Half-Band Filter.
Example: Decimation = 8x with DDC-IQ option actually has 16x decimation with 8x provided by the decimation filter
and 2x from the DDC Half-Band Filter.
2: Output data and clock rate control register.
3: 0x80<5,1,0> = <EN_NCO, EN_DDC_FS/8, EN_DDC1>.
4: 0x81<6> = <EN_DDC2>.
5: Each of I/Q has 1/2 of fS bandwidth. The combined bandwidth is the same as the fS bandwidth. Therefore, the data rate
adjustment is not needed.
6: The Half-Band Filter A includes decimation of 2.
2015-2016 Microchip Technology Inc. DS20005396B-page 49
MCP37220-200 AND MCP37D20-200
TABLE 4-12: OUTPUT TYPE VS. CONTROL PARAMETERS FOR DDC – EXAMPLE
Output Type Control Parameter Register Descriptions
Complex: I and Q EN_DDC1 = 10X80 Enable DDC1 block
EN_NCO = 10X80 Enable 32-bit NCO
HBFILTER_A = 10X80 Enable Half-Band Filter A, includes 2x decimation
EN_DDC_FS/8 = 00X80 NCO (fS/8/DER) is disabled
EN_DDC2 = 00X81 DDC2 is disabled
FIR_A<8:1>=0x00 0X7B FIR A decimation filter is disabled
FIR_B<7:0>=0x00 0X7C FIR B decimation filter is disabled
OUT_CLKRATE<3:0> 0X02 Output clock rate is not affected (no need to change)
Decimated I and
Q:IDEC, QDEC
EN_DDC1 = 10X80 Enable DDC1 block
EN_NCO = 10X80 Enable 32-bit NCO
HBFILTER_A = 10X80 Enable Half-Band Filter A, includes 2x decimation
EN_DDC_FS/8 = 00X80 NCO (fS/8/DER) is disabled
EN_DDC2 = 00X81 DDC2 is disabled
FIR_A<8:1> 0X7B Program FIR A filter for extra decimation(1)
FIR_B<7:0> 0X7C Program FIR B filter for extra decimation(1)
OUT_CLKRATE<3:0> 0X02 Adjust the output clock rate to the decimation rate
Real:
RealA after
DDC(fS/8/DER)
without using
Decimation Filter
EN_DDC1 = 10X80 Enable DDC1 block
EN_NCO = 10X80 Enable 32-bit NCO
HBFILTER_A = 10X80 Enable Half-Band Filter A, includes 2x decimation
EN_DDC_FS/8 = 10X80 NCO (fS/8/DER) is enabled. This translates the input
signal from DC to fS/8(2)
EN_DDC2 = 10X81 DDC2 is enabled
FIR_A<8:1>=0x00 0X7B Decimation filter FIR A is disabled
FIR_B<7:0>=0x00 0X7C Decimation filter FIR B is disabled
OUT_CLKRATE<3:0> = 0001 0X02 Adjust the output clock rate to divided by 2(3)
Decimated Real:
RealA_DEC
after Decimation
Filter and
DDC(fS/8/DER)
EN_DDC1 = 10X80 Enable DDC1 block
EN_NCO = 10X80 Enable 32-bit NCO
HBFILTER_A = 10X80 Enable Half-Band Filter A, includes 2x decimation
EN_DDC_FS/8 = 10X80 NCO (fS/8/DER) is enabled. This translates the input
signal from DC to fS/8/DER(2)
EN_DDC2 = 10X81 DDC2 is enabled
FIR_A<8:1> 0X7B Program FIR B filter for extra decimation(4)
FIR_B<7:0> 0X7C Program FIR B filter for extra decimation(4)
OUT_CLKRATE<3:0> 0X02 Adjust the output clock rate to the total decimation
rate including the 2x decimation by the Half-Band
Filter A
Note 1: For I/Q decimation, the maximum decimation rate for the FIR A and FIR B filters is 128x each since the
input is already decimated by 2x in the Half-Band Filter. See Figure 4-12 for details.
2: DER is the decimation rate setting of the FIR A and FIR B filters.
3: The Half-Band Filter A includes decimation of 2.
4: When this filter is used, the up-conversion frequency is reduced by the extra decimation rates (DER).
MCP37220-200 AND MCP37D20-200
DS20005396B-page 50 2015-2016 Microchip Technology Inc.
4.7 Digital Offset and Digital Gain
Settings
Figure 4-17 shows a simplified block diagram of the
digital offset and gain settings. Offset is applied prior to
the gain. Offset and gain adjustments occur prior to
DDC or decimation when these features are used.
4.7.1 DIGITAL OFFSET SETTINGS
The ADC digital offset can be controlled using two
combined digital offset correction registers:
DIG_OFFSET<15:0> in Addresses 0x66 - 0x67.
4.7.2 DIGITAL GAIN SETTINGS
The ADC digital gain can be controlled using
DIG_GAIN<7:0> in Addresses 0x96 - 0x9D. All
DIG_GAIN<7:0> in Addresses 0x96 - 0x9D must be
programmed with the same value.
When the device is first powered-up or has hardware
reset, DIG_GAIN<7:0> is set with a default setting
(‘0011-1100’). The user may program the
DIG_GAIN<7:0> to ‘0011-1000’ for optimum SNR
performance (0.7 dB higher than the default setting).
FIGURE 4-17: Simplified Block Diagram for
Digital Offset and Gain Settings.
DIG_GAIN<7:0>
Digital
ADC
Offset Control
Digital
Gain Control
Output
Corrected
ADC Output
DIG_OFFSET<15:0>
2015-2016 Microchip Technology Inc. DS20005396B-page 51
MCP37220-200 AND MCP37D20-200
4.8 Output Data Format
The device can output the ADC data in offset binary or
two’s complement. The data format is selected by the
DATA_FORMAT bit in Address 0x62 (Register 5-20).
Table 4-13 shows the relationship between the analog
input voltage, the digital data output bits and the
overrange bit. By default, the output data format is
two’s complement.
4.9 Digital Output
The MCP37220-200 and MCP37D20-200 can operate
in one of the following two digital output modes:
• Full-Rate CMOS
• Double-Data-Rate (DDR) LVDS
The outputs are powered by DVDD18 and GND.
LVDS mode is recommended for data rates above
80 Msps. The digital output mode is selected by the
OUTPUT_MODE<1:0> bits in Address 0x62
(Register 5-20). Figures 2-1 – 2-2 show the timing
diagrams of the digital output.
4.9.1 FULL-RATE CMOS MODE
In full-rate CMOS mode, the data outputs (Q13 to Q0),
overrange indicator (OVR), word clock (WCK) and the
data output clock (DCLK+, DCLK-) have CMOS output
levels. The WCK is disabled, except for the I/Q data
output mode in the MCP37D20. The digital output
should drive minimal capacitive loads. If the load
capacitance is larger than 10 pF, a digital buffer should
be used.
4.9.2 DOUBLE-DATA-RATE LVDS MODE
The double-data-rate (DDR) LVDS mode is a parallel
data stream which changes on each edge of the output
clock. See Figure 2-2 for details.
In I/Q data output mode in the MCP37D20-200, I and Q
data are clocked out sequentially with the WCK that is
synchronized to I data. OVR and WCK are an LVDS pair.
The device outputs the following LVDS output pairs:
• Output data: Q6+/Q6- through Q0+/Q0-
• Output clock: DCLK+/DCLK-
•OVR/WCK
Note that WCK is logic ‘0’ except in I/Q mode.
A 100Ω differential termination resistor is required for
each LVDS output pin pair. The termination resistor
should be located as close as possible to the LVDS
receiver. By default, the outputs are standard LVDS
levels: 3.5 mA output current with a 1.15V output
common-mode voltage on 100 differential load.
See Address 0x63 (Register 5-21) for more details of
the LVDS mode control.
TABLE 4-13: ADC OUTPUT CODE VS. INPUT VOLTAGE
Input Range Offset Binary (1)Two’s Complement (1)Overrange (OVR)
AIN >A
FS 11-1111-1111-1111 01-1111-1111-1111 1
AIN =A
FS 11-1111-1111-1111 01-1111-1111-1111 0
AIN =A
FS –1LSb 11-1111-1111-1110 01-1111-1111-1110 0
AIN =A
FS –2LSb 11-1111-1111-1100 01-1111-1111-1100 0
•
•
•
AIN =A
FS/2 11-0000-0000-0000 01-0000-0000-0000 0
AIN =0 10-0000-0000-0000 00-0000-0000-0000 0
AIN =-A
FS/2 00-1111-1111-1111 10-1111-1111-1111 0
•
•
•
AIN =-A
FS +2LSb 00-0000-0000-0010 10-0000-0000-0010 0
AIN =-A
FS +1LSb 00-0000-0000-0001 10-0000-0000-0001 0
AIN =-A
FS 00-0000-0000-0000 10-0000-0000-0000 0
AIN <-A
FS 00-0000-0000-0000 10-0000-0000-0000 1
Note 1: MSb is sign bit.
Note: LVDS output polarity can be controlled
independently for each LVDS pair.
See POL_LVDS<6:0> setting in
Address 0x65 (Register 5-23)
MCP37220-200 AND MCP37D20-200
DS20005396B-page 52 2015-2016 Microchip Technology Inc.
4.9.3 OVERRANGE BIT (OVR)
The input overrange status bit is asserted (logic high)
when the analog input has exceeded the full-scale
range of the ADC in either the positive or negative
direction. The OVR bit has the same pipeline latency as
the ADC data bits. See Address 0x68 (Register 5-26)
for OVR control options.
If DSPP option is enabled, OVR pipeline latency will be
unaffected; however, the data will incur additional
delay. This has the effect of allowing the OVR indicator
to precede the affected data.
4.9.3.1 OVR Bit in LVDS DDR Output Mode
(a) Normal ADC Output Mode:
The device outputs the OVR bit on the falling edge of
the data output clock.
(b) I and Q Output Mode in MCP37D20-200:
The OVR bit is multiplexed with the word clock (WCK)
output bit, such that OVR is output on the falling edge
of the data output clock and WCK on the rising edge.
4.9.4 WORD CLOCK (WCK)
• MCP37220-200: WCK is disabled.
• MCP37D20-200: WCK is available in I/Q data
output mode only. WCK is asserted coincidentally
with the I data. See Address 0x68 (Register 5-26)
for OVR and WCK control options.
4.9.5 LVDS OUTPUT POLARITY CONTROL
In LVDS mode, the output polarity can be controlled
independently for each LVDS pair. Table 4-14
summarizes the LVDS output polarity control register bits.
4.9.6 PROGRAMMABLE LVDS OUTPUT
CURRENT
In LVDS mode, the default output driver current is
3.5 mA. This current can be adjusted by using the
LVDS_IMODE<2:0> bit setting in Address 0x63
(Register 5-21). Available output drive currents are
1.8 mA, 3.5 mA, 5.4 mA, and 7.2 mA.
4.9.7 OPTIONAL LVDS DRIVER
INTERNAL TERMINATION
In most cases, using an external 100Ω termination
resistor will give excellent LVDS signal integrity. In
addition, an optional internal 100Ω termination resistor
can be enabled by setting the LVDS_LOAD bit in
Address 0x63 (Register 5-21). The internal termination
helps absorb any reflections caused by imperfect
impedance termination at the receiver.
4.9.8 OUTPUT DATA AND CLOCK RATES
The user can reduce output data and output clock rates
using Address 0x02 (Register 5-3). When decimation
or digital down-conversion (DDC) is used, the output
data rate has to be reduced to synchronize with the
reduced output clock rate.
4.9.9 PHASE SHIFTING OF OUTPUT
CLOCK (DCLK)
In full-rate CMOS mode, the data output bit transition
occurs at the rising edge of DCLK+, so the falling edge
of DCLK+ can be used to latch the output data.
In double-data-rate LVDS mode, the data transition
occurs at both the rising and falling edges of DCLK+.
For adequate setup and hold time when latching the
data into the external host device, the user can shift the
phase of the digital clock output (DCLK+/DCLK-),
relative to the data output bits.
The output phase shift (delay) is controlled by each
unique register, depending on which timing source is
used or if decimation is used. Table 4-15 shows the
output clock phase control registers for each
configuration mode: (a) when DLL is used, (b) when
decimation is used and (c) when PLL is used.
Figure 4-18 shows an example of the output clock
phase delay control using DCLK_PHDLY_DLL<2:0>
when DLL is used.
TABLE 4-14: LVDS OUTPUT POLARITY
CONTROL
Control
Parameter Register Descriptions
POL_LVDS<6:0> 0x65 Control polarity of LVDS
data pairs
POL_OVR_WCK 0x68 Control polarity of OVR
and WCK bit pair
2015-2016 Microchip Technology Inc. DS20005396B-page 53
MCP37220-200 AND MCP37D20-200
FIGURE 4-18: Example of Phase Shifting of Digital Output Clock (DCLK+) when DLL is used.
TABLE 4-15: OUTPUT CLOCK (DCLK) PHASE CONTROL PARAMETERS
Control Parameter Register Operating Condition(1)
When DLL is used:
EN_PHDLY 0x64 EN_PHDLY = 1: Enable output clock phase delay control
DCLK_PHDLY_DLL<2:0> 0x52 DCLK phase delay control when DLL is used. Decimation is not used.
When decimation is used:
EN_PHDLY 0x64 EN_PHDLY = 1: Enable output clock phase delay control
DCLK_PHDLY_DEC<2:0> DCLK phase delay control when decimation filter is used. The phase delay
is controlled in digital clock output control block.
When PLL is used:
DCLK_DLY_PLL<2:0> 0x6D DCLK delay control when PLL is used.
Note 1: See Figure 4-11 for details.
Output Clock
Phase Shift:
0°
45° + Default
90° + Default
135° + Default
180° + Default
225° + Default
270° + Default
315° + Default
DCLK_PHDLY_DLL<2:0>
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
(DCLK+)
LVDS Data Output:
= 0 0 0
Note 1: Default value may not be 0° in all operations
(Default)(1)
MCP37220-200 AND MCP37D20-200
DS20005396B-page 54 2015-2016 Microchip Technology Inc.
4.9.10 DIGITAL OUTPUT RANDOMIZER
Depending on PCB layout considerations and power
supply coupling, SFDR may be improved by
decorrelating the ADC input from the ADC digital output
data. The device includes an output data randomizer
option. When this option is enabled, the digital output is
randomized by applying an exclusive-OR logic
operation between the LSb (D0) and all other data
output bits.
To decode the randomized data, the reverse operation
is applied: an exclusive-OR operation is applied
between the LSb (D0) and all other bits. The DCLK,
OVR, WCK and LSb (D0) outputs are not affected.
Figure 4-19 shows the block diagram of the data
randomizer and decoder logic. The output randomizer
is enabled by setting the EN_OUT_RANDOM bit in
Address 0x07 (Register 5-5).
FIGURE 4-19: Logic Diagram for Digital Output Randomizer and Decoder.
4.9.11 OUTPUT DISABLE
The digital output can be disabled by setting
OUTPUT_MODE<1:0> = 00 in Address 0x62
(Register 5-20). All digital outputs are disabled,
including OVR, DCLK, etc.
4.9.12 OUTPUT TEST PATTERNS
To facilitate testing of the I/O interface, the device can
produce various predefined or user-defined patterns on
the digital outputs. See TEST_PATTERNS<2:0> in
Address 0x62 (Register 5-20) for the predefined test
patterns. For the user-defined test patterns, Addresses
0x74–0x77 (Registers 5-29 – 5-32) can be used.
When an output test mode is enabled, the ADC’s
analog section can still be operational, but does not
drive the digital outputs. The outputs are driven only
with the selected test pattern.
Since the output test pins (TP, TP1 and TP2) can toggle
during this test, always leave these test pins floating (not
connected) to avoid contention and excess current draws.
4.9.12.1 Pseudo-Random Number (PN)
Sequence Output
When TEST_PATTERNS<2:0> = 111, the device
outputs a pseudo-random number (PN) sequence
which is defined by the polynomial of degree 16, as
shown in Equation 4-7. Figure 4-20 shows the block
diagram of a 16-bit Linear Feedback Shift Register
(LFSR) for the PN sequence.
EQUATION 4-7: POLYNOMIAL FOR PN
Q0
Q1
Q2
Q12
Q13
DCLK
OVR
Q1
Q2
Q12
Q13
DCLK
OVR
Q0
Data Acquisition Device
(a) Data Randomizer (b) Data Decoder
DCLK
Q13
OVR
Q0
Q12 Q0
Q2 Q0
Q1 Q0
Q0
EN_OUT_RANDOM
MCP37XXX
WCK WCK
WCK
Px 1x
4x13 x15 x16
++++=
2015-2016 Microchip Technology Inc. DS20005396B-page 55
MCP37220-200 AND MCP37D20-200
The output PN[15:2] is directly applied to the output
pins Qn[13:0]. In addition to the output at the Qn[13:0]
pins, PN[15] is copied to the OVR pin and PN[14] is
copied to the WCK pin. In CMOS output mode, the
pattern is always applied to all CMOS I/O pins,
regardless whether or not they are enabled. In LVDS
output mode, the pattern is only applied to the LVDS
pairs that are enabled.
FIGURE 4-20: Block Diagram of 16-bit LFSR
for Pseudo-Random Number (PN) Sequence for
Output Test Pattern.
4.10 System Calibration
The built-in system calibration algorithm includes:
• Harmonic Distortion Correction (HDC)
• DAC Noise Cancellation (DNC)
• Dynamic Element Matching (DEM)
HDC and DNC correct the nonlinearity in the residue
amplifier and DAC, respectively. The system calibration
is performed by:
• Power-up calibration, which takes place during
the Power-on Reset sequence (requires 3×226
clock cycles)
• Background calibration, which takes place during
normal operation (per 230 clock cycles).
Background calibration time is invisible to the user and
primarily affects the ADC's ability to track variations in
ambient temperature.
The calibration status is monitored by the CAL pin or
the ADC_CAL_STAT bit in Address 0xC0 (Register 5-
67). See also Address 0x07 (Register 5-5) and 0x1E
(Register 5-6) for time delay control of the
auto-calibration. Tabl e 4-16 shows the calibration time
for various ADC core sample rates.
4.10.1 RESET COMMAND
Although the background calibration will track changes
in temperature or supply voltage, changes in clock
frequency or register configuration should be followed
by a recalibration of the ADC. This can be
accomplished via either the Hard or the Soft Reset
command. The recalibration time is the same as the
power-up calibration time. Resetting the device is
highly recommended when exiting from Shutdown or
Standby mode after an extended amount of time.
During the reset, the device has the following state:
• No ADC output
• No change in power-on condition of internal
reference
• Most of the internal clocks are not distributed
• Contents of internal user registers:
- Not affected by Soft Reset
- Reset to default values by Hardware Reset
• Current consumption of the digital section is
negligible, but no change in the analog section.
4.10.1.1 Hardware Reset
A hard reset is triggered by toggling the RESET pin. On
the rising edge, all internal calibration registers and
user registers are initialized to their default states and
recalibration of the ADC begins. The recalibration time
is the same as the power-up calibration time. See
Figure 2-6 for the timing details of the hardware
RESET pin.
4.10.1.2 Soft Reset
The user can issue a Soft Reset command for a fast
recalibration of the ADC by setting the SOFT_RESET
bit to ‘0’ in Address 0x00 (Register 5-1). During
Soft Reset, all internal calibration registers are
initialized to their initial default states. User registers are
unaffected. When exiting the Soft Reset (changing from
‘0’ to ‘1’), an automatic device calibration takes place.
TABLE 4-16: CALIBRATION TIME VS. ADC
CORE SAMPLE RATE
fS(Msps) 200 150 100 70 50
Power-Up
Calibration Time (s)
1.01 1.34 2.01 2.88 4.03
Background
Calibration Time (s)
5.37 7.16 10.73 15.34 21.48
Z-4 Z-9 Z-2 Z-1
XOR
PN[3] PN[12] PN[14] PN[15]
MCP37220-200 AND MCP37D20-200
DS20005396B-page 56 2015-2016 Microchip Technology Inc.
4.11 Power Dissipation and Power
Savings
The power dissipation of the ADC core is proportional
to the sample rate (fS). The digital power dissipation of
the CMOS outputs are determined primarily by the
strength of the digital drivers and the load condition on
each output pin. The maximum digital load current
(ILOAD) can be calculated as:
EQUATION 4-8: CMOS OUTPUT LOAD
CURRENT
The capacitive load presented at the output pins needs
to be minimized to minimize digital power consumption.
The output load current of the LVDS output is constant,
since it is set by LVDS_IMODE<2:0> in Address 0x63
(Register 5-21).
4.11.1 POWER-SAVING MODES
This device has two power-saving modes:
• Shutdown
• Standby
They are set by the SHUTDOWN and STANDBY bits in
Address 0x00 (Register 5-1).
In Shutdown mode, most of the internal circuitry,
including the reference and clock, are turned off with
the exception of the SPI interface. During Shutdown
mode, the device consumes 25 mA (typical), primarily
due to digital leakage. When exiting from Shutdown
mode, issuing a Soft Reset at the same time is highly
recommended. This will perform a fast recalibration of
the ADC. The contents of the internal registers are not
affected by the Soft Reset.
In Standby mode, most of the internal circuitry is
disabled, except for the reference, clock and SPI
interface. If the device has been in standby for an
extended period of time, the current calibration value
may not be accurate. Therefore, when exiting from
Standby mode, executing the device Soft Reset at the
same time is highly recommended.
ILOAD DVDD1.8 fDCLK NC
LOAD
=
Where:
N = Number of bits
CLOAD = Capacitive load of output pin
2015-2016 Microchip Technology Inc. DS20005396B-page 57
MCP37220-200 AND MCP37D20-200
5.0 SERIAL PERIPHERAL
INTERFACE (SPI)
The user can configure the ADC for specific functions
or optimized performance by setting the device’s
internal registers through the Serial Peripheral
Interface (SPI). The SPI communication uses three
pins: CS, SCLK and SDIO. Ta b l e 5 - 1 summarizes the
SPI pin functions. The SCLK is used as serial timing
clock and can be used up to 50 MHz.
SDIO (Serial Data Input/Output) is a dual-purpose pin
that allows data to be sent or read from the internal
registers. The Chip Select (CS) pin enables the SPI
communication when active-low. The falling edge of CS
followed by a rising edge of SCLK determines the start
of the SPI communication. When CS is tied to high, the
SPI communication is disabled and SPI pins are placed
in high-impedance mode. The internal registers are
accessible by their address.
Figures 5-1 and 5-2 show the SPI data communication
protocols for this device with MSb-first and LSb-first
option, respectively. It consists of:
• 16-bit wide instruction header + Data byte 1 +
Data byte 2 +. . .+ Data Byte N
Table 5-2 summarizes the bit functions. The R/W bit of
the instruction header indicates whether the command
is a read (‘1’) or a write (‘0’):
•If the R/W
bit is ‘1’, the SDIO pin changes
direction from an input (SDI) to an output (SDO)
after the 16-bit wide instruction header.
By selecting the R/W bit, the user can write the register
or read back the register contents. The W1 and W2 bits
in the instruction header indicate the number of data
bytes to transmit or receive in the following data frame.
A2 – A0 bits are the SPI device address bits. These bits
are used when multiple devices are used in the same
SPI bus. A2 is internally hard-coded to ‘0’. A1 and A0
bits correspond to the logic level of ADR1 and ADR0
pins, respectively.
The R9 – R0 bits represent the starting address of the
configuration register to write or read. The data bytes
following the instruction header are the register data. All
register data is eight bits wide. Data can be sent in
MSb-first mode (default) or in LSb-first mode, which is
determined by the <LSB_ FIRST> bit setting in
Address 0x00 (Register 5-1). In Write mode, the data is
clocked in at the rising edge of the SCLK. In Read mode,
the data is clocked out at the falling edge of the SCLK.
Note: In VTLA-124 package, ADR1 is internally
bonded to ground (logic ‘0’).
TABLE 5-1: SPI PIN FUNCTIONS
Pin
Name Descriptions
CSChip Select pin. SPI mode is initiated at
the falling edge. It needs to maintain
active-low for the entire period of the
SPI communication. The device exits the
SPI communication at the rising edge.
SCLK Serial clock input pin.
• Writing to the device: Data is latched
at the rising edge of SCLK
• Reading from the device: Data is
latched at the falling edge of SCLK
SDIO Serial data input/output pin. This pin is
initially input pin (SDI) during the first
16-bit instruction header. After the
instruction header, it’s I/O status can be
changed depending on R/W bit:
•if R/W=0: Data input pin (SDI) for
writing
•if R/W
=1: Data output pin (SDO) for
reading
TABLE 5-2: SPI DATA PROTOCOL BIT
FUNCTIONS
Bit Name Descriptions
R/W 1= Read Mode
0= Write Mode
W1, W0
(Data Length)
00 = Data for one register (1 byte)
01 = Data for two registers (2 bytes)
10 = Data for three registers (3 bytes)
11 = Continuous reading or writing by
clocking SCLK(1)
A2 - A0 Device SPI Address for multiple
devices in SPI bus.
A2: Internally hard-coded to ‘0’
A1: Logic level of ADR1 pin
A0: Logic level of ADR0 pin
R9 - R0 Address of starting register.
D7 - D0 Register data. MSb or LSb first,
depending on the LSB_FIRST bit
setting in 0x00.
Note 1: The register address counter is
incremented by one per step. The counter
does not automatically reset to 0x00 after
reaching the last address (0x15D). Be
aware that the user-registers are not
sequentially allocated.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 58 2015-2016 Microchip Technology Inc.
FIGURE 5-1: SPI Serial Data Communication Protocol with MSb-first. See Figures 2-5 and 2-6 for
Timing Specifications.
FIGURE 5-2: SPI Serial Data Communication Protocol with LSb-First. See Figures 2-5 and 2-6 for
Timing Specifications.
5.1 Register Initialization
The internal configuration registers are initialized to
their default values by two different ways:
• After 220 clock cycles of delay from the Power-on
Reset (POR).
• Reset by the hardware reset pin (RESET).
Figures 2-5 and 2-6 show the timing details.
5.2 Configuration Registers
The internal registers are mapped from address 0x00 to
0x15D. These user registers are not sequentially located.
Some user configuration registers include
factory-controlled bits. The factory-controlled register
bits should not be overwritten by the user.
All user configuration registers are read/write, except
for the last four registers, which are read-only. Each
register is made of an 8-bit-wide volatile memory and
their default values are loaded during the power-up
sequence or by using the hardware RESET pin. All
registers are accessible by the SPI command using the
register address. Table 5-3 shows the user-
configuration memory map and Registers 5-1 to 5-70
show the details of the register bit functions.
CS
R/W W1 W0 A2 A1 A0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
Register Data of
Register Data 2 Register Data N
16-Bit Instruction Header
Address of
SCLK
SDIO
Register Data
defined by R9 - R0
D7 D6 D5 D4 D3 D2 D1 D0 D0D1
D2
D7 D6 D5 D4 D3 D2 D1 D0
Device Address starting register
Starting Register
CS
R/WW1W0A2A1A0R9R8R7R6R5R4R3R2R1R0
Register Data 2 Register Data N
16-Bit Instruction Header
Address of
SCLK
SDIO
Register Data
D7D6
D5
D4
D3D2
D1
D0 D7D6
D5
D4
D3D2
D1
D0 D7D6
D5
Device Address Register Data of
defined by R9 - R0
starting register
Starting Register
Note 1: All address and bit locations that are not
included in the following Register map
table should not be written or modified by
the user.
2: Some registers include factory-controlled
bits (FCB). Do not overwrite these bits.
2015-2016 Microchip Technology Inc. DS20005396B-page 59
MCP37220-200 AND MCP37D20-200
TABLE 5-3: REGISTER MAP TABLE
Addr. Register Name
Bits Default
Value
b7 b6 b5 b4 b3 b2 b1 b0
0x00 SPI Bit Ordering and ADC
Mode Selection
SHUTDOWN LSb-First SOFT_RESET STANDBY STANDBY SOFT_RESET LSb-First SHUTDOWN 0x24
1= Shutdown 1=LSb first
0=MSb first
0= Soft Reset 1= Standby 1= Standby 0= Soft Reset 1= LSb first
0= MSb first
1= Shutdown
0x01 Independency Control of
Output Data and Clock
Divider
EN_DATCLK_IND
FCB<6:0> = 000 1111 0x0F
0x02 Output Data and
Clock Rate Control
OUT_DATARATE<3:0> OUT_CLKRATE<3:0> 0x00
0x04 SPI SDO Timing Control SDO_TIME FCB<6:0> = 0011111 0x9F
0x07 Output Randomizer and
WCK Polarity Control
POL_WCK EN_AUTOCAL_
TIMEDLY
FCB<4:0> = 10001 EN_OUT_
RANDOM
0x62
0x1E Auto-Calibration
Time Delay Control
AUTOCAL_TIMEDLY<7:0> 0x80
0x52 DLL Control EN_DUTY DCLK_PHDLY_DLL<2:0> EN_DLL_DCLK EN_DLL EN_CLK RESET_DLL 0x0A
0x53 Clock Source Selection FCB<6:4>= 010 CLK_SOURCE FCB<3:0>= 0101 0x45
0x54 PLL Reference Divider PLL_REFDIV<7:0> 0x00
0x55 PLL Output and
Reference Divider
PLL_OUTDIV<3:0> FCB<1:0> = 10 PLL_REFDIV<9:8> 0x48
0x56 PLL Prescaler (LSB) PLL_PRE (LSB)<7:0> 0x78
0x57 PLL Prescaler (MSB) FCB<3:0> = 0100 PLL_PRE (MSB)<11:8> 0x40
0x58 PLL Charge-Pump FCB<2:0> = 000 PLL_BIAS PLL_CHAGPUMP<3:0> 0x12
0x59 PLL Enable Control 1 UFCB<4:3> = 10
EN_PLL_REFDIV
FCB<2:1> = 00 EN_PLL FCB<0> = 10x41
0x5A PLL Loop Filter Resistor UFCB<1:0> = 01 PLL_RES<4:0> 0x2F
0x5B PLL Loop Filter Cap3 UFCB<1:0> = 01 PLL_CAP3<4:0> 0x27
0x5C PLL Loop Filter Cap1 UFCB<1:0> = 01 PLL_CAP1<4:0> 0x27
0x5D PLL Loop Filter Cap2 UFCB<1:0> = 01 PLL_CAP2<4:0> 0x27
0x5F PLL Enable Control 2 FCB<5:2> = 1111
EN_PLL_OUT
EN_PLL_BIAS FCB<1:0> = 01 0xF1
0x62 Output Data Format and
Output Test Pattern
UFCB<0> = 0DATA_FORMAT OUTPUT_MODE<1:0> TEST_PATTERNS<2:0> 0x10
0x63 LVDS Output Load and
Driver Current Control
FCB<3:0> = 0000 LVDS_LOAD LVDS_IMODE<2:0> 0x01
0x64 Output Clock Phase
Control when Decimation
Filter is used
EN_PHDLY
DCLK_PHDLY_DEC<2:0> FCB<3:0> = 0011 0x03
0x65 LVDS Output Polarity Control POL_LVDS<6:0> NO-EFFECT 0x00
0x66 Digital Offset
Correction - Lower Byte
DIG_OFFSET<7:0> 0x00
Legend: U = Unimplemented bit, read as ‘0’ FCB = Factory-Controlled bits. Do not program 1 = bit is set 0 = bit is cleared x = bit is unknown
Note 1: Read-only register. Preprogrammed at the factory for internal use.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 60 2015-2016 Microchip Technology Inc.
0x67 Digital Offset
Correction - Upper Byte
DIG_OFFSET<15:8> 0x00
0x68 OVR and WCK Bit Control FCB<5:2> = 0010
POL_OVR_WCK
EN_OVR_WCK FCB<1:0> = 00 0x24
0x6B PLL Calibration FCB<6:2> = 00001 PLL_CAL_TRIG FCB<1:0> = 00 0x08
0x6D PLL Output and Output Clock
Phase
U<1:0> EN_PLL_CLK FCB<1> = 0DCLK_DLY_PLL<2:0> FCB<0> = 00x00
0x74 User-Defined Output
Pattern A - Lower Byte
PATTERN A<5:0> Do not use
(Leave these bits as ‘00’)
0x00
0x75 User-Defined Output
Pattern A - Upper Byte
PATTERN A<13:6> 0x00
0x76 User-Defined Output
Pattern B - Lower Byte
PATTERN B<5:0> Do not use
(Leave these bits as ‘00’)
0x00
0x77 User-Defined Output
Pattern B - Upper Byte
PATTERN B<13:6> 0x00
0x79 I/Q-Channel DSPP Control EN_DSPP_I/Q FCB<6:0> = 000 0000 0x00
0x7A FIR_A0 Bit Control FCB<6> = 0FIR_A<0> FCB<5:0> = 00 0000 0x00
0x7B FIR A Filter FIR_A<8:1> 0x00
0x7C FIR B Filter FIR_B<7:0> 0x00
0x80 Digital Down-Converter
Control 1
FCB<0> = 0HBFILTER_A EN_NCO EN_AMPDITH EN_PHSDITH EN_LFSR
EN_DDC_FS/8
EN_DDC1 0x00
0x81 Digital Down-Converter
Control 2
FCB<5> = 0EN_DDC2 GAIN_HBF_DDC FCB<4:0> = 00000 0x00
0x82 Numerically Controlled
Oscillator (NCO)
Tuning - Lower Byte
NCO_TUNE<7:0> 0x00
0x83 Numerically Controlled
Oscillator (NCO)
Tuning - Middle Lower Byte
NCO_TUNE<15:8> 0x00
0x84 Numerically Controlled
Oscillator (NCO)
Tuning - Middle Upper Byte
NCO_TUNE<23:16> 0x00
0x85 Numerically Controlled
Oscillator (NCO)
Tuning - Upper Byte
NCO_TUNE<31:24> 0x00
0x86 NCO Phase Offset in DDC
Mode - Lower Byte
NCO_PHASE<7:0> 0x00
0x87 NCO Phase Offset in DDC
Mode - Upper Byte
NCO_PHASE<15:8> 0x00
0x88 NCO Phase Offset in DDC
Mode - Lower Byte
NCO_PHASE<7:0> - Repeat of Address 0x86 0x00
TABLE 5-3: REGISTER MAP TABLE (CONTINUED)
Addr. Register Name
Bits Default
Value
b7 b6 b5 b4 b3 b2 b1 b0
Legend: U = Unimplemented bit, read as ‘0’ FCB = Factory-Controlled bits. Do not program 1 = bit is set 0 = bit is cleared x = bit is unknown
Note 1: Read-only register. Preprogrammed at the factory for internal use.
2015-2016 Microchip Technology Inc. DS20005396B-page 61
MCP37220-200 AND MCP37D20-200
0x89 NCO Phase Offset in DDC
Mode - Upper Byte
NCO_PHASE<15:8> - Repeat of Address 0x87 0x00
0x8A NCO Phase Offset in DDC
Mode - Lower Byte
NCO_PHASE<7:0> - Repeat of Address 0x86 0x00
0x8B NCO Phase Offset in DDC
Mode - Upper Byte
NCO_PHASE<15:8> - Repeat of Address 0x87 0x00
0x8C NCO Phase Offset in DDC
Mode - Lower Byte
NCO_PHASE<7:0> - Repeat of Address 0x86 0x00
0x8D NCO Phase Offset in DDC
Mode - Upper Byte
NCO_PHASE<15:8> - Repeat of Address 0x87 0x00
0x8E NCO Phase Offset in DDC
Mode - Lower Byte
NCO_PHASE<7:0> - Repeat of Address 0x86 0x00
0x8F NCO Phase Offset in DDC
Mode - Upper Byte
NCO_PHASE<15:8> - Repeat of Address 0x87 0x00
0x90 NCO Phase Offset in DDC
Mode - Lower Byte
NCO_PHASE<7:0> - Repeat of Address 0x86 0x00
0x91 NCO Phase Offset in DDC
Mode - Upper Byte
NCO_PHASE<15:8> - Repeat of Address 0x87 0x00
0x92 NCO Phase Offset in DDC
Mode - Lower Byte
NCO_PHASE<7:0> - Repeat of Address 0x86 0x00
0x93 NCO Phase Offset in DDC
Mode - Upper Byte
NCO_PHASE<15:8> - Repeat of Address 0x87 0x00
0x94 NCO Phase Offset in DDC
Mode - Lower Byte
NCO_PHASE<7:0> - Repeat of Address 0x86 0x00
0x95 NCO Phase Offset in DDC
Mode - Upper Byte
NCO_PHASE<15:8> - Repeat of Address 0x87 0x00
0x96 Digital Gain Control DIG_GAIN<7:0> 0x3C
0x97 DIG_GAIN<7:0> - Repeat of Address 0x96 0x3C
0x98 DIG_GAIN<7:0> - Repeat of Address 0x96 0x3C
0x99 DIG_GAIN<7:0> - Repeat of Address 0x96 0x3C
0x9A DIG_GAIN<7:0> - Repeat of Address 0x96 0x3C
0x9B DIG_GAIN<7:0> - Repeat of Address 0x96 0x3C
0x9C DIG_GAIN<7:0> - Repeat of Address 0x96 0x3C
0x9D DIG_GAIN<7:0> - Repeat of Address 0x96 0x3C
TABLE 5-3: REGISTER MAP TABLE (CONTINUED)
Addr. Register Name
Bits Default
Value
b7 b6 b5 b4 b3 b2 b1 b0
Legend: U = Unimplemented bit, read as ‘0’ FCB = Factory-Controlled bits. Do not program 1 = bit is set 0 = bit is cleared x = bit is unknown
Note 1: Read-only register. Preprogrammed at the factory for internal use.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 62 2015-2016 Microchip Technology Inc.
0xC0 Calibration Status
Indication (Read only)
ADC_CAL_STAT FCB<6:0> = 000-0000 ─
0xD1 PLL Calibration Status
and PLL Drift Status Indica-
tion (Read only)
FCB<4:3> = xx PLL_CAL_STAT FCB<2:1> = xx
PLL_VCOL_STAT
PLL_VCOH_STAT
FCB<0> = x─
0x15C CHIP ID - Lower Byte(1)
(Read only) CHIP_ID<7:0> ─
0x15D CHIP ID - Upper Byte(1)
(Read only)
CHIP_ID<15:8> ─
TABLE 5-3: REGISTER MAP TABLE (CONTINUED)
Addr. Register Name
Bits Default
Value
b7 b6 b5 b4 b3 b2 b1 b0
Legend: U = Unimplemented bit, read as ‘0’ FCB = Factory-Controlled bits. Do not program 1 = bit is set 0 = bit is cleared x = bit is unknown
Note 1: Read-only register. Preprogrammed at the factory for internal use.
2015-2016 Microchip Technology Inc. DS20005396B-page 63
MCP37220-200 AND MCP37D20-200
REGISTER 5-1: ADDRESS 0X00 – SPI BIT ORDERING AND ADC MODE SELECTION(1)
R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0
SHUTDOWN LSB_FIRST SOFT_RESET STANDBY STANDBY SOFT_RESET LSB_FIRST SHUTDOWN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SHUTDOWN: Shutdown mode setting for power saving(2)
1 = ADC in Shutdown mode
0 = Not in Shutdown mode (Default)
bit 6 LSB_FIRST: Select SPI communication bit order
1 = Start SPI communication with LSb first
0 = Start SPI communication with MSb first (Default)
bit 5 SOFT_RESET: Soft Reset control bit(3)
1 = Not in Soft Reset mode (Default)
0 = ADC in Soft Reset
bit 4 STANDBY: Send the device into a power-saving Standby mode(4)
1 = ADC in Standby mode
0 = Not in Standby mode (Default)
bit 3 STANDBY: Send the device into a power-saving Standby mode(4)
1 = ADC in Standby mode
0 = Not in Standby mode (Default)
bit 2 SOFT_RESET: Soft Reset control bit(3)
1 = Not in Soft Reset mode (Default)
0 = ADC in Soft Reset
bit 1 LSB_FIRST: Select SPI communication bit order
1 = Start SPI communication with LSb first
0 = Start SPI communication with MSb first (Default)
bit 0 SHUTDOWN: Shutdown mode setting for power-saving(2)
1 = ADC in Shutdown mode
0 = Not in Shutdown mode (Default)
Note 1: Upper and lower nibble are mirrored, which makes the MSb- or LSb-first mode interchangeable. The lower nibble
(bit <3:0>) has a higher priority when the mirrored bits have different values.
2: During Shutdown mode, most of the internal circuits, including the reference and clock, are turned-off, except for the
SPI interface. When exiting from Shutdown (changing from ‘1’ to ‘0’), executing the device Soft Reset simultaneously is
highly recommended for a fast recalibration of the ADC. The internal user registers are not affected.
3: This bit forces the device into Soft Reset mode, which initializes the internal calibration registers to their initial default
states. The user-registers are not affected. When exiting Soft Reset mode (changing from ‘0’ to ‘1’), the device per-
forms an automatic device calibration including PLL calibration if PLL is enabled. DLL is reset if enabled. During Soft
Reset, the device has the following states:
- no ADC output
- no change in power-on condition of internal reference
- most of the internal clocks are not distributed
- power consumption: (a) digital section - negligible, (b) analog section - no change.
4: During Standby mode, most of the internal circuits are turned off, except for the reference, clock and SPI interface.
When exiting from Standby mode (changing from ‘1’ to ‘0’) after an extended amount of time, executing Soft Reset
simultaneously is highly recommended. The internal user registers are not affected.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 64 2015-2016 Microchip Technology Inc.
REGISTER 5-2: ADDRESS 0X01 – INDEPENDENCY CONTROL OF OUTPUT DATA AND CLOCK DIVIDER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1
EN_DATCLK_IND FCB<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EN_DATCLK_IND: Enable data and clock divider independently(1)
1 = Enabled
0 = Disabled (Default)
bit 6-0 FCB<6:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
Note 1: EN_DATCLK_IND = 1 enables OUT_CLKRATE<3:0> settings in Address 0x02 (Register 5-3).
2015-2016 Microchip Technology Inc. DS20005396B-page 65
MCP37220-200 AND MCP37D20-200
REGISTER 5-3: ADDRESS 0X02 – OUTPUT DATA AND CLOCK RATE CONTROL(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OUT_DATARATE<3:0> OUT_CLKRATE<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 OUT_DATARATE<3:0>: Output data rate control bits
1111 = Output data is all 0’s
1110 = Output data is all 0’s
1101 = Output data is all 0’s
1100 = Internal test only(2)
1011 = Internal test only(2)
1010 = Internal test only(2)
1001 = Full speed divided by 512
1000 = Full speed divided by 256
0111 = Full speed divided by 128
0110 = Full speed divided by 64
0101 = Full speed divided by 32
0100 = Full speed divided by 16
0011 = Full speed divided by 8
0010 = Full speed divided by 4
0001 = Full speed divided by 2
0000 = Full speed rate (Default)
bit 3-0 OUT_CLKRATE<3:0>: Output clock rate control bits(3,4)
1111 = Full speed rate
1110 = No clock output
1101 = No clock output
1100 = No clock output
1011 = No clock output
1010 = No clock output
1001 = Full speed divided by 512
1000 = Full speed divided by 256
0111 = Full speed divided by 128
0110 = Full speed divided by 64
0101 = Full speed divided by 32
0100 = Full speed divided by 16
0011 = Full speed divided by 8
0010 = Full speed divided by 4
0001 = Full speed divided by 2
0000 = No clock output (Default)
Note 1: This register should be used when the decimation filter selection option (see Addresses 0x7B and 0x7C - Registers 5-
35 and 5-36) or digital down-conversion (DDC) option (see Address 0x80 - Register 5-37) is used.
2: 1100 - 1010: Do not reprogram. These settings are used for the internal test only. If these bits are reprogrammed
with different settings, the outputs will be in an undefined state.
3: Bits <3:0> become active if EN_DATCLK_IND = 1 in Address 0x01 (Register 5-2).
4: When no clock output is selected (Bits 1110 - 1010): clock output is not available at the DCLK+/DCLK- pins.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 66 2015-2016 Microchip Technology Inc.
REGISTER 5-4: ADDRESS 0X04 – SPI SDO OUTPUT TIMING CONTROL
R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
SDO_TIME FCB<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SDO_TIME: SPI SDO output timing control bit
1 = SDO output at the falling edge of clock (Default)
0 = SDO output at the rising edge of clock
bit 6-0 FCB<6:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
REGISTER 5-5: ADDRESS 0X07 – OUTPUT RANDOMIZER AND WCK POLARITY CONTROL
R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0
POL_WCK EN_AUTOCAL_TIMEDLY FCB<4:0> EN_OUT_RANDOM
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 POL_WCK: WCK polarity control bit in DDC mode(1)
1 = Inverted
0 = Not inverted (Default)
bit 6 EN_AUTOCAL_TIMEDLY: Auto-calibration starter time delay counter control bit(2)
1 = Enabled (Default)
0 = Disabled
bit 5-1 FCB<4:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 0 EN_OUT_RANDOM: Output randomizer control bit
1 = Enabled: ADC data output is randomized
0 = Disabled (Default)
Note 1: Applicable in the MCP37D20-200 only. See Address 0x68 (Register 5-26) for OVR/WCK pair control.
2: This bit enables the AUTOCAL_TIMEDLY<7:0> settings. See Address 0x1E (Register 5-6).
2015-2016 Microchip Technology Inc. DS20005396B-page 67
MCP37220-200 AND MCP37D20-200
REGISTER 5-6: ADDRESS 0X1E – AUTOCAL TIME DELAY CONTROL(1)
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AUTOCAL_TIMEDLY<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 AUTOCAL_TIMEDLY<7:0>: Auto-calibration start time delay control bits
1111-1111 = Maximum value
• • •
1000-0000 = (Default)
• • •
0000-0000 = Minimum value
Note 1: EN_AUTOCAL_TIMEDLY in Address 0x07 (Register 5-5) enables this register setting. This register controls the time delay
before the auto-calibration starts. The value increases linearly with the bit settings, from minimum to maximum values.
REGISTER 5-7: ADDRESS 0X52 – DLL CONTROL
R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0
EN_DUTY DCLK_PHDLY_DLL<2:0> EN_DLL_DCLK EN_DLL EN_CLK RESET_DLL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EN_DUTY: Enable DLL circuit for duty cycle correction (DCC) of input clock(1)
1 = Correction is ON
0 = Correction is OFF (Default)
bit 6-4 DCLK_PHDLY_DLL<2:0>: Select the phase delay of the digital clock output when using DLL(2)
111 = +315° phase-shifted from default
110 = +270° phase-shifted from default
• • •
010 = +90° phase-shifted from default
001 = +45° phase-shifted from default
000 = (Default)
bit 3 EN_DLL_DCLK: Enable DLL digital clock output
1 = Enabled (Default)
0 = Disabled: DLL digital clock is turned off. ADC output is not available when using DLL
bit 2 EN_DLL: Enable DLL circuitry to provide a selectable phase clock to digital output clock
1 = Enabled
0 = Disabled. DLL block is disabled (Default)
bit 1 EN_CLK: Enable clock input buffer
1 = Enabled (Default)
0 = Disabled. No clock is available to the internal circuits, ADC output is not available
bit 0 RESET_DLL: DLL circuit reset control(3)
1 = DLL is active
0 = DLL circuit is held in reset (Default)
Note 1: Enable the DLL circuitry for the duty cycle correction.
2: These bits have an effect only if EN_PHDLY = 1 and decimation is not used.
3: DLL reset control procedure: Set this bit to ‘0’ (reset) and then to ‘1’.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 68 2015-2016 Microchip Technology Inc.
REGISTER 5-8: ADDRESS 0X53 – CLOCK SOURCE SELECTION
R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
FCB<6:4> CLK_SOURCE FCB<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 FCB<6:4>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 4 CLK_SOURCE: Select internal timing source
1 = PLL output is selected as timing source
0 = External clock input is selected as timing source (Default)
bit 3-0 FCB<3:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
REGISTER 5-9: ADDRESS 0X54 – PLL REFERENCE DIVIDER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PLL_REFDIV<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PLL_REFDIV<7:0>: PLL Reference clock divider control bits(1)
1111-1111 = PLL reference divided by 255 (if PLL_REFDIV<9:8> = 00)
1111-1110 = PLL reference divided by 254 (if PLL_REFDIV<9:8> = 00)
• • •
0000-0011 = PLL reference divided by 3 (if PLL_REFDIV<9:8> = 00)
0000-0010 = Do not use (No effect)
0000-0001 = PLL reference divided by 1 (if PLL_REFDIV<9:8> = 00)
0000-0000 = PLL reference not divided (if PLL_REFDIV<9:8> = 00) (Default)
Note 1: PLL_REFDIV is a 10-bit-wide setting. See Address 0x55 (Register 5-10) for the upper two bits and Table 4-5 for
PLL_REFDIV<9:0> bit settings. This setting controls the clock division ratio of the PLL reference clock (external clock
input at the clock input pin) before the PLL phase-frequency detector circuitry. Note that the divider value of 2 is not
supported. EN_PLL_REFDIV in Address 0x59 (Register 5-14) must be set.
2015-2016 Microchip Technology Inc. DS20005396B-page 69
MCP37220-200 AND MCP37D20-200
REGISTER 5-10: ADDRESS 0X55 – PLL OUTPUT AND REFERENCE DIVIDER
R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
PLL_OUTDIV<3:0> FCB<1:0> PLL_REFDIV<9:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 PLL_OUTDIV<3:0>: PLL output divider control bits(1)
1111 = PLL output divided by 15
1110 = PLL output divided by 14
• • •
0100 = PLL output divided by 4 (Default)
0011 = PLL output divided by 3
0010 = PLL output divided by 2
0001 = PLL output divided by 1
0000 = PLL output not divided
bit 3-2 FCB<1:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 1-0 PLL_REFDIV<9:8>: Upper two MSb bits of PLL_REFDIV<9:0>(2)
00 = see Table 5-4. (Default)
Note 1: PLL_OUTDIV<3:0> controls the PLL output clock divider: VCO output is divided by the PLL_OUTDIV<3:0> setting.
2: See Address 0x54 (Register 5-9) and Table 5-4 for PLL_REFDIV<9:0> bit settings. EN_PLL_REFDIV in Address 0x59
(Register 5-14) must be set.
TABLE 5-4: Example – PLL Reference Divider Bit Settings Vs. PLL Reference Input Frequency
PLL_REFDIV<9:0> PLL Reference Frequency
11-1111-1111 Reference frequency divided by 1023
11-1111-1110 Reference frequency divided by 1022
——
00-0000-0011 Reference frequency divided by 3
00-0000-0010 Do not use (Not supported)
00-0000-0001 Reference frequency divided by 1
00-0000-0000 Reference frequency divided by 1
MCP37220-200 AND MCP37D20-200
DS20005396B-page 70 2015-2016 Microchip Technology Inc.
REGISTER 5-11: ADDRESS 0X56 – PLL PRESCALER (LSB)
R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0
PLL_PRE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PLL_PRE<7:0>: PLL prescaler selection(1)
1111-1111 = VCO clock divided by 255 (if PLL_PRE<11:8> = 0000)
• • •
0111-1000 = VCO clock divided by 120 (if PLL_PRE<11:8> = 0000) (Default)
• • •
0000-0010 = VCO clock divided by 2 (if PLL_PRE<11:8> = 0000)
0000-0001 = VCO clock divided by 1 (if PLL_PRE<11:8> = 0000)
0000-0000 = VCO clock not divided (if PLL_PRE<11:8> = 0000)
Note 1: PLL_PRE is a 12-bit-wide setting. The upper four bits (PLL_PRE<11:8>) are defined in Address 0x57. See Table 4-5 for
the PLL_PRE<11:0> bit settings. The PLL Prescaler is used to divide down the VCO output clock in the PLL
phase-frequency detector loop circuit.
REGISTER 5-12: ADDRESS 0X57 – PLL PRESCALER (MSB)
R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FCB<3:0> PLL_PRE<11:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 FCB<3:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 3-0 PLL_PRE<11:8>: PLL prescaler selection(1)
1111 = 212 - 1 (max), if PLL_PRE<7:0> = 0xFF
• • •
0000 = (Default)
Note 1: PLL_PRE is a 12-bit-wide setting. See the lower eight bit settings (PLL_PRE<7:0>) in Address 0x56 (Register 5-11).
See Table 5-5 for the PLL_PRE<11:0> bit settings for PLL feedback frequency.
TABLE 5-5: Example: PLL Prescaler Bit Settings and PLL Feedback Frequency
PLL_PRE<11:0> PLL Feedback Frequency
1111-1111-1111 VCO clock divided by 4095 (212 -1)
1111-1111-1110 VCO clock divided by 4094 (212 -2)
——
0000-0000-0011 VCO clock divided by 3
0000-0000-0010 VCO clock divided by 2
0000-0000-0001 VCO clock divided by 1
0000-0000-0000 VCO clock divided by 1
2015-2016 Microchip Technology Inc. DS20005396B-page 71
MCP37220-200 AND MCP37D20-200
REGISTER 5-13: ADDRESS 0X58 – PLL CHARGE PUMP
R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0
FCB<2:0>: PLL_BIAS PLL_CHAGPUMP<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 FCB<2:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 4 PLL_BIAS: PLL charge pump bias source selection bit
1 = Self-biasing coming from AVDD (Default)
0 = Bandgap voltage from the reference generator (1.2V)
bit 3-0 PLL_CHAGPUMP<3:0>: PLL charge-pump bias current control bits(1)
1111 = Maximum current
• • •
0010 = (Default)
• • •
0000 = Minimum current
Note 1: PLL_CHAGPUMP<3:0> bits should be set based on the phase detector comparison frequency. The bias current
amplitude increases linearly with increasing the bit setting values. The increase is from approximately 25 µA to 375 µA,
25 µA per step. See Section 4.5.2.1 “PLL Output Frequency and Output Control Parameters” for more details of
the PLL block.
REGISTER 5-14: ADDRESS 0X59 – PLL ENABLE CONTROL 1
U-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
—FCB<4:3> EN_PLL_REFDIV FCB<2:1> EN_PLL FCB<0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Not used.
bit 6-5 FCB<4:3>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 4 EN_PLL_REFDIV: Enable PLL Reference Divider (PLL_REFDIV<9:0>).
1 = Enable PLL_REFDIV<9:0> register
0 = Reference divider is bypassed (Default)
bit 3-2 FCB<2:1>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 1 EN_PLL: Master enable bit for PLL circuit.
1 = Enable PLL circuit
0 = Disable PLL circuit (Default)
bit 0 FCB<0>: Factory-Controlled bit. This is not for the user. Do not change default setting.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 72 2015-2016 Microchip Technology Inc.
REGISTER 5-15: ADDRESS 0X5A – PLL LOOP FILTER RESISTOR
U-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1
—FCB<1:0> PLL_RES<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Not used.
bit 6-5 FCB<1:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 4-0 PLL_RES<4:0>: Resistor value selection bits for PLL loop filter(1)
11111 = Maximum value
• • •
01111= (Default)
• • •
00000 = Minimum value
Note 1: PLL_RES<4:0> bits should be set based on the phase detector comparison frequency. The resistor value increases
linearly with the bit settings, from minimum to maximum values. See the PLL loop filter section in Section 4.5.2.1 “PLL
Output Frequency and Output Control Parameters”.
REGISTER 5-16: ADDRESS 0X5B – PLL LOOP FILTER CAP3
U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
—FCB<1:0> PLL_CAP3<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Not used.
bit 6-5 FCB<1:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 4-0 PLL_CAP3<4:0>: Capacitor 3 value selection bits for PLL loop filter(1)
11111 = Maximum value
• • •
00111= (Default)
• • •
00000 = Minimum value
Note 1: This capacitor is in series with the shunt resistor, which is set by PLL_RES<4:0> bits. The capacitor value increases
linearly with the bit settings, from minimum to maximum values. This setting should be set based on the phase detector
comparison frequency.
2015-2016 Microchip Technology Inc. DS20005396B-page 73
MCP37220-200 AND MCP37D20-200
REGISTER 5-17: ADDRESS 0X5C – PLL LOOP FILTER CAP1
U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
—FCB<1:0> PLL_CAP1<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Not used.
bit 6-5 FCB<1:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 4-0 PLL_CAP1<4:0>: Capacitor 1 value selection bits for PLL loop filter(1)
11111 = Maximum value
• • •
00111= (Default)
• • •
00000 = Minimum value
Note 1: This capacitor is located between the charge pump output and ground, and in parallel with the shunt resistor which is
defined by the PLL_RES<4:0>. The capacitor value increases linearly with the bit settings, from minimum to maximum
values. This setting should be set based on the phase detector comparison frequency.
REGISTER 5-18: ADDRESS 0X5D – PLL LOOP FILTER CAP2
U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
—FCB<1:0> PLL_CAP2<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Not used.
bit 6-5 FCB<1:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 4-0 PLL_CAP2<4:0>: Capacitor 2 value selection bits for PLL loop filter(1)
11111 = Maximum value
• • •
00111= (Default)
• • •
00000 = Minimum value
Note 1: This capacitor is located between the charge pump output and ground, and in parallel with CAP1 which is defined by
the PLL_CAP1<4:0>. The capacitor value increases linearly with the bit settings, from minimum to maximum values.
This setting should be set based on the phase detector comparison frequency.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 74 2015-2016 Microchip Technology Inc.
REGISTER 5-19: ADDRESS 0X5F – PLL ENABLE CONTROL 2(1)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1
FCB<5:2> EN_PLL_OUT EN_PLL_BIAS FCB<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 FCB<5:2>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 3 EN_PLL_OUT: Enable PLL output.
1 = Enabled
0 = Disabled (Default)
bit 2 EN_PLL_BIAS: Enable PLL bias
1 = Enabled
0 = Disabled (Default)
bit 1-0 FCB<1:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
Note 1: To enable PLL output, EN_PLL_OUT, EN_PLL_BIAS and EN_PLL in Address 0x59 (Register 5-14) must be set.
2015-2016 Microchip Technology Inc. DS20005396B-page 75
MCP37220-200 AND MCP37D20-200
REGISTER 5-20: ADDRESS 0X62 – OUTPUT DATA FORMAT AND OUTPUT TEST PATTERN
U-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
—FCB<0> DATA_FORMAT OUTPUT_MODE<1:0> TEST_PATTERNS<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Not used
bit 6 FCB<0>: Factory-Controlled bit. This is not for the user. Do not change default setting.
bit 5 DATA_FORMAT: Output data format selection
1 = Offset binary (unsigned)
0 = Two’s complement (Default)
bit 4-3 OUTPUT_MODE<1:0>: Output mode selection(1)
11 = Do not use. Output is undefined.
10 = DDR LVDS output mode with even bit first(2)(Default)
01 = CMOS output mode
00 = Output disabled
bit 2-0 TEST_PATTERNS<2:0>: Test output data pattern selection(3)
111 = Output data is pseudo-random number (PN) sequence(4)
110 = Sync Pattern for LVDS output: '11111111 000000'
101 = Alternating Sequence for LVDS mode: ‘01010101 101010’
100 = Alternating Sequence for CMOS mode: ‘11111111 111111’ alternating with ‘00000000 000000’
011 = Alternating Sequence for CMOS mode: ‘01010101 010101’ alternating with ‘10101010 101010’
010 = Ramp Pattern. Output (Q0) is incremented by 1 LSb per 16 clock cycles
001 = Double Custom Patterns.
Output: Alternating custom pattern A (see Addresses 0X74 – 0X75 - Registers 5-29 – 5-30) and custom
pattern B (see Address 0X76 - 0X77 - Registers 5-31 – 5-32)(5)
000 = Normal Operation. Output: ADC data (Default)
Note 1: See Figures 2-1 – 2-2 for the timing diagram.
2: Rising edge: Q12, Q10...Q0.
Falling edge: Q13, Q11...Q1.
3: See Section 4.9.12 “Output Test Patterns” for more details.
(a) In LVDS mode: only the active pins (per register settings) are active. Inactive output pins are in High Z state.
(b) In CMOS mode: all data output pins (Q13-Q0), output test pins (TP, TP1, TP2), OVR and WCK pins are active, even
if they are disabled by register settings. Since the output test pins (TP, TP1, TP2) can toggle during this test, the output
test pins can draw extra current if they are connected to the supply pin or ground. To avoid the extra current draws,
always leave the test pins floating (not connected).
4: Pseudo-random number (PN) code is generated by the linear feedback shift register (LFSR).
See Section 4.9.12.1 “Pseudo-Random Number (PN) Sequence Output” for more details.
5: Pattern A<13:0> and B<13:0> are applied to Q<13:0>. Q13 = OVR, Q12 = WCK.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 76 2015-2016 Microchip Technology Inc.
REGISTER 5-21: ADDRESS 0X63 – LVDS OUTPUT LOAD AND DRIVER CURRENT CONTROL
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
FCB<3:0> LVDS_LOAD LVDS_IMODE<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 FCB<3:0>: Factory-controlled bits. This is not for the user. Do not change default settings.
bit 3 LVDS_LOAD: Enable internal LVDS load termination
1 = Enabled
0 = Disabled (Default)
bit 2-0 LVDS_IMODE<2:0>: LVDS driver current control bits
111 = 7.2 mA
011 = 5.4 mA
001 = 3.5 mA (Default)
000 = 1.8 mA
Do not use the following settings(1):
110, 101, 100, 010
Note 1: These settings can result in unknown outputs currents.
REGISTER 5-22: ADDRESS 0X64 – OUTPUT CLOCK PHASE CONTROL WHEN DECIMATION FILTER IS
USED
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
EN_PHDLY DCLK_PHDLY_DEC<2:0> FCB<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EN_PHDLY: Enable digital output clock phase delay control when DLL or decimation filter is used.
1 = Enabled
0 = Disabled (Default)
bit 6-4 DCLK_PHDLY_DEC<2:0>: Digital output clock phase delay control when decimation filter is used(1)
111 = +315° phase-shifted from default(2)
110 = +270° phase-shifted from default
101 = +225° phase-shifted from default(2)
100 = +180° phase-shifted from default
011 = +135° phase-shifted from default(2)
010 = +90° phase-shifted from default
001 = +45° phase-shifted from default(2)
000 = Default(3)
bit 3-0 FCB<3:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
Note 1: These bits have an effect only if EN_PHDLY = 1. See Address 0x52 (Register 5-7) for the same feature when DLL is used.
2: Only available when the decimation filter setting is greater than 2. When FIR_A/B <8:1> = 0’s (default) and FIR_A<6> = 0,
only 4-phase shifts are available (+45°, +135°, +225°, +315°) from default. See Addresses 0x7A, 0x7B and 0x7C
(Registers 5-34 – 5-36). See address 0x6D and 0x52 for DCLK (Registers 5-28 and 5-7) phase shift for other modes.
3: The phase delay for all other settings is referenced to this default phase.
2015-2016 Microchip Technology Inc. DS20005396B-page 77
MCP37220-200 AND MCP37D20-200
REGISTER 5-23: ADDRESS 0X65 – LVDS OUTPUT POLARITY CONTROL
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
POL_LVDS<6:0> NO-EFFECT<0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 POL_LVDS<6:0>: Control polarity of LVDS data pairs
111-1111 = Invert all LVDS pairs
111-1110 = Invert all LVDS pairs except the LSb pair
• • •
100-0000 = Invert MSb LVDS pair
• • •
000-0001 = Invert LSb LVDS pair
000-0000 = No inversion of LVDS bit pairs (Default)
bit 6-0 NO EFFECT<0>: No effect bit.
REGISTER 5-24: ADDRESS 0X66 – DIGITAL OFFSET CORRECTION (LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIG_OFFSET <7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DIG_OFFSET <7:0>: Lower byte of DIG_OFFSET<15:0>(1)
0000-0000 = Default
Note 1: Offset is added to the ADC output. Setting is two’s complement using two combined registers (16 bits wide).
- 0 LSb if DIG_OFFSET<15:0> = 0x0000
- Step size: 0.25 LSb per each bit setting
- Setting Range: (-215 to 215 - 1) × 0.25 LSb or (-32768 to +32767) × 0.25 LSb
REGISTER 5-25: ADDRESS 0X67 – DIGITAL OFFSET CORRECTION (UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DIG_OFFSET<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DIG_OFFSET <15:8>: Upper byte of DIG_OFFSET<15:0>(1)
0000-0000 = Default
Note 1: See Note 1 in Address 0x66 (Register 5-24).
MCP37220-200 AND MCP37D20-200
DS20005396B-page 78 2015-2016 Microchip Technology Inc.
REGISTER 5-26: ADDRESS 0X68 – OVR AND WCK BIT CONTROL
R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0
FCB<5:2> POL_OVR_WCK EN_OVR_WCK FCB<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 FCB<5:2>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 3 POL_OVR_WCK: Polarity control for OVR and WCK bit pair in LVDS mode
1 = Inverted
0 = Not inverted (Default)
bit 2 EN_OVR_WCK: Enable OVR and WCK output bit pair
1 = Enabled (Default)
0 = Disabled
bit 1-0 FCB<1:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
REGISTER 5-27: ADDRESS 0X6B – PLL CALIBRATION
R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
FCB<6:2> PLL_CAL_TRIG FCB<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-3 FCB<6:2>: Factory-Controlled bits. This is not for the user. Do not change default settings.
bit 2 PLL_CAL_TRIG: Manually force recalibration of the PLL at the state of bit transition(1)
Toggle from ‘1’ to ‘0’, or ‘0’ to ‘1’ = Start PLL calibration
bit 1-0 FCB<1:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
Note 1: See PLL_CAL_STAT in Address 0xD1 (Register 5-68) for calibration status indication.
2015-2016 Microchip Technology Inc. DS20005396B-page 79
MCP37220-200 AND MCP37D20-200
REGISTER 5-28: ADDRESS 0X6D – PLL OUTPUT AND OUTPUT CLOCK PHASE(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
─EN_PLL_CLK FCB<1> DCLK_DLY_PLL<2:0> FCB<0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Not used
bit 5 EN_PLL_CLK: Enable PLL output clock
1 = PLL output clock is enabled to the ADC core
0 = PLL clock output is disabled (Default)
bit 4 FCB<1>: Factory-Controlled bit. This is not for the user. Do not change default setting.
bit 3-1 DCLK_DLY_PLL<2:0>: Output clock is delayed by the number of VCO clock cycles from the nominal PLL output(2)
111 = Delay of 15 cycles
110 = Delay of 14 cycles
• • •
001 = Delay of one cycle
000 = No delay (Default)
bit 0 FCB<0>: Factory-Controlled bit. This is not for the user. Do not change default setting.
Note 1: This register has effect only when the PLL clock is selected by CLK_SOURCE bit in Address 0x53 (Register 5-8) and
PLL circuit is enabled by EN_PLL bit in Address 0x59 (Register 5-14).
2: This bit setting enables the output clock phase delay. This phase delay control option is applicable when PLL is used as
the clock source and the decimation is not used.
REGISTER 5-29: ADDRESS 0X74 – USER-DEFINED OUTPUT PATTERN A (LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PATTERN_A<5:0> Do not use (leave as ‘00’)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 PATTERN_A<5:0>: Lower bit portion of PATTERN_A<13:0>(1)
bit 1-0 Do not use: Leave these bits to default settings (‘00’)(2)
Note 1: See PATTERN_A<13:6> in Address 0x75 (Register 5-30) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20).
2: The output from these bit settings is on “Unused Output Pattern Test Pins”, which are recommended to not be
connected to the host device. Therefore, the effect of these bit settings is not monitored. Leave these bits as default
settings (‘00’) all the time.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 80 2015-2016 Microchip Technology Inc.
REGISTER 5-30: ADDRESS 0X75 – USER-DEFINED OUTPUT PATTERN A (UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PATTERN_A<13:6>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PATTERN_A<13:6>: Upper byte of PATTERN_A<15:0>(1)
Note 1: See PATTERN_A<5:0> in Address 0x74 (Register 5-29) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20).
REGISTER 5-31: ADDRESS 0X76 – USER-DEFINED OUTPUT PATTERN B (LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PATTERN_B<5:0> Do not use (Leave as ‘00’)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 PATTERN_B<5:0>: Lower bit portion of PATTERN_B<13:0>(1)
bit 1-0 Do not use: Leave these bits to default settings (‘00’)
Note 1: See PATTERN_B<13:6> in Address 0x77 (Register 5-32) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20).
2: The output from these bit settings is on “Unused Output Pattern Test Pins”, which are recommended to not be
connected to the host device. Therefore, the effect of these bit settings is not monitored. Leave these bits as default
settings (‘00’) all the time.
REGISTER 5-32: ADDRESS 0X77 – USER-DEFINED OUTPUT PATTERN B (UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PATTERN_B<13:6>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PATTERN_B<13:6>: Upper byte of PATTERN_B<13:0>(1)
Note 1: See PATTERN_B<5:0> in Address 0x76 (Register 5-31) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20).
2015-2016 Microchip Technology Inc. DS20005396B-page 81
MCP37220-200 AND MCP37D20-200
REGISTER 5-33: ADDRESS 0X79 – I/Q CHANNEL DIGITAL SIGNAL POST-PROCESSING CONTROL
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EN_DSPP_I/Q FCB<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EN_DSPP_I/Q: Enable all digital signal post-processing functions for I/Q-channel operation.
1 = Enabled
0 = Disabled (Default)
bit 6-0 FCB<6:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
REGISTER 5-34: ADDRESS 0X7A – FIR_A0 BIT CONTROL
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FCB<6> FIR_A<0> FCB<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 FCB<6>: Factory-Controlled bit. This is not for the user. Do not change default setting.
bit 6 FIR_A<0>: Enable the first 2x decimation (Stage 1A in FIR A)(1)
1 = Enabled
0 = Disabled (Default)
bit 5-0 FCB<5:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
Note 1: Set FIR_A<0> = 0 for I and Q channels in DDC mode (MCP37D20-200). See Address 0x7B (Register 5-35) for
FIR_A<8:1>.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 82 2015-2016 Microchip Technology Inc.
REGISTER 5-35: ADDRESS 0X7B – FIR A FILTER(1,4)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FIR_A<8:1>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 FIR_A<8:1>: Decimation Filter FIR A settings(2)
Normal Decimation Operation:
FIR_A<8:0> =
1-1111-1111 = Enabled stage 1 - 9 filters (decimation rate: 512)
0-1111-1111 = Enabled stage 1 - 8 filters
0-0111-1111 = Enabled stage 1 - 7 filters
0-0011-1111 = Enabled stage 1 - 6 filters
0-0001-1111 = Enabled stage 1 - 5 filters
0-0000-1111 = Enabled stage 1 - 4 filters
0-0000-0111 = Enabled stage 1 - 3 filters (decimation rate = 8)
0-0000-0011 = Enabled stage 1 - 2 filters (decimation rate = 4)
0-0000-0001 = Enabled stage 1 filter (decimation rate = 2)
0-0000-0000 = Disabled all FIR A filters. (Default)
In-Phase (I) Data Channel in DDC Mode (MCP37D20-200):(3)
FIR_A<8:0> =
1-1111-1100 = Enabled stage 3 - 9 filters (decimation rate: 128)
0-1111-1100 = Enabled stage 3 - 8 filters
0-0111-1100 = Enabled stage 3 - 7 filters
0-0011-1100 = Enabled stage 3 - 6 filters
0-0001-1100 = Enabled stage 3 - 5 filters
0-0000-1100 = Enabled stage 3 - 4 filters
0-0000-0100 = Enabled stage 3 filter (decimation rate = 2)
0-0000-0000 = Disabled all FIR A filters. (Default)
Note 1: The register values are thermometer encoded.
2: FIR_A<0> is placed in Address 0x7A (Register 5-34).
3: In I and Q channel operation, it starts with the 3rd stage filter.
4: SNR is improved by approximately 2.5 dB per each filter stage, but output data rate is reduced by a factor of 2 per
stage. The data and clock rates in Address 0X02 (Register 5-3) need to be updated accordingly when this register is
updated. Address 0x64 (Register 5-22) setting is also affected. The maximum decimation factor is 512, and 128 for the
I and Q channel operation in DDC mode (MCP37D20).
2015-2016 Microchip Technology Inc. DS20005396B-page 83
MCP37220-200 AND MCP37D20-200
REGISTER 5-36: ADDRESS 0X7C – FIR B FILTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FIR_B<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 FIR_B<7:0>:Decimation Filter FIR B settings for Quadrature (Q) data channel
1111-1111 = Enabled stage 3 - 9 filters (decimation rate: 128)
0111-1111 = Enabled stage 3 - 8 filters
0011-1111 = Enabled stage 3 - 7 filters
0001-1111 = Enabled stage 3 - 6 filters
0000-1111 = Enabled stage 3 - 5 filters
0000-0111 = Enabled stage 3 - 4 filters
0000-0011 = Enabled stage 3 filter (decimation rate = 2)
0000-0001 = No effect
0000-0000 = Disabled all FIR B filters. (Default)
Note 1: This register is used only for Q data channel in DDC mode (MCP37D20-200). The register values are thermometer encoded.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 84 2015-2016 Microchip Technology Inc.
REGISTER 5-37: ADDRESS 0X80 – DIGITAL DOWN-CONVERTER CONTROL 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FCB<0> HBFILTER_A EN_NCO EN_AMPDITH EN_PHSDITH EN_LFSR EN_DDC_FS/8 EN_DDC1
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 FCB<0>: Factory-Controlled bit. This is not for the user. Do not change default setting.
bit 6 HBFILTER_A: Select half-bandwidth filter at DDC output of channel A(1)
1 = Select High-Pass filter at DDC output
0 = Select Low-Pass filter at DDC output (Default)
bit 5 EN_NCO: Enable NCO of DDC1
1 = Enabled
0 = Disabled (Default)
bit 4 EN_AMPDITH: Enable amplitude dithering for NCO(2, 3)
1 = Enabled
0 = Disabled (Default)
bit 3 EN_PHSDITH: Enable phase dithering for NCO(2, 3)
1 = Enabled
0 = Disabled (Default)
bit 2 EN_LFSR: Enable linear feedback shift register (LFSR) for amplitude and phase dithering for NCO
1 = Enabled
0 = Disabled (Default)
bit 1 EN_DDC_FS/8: Enable NCO for the DDC2 to center the DDC output signal to be around fS/8/DER(4)
1 = Enabled
0 = Disabled (Default)
bit 0 EN_DDC1: Enable digital down converter 1 (DDC1)
1 = Enabled(5)
0 = Disabled (Default)
Note 1: This filter includes a decimation of 2.
2: This requires the LFSR to be enabled: <EN_LFSR> = 1
3: EN_AMPDITH = 1 and EN_PHSDITH = 1 are recommended for the best performance.
4: DER is the decimation rate defined by FIR A or FIR B filter. If up-converter is not enabled (disabled), output is I/Q data.
5: DDC and NCO are enabled. For DDC function, bits 0, 2 and 5 need to be enabled all together.
2015-2016 Microchip Technology Inc. DS20005396B-page 85
MCP37220-200 AND MCP37D20-200
REGISTER 5-38: ADDRESS 0X81 – DIGITAL DOWN-CONVERTER CONTROL 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FCB<5> EN_DDC2 GAIN_HBF_DDC FCB<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 FCB<5>: Factory-Controlled bit. This is not for the user. Do not change default setting.
bit 6 EN_DDC2: Enable DDC2 after the digital half-band filter (HBF) in DDC
1 = Enabled
0 = Disabled (Default)
bit 5 GAIN_HBF_DDC: Gain select for the output of the digital half-band filter (HBF) in DDC
1 =x2
0 =x1 (Default)
bit 4-0 FCB<4:0>: Factory-Controlled bits. This is not for the user. Do not change default settings.
REGISTER 5-39: ADDRESS 0X82 – NUMERICALLY CONTROLLED OSCILLATOR (NCO) TUNING
(LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_TUNE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_TUNE <7:0>: Lower byte of NCO_TUNE<31:0>(1)
0000-0000 = DC (0 Hz) when NCO_TUNE<31:0> = 0x00000000 (Default)
Note 1: See Note 1 and Note 2 in Address 0x85 (Register 5-42).
REGISTER 5-40: ADDRESS 0X83 – NUMERICALLY CONTROLLED OSCILLATOR (NCO) TUNING
(MIDDLE LOWER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_TUNE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_TUNE<15:8>: Middle lower byte of NCO_TUNE<31:0>(1)
0000-0000 = Default
Note 1: See Note 1 and Note 2 in Address 0x85 (Register 5-42).
MCP37220-200 AND MCP37D20-200
DS20005396B-page 86 2015-2016 Microchip Technology Inc.
REGISTER 5-41: ADDRESS 0X84 – NUMERICALLY CONTROLLED OSCILLATOR (NCO) TUNING
(MIDDLE UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_TUNE<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_TUNE<23:16>: Middle-upper byte of NCO_TUNE<31:0>(1)
0000-0000 = Default
Note 1: See Note 1 and Note 2 in Address 0x85 (Register 5-42).
REGISTER 5-42: ADDRESS 0X85 – NUMERICALLY CONTROLLED OSCILLATOR (NCO) TUNING
(UPPER BYTE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_TUNE<31:24>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_TUNE<31:24>: Upper byte of NCO_TUNE<31:0>(2)
1111-1111 = fS if NCO_TUNE<31:0> = 0xFFFF FFFF
• • •
0000-0000 = Default
Note 1: This Register is used only when DDC is enabled: EN_DDC1 = 1 in Address 0x80 (Register 5-37). See Section 4.6.2.1
“Numerically Controlled Oscillator (NCO)” for the details of NCO.
2: NCO frequency = (NCO_TUNE<31:0>/232) × fS, where fS is the ADC core sampling frequency.
2015-2016 Microchip Technology Inc. DS20005396B-page 87
MCP37220-200 AND MCP37D20-200
REGISTER 5-43: ADDRESS 0X86 – NCO PHASE OFFSET IN DDC MODE (LOWER BYTE)(1,3)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<7:0>: Lower byte of NCO_PHASE<15:0>(2)
1111-1111 = 1.4° when NCO_PHASE<15:0> = 0x00FF
•
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: This register has effect only when DDC mode is used in MCP37D20-200.
2: NCO_PHASE_OFFSET<15:0> = 216 × Phase Offset Value/360.
3: When this register is used, the same setting must be repeated in Addresses 0x88, 0x8A, 0x8C, 0x8E, 0x90, 0x92 and 0x94.
REGISTER 5-44: ADDRESS 0X87 – NCO PHASE OFFSET IN DDC MODE (UPPER BYTE)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<15:8>: Upper byte of NCO_PHASE<15:0>(2)
1111-1111 = 359.995° when NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 and Note 2 in Register 5-43.
2: When this register is used, the same setting must be repeated in Addresses 0x89, 0x8B, 0x8D, 0x8F, 0x91, 0x93 and 0x95.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 88 2015-2016 Microchip Technology Inc.
REGISTER 5-45: ADDRESS 0X88 – NCO PHASE OFFSET (REPEAT) IN DDC MODE (LOWER BYTE)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<7:0>: Lower byte of NCO_PHASE<15:0>(1)
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 in Register 5-43. Keep this register setting the same as in Address 0x86.
REGISTER 5-46: ADDRESS 0X89 – NCO PHASE OFFSET (REPEAT) IN DDC MODE (UPPER BYTE)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<15:8>: Upper byte of NCO_PHASE<15:0>(1)
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 in Register 5-43. Keep this register setting the same as in Address 0x87.
REGISTER 5-47: ADDRESS 0X8A – NCO PHASE OFFSET (REPEAT) IN DDC MODE (LOWER BYTE)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<7:0>: Lower byte of NCO_PHASE<15:0>(1)
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 in Register 5-43. Keep this register setting the same as in Address 0x86.
2015-2016 Microchip Technology Inc. DS20005396B-page 89
MCP37220-200 AND MCP37D20-200
REGISTER 5-48: ADDRESS 0X8B – NCO PHASE OFFSET (REPEAT) IN DDC MODE (UPPER BYTE)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<15:8>: Upper byte of NCO_PHASE<15:0>(1)
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 in Register 5-43. Keep this register setting the same as in Address 0x87.
REGISTER 5-49: ADDRESS 0X8C – NCO PHASE OFFSET (REPEAT) IN DDC MODE (LOWER BYTE)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<7:0>: Lower byte of NCO_PHASE<15:0>(1)
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 in Register 5-43. Keep this register setting the same as in Address 0x86.
REGISTER 5-50: ADDRESS 0X8D – NCO PHASE OFFSET (REPEAT) IN DDC MODE (UPPER BYTE)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<15:8>: Upper byte of NCO_PHASE<15:0>(1)
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 in Register 5-43. Keep this register setting the same as in Address 0x87.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 90 2015-2016 Microchip Technology Inc.
REGISTER 5-51: ADDRESS 0X8E – NCO PHASE OFFSET (REPEAT) IN DDC MODE (LOWER BYTE)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<7:0>: Lower byte of NCO_PHASE<15:0>(1)
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 in Register 5-43. Keep this register setting the same as in Address 0x86.
REGISTER 5-52: ADDRESS 0X8F – NCO PHASE OFFSET (REPEAT) IN DDC MODE (UPPER BYTE)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<15:8>: Upper byte of NCO_PHASE<15:0>(1)
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 in Register 5-43. Keep this register setting the same as in Address 0x87.
REGISTER 5-53: ADDRESS 0X90 – NCO PHASE OFFSET (REPEAT) IN DDC MODE (LOWER BYTE)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<7:0>: Lower byte of NCO_PHASE<15:0>(1)
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 in Register 5-43. Keep this register setting the same as in Address 0x86.
2015-2016 Microchip Technology Inc. DS20005396B-page 91
MCP37220-200 AND MCP37D20-200
REGISTER 5-54: ADDRESS 0X91 – NCO PHASE OFFSET (REPEAT) IN DDC MODE (UPPER BYTE)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<15:8>: Upper byte of NCO_PHASE<15:0>(1)
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 in Register 5-43. Keep this register setting the same as in Address 0x87.
REGISTER 5-55: ADDRESS 0X92 – NCO PHASE OFFSET (REPEAT) IN DDC MODE (LOWER BYTE)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<7:0>: Lower byte of NCO_PHASE<15:0>(1)
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 in Register 5-43. Keep this register setting the same as in Address 0x86.
REGISTER 5-56: ADDRESS 0X93 – NCO PHASE OFFSET (REPEAT) IN DDC MODE (UPPER BYTE)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<15:8>: Upper byte of NCO_PHASE<15:0>(1)
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 in Register 5-43. Keep this register setting the same as in Address 0x87.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 92 2015-2016 Microchip Technology Inc.
REGISTER 5-57: ADDRESS 0X94 – NCO PHASE OFFSET (REPEAT) IN DDC MODE (LOWER BYTE)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<7:0>: Lower byte of NCO_PHASE<15:0>(1)
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 in Register 5-43. Keep this register setting the same as in Address 0x86.
REGISTER 5-58: ADDRESS 0X95 – NCO PHASE OFFSET (REPEAT) IN DDC MODE (UPPER BYTE)(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NCO_PHASE<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 NCO_PHASE<15:8>: Upper byte of NCO_PHASE<15:0>(1)
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 in Register 5-43. Keep this register setting the same as in Address 0x87.
2015-2016 Microchip Technology Inc. DS20005396B-page 93
MCP37220-200 AND MCP37D20-200
REGISTER 5-59: ADDRESS 0X96 – DIGITAL GAIN CONTROL(1,2)
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DIG_GAIN<7:0>: Digital gain setting(3)
1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
• • •
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
• • •
0011-1100 = 1.875 (Default)
0011-1011 = 1.84375
0011-1010 =1.8125
0011-1001 =1.78125
0011-1000 =1.75 (Optimum)(3)
• • •
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
Note 1: When this setting is updated, the same setting must be repeated in Addresses 0x97 - 0x9D.
2: Max = 0x7F (3.96875), Min = 0x80 (-4), Step size = 0x01 (0.03125). Bit range from 0x81 - 0xFF is two’s complementary of
0x00 - 0x80. Negative gain setting inverts output.
3: This setting improves SNR by 0.7 dB from the default setting. This setting is recommended for optimum SNR performance.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 94 2015-2016 Microchip Technology Inc.
REGISTER 5-60: ADDRESS 0X97 – DIGITAL GAIN CONTROL (REPEAT)(1)
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DIG_GAIN<7:0>: Digital gain setting(1)
0011-1100 = 1.875 (Default)
Note 1: Keep this register setting the same as in Address 0x96. See Notes 1-3 in Register 5-59
REGISTER 5-61: ADDRESS 0X98 – DIGITAL GAIN CONTROL (REPEAT)(1)
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DIG_GAIN<7:0>: Digital gain setting(1)
0011-1100 = 1.875 (Default)
Note 1: Keep this register setting the same as in Address 0x96. See Notes 1-3 in Register 5-59
REGISTER 5-62: ADDRESS 0X99 – DIGITAL GAIN CONTROL (REPEAT)(1)
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DIG_GAIN<7:0>: Digital gain setting(1)
0011-1100 = 1.875 (Default)
Note 1: Keep this register setting the same as in Address 0x96. See Notes 1-3 in Register 5-59
REGISTER 5-63: ADDRESS 0X9A – DIGITAL GAIN CONTROL (REPEAT)(1)
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DIG_GAIN<7:0>: Digital gain setting(1)
0011-1100 = 1.875 (Default)
Note 1: Keep this register setting the same as in Address 0x96. See Notes 1-3 in Register 5-59
2015-2016 Microchip Technology Inc. DS20005396B-page 95
MCP37220-200 AND MCP37D20-200
REGISTER 5-64: ADDRESS 0X9B – DIGITAL GAIN CONTROL (REPEAT)(1)
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DIG_GAIN<7:0>: Digital gain setting(1)
0011-1100 = 1.875 (Default)
Note 1: Keep this register setting the same as in Address 0x96. See Notes 1-3 in Register 5-59
REGISTER 5-65: ADDRESS 0X9C – DIGITAL GAIN CONTROL (REPEAT)(1)
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DIG_GAIN<7:0>: Digital gain setting(1)
0011-1100 = 1.875 (Default)
Note 1: Keep this register setting the same as in Address 0x96. See Notes 1-3 in Register 5-59
REGISTER 5-66: ADDRESS 0X9D – DIGITAL GAIN CONTROL (REPEAT)(1)
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
DIG_GAIN<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DIG_GAIN<7:0>: Digital gain setting(1)
0011-1100 = 1.875 (Default)
Note 1: Keep this register setting the same as in Address 0x96. See Notes 1-3 in Register 5-59
MCP37220-200 AND MCP37D20-200
DS20005396B-page 96 2015-2016 Microchip Technology Inc.
REGISTER 5-67: ADDRESS 0XC0 – CALIBRATION STATUS INDICATION
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
ADC_CAL_STAT FCB<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ADC_CAL_STAT: Power-Up auto-calibration status indication flag bit
1 = Device power-up calibration is completed
0 = Device power-up calibration is not completed
bit 6-0 FCB<6:0>: Factory-Controlled bits. These bits are read only and have no meaning for the user.
REGISTER 5-68: ADDRESS 0XD1 – PLL CALIBRATION STATUS AND PLL DRIFT STATUS INDICATION
R-x R-x R-x R-x R-x R-x R-x R-x
FCB<4:3> PLL_CAL_STAT FCB<2:1> PLL_VCOL_STAT PLL_VCOH_STAT FCB<0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 FCB<4:3>: Factory-Controlled bits. These bits are read only and have no meaning for the user.
bit 5 PLL_CAL_STAT: PLL auto-calibration status indication flag bit(1)
1 = Complete: PLL auto-calibration is completed
0 = Incomplete: PLL auto-calibration is not completed
bit 4-3 FCB<2:1>: Factory-Controlled bits. These bits are read only and have no meaning for the user.
bit 2 PLL_VCOL_STAT: PLL drift status indication bit
1 = PLL drifts out of lock with low VCO frequency
0 = PLL operates as normal
bit 1 PLL_VCOH_STAT: PLL drift status indication bit
1 = PLL drifts out of lock with high VCO frequency
0 = PLL operates as normal
bit 0 FCB<0>: Factory-Controlled bit. This bit is read only and have no meaning for the user.
Note 1: See PLL_CAL_TRIG bit setting in Address 0x6B (Register 5-27).
2015-2016 Microchip Technology Inc. DS20005396B-page 97
MCP37220-200 AND MCP37D20-200
REGISTER 5-69: ADDRESS 0X15C – CHIP ID (LOWER BYTE)(1)
R-x R-x R-x R-x R-x R-x R-x R-x
CHIP_ID<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CHIP_ID<7:0>: Chip ID of the device: Lower byte of the CHIP ID<15:0>
Note 1: Read-only register. Preprogrammed at the factory for internal use.
Example: MCP37220-200: '0001000001010000’
MCP37D20-200: '0001001001010000’
REGISTER 5-70: ADDRESS 0X15D – CHIP ID (UPPER BYTE)(1)
R-x R-x R-x R-x R-x R-x R-x R-x
CHIP_ID<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CHIP_ID<15:8>: Chip ID of the device: Upper byte of the CHIP_ID<15:0>
Note 1: Read-only register. Preprogrammed at the factory for internal use.
Example: MCP37220-200: '0001000001010000’
MCP37D20-200: '0001001001010000’
MCP37220-200 AND MCP37D20-200
DS20005396B-page 98 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS20005396B-page 99
MCP37220-200 AND MCP37D20-200
6.0 DEVELOPMENT SUPPORT
Microchip offers a high-speed ADC evaluation platform
which can be used to evaluate Microchip’s high-speed
ADC products. The platform consists of an MCP37XXX-
200 evaluation board, an FPGA-based data capture
card board and PC-based Graphical User Interface
(GUI) software for ADC configuration and evaluation.
Figure 6-1 and Figure 6-2 show this evaluation tool.
This evaluation platform allows users to quickly
evaluate the ADC’s performance for their specific
application requirements. More information is available
at http://www.microchip.com.
FIGURE 6-1: MCP37XX0 Evaluation Kit.
FIGURE 6-2: PC-Based Graphical User Interface Software.
(b) Data Capture Board(a) MCP37XX0-200 Evaluation Board
MCP37220-200 AND MCP37D20-200
DS20005396B-page 100 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS20005396B-page 101
MCP37220-200 AND MCP37D20-200
7.0 TERMINOLOGY
Analog Input Bandwidth (Full-Power
Bandwidth)
The analog input frequency at which the spectral power
of the fundamental frequency (as determined by FFT
analysis) is reduced by 3 dB.
Aperture Delay or Sampling Delay
The time delay between the rising edge of the input
sampling clock and the actual time at which the
sampling occurs.
Aperture Uncertainty
The sample-to-sample variation in aperture delay.
Aperture Delay Jitter
The variation in the aperture delay time from
conversion to conversion. This random variation will
result in noise when sampling an AC input. The
signal-to-noise ratio due to the jitter alone will be:
EQUATION 7-1:
Calibration Algorithms
This device utilizes two patented analog and digital
calibration algorithms, Harmonic Distortion Correction
(HDC) and DAC Noise Cancellation (DNC), to improve
the ADC performance. The algorithms compensate
various sources of linear impairments such as
capacitance mismatch, charge injection error and finite
gain of operational amplifiers. These algorithms
execute in both power-up sequence (foreground) and
background mode:
• Power-Up Calibration: The calibration is
conducted within the first 3x226 clock cycles after
power-up. The user needs to wait this Power-Up
Calibration period after the device is powered-up
for an accurate ADC performance.
• Background Calibration: This calibration is
conducted in background while the ADC is
performing conversions. The update rate is about
once every 230 clock cycles.
Pipeline Delay (LATENCY)
LATENCY is the number of clock cycles between the
initiation of conversion and when that data is presented
to the output driver stage. Data for any given sample is
available after the pipeline delay plus the output delay
after that sample is taken. New data is available at
every clock cycle, but the data lags the conversion by
the pipeline delay plus the output delay.
Clock Pulse Width and Duty Cycle
The clock duty cycle is the ratio of the time the clock
signal remains at a logic high (clock pulse width) to one
clock period. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock
results in a 50% duty cycle.
Differential Nonlinearity
(DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly
1 LSb apart. DNL is the deviation from this ideal value. No
missing codes to 12-bit resolution indicates that all 4096
codes must be present over all the operating conditions.
Integral Nonlinearity (INL)
INL is the maximum deviation of each individual code
from an ideal straight line drawn from negative full
scale through positive full scale.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS) to
the noise floor power (PN), below the Nyquist frequency
and excluding the power at DC and the first nine
harmonics.
EQUATION 7-2:
SNR is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of
the fundamental is extrapolated to the converter
full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS)
to the power of all the other spectral components
including noise (PN) and distortion (PD) below the
Nyquist frequency, but excluding DC:
EQUATION 7-3:
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used as
the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
converter full-scale range.
SNRJITTER 20 2
fIN tJITTER
log–=
SNR 10
PS
PN
-------



log=
SINAD 10
PS
PDPN
+
----------------------



log=
10–=10
SNR
10
-----------–
10
THD
10
------------–
–log
MCP37220-200 AND MCP37D20-200
DS20005396B-page 102 2015-2016 Microchip Technology Inc.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a
given input frequency can be calculated directly from its
measured SINAD using the following formula:
EQUATION 7-4:
Gain Error
Gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
Gain error is usually expressed in LSb or as a
percentage of full-scale range (%FSR).
Gain-Error Drift
Gain-error drift is the variation in gain error due to a
change in ambient temperature, typically expressed in
ppm/°C.
Offset Error
The major carry transition should occur for an analog
value of ½ LSb below AIN+=A
IN−. Offset error is
defined as the deviation of the actual transition from
that point.
Temperature Drift
The temperature drift for offset error and gain error
specifies the maximum change from the initial (+25°C)
value to the value across the TMIN to TMAX range.
Maximum Conversion Rate
The maximum clock rate at which parametric testing is
performed.
Minimum Conversion Rate
The minimum clock rate at which parametric testing is
performed.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier) or dBFS.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to
the summed power of the first 13 harmonics (PD).
EQUATION 7-5:
THD is typically given in units of dBc (dB to carrier).
THD is also shown by:
EQUATION 7-6:
Two-Tone Intermodulation Distortion
(Two-Tone IMD, IMD3)
Two-tone IMD is the ratio of the power of the fundamental
(at frequencies fIN1 and fIN2) to the power of the worst
spectral component at either frequency 2fIN1 –f
IN2 or
2fIN2 –f
IN1. Two-tone IMD is a function of the input
amplitudes and frequencies (fIN1 and fIN2). It is either
given in units of dBc (dB to carrier) when the absolute
power of the fundamental is used as the reference, or
dBFS (dB to full-scale) when the power of the
fundamental is extrapolated to the ADC full-scale range.
Common-Mode Rejection Ratio (CMRR)
Common-mode rejection is the ability of a device to
reject a signal that is common to both sides of a
differential input pair. The common-mode signal can be
an AC or DC signal or a combination of the two. CMRR
is measured using the ratio of the differential signal
gain to the common-mode signal gain and expressed in
dB with the following equation:
EQUATION 7-7:
ENOB SINAD 1.76–
6.02
----------------------------------=
THD 10
PS
PD
--------



log=
THD 20
V2
2V3
2V4
2
Vn
2
++++
V1
2
------------------------------------------------------------------log–=
Where:
V1= RMS amplitude of the
fundamental frequency
V1 through Vn= Amplitudes of the second
through nth harmonics
CMRR 20
ADIFF
ACM
------------------



log=
Where:
ADIFF =Output Code/Differential Voltage
ADIFF =Output Code/Common Mode Voltage
2015-2016 Microchip Technology Inc. DS20005396B-page 103
MCP37220-200 AND MCP37D20-200
8.0 PACKAGING INFORMATION
8.1 Package Marking Information
A1
A1
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
XXXXXXXXXXX
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for SnAgCu
Pb-free JEDEC® designator for NiPdAu
*This package is Pb-free. The Pb-free JEDEC designator ( or )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will be
carried over to the next line, thus limiting the number of available characters for
customer-specific information.
121-Lead TFBGA (8x8 mm) Example
MCP37D20-200
200-I/TL
^^
160991C
124-Lead VTLA (9x9x0.9 mm) Example
A1
A1
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
XXXXXXXXXXX
MICROCHIP
MCP37220
200/TE
^^
160991C
e1
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
e4
e1
e1
e4
e4
MCP37220-200 AND MCP37D20-200
DS20005396B-page 104 2015-2016 Microchip Technology Inc.
B
A
0.15 C
0.15 C
C
SEATING
PLANE
2X
BOTTOM VIEW
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
0.10 C
D
E
2X
NOTE 1
(DATUM A)
(DATUM B)
A
A1
A2
0.10 C
SIDE VIEW
TOP VIEW
1234567891011
E1
eE
A
B
C
D
E
F
G
H
J
K
L
DETAIL A
Microchip Technology Drawing C04-212A Sheet 1 of 2
D1
eD
A1 BALL PAD CORNER
121-Ball Thin Fine Pitch Ball Grid Array (TE) - 8x8 mm Body [TFBGA]
System In Package
2015-2016 Microchip Technology Inc. DS20005396B-page 105
MCP37220-200 AND MCP37D20-200
Microchip Technology Drawing C04-212A Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
Notes:
Terminal A1 visual index feature may vary, but must be located within the hatched area.
Dimensioning and tolerancing per ASME Y14.5M
0.15 C A B
0.08 C
121X Øb
Number of Terminals
Overall Height
Terminal Diameter
Overall Width
Overall Length
Overall Pitch
Overall Pitch
Cap Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
D
E1
D1
A2
eE
E
N
0.65 BSC
0.45
.035
-
0.21
0.40
8.00 BSC
6.50 BSC
6.50 BSC
-
0.32
8.00 BSC
MILLIMETERS
MIN NOM
121
0.45
1.08
-
MAX
Pitch eD 0.65 BSC
0.40 0.50
DETAIL A
121-Ball Thin Fine Pitch Ball Grid Array (TE) - 8x8 mm Body [TFBGA]
System In Package
MCP37220-200 AND MCP37D20-200
DS20005396B-page 106 2015-2016 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
SILK SCREEN
Dimension Limits
Units
C1Contact Pad Spacing
Contact Pad Spacing
Contact Pitch
C2
MILLIMETERS
0.65 BSC
MIN
E
MAX
6.50
6.50
Contact Pad Diameter (X121) B 0.35
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing No. C04-2212B-TE
NOM
121-Ball Thin Fine Pitch Ball Grid Array (TE) - 8x8 mm Body [TFBGA]
E
121X ØB
C2
E
C1
System In Package
2015-2016 Microchip Technology Inc. DS20005396B-page 107
MCP37220-200 AND MCP37D20-200
MCP37220-200 AND MCP37D20-200
DS20005396B-page 108 2015-2016 Microchip Technology Inc.
2015-2016 Microchip Technology Inc. DS20005396B-page 109
MCP37220-200 AND MCP37D20-200
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
RECOMMENDED LAND PATTERN
SILK SCREEN
Dimension Limits
Units
C1
Optional Center Pad Length
Contact Pad Spacing
Contact Pad Spacing
Optional Center Pad Chamfer (X4)
C2
W3
W2
0.10
6.60
MILLIMETERS
MIN MAX
8.50
8.50
Contact Pad Length (X124)
Contact Pad Width (X124)
X2
X1
0.30
0.30
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing No. C04-2193A
NOM
Optional Center Pad Width T2
Contact to Center Pad Clearance (X4) G5
Pad Clearance G4
Pad Clearance G3
Pad Clearance G2
Contact Pitch 0.50 BSCE
Pad Clearance G1
6.60
0.30
0.20
0.20
0.20
0.20
E
E/2
W2
W3
G2
G4
X1
G5
X4
C2
C1
G3
G1
X2
E
T2
124-Very Thin Leadless Array Package (TL) – 9x9x0.9 mm Body [VTLA]
MCP37220-200 AND MCP37D20-200
DS20005396B-page 110 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS20005396B-page 111
MCP37220-200 AND MCP37D20-200
APPENDIX A: REVISION HISTORY
Revision B (April 2016)
• Modified package types and device offers to
reflect the availability of the TFBGA package.
• Updated input leakage current at CLK input pin in
Table 2-1.
• Minor typographical changes.
Revision A (April 2015)
• Original Release of this Document.
MCP37220-200 AND MCP37D20-200
DS20005396B-page 112 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS20005396B-page 113
MCP37220-200 AND MCP37D20-200
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX-XXX
Sample PackageTemperature
Range
Device
Device: MCP37220-200: 14-Bit Low-Power Single-Channel ADC
MCP37D20-200: 14-Bit Low-Power Single-Channel ADC with
digital down-converter option
Tape and
Reel Option:
Blank = Standard packaging (tube or tray)
T = Tape and Reel(1)
Sample Rate 200 = 200 Msps
Temperature
Range:
I= -40C to +85C (Industrial)
Package: TL = Terminal Very Thin Leadless Array Package -
9x9x0.9 mm Body (VTLA), 124-Lead
TE = Ball Plastic Thin Profile Fine Pitch Ball Grid Array -
8x8 mm Body (TFBGA), 121-Lead
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This identifier is
used for ordering purposes and is not printed on
the device package. Check with your Microchip
Sales Office for package availability with the
Tape and Reel option.
[X](1)
Tape and Reel
Option Rate
Examples:
a) MCP37220-200I/TL: Industrial temperature,
124LD VTLA, 200 Msps
b) MCP37220T-200I/TL: Tape and Reel,
Industrial temperature,
124LD VTLA, 200 Msps
c) MCP37220-200I/TE: Industrial temperature,
121LD TFBGA, 200 Msps
a) MCP37D20-200I/TL: Industrial temperature,
124LD VTLA, 200 Msps
b) MCP37D20T-200I/TL: Tape and Reel,
Industrial temperature,
124LD VTLA, 200 Msps
c) MCP37D20-200I/TE: Industrial temperature,
121LD TFBGA, 200 Msps
MCP37220-200 AND MCP37D20-200
DS20005396B-page 114 2015-2016 Microchip Technology Inc.
NOTES:
2015-2016 Microchip Technology Inc. DS20005396B-page 115
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0525-2
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20005396B-page 116 2015-2016 Microchip Technology Inc.
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