UG277: Si52204-EVB User's Guide 4-Output PCI-Express Gen1/2/3/4 and SRIS Clock Generator Evaluation Board This document describes operation of the Silicon Laboratories Si52204-EVB evaluation board designed to evaluate the Si52204, 4-output PCI-Express Gen1/2/3/4 and SRIS Clock Generator. Selector switches make it easy to select the voltage for both core and IO supplies. Jumpers allow for easy static configuration of the control inputs as well as provide a port for external test equipment access. Similarly, each regulated supply can be bypassed and driven externally for precise voltage control or to measure PSRR performance. I2C ports allow for communication to the DUT by external I2C bus analyzers/ exercisers. Optimal XTAL placement and layout provide excellent phase noise performance. Convenient probe pads and isolation resistors permit on-board single-ended or differential measurements. Finally, the PCB layout optimizes signal integrity and skew which rounds out the capabilities of this EVB. silabs.com | Building a more connected world. KEY FEATURES * Evaluation of Silicon Labs Si52204 * DC-coupled differential output clocks * DC-coupled single-ended reference clock * External power or USB powered * Switchable voltage settings * Easy manual configuration via jumpers * I2C port access * Easy current measurement Rev. 0.1 UG277: Si52204-EVB User's Guide Functional Description 1. Functional Description The Si52204-EVB is an evaluation board designed to support the Si52204 device. The Si52204-EVB is designed to operate in one of two general operational modes: 1. Stand-alone mode: The stand-alone mode is for manual evaluation of the device. Control of device pins such as OE_xb, FS, PWRGD, REF_SA, and SS_EN is done via on-board jumpers. The jumper header (J14) also allows the user to test the enable/ disable time by providing an access point for external test equipment to easily drive the enable or PWRGD pins. The DUT supply voltages (e.g. VDD, VDDR, VDDX, VDDA, and VDDIO) can be set via on-board switches as shown in Section 2. Each supply can be sourced either by an on-board regulator for nominal values or via an external supply to test the device over a range of voltages (e.g. min/max supply testing). 2. I2C mode: The Evaluation Board also allows the user to setup the device via I2C commands using an external I2C driver/analyzer and connecting to the SCL/SDA header (JP7). silabs.com | Building a more connected world. Rev. 0.1 | 2 UG277: Si52204-EVB User's Guide Power Supply Switch Settings 2. Power Supply Switch Settings The device supplies use a linear voltage regulator to drop the externally supplied +5 V (sourced either via USB or an external power supply using switch SW3) voltage to one of the supported nominal VDD voltages (+1.8 V or +1.5 V for VDD, VDDA, VDDR, and VDDX using switch SW1 and +1.8 V, +1.5 V, +1.2 V, or +1.0 V for VDDIO using switch SW2). 2.1 +5 V Selection The +5 V main supply is sourced by either an external power supply or by USB-B connected to a computer, via switch SW3 located as shown in the figure below. Position the slide in the up position to select the USB port (J13) and in the down position to select the external supply (J11, J12). Figure 2.1. Location of EVB Power and Voltage Switches and Jumpers 2.2 Voltage Selection for Non-Output Supplies (VDD, VDDR, VDDX, VDDA, and VDD_AUX) The nominal voltage setting for all but VDD_IO is controlled by switch SW1 as shown in Figure 2.1 Location of EVB Power and Voltage Switches and Jumpers on page 3. Positioning the switch in the open position selects 1.5 V for all these supplies and positioning the switch in the closed position selects 1.8 V. Jumpers JP1-JP5 should be installed if the on-board regulator is desired. Alternatively, an external voltage source can be connected to a supply by removing the corresponding jumper and connecting the (+) voltage of the supply to pin 2 of the jumper and (-) voltage to GND (TP13). Note that pin 1 of the jumpers is identified by the highlighted square. silabs.com | Building a more connected world. Rev. 0.1 | 3 UG277: Si52204-EVB User's Guide Power Supply Switch Settings 2.3 Voltage Selection for Output Supply (VDD_IO) The nominal voltage setting for VDD_IO is controlled by switch SW2 as shown in Figure 2.1 Location of EVB Power and Voltage Switches and Jumpers on page 3. The table below shows the switch settings for nominal voltages: +1.8 V, +1.5 V, +1.2 V, and +1.0 V. Jumper JP6 should be installed if the on-board regulator is desired. Alternatively, an external voltage source can be connected to this supply by removing this jumper and connecting the (+) voltage of the supply to pin 2 of the jumper and (-) voltage to GND (TP13). Note that this is an excellent way to test the PSRR performance of the part as the dc supply can be modulated with a sinusoidal (noise) waveform and inserted on JP6, pin 2. Table 2.1. Switch 2 Settings for Output Voltage Supply SW2-1 SW2-2 SW2-3 VDD_IO OPEN OPEN OPEN 1.0V CLOSED OPEN OPEN 1.2V OPEN CLOSED OPEN 1.5V OPEN OPEN CLOSED 1.8V 2.4 Measuring Supply Currents (IDD, IDDA, IDDX, IDDR, and IDDIO) Measuring the current on any supply rail can be performed by simply measuring the voltage between test points VDDx and VDDx_PIN since between these two test points is a precision (100 ppm) 1 ohm resistor. Therefore, whatever voltage is measured maps to the equivalent current measurement (e.g., 30 mV 30 mA). silabs.com | Building a more connected world. Rev. 0.1 | 4 UG277: Si52204-EVB User's Guide Control Signal Jumper Settings 3. Control Signal Jumper Settings Header J14 is an 8x3, 100 mil header stake that provides access to the eight control input pins allowing these pins to be configured to the low, mid, or high input state. The table below defines how to configure each input Table 3.1. Control Input Jumper Configuration Settings Control Input Pin LO NONE HI OE_0b Enable Enable Disable OE_1b Enable Enable Disable OE_2b Enable Enable Disable OE_3b Enable Enable Disable REF_SA 0xD2 PWRGD PWRDN ACTIVE ACTIVE SS_EN -0.25% OFF -0.50% FS 100MHz 200MHz 133MHz 0xD4 Enable/Disable times can be measured by connecting an external pulse generator to the "B" pin of the header and GND to the "A" pin and sending this signal to trigger a scope. By measuring the time differential between the rising (falling) edge of the trigger and last (first) output clock edge of the corresponding output, the user can determine the disable (enable) time for that output. silabs.com | Building a more connected world. Rev. 0.1 | 5 UG277: Si52204-EVB User's Guide Output Clock Terminations 4. Output Clock Terminations 4.1 Differential Outputs (DIFF_0:3) The figure below shows the output termination circuit for each of the four differential clock outputs: Diff_0:3. To simplify on-board probing of the clock, exposed copper pads have been included (PCB11:18 for signals, PCB2:9 for GND) and are spaced to accommodate a differential probe (e.g., Ag1132A). An isolation resistor (953 ohms) is included immediately following the pads to buffer the stub length from the pads to the SMA connectors so the user can observe the response after 5 inches of PCB length with a 2 pF load capacitor. Also, the isolation resistor value effectively creates a 20:1 probe for observation using coax cables connected to the 50 ohm input of the scope. Determine the type of measurements you want to take--for signal integrity measurements, no changes are required but remember that if observing the outputs via the SMA connectors to a 50-ohm input scope, the scale is 1:20. For phase noise measurements, change resistors R37:R44 from 953 to 0 ohms (all 0402 size). Note that most phase noise analyzers have a single-ended input, so a balun should be added to convert the differential output to single-ended. 5 INCHES DUT 2 DIFF_1 2 DIFF_1b PCB6 TP-PAD GND PCB13 R41 953 C46 2pF PCB14 R43 C49 2pF 5 INCHES DUT 953 J7 DIFF_1 SMA J9 DIFF_1b SMA PCB8 TP-PAD GND Figure 4.1. Differential Output Clock Termination silabs.com | Building a more connected world. Rev. 0.1 | 6 UG277: Si52204-EVB User's Guide Output Clock Terminations 4.2 Reference Output (REF_SA) The figure below shows the output termination circuit for the reference (25 MHz) output: REF_SA. To simplify on-board probing of the clock, exposed copper pads have been included (PCB10 for REF_SA and PCB1 for GND) and are spaced to accommodate a differential probe (e.g., Ag1132A). A series termination resistor (R35) is used to make the total output impedance of the driver match the characteristic impedance of the PCB trace (50 ohms). An isolation resistor (953 ohms) is included immediately following the pad to buffer the stub length from the pad to the SMA connector so the user can observe the response after 5 inches of PCB length with a 4.7 pF load capacitor. Also, the isolation resistor value effectively creates a 20:1 probe for observation using coax cables connected to the 50 ohm input of the scope. PCB1 TP-PAD GND PCB10 2,9 REF_SA R36 R35 10.0 RS 953 C41 4.7pF CL J2 SMA Figure 4.2. Reference Output Clock Termination silabs.com | Building a more connected world. Rev. 0.1 | 7 UG277: Si52204-EVB User's Guide XTAL and External Input Clock 5. XTAL and External Input Clock The on-board crystal (U8) layout will accommodate multiple size packages: 2.5x2.0 mm, 3.2x2.5 mm, and 3.2x5.0 mm so the user can experiment with different sized crystals if he chooses. The crystal used on the CEVB (25 MHz) is from Epson and is 3.2x2.5 mm. Optionally, the user can drive the input clock externally via SMA connector J1 (CLKIN). To switch the DUT input from the crystal to a single-ended external clock, populate R64 (0 ohms 0402 size) and de-populate R32 (0 ohms). If a 50 ohm termination is required, also populate R33 (49.9 ohms) and C39 (0.1F) (all 0402 size). Refer to the datasheet for clock input specifications. silabs.com | Building a more connected world. Rev. 0.1 | 8 UG277: Si52204-EVB User's Guide LEDs 6. LEDs The Si52204-EVB has 2 status LEDs as shown in table below. The board silkscreen identifies each LED. Table 6.1. Status LEDs LED name Color Location Description +5V_EXT Green D1 External +5 V source is present (independent of +5V_SELECT (SW3) switch setting) +5V_USB Blue D3 USB port is present (independent of +5V_SELECT (SW3) switch setting) silabs.com | Building a more connected world. Rev. 0.1 | 9 UG277: Si52204-EVB User's Guide I2C Interface 7. I2C Interface Header JP7 provides header stakes for GND, SCLK, and SDATA (SDA) (See figure below). SCLK and SDA have on-board 1k ohm pull-ups to VDD_AUX (supply that tracks to VDD). The device address is controlled by the jumper setting (at power up) of REF_SA on J14 as shown in Table 3.1 Control Input Jumper Configuration Settings on page 5. Figure 7.1. I2C Access Header Location silabs.com | Building a more connected world. Rev. 0.1 | 10 UG277: Si52204-EVB User's Guide Quick Start--Board Configuration Check List 8. Quick Start--Board Configuration Check List 1. Start with EVB board powered down/off. 2. Set the voltage supply DIP switches (described in 2.2 Voltage Selection for Non-Output Supplies (VDD, VDDR, VDDX, VDDA, and VDD_AUX) and 2.3 Voltage Selection for Output Supply (VDD_IO)) according to the following: a. Switch SW1 controls the voltage setting (either 1.5 V or 1.8 V) for the following supplies: i. VDD ii. VDDA iii. VDDR iv. VDDX v. VDD_AUX b. Switch SW2 controls the voltage setting (either 1.0 V, 1.2 V, 1.5 V, or 1.8 V) for VDD_IO (voltage supply for output DIFF_0:3). c. Make sure that jumpers JP1:6 are installed. 3. Choose clock input source--the board defaults to the 25 MHz XTAL (U8). Refer to 5. XTAL and External Input Clock for instructions on how to switch the input clock source to an external clock. 4. Determine the type of measurements you want to take--for signal integrity measurements, no changes are required but remember that if observing the outputs via the SMA connectors to a 50-ohm input scope, the scale is 1:20. For phase noise measurements, change resistors R37:R44 from 953 to 0 ohms (all 0402 size). Note that most phase noise analyzers have a single-ended input, so a balun should be added to convert the differential output to single-ended. 5. Configure the jumpers at J14 according to how you plan to test the part. a. Outputs 0:3 enabled/disabled b. I2C address (0xD2 or 0xD4) c. Part active or powered-down d. Spread-spectrum setting (-0.25%, -0.5%, or OFF) e. Output frequency (100, 133, or 200 MHz) 6. Set +5V Select switch (SW3) based on how you will power the EVB, either via USB or via external +5 V supply. 7. Connect power, either via USB port or external +5 V power supply as chosen in previous step. silabs.com | Building a more connected world. Rev. 0.1 | 11 A B C D 5 JP7 XOUT CLKIN J14 U8 4 U1 <-500mil-> J2 DIFF_2 <---750mil--> DIFF_1 DIFF_1b J5 DIFF_0b <-500mil-> J3 DIFF_0 SiLabs Logo Si52204 - EVB 4-OUTPUT - QFN32 Rev 1.0 - ____________ REF_SA SW2 DIFF_2b <---750mil--> J8 DIFF_3 <-500mil-> J10 DIFF_3b U2 U3 U4 U5 U6 U7 J1 <-500mil-> <-------------------- 3000mil ---------------------> J12 GND J11 +5V SW3 J13 J15 <-500mil-> SW1 MECHANICAL & FABRICATION 4 J7 3 J9 J4 J6 3 <---750mil--> <-500mil> <-500mil> <-500mil> silabs.com | Building a more connected world. <---750mil--> 5 Total Board Thickness: 62 mil 2 Date: Size B Title 1 Monday, May 01, 2017 1 Sheet Document Number SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 . MECHANICAL & FABRICATION 400 W Cesar Chavez Austin, TX 78701 SIGNAL + GND FLOOD (COPLANAR) GROUND POWER VDD GROUND SIGNAL + GND FLOOD (COPLANAR) 6 BOARD LAYERS: and 0.5oz thickness for RF signal layers - Use FR-406, DK=3.9 BOARD MATERIAL: 2 1 of 9 Rev 2.0 A B C D UG277: Si52204-EVB User's Guide Si52204-EVB Schematic 9. Si52204-EVB Schematic Rev. 0.1 | 12 A B C D 5 DUT CONNECTIONS 9 9 SDA SCLK SS_EN 9 9 XIN_CLKIN 5 XOUT OE_2b OE_3b 9 9 4 OE_1b 9 FS OE_0b 9 9 PWRGD_PWRDNb 5 4 VDD_IO C1 0.1uF VDDA VDDR VDDX C2 1uF VDD 1 2 3 4 5 6 7 8 VDDA C3 0.1uF C5 1uF SS_EN PWRGD/PWRDNb XIN/CLKIN XOUT VDDX VDDR REF/SA VSSR C4 0.1uF VDD C6 1uF VDDX 3 32 31 30 29 28 27 26 25 GNDA VDDA NC3 VDD2 NC2 OE_3b DIFF_3b DIFF_3 SDA SCLK FS DIFF_0 DIFF_0b OE_0b VDD_IO1 OE_1b MH1 MH2 3 MH3 MH4 9 10 11 12 13 14 15 16 VDD_IO2 OE_2b DIFF_2b DIFF_2 NC1 VDD1 DIFF_1b DIFF_1 C7 0.1uF MH21 Toe_Tag 24 23 22 21 20 19 18 17 U1 Si52204-32QFN C8 0.1uF VDD_IO ePAD silabs.com | Building a more connected world. 33 5 C9 0.1uF C10 1uF VDDR C11 1uF 2 2 REF_SA DIFF_0 DIFF_0b 6,9 7 7 DIFF_1b 7 DIFF_1 7 DIFF_2b 7 DIFF_2 7 DIFF_3b 7 DIFF_3 7 C12 0.1uF Date: Size B Title Monday, May 01, 2017 1 Sheet Document Number SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 . DUT Connections 400 W Cesar Chavez Austin, TX 78701 1 2 of 9 Rev 2.0 A B C D UG277: Si52204-EVB User's Guide Si52204-EVB Schematic Rev. 0.1 | 13 A B C D 5V 2 OUT TPS76201 GND FB EN IN U2 0.6663V 4 5 5 5V C31 1uF Vo=0.6663 x (1 + R1/R2) C22 1uF 3 1 NI TP1 2 3 1 R2 C13 0.01uF VDDA_PIN R1 R9 21.5K ESR=1.0 C14 4.7uF +/-100ppm R10 8.06K R3 10K NI TP2 OUT TPS76201 0.6663V 4 5 TP6 NI C25 0.01uF + C15 4.7uF VDDA + 4 R21 21.5K C26 4.7uF C23 1uF R22 8.06K R17 10K NI TP7 OUT + C27 4.7uF VDDX TPS76201 GND FB EN IN U3 JS13 Jumper Shunt JP4 2 3 1 4 5 R11 21.5K C17 4.7uF ESR=1.0 +/-100ppm 3 OPEN 5V C32 1uF SWITCH CLOSED = 1.8V SWITCH OPEN = 1.5V SW1-DIP-SMT R12 8.06K R4 10K NI TP3 + 2 3 1 2 C24 1uF OUT TPS76201 2 0.6663V 4 5 NI TP8 C28 0.01uF VDDR_PIN 5V + OUT 4 R23 21.5K C29 4.7uF ESR=1.0 Date: Size B Title R13 21.5K C20 4.7uF ESR=1.0 + 1 Monday, May 01, 2017 1 Sheet 3 R14 8.06K R7 10K NI TP5 VDD Document Number SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 . C30 4.7uF VDDR JS14 Jumper Shunt JP5 + +/-100ppm 400 W Cesar Chavez Austin, TX 78701 R24 8.06K R18 10K NI TP9 VDDR 0.6663V C19 0.01uF R2 1 Output Voltage Regulators +/-100ppm TPS76201 5 NI TP4 VDD_PIN GND FB EN IN U4 R16 1 2 3 1 Group JP1:JP6 together GND FB EN IN U6 C18 4.7uF VDD_AUX JS11 Jumper Shunt JP2 VDD_AUX Text in BLUE should be added to TOP SILK CORE VOLTAGE SELECT CLOSED + SW1 0.6663V C16 0.01uF Identify Pin1 of all jumpers and IC's! VDDX 5V +/-100ppm ESR=1.0 R15 1 JS10 Jumper Shunt JP1 VDDA VDDX_PIN GND FB EN IN U5 + 1 R1 1.8V 3 2 1 100 mA Adjustable Voltage Regulator 1.8V 1.8V 4 1.8V silabs.com | Building a more connected world. 1.8V 5 + of 9 Rev 2.0 C21 4.7uF VDD JS12 Jumper Shunt JP3 A B C D UG277: Si52204-EVB User's Guide Si52204-EVB Schematic Rev. 0.1 | 14 OPEN 3 CLOSED R29 13.3K C34 4.7uF R1 R30 33K R31 20K R26 10K + 2 Vo=0.6663 x (1 + R1/R2) C35 4.7uF VDD_IO JS15 Jumper Shunt JP6 Title 400 W Cesar Chavez Austin, TX 78701 4 of 9 Rev 2.0 C Date: Size B Monday, May 01, 2017 1 Sheet Document Number SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 . Other Voltage Regulators A 4 4 5 6 SW2 R28 8.25K C33 0.01uF ESR=1.0 NI TP11 VDD_IO D A 5 3 2 1 R2 0.6663V 4 5 SW3-DIP-SMT TPS76201 GND FB OUT IO VOLTAGE SELECT 2 EN IN + +/-100ppm 1 B C36 1uF 3 1 U7 1 R25 2 B C 5V NI TP10 VDD_IO_PIN 3 1.8V D 100 mA Adjustable Voltage Regulator 4 1.5V silabs.com | Building a more connected world. 1.2V 5 UG277: Si52204-EVB User's Guide Si52204-EVB Schematic Rev. 0.1 | 15 A B C D 5 Make sure that layer above bottom layer (5) is solid GND for length of diff'l trace J15 Keep U8 as close to DUT as possible J1 Bottom Layer U8 Bottom Layer R34 R32 4 J1 SMA C39 C53 <GND> <- To DUT <GND> XOUT J15 SMA Place R33 (R59) and C39 (C53) close to R64 (R65) CLKIN Keep R33,C39,R59,C53 as close to DUT as possible Dashed lines/squares indicate bottom layer traces/pads Crystal/Input Clock Connections C38 C40 4 R64 R65 R33 R59 NI NI R65 0 R59 49.9 R33 49.9 R32 3 Keep X as short as possible by placing all components close to the XA/XB pins <--------- X ----------> 0.1uF NI C53 0.1uF NI C39 NI NI R64 0 R32 and R64 should share a pad and be placed right at DUT pin XIN 3 18pF C38 0 4 R34 0 18pF C40 U8 25MHz 2 2 3.2 x 5.0 mm 3.2 x 2.5 mm 2.5 x 2.0 mm * CRYSTAL FOOTPRINT: Please create a footprint with pads that can accommodate the following crystal sizes: XOUT XIN_CLKIN - Place crystal as close to U1 pins as possible! - Route signals carefully, match trace lengths! GND GND 3 XTAL1 XTAL2 1 silabs.com | Building a more connected world. 2 5 2 2 Date: Size B Title Monday, May 01, 2017 1 Sheet B 5 of 9 <- Plane cutout Document Number SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 . Crystal Input Connections 400 W Cesar Chavez Austin, TX 78701 Traces are just an illustration! 90 degree placement -> Cut planes underneath crystal to reduce capacitive coupling! 1 Rev 2.0 A C D UG277: Si52204-EVB User's Guide Si52204-EVB Schematic Rev. 0.1 | 16 A B C D REF_SA U1 2,9 5 <----------- 5" total ---------> RS 10.0 R35 GND CL C41 4.7pF PCB10 4 953 R43 R41 R38 R40 4 SMA J2 Place isolation resistor right by load cap; Place RS as close to the DUT pin as possible Make total trace length = 5" (from DUT pin to CLoad); <- This is the only single-ended output 3 J6 J7 DIFF_1 J9 J4 2 - COMPONENT PLACEMENT: 3 - TOPOLOGY: use microstip for all traces - GEOMETRY: maintain the trace symmetry across all output differential pairs the SMA connectors as needed - IMPEDANCE: all traces to have 50 ohms of controlled impedance 2 - ROUTING: route each differential pair losely coupled. Serpentine to length and preserve symmetry on diff. pair. Keep distance b/w serpentine traces at least 5w apart and use arcs rather than 45's Date: Size B Title 400 W Cesar Chavez Austin, TX 78701 1 Monday, May 01, 2017 1 Sheet Document Number SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 . Output Connections B A sufficient number of via holes connected to ground should be used around all input/output traces! Flood top and bottom layers with copper as shown OUTPUT SIGNALS LAYOUT NOTES - APPLIES TO THIS PAGE AND NEXT PAGE AS WELL! (Refer to image on left): GND plane cutout -> <- Board edge SMA FOOTPRINT NOTE: Make sure pad for center pin on SMA matches exactly the actual width of the center pin in order to improve performance DIFF_2 PLACE PAD PCB1 ~150 MILS FROM PAD PCB10 AND PLACE PCB10 B/W C41 AND R36; R36 SHOULD BE CLOSE TO C41 R36 C45 C42 C49 silabs.com | Building a more connected world. C46 PCB1 TP-PAD OUTPUT CONNECTIONS, PART 1 5 6 of 9 Rev 2.0 A C D UG277: Si52204-EVB User's Guide Si52204-EVB Schematic Rev. 0.1 | 17 silabs.com | Building a more connected world. A B C D 5 2 2 DUT DIFF_1b <-----------5 INCHES -----------> <-----------5 INCHES -----------> DUT DIFF_1 <-----------5 INCHES -----------> DIFF_0b 2 4 4 PLACE CAP PAD IN-TRACE (NO STUB) SEE DGM ON PREVIOUS PAGE <-----------5 INCHES -----------> DUT DIFF_0 2 DUT OUTPUT CONNECTIONS 5 C49 2pF GND 953 953 C46 2pF PCB14 R43 PCB8 TP-PAD GND PCB6 TP-PAD GND 953 PCB12 R39 953 PCB11 R37 PCB13 R41 C44 2pF C43 2pF PCB4 TP-PAD GND PCB2 TP-PAD J9 DIFF_1b SMA J7 DIFF_1 SMA J5 DIFF_0b SMA J3 DIFF_0 SMA 3 PLACE R37 (R39) CLOSE TO C43 (C44) AND KEEP DISTANCE B/W PCB11 AND PCB12 <180 MILS (SIMILARLY FOR THE OTHER OUTPUTS). (SEE DGM ON PAGE 6) PLACE PAD PCB2 (PCB4) ~150 MILS FROM PAD PCB11 (PCB12) AND PLACE PCB11 (PCB12) B/W C43 (C44) AND R37 (R39); 3 2 2 2 2 DUT DIFF_3b DIFF_3 DUT DUT DIFF_2b DIFF_2 DUT 2 <-----------5 INCHES -----------> <-----------5 INCHES -----------> <-----------5 INCHES -----------> <-----------5 INCHES -----------> 2 C45 2pF C42 2pF C48 2pF C47 2pF Date: Size B Title J10 DIFF_3b SMA J8 DIFF_3 SMA J6 DIFF_2b SMA J4 DIFF_2 SMA 400 W Cesar Chavez Austin, TX 78701 953 PCB18 R44 953 PCB17 R42 953 PCB16 R40 953 PCB15 R38 Monday, May 01, 2017 1 Sheet Document Number SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 . Output Connections GND PCB9 TP-PAD GND PCB7 TP-PAD GND PCB5 TP-PAD GND PCB3 TP-PAD 1 7 of 9 Rev 2.0 A B C D UG277: Si52204-EVB User's Guide Si52204-EVB Schematic Rev. 0.1 | 18 A B C D 5 External Power 4 GND +5V 4 FB1 +5V_EXT 22 Ohm +V DD+ GND J13 USB Type B BND_POST J12 BND_POST J11 SH SH silabs.com | Building a more connected world. 6 5 5 1 2 3 4 D1 Green R45 6.8K 3 2 1 3 D3 Blue 5VUSB MAIN R48 8.06K FB2 SW_SLIDE_2POS D2 SP0503BAHT 1-2 USB +5V 2-3 External +5V SW3 +5V_SELECT +5V Input Select 3 C52 1uF 22 Ohm C50 1uF 5V_USB C51 0.1uF NI NI TP13 BLACK GND TP12 RED +5V 5V 2 2 Date: Size B Title Monday, May 01, 2017 1 Sheet Document Number SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 . External Power 400 W Cesar Chavez Austin, TX 78701 1 8 of 9 Rev 2.0 A B C D UG277: Si52204-EVB User's Guide Si52204-EVB Schematic Rev. 0.1 | 19 A B C D 2 5 REF_SA OE_3b 2 2 FS SS_EN PWRGD_PWRDNb 2,6 OE_2b 2 OE_1b 2 2 OE_0b 2 R60 1K R61 1K FS 10K R58 REF_SA 10K R55 SS_EN OE_3b 1K R54 10K R57 OE_2b 1K R53 PWRGD OE_1b 1K R50 1K R56 OE_0b 1K R49 DC Inputs/I2C Access 4 4 R63 1K 1A 1B 2A 2B 3A 3B 4A 4B 5A 5B 6A 6B 7A 7B 8A 8B LO HI 8C 7C 6C 5C 4C 3C 2C 1C JS5 Jumper Shunt JS7 Jumper Shunt JS9 Jumper Shunt JS4 Jumper Shunt JS6 Jumper Shunt JS8 Jumper Shunt JS3 Jumper Shunt HEADER 8x3 J14 JS2 Jumper Shunt R62 1K VDD_AUX 3 3 2 2 2 SDA SCLK 2 R51 1K 2 JP7 R52 1K VDD_AUX 3 silabs.com | Building a more connected world. 400 W Cesar Chavez Austin, TX 78701 1 Friday, May 05, 2017 1 Sheet Document Number SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 . DC Inputs/I2C Access SCL SDA GND HEADER 1x3 Date: Size B Title 1 5 9 of 9 Rev 2.0 A B C D UG277: Si52204-EVB User's Guide Si52204-EVB Schematic Rev. 0.1 | 20 UG277: Si52204-EVB User's Guide Bill of Materials 10. Bill of Materials silabs.com | Building a more connected world. Rev. 0.1 | 21 UG277: Si52204-EVB User's Guide Appendix: Typical Waveplots 11. Appendix: Typical Waveplots The plots displayed in this section are provided to give the user an example of what they should expect to observe when measuring signals on this evaluation board with a good lab setup. These plots were taken on signals probed on-board using a Keysight 5 GHz differential probe (Ag 1132A) (for the differential waveforms), and Keysight 2 GHz high-impedance FET probe (Keysight N2796A) (for single-ended waveforms) and an 8 GHz bandwidth oscilloscope (Keysight Ag DSA90804A). 11.1 Reference Clock Output (Differential waveform) silabs.com | Building a more connected world. Rev. 0.1 | 22 UG277: Si52204-EVB User's Guide Appendix: Typical Waveplots 11.2 Differential Clock (DIFF_0) Output (Differential waveform) silabs.com | Building a more connected world. Rev. 0.1 | 23 UG277: Si52204-EVB User's Guide Appendix: Typical Waveplots 11.3 Differential Clock (DIFF_0) Crossing Voltage (100MHz) (Single-ended waveform) silabs.com | Building a more connected world. Rev. 0.1 | 24 UG277: Si52204-EVB User's Guide Appendix: Typical Waveplots 11.4 Differential Clock (DIFF_0) Crossing Voltage (200MHz) (Single-ended waveform) silabs.com | Building a more connected world. Rev. 0.1 | 25 UG277: Si52204-EVB User's Guide Appendix: Typical Waveplots 11.5 Spread Spectrum Clock @-0.5% spread (Differential waveform) 11.6 Spread Spectrum Clock @-0.25% spread (Differential waveform) silabs.com | Building a more connected world. Rev. 0.1 | 26 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW www.silabs.com/CBPro Quality www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. 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