UG277: Si52204-EVB User's Guide
4-Output PCI-Express Gen1/2/3/4 and SRIS Clock Generator
Evaluation Board
This document describes operation of the Silicon Laboratories Si52204-EVB evaluation
board designed to evaluate the Si52204, 4-output PCI-Express Gen1/2/3/4 and SRIS
Clock Generator. Selector switches make it easy to select the voltage for both core and
IO supplies. Jumpers allow for easy static configuration of the control inputs as well as
provide a port for external test equipment access. Similarly, each regulated supply can
be bypassed and driven externally for precise voltage control or to measure PSRR per-
formance. I2C ports allow for communication to the DUT by external I2C bus analyzers/
exercisers. Optimal XTAL placement and layout provide excellent phase noise perform-
ance. Convenient probe pads and isolation resistors permit on-board single-ended or
differential measurements. Finally, the PCB layout optimizes signal integrity and skew
which rounds out the capabilities of this EVB.
KEY FEATURES
• Evaluation of Silicon Labs Si52204
• DC-coupled differential output clocks
• DC-coupled single-ended reference clock
• External power or USB powered
• Switchable voltage settings
• Easy manual configuration via jumpers
• I2C port access
• Easy current measurement
silabs.com | Building a more connected world. Rev. 0.1
1. Functional Description
The Si52204-EVB is an evaluation board designed to support the Si52204 device. The Si52204-EVB is designed to operate in one of
two general operational modes:
1. Stand-alone mode: The stand-alone mode is for manual evaluation of the device. Control of device pins such as OE_xb, FS,
PWRGD, REF_SA, and SS_EN is done via on-board jumpers. The jumper header (J14) also allows the user to test the enable/
disable time by providing an access point for external test equipment to easily drive the enable or PWRGD pins. The DUT supply
voltages (e.g. VDD, VDDR, VDDX, VDDA, and VDDIO) can be set via on-board switches as shown in Section 2. Each supply can
be sourced either by an on-board regulator for nominal values or via an external supply to test the device over a range of voltages
(e.g. min/max supply testing).
2. I2C mode: The Evaluation Board also allows the user to setup the device via I2C commands using an external I2C driver/analyzer
and connecting to the SCL/SDA header (JP7).
UG277: Si52204-EVB User's Guide
Functional Description
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2. Power Supply Switch Settings
The device supplies use a linear voltage regulator to drop the externally supplied +5 V (sourced either via USB or an external power
supply using switch SW3) voltage to one of the supported nominal VDD voltages (+1.8 V or +1.5 V for VDD, VDDA, VDDR, and VDDX
using switch SW1 and +1.8 V, +1.5 V, +1.2 V, or +1.0 V for VDDIO using switch SW2).
2.1 +5 V Selection
The +5 V main supply is sourced by either an external power supply or by USB-B connected to a computer, via switch SW3 located as
shown in the figure below. Position the slide in the up position to select the USB port (J13) and in the down position to select the exter-
nal supply (J11, J12).
Figure 2.1. Location of EVB Power and Voltage Switches and Jumpers
2.2 Voltage Selection for Non-Output Supplies (VDD, VDDR, VDDX, VDDA, and VDD_AUX)
The nominal voltage setting for all but VDD_IO is controlled by switch SW1 as shown in Figure 2.1 Location of EVB Power and Voltage
Switches and Jumpers on page 3. Positioning the switch in the open position selects 1.5 V for all these supplies and positioning the
switch in the closed position selects 1.8 V. Jumpers JP1-JP5 should be installed if the on-board regulator is desired. Alternatively, an
external voltage source can be connected to a supply by removing the corresponding jumper and connecting the (+) voltage of the
supply to pin 2 of the jumper and (-) voltage to GND (TP13). Note that pin 1 of the jumpers is identified by the highlighted square.
UG277: Si52204-EVB User's Guide
Power Supply Switch Settings
silabs.com | Building a more connected world. Rev. 0.1 | 3
2.3 Voltage Selection for Output Supply (VDD_IO)
The nominal voltage setting for VDD_IO is controlled by switch SW2 as shown in Figure 2.1 Location of EVB Power and Voltage
Switches and Jumpers on page 3. The table below shows the switch settings for nominal voltages: +1.8 V, +1.5 V, +1.2 V, and +1.0 V.
Jumper JP6 should be installed if the on-board regulator is desired. Alternatively, an external voltage source can be connected to this
supply by removing this jumper and connecting the (+) voltage of the supply to pin 2 of the jumper and (-) voltage to GND (TP13). Note
that this is an excellent way to test the PSRR performance of the part as the dc supply can be modulated with a sinusoidal (noise)
waveform and inserted on JP6, pin 2.
Table 2.1. Switch 2 Settings for Output Voltage Supply
SW2-1 SW2-2 SW2-3 VDD_IO
OPEN OPEN OPEN 1.0V
CLOSED OPEN OPEN 1.2V
OPEN CLOSED OPEN 1.5V
OPEN OPEN CLOSED 1.8V
2.4 Measuring Supply Currents (IDD, IDDA, IDDX, IDDR, and IDDIO)
Measuring the current on any supply rail can be performed by simply measuring the voltage between test points VDDx and VDDx_PIN
since between these two test points is a precision (±100 ppm) 1 ohm resistor. Therefore, whatever voltage is measured maps to the
equivalent current measurement (e.g., 30 mV →30 mA).
UG277: Si52204-EVB User's Guide
Power Supply Switch Settings
silabs.com | Building a more connected world. Rev. 0.1 | 4
3. Control Signal Jumper Settings
Header J14 is an 8x3, 100 mil header stake that provides access to the eight control input pins allowing these pins to be configured to
the low, mid, or high input state. The table below defines how to configure each input
Table 3.1. Control Input Jumper Configuration Settings
Control Input Pin LO NONE HI
OE_0b Enable Enable Disable
OE_1b Enable Enable Disable
OE_2b Enable Enable Disable
OE_3b Enable Enable Disable
REF_SA 0xD2 0xD4
PWRGD PWRDN ACTIVE ACTIVE
SS_EN -0.25% OFF -0.50%
FS 100MHz 200MHz 133MHz
Enable/Disable times can be measured by connecting an external pulse generator to the "B" pin of the header and GND to the "A" pin
and sending this signal to trigger a scope. By measuring the time differential between the rising (falling) edge of the trigger and last
(first) output clock edge of the corresponding output, the user can determine the disable (enable) time for that output.
UG277: Si52204-EVB User's Guide
Control Signal Jumper Settings
silabs.com | Building a more connected world. Rev. 0.1 | 5
4. Output Clock Terminations
4.1 Differential Outputs (DIFF_0:3)
The figure below shows the output termination circuit for each of the four differential clock outputs: Diff_0:3. To simplify on-board prob-
ing of the clock, exposed copper pads have been included (PCB11:18 for signals, PCB2:9 for GND) and are spaced to accommodate a
differential probe (e.g., Ag1132A). An isolation resistor (953 ohms) is included immediately following the pads to buffer the stub length
from the pads to the SMA connectors so the user can observe the response after 5 inches of PCB length with a 2 pF load capacitor.
Also, the isolation resistor value effectively creates a 20:1 probe for observation using coax cables connected to the 50 ohm input of the
scope.
Determine the type of measurements you want to take—for signal integrity measurements, no changes are required but remember that
if observing the outputs via the SMA connectors to a 50-ohm input scope, the scale is 1:20. For phase noise measurements, change
resistors R37:R44 from 953 to 0 ohms (all 0402 size). Note that most phase noise analyzers have a single-ended input, so a balun
should be added to convert the differential output to single-ended.
DIFF_12
DIFF_1b2
DUT
DUT
PCB6
TP-PAD
GND
R41
953
PCB13
PCB14
R43
953
J7
SMA DIFF_1
PCB8
TP-PAD
GND
J9
SMA DIFF_1b
C46
2pF
C49
2pF
5 INCHES
5 INCHES
Figure 4.1. Differential Output Clock Termination
UG277: Si52204-EVB User's Guide
Output Clock Terminations
silabs.com | Building a more connected world. Rev. 0.1 | 6
4.2 Reference Output (REF_SA)
The figure below shows the output termination circuit for the reference (25 MHz) output: REF_SA. To simplify on-board probing of the
clock, exposed copper pads have been included (PCB10 for REF_SA and PCB1 for GND) and are spaced to accommodate a differen-
tial probe (e.g., Ag1132A). A series termination resistor (R35) is used to make the total output impedance of the driver match the char-
acteristic impedance of the PCB trace (50 ohms). An isolation resistor (953 ohms) is included immediately following the pad to buffer
the stub length from the pad to the SMA connector so the user can observe the response after 5 inches of PCB length with a 4.7 pF
load capacitor. Also, the isolation resistor value effectively creates a 20:1 probe for observation using coax cables connected to the 50
ohm input of the scope.
REF_SA2,9
RS
CL
R35
10.0
C41
4.7pF
R36
953
J2
SMA
PCB10
PCB1
TP-PAD
GND
Figure 4.2. Reference Output Clock Termination
UG277: Si52204-EVB User's Guide
Output Clock Terminations
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5. XTAL and External Input Clock
The on-board crystal (U8) layout will accommodate multiple size packages: 2.5x2.0 mm, 3.2x2.5 mm, and 3.2x5.0 mm so the user can
experiment with different sized crystals if he chooses. The crystal used on the CEVB (25 MHz) is from Epson and is 3.2x2.5 mm. Op-
tionally, the user can drive the input clock externally via SMA connector J1 (CLKIN). To switch the DUT input from the crystal to a sin-
gle-ended external clock, populate R64 (0 ohms 0402 size) and de-populate R32 (0 ohms). If a 50 ohm termination is required, also
populate R33 (49.9 ohms) and C39 (0.1μF) (all 0402 size). Refer to the datasheet for clock input specifications.
UG277: Si52204-EVB User's Guide
XTAL and External Input Clock
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6. LEDs
The Si52204-EVB has 2 status LEDs as shown in table below. The board silkscreen identifies each LED.
Table 6.1. Status LEDs
LED name Color Location Description
+5V_EXT Green D1 External +5 V source is present (independent of +5V_SELECT (SW3) switch setting)
+5V_USB Blue D3 USB port is present (independent of +5V_SELECT (SW3) switch setting)
UG277: Si52204-EVB User's Guide
LEDs
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7. I2C Interface
Header JP7 provides header stakes for GND, SCLK, and SDATA (SDA) (See figure below). SCLK and SDA have on-board 1k ohm
pull-ups to VDD_AUX (supply that tracks to VDD). The device address is controlled by the jumper setting (at power up) of REF_SA on
J14 as shown in Table 3.1 Control Input Jumper Configuration Settings on page 5.
Figure 7.1. I2C Access Header Location
UG277: Si52204-EVB User's Guide
I2C Interface
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8. Quick Start—Board Configuration Check List
1. Start with EVB board powered down/off.
2. Set the voltage supply DIP switches (described in 2.2 Voltage Selection for Non-Output Supplies (VDD, VDDR, VDDX, VDDA, and
VDD_AUX) and 2.3 Voltage Selection for Output Supply (VDD_IO)) according to the following:
a. Switch SW1 controls the voltage setting (either 1.5 V or 1.8 V) for the following supplies:
i. VDD
ii. VDDA
iii. VDDR
iv. VDDX
v. VDD_AUX
b. Switch SW2 controls the voltage setting (either 1.0 V, 1.2 V, 1.5 V, or 1.8 V) for VDD_IO (voltage supply for output DIFF_0:3).
c. Make sure that jumpers JP1:6 are installed.
3. Choose clock input source—the board defaults to the 25 MHz XTAL (U8). Refer to 5. XTAL and External Input Clock for instruc-
tions on how to switch the input clock source to an external clock.
4. Determine the type of measurements you want to take—for signal integrity measurements, no changes are required but
remember that if observing the outputs via the SMA connectors to a 50-ohm input scope, the scale is 1:20. For phase
noise measurements, change resistors R37:R44 from 953 to 0 ohms (all 0402 size). Note that most phase noise analyzers
have a single-ended input, so a balun should be added to convert the differential output to single-ended.
5. Configure the jumpers at J14 according to how you plan to test the part.
a. Outputs 0:3 enabled/disabled
b. I2C address (0xD2 or 0xD4)
c. Part active or powered-down
d. Spread-spectrum setting (-0.25%, -0.5%, or OFF)
e. Output frequency (100, 133, or 200 MHz)
6. Set +5V Select switch (SW3) based on how you will power the EVB, either via USB or via external +5 V supply.
7. Connect power, either via USB port or external +5 V power supply as chosen in previous step.
UG277: Si52204-EVB User's Guide
Quick Start—Board Configuration Check List
silabs.com | Building a more connected world. Rev. 0.1 | 11
9. Si52204-EVB Schematic
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SW2
SiLabs Logo
Si52204 - EVB
4-OUTPUT - QFN32
Rev 1.0 - ____________
U1
POWER VDD
6 BOARD LAYERS:
MECHANICAL & FABRICATION BOARD MATERIAL:
and 0.5oz thickness for RF signal layers
- Use FR-406, DK=3.9
62 mil
Total Board Thickness:
<-------------------- 3000mil --------------------->
U2
U8
DIFF_0
J13
SIGNAL + GND FLOOD (COPLANAR)
SIGNAL + GND FLOOD (COPLANAR)
GROUND
GROUND
J6
DIFF_0b
DIFF_1
DIFF_1b
DIFF_2b
DIFF_2
DIFF_3DIFF_3b
U3 U4 U5 U6
REF_SA
J11
J12
+5V
GND
SW1
U7
<-500mil> <---750mil-->
<---750mil-->
<-500mil> <-500mil><---750mil-->
<-500mil->
<-500mil-> <---750mil--><-500mil->
SW3
<-500mil->
CLKIN
J14
JP7
J1 J10 J8
J4
J9
J7
J5J3J2
XOUT
J15
<-500mil->
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SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
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UG277: Si52204-EVB User's Guide
Si52204-EVB Schematic
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DUT CONNECTIONS
Toe_Tag
VDDXVDDA VDD VDD_IO VDDR
VDDXVDDRVDD_IO VDDVDDA
XOUT5
REF_SA 6,9
XIN_CLKIN5
SDA9
SCLK9
DIFF_3b 7
DIFF_3 7
DIFF_2b 7
DIFF_2 7
DIFF_1b 7
DIFF_1 7
DIFF_0b 7
DIFF_0 7
FS9
OE_0b9
OE_1b9
OE_2b9
OE_3b9
PWRGD_PWRDNb9
SS_EN9
Title
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Title
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SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
DUT Connections
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C2
1uF
C11
1uF
MH21
C12
0.1uF
U1
Si52204-32QFN
SS_EN
1
PWRGD/PWRDNb
2
XIN/CLKIN
3
XOUT
4
VDDR
6
REF/SA
7
VSSR
8
FS
11
DIFF_0
12
DIFF_0b
13
OE_0b
14
VDD_IO1
15
OE_1b
16
DIFF_1 17
NC1 20
VDD1 19
DIFF_1b 18
DIFF_2 21
DIFF_2b 22
OE_2b 23
VDD_IO2 24
DIFF_3 25
DIFF_3b 26
OE_3b 27
NC2 28
VDD2 29
GNDA 32
NC3 30
VDDA 31
VDDX
5
ePAD
33
SCLK
10 SDA
9
C4
0.1uF
C5
1uF
C1
0.1uF
C9
0.1uF
C10
1uF
C7
0.1uF
MH2
C8
0.1uF
C3
0.1uF
C6
1uF
MH3 MH4MH1
UG277: Si52204-EVB User's Guide
Si52204-EVB Schematic
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
100 mA Adjustable Voltage Regulator
1.8V
1.8V
1.8V
1.8V
SWITCH CLOSED = 1.8V
SWITCH OPEN = 1.5V
ESR=1.0 ESR=1.0
ESR=1.0ESR=1.0
+/-100ppm
+/-100ppm +/-100ppm
+/-100ppm
0.6663V
0.6663V
0.6663V
0.6663V
+/-100ppm
0.6663V
1.8V
ESR=1.0
CLOSED
OPEN
Text in BLUE should
be added to TOP SILK
Vo=0.6663 x (1 + R1/R2)
R1
R2
Group JP1:JP6 together
Identify Pin1 of all jumpers and IC's!
CORE VOLTAGE SELECT
VDDX VDDR
VDDVDDA
5V
5V
5V
5V
5V
VDD_AUX
Title
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Output Voltage Regulators
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Title
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Date: Sheet of
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SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
Output Voltage Regulators
B
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Title
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Output Voltage Regulators
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R3
10K
R7
10K
R14
8.06K
TP7
NI
VDDX
R11
21.5K
R16
1
JS13
Jumper Shunt
U3
TPS76201
IN
1
GND
2
EN
3
FB 4
OUT 5
TP8
NI
VDDR_PIN
SW1
SW1-DIP-SMT
1 2
C28
0.01uF
R13
21.5K
C19
0.01uF
+
C15
4.7uF
+
C20
4.7uF
+
C30
4.7uF
R2
1
TP6
NI
VDDX_PIN
TP9
NI
VDDR
U6
TPS76201
IN
1
GND
2
EN
3
FB 4
OUT 5
JS14
Jumper Shunt
C16
0.01uF
R1
1
R24
8.06K
JP5
U2
TPS76201
IN
1
GND
2
EN
3
FB 4
OUT 5
+
C14
4.7uF
+
C26
4.7uF
C25
0.01uF
C32
1uF
C23
1uF
+
C27
4.7uF
JP4
R23
21.5K
JS10
Jumper Shunt
R10
8.06K
TP5
NI
VDD
+
C17
4.7uF
R4
10K
R18
10K
R15
1
+
C21
4.7uF
U4
TPS76201
IN
1
GND
2
EN
3
FB 4
OUT 5
C13
0.01uF
JS11
Jumper Shunt
TP4
NI
VDD_PIN
C31
1uF
JP2
R22
8.06K
TP1
NI
VDDA_PIN
R17
10K
C22
1uF
R9
21.5K
TP2
NI
VDDA
JP1
+
C29
4.7uF
JP3
TP3
NI
VDD_AUX
+
C18
4.7uF
R21
21.5K
R12
8.06K JS12
Jumper Shunt
C24
1uF
U5
TPS76201
IN
1
GND
2
EN
3
FB 4
OUT 5
UG277: Si52204-EVB User's Guide
Si52204-EVB Schematic
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
100 mA Adjustable Voltage Regulator
1.5V
1.2V
1.8V
ESR=1.0
+/-100ppm
0.6663V
Vo=0.6663 x (1 + R1/R2)
R1
R2
CLOSEDOPEN
IO VOLTAGE SELECT
VDD_IO
5V
Title
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SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
Other Voltage Regulators
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Title
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R31
20K
JP6
+
C35
4.7uF
R30
33K
TP11
NI
VDD_IO
SW2
SW3-DIP-SMT
1
2
3 4
5
6
R29
13.3K
JS15
Jumper ShuntR28
8.25K
+
C34
4.7uF
U7
TPS76201
IN
1
GND
2
EN
3
FB 4
OUT 5C33
0.01uF
TP10
NI
VDD_IO_PIN
C36
1uF
R25
1
R26
10K
UG277: Si52204-EVB User's Guide
Si52204-EVB Schematic
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Crystal/Input Clock Connections
90 degree placement ->
<- Plane cutout
Traces are just an illustration!
Cut planes underneath crystal
to reduce capacitive coupling!
<--------- X ---------->
- Place crystal as close
to U1 pins as possible!
- Route signals carefully,
match trace lengths!
Keep X as short as possible
by placing all components
close to the XA/XB pins
* CRYSTAL FOOTPRINT:
Please create a footprint with
pads that can accommodate
the following crystal sizes:
3.2 x 5.0 mm
3.2 x 2.5 mm
2.5 x 2.0 mm
J1
<- To DUT
R64
R33
U8
C39
<GND>
C38C40
R32
R34
R32 and R64 should
share a pad and be
placed right at DUT
pin XIN
J15
R59
C53
<GND>
R65
Place R33 (R59) and C39
(C53) close to R64 (R65)
Bottom Layer
Bottom Layer
Dashed lines/squares
indicate bottom layer
traces/pads
Keep R33,C39,R59,C53
as close to DUT as possible
Keep U8 as close to
DUT as possible
Make sure that layer
above bottom layer (5)
is solid GND for length
of diff'l trace
XIN_CLKIN 2
XOUT 2
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Date: Sheet of
400 W Cesar Chavez
Austin, TX 78701
SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
Crystal Input Connections
B
5 9Monday, May 01, 2017
.
J1
SMA
CLKIN
R34
0
J15
SMA
XOUT
C39
0.1uF
NI
R64 0
NI
C53
0.1uF
NI
R33
49.9
NI
R65 0
NI
25MHz
U8
XTAL1
1
GND
2
XTAL2 3
GND 4
C40
18pF
R59
49.9
NI
C38
18pF
R32 0
UG277: Si52204-EVB User's Guide
Si52204-EVB Schematic
silabs.com | Building a more connected world. Rev. 0.1 | 16
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GND plane cutout ->
<- Board edge
OUTPUT CONNECTIONS, PART 1
SMA FOOTPRINT NOTE:
Make sure pad for center pin on SMA matches exactly
the actual width of the center pin in order to improve performance
A sufficient number of via holes connected
to ground should be used around all input/output
traces!
Flood top and bottom layers with copper as shown
OUTPUT SIGNALS LAYOUT NOTES - APPLIES TO THIS PAGE AND NEXT PAGE AS WELL!
(Refer to image on left):
- ROUTING: route each differential pair losely coupled. Serpentine to length and preserve
symmetry on diff. pair. Keep distance b/w serpentine traces
at least 5w apart and use arcs rather than 45's
- IMPEDANCE: all traces to have 50 ohms of controlled impedance
the SMA connectors as needed
- GEOMETRY: maintain the trace symmetry across all output differential pairs
- TOPOLOGY: use microstip for all traces
- COMPONENT PLACEMENT:
C42 C45
<----------- 5" total --------->
J6
J4
R38
R40
U1
RS
CL
<- This is the only single-ended output
Place RS as close to the DUT pin as possible
Make total trace length = 5" (from DUT pin to CLoad);
Place isolation resistor right by load cap;
C46 C49
J9
J7
R41
R43
DIFF_2
DIFF_1
PLACE PAD PCB1
~150 MILS FROM PAD
PCB10 AND PLACE PCB10
B/W C41 AND R36; R36
SHOULD BE CLOSE TO C41
REF_SA2,9
Title
Size Document Number Rev
Date: Sheet of
400 W Cesar Chavez
Austin, TX 78701
SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
Output Connections
B
6 9Monday, May 01, 2017
.
Title
Size Document Number Rev
Date: Sheet of
400 W Cesar Chavez
Austin, TX 78701
SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
Output Connections
B
6 9Monday, May 01, 2017
.
Title
Size Document Number Rev
Date: Sheet of
400 W Cesar Chavez
Austin, TX 78701
SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
Output Connections
B
6 9Monday, May 01, 2017
.
PCB1
TP-PAD
GND
R35
10.0
J2
SMA
PCB10
C41
4.7pF
R36
953
UG277: Si52204-EVB User's Guide
Si52204-EVB Schematic
silabs.com | Building a more connected world. Rev. 0.1 | 17
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
OUTPUT CONNECTIONS
<-----------5 INCHES ----------->
DUT
PLACE R37 (R39)
CLOSE TO C43 (C44)
AND KEEP DISTANCE
B/W PCB11 AND PCB12
<180 MILS
(SIMILARLY FOR THE
OTHER OUTPUTS). (SEE
DGM ON PAGE 6)
<-----------5 INCHES ----------->
DUT
<-----------5 INCHES ----------->
DUT
<-----------5 INCHES ----------->
DUT
<-----------5 INCHES ----------->
DUT
<-----------5 INCHES ----------->
DUT
<-----------5 INCHES ----------->
DUT
<-----------5 INCHES ----------->
DUT
PLACE CAP PAD
IN-TRACE (NO STUB)
SEE DGM ON
PREVIOUS PAGE
PLACE PAD PCB2 (PCB4)
~150 MILS FROM PAD
PCB11 (PCB12) AND PLACE
PCB11 (PCB12) B/W C43 (C44)
AND R37 (R39);
DIFF_02
DIFF_0b2
DIFF_12
DIFF_1b2
DIFF_22
DIFF_2b2
DIFF_32
DIFF_3b2
Title
Size Document Number Rev
Date: Sheet of
400 W Cesar Chavez
Austin, TX 78701
SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
Output Connections
B
7 9Monday, May 01, 2017
.
Title
Size Document Number Rev
Date: Sheet of
400 W Cesar Chavez
Austin, TX 78701
SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
Output Connections
B
7 9Monday, May 01, 2017
.
Title
Size Document Number Rev
Date: Sheet of
400 W Cesar Chavez
Austin, TX 78701
SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
Output Connections
B
7 9Monday, May 01, 2017
.
C48
2pF
J6
SMA DIFF_2b
C42
2pF
PCB6
TP-PAD
GND
PCB7
TP-PAD
GND
R41
953
C45
2pF
PCB4
TP-PAD
GND
R42
953
PCB13
R39
953
PCB3
TP-PAD
GND
PCB14
R43
953
J7
SMA DIFF_1
C44
2pF
PCB8
TP-PAD
GND
PCB11
R38
953
R44
953
J3
SMA DIFF_0
J8
SMA DIFF_3
PCB9
TP-PAD
GND
J9
SMA DIFF_1b
C43
2pF
C46
2pF
PCB17
R40
953
PCB18
J10
SMA DIFF_3b
PCB5
TP-PAD
GND
PCB15
J4
SMA DIFF_2
C47
2pF
PCB12
PCB16
R37
953
C49
2pF
PCB2
TP-PAD
GND
J5
SMA DIFF_0b
UG277: Si52204-EVB User's Guide
Si52204-EVB Schematic
silabs.com | Building a more connected world. Rev. 0.1 | 18
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1-2 USB +5V
2-3 External +5V
+5V Input Select
External Power
MAIN
5V_USB
5V
Title
Size Document Number Rev
Date: Sheet of
400 W Cesar Chavez
Austin, TX 78701
SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
External Power
B
8 9Monday, May 01, 2017
.
Title
Size Document Number Rev
Date: Sheet of
400 W Cesar Chavez
Austin, TX 78701
SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
External Power
B
8 9Monday, May 01, 2017
.
Title
Size Document Number Rev
Date: Sheet of
400 W Cesar Chavez
Austin, TX 78701
SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
External Power
B
8 9Monday, May 01, 2017
.
J13
USB Type B
+V 1
D- 2
D+ 3
GND 4
SH
5SH
6
SW3
SW_SLIDE_2POS
+5V_SELECT
1
2
3
D3
Blue
5VUSB
C52
1uF
D1
Green
+5V_EXT
C51
0.1uF
FB1 22 Ohm
D2
SP0503BAHT
TP12
+5V
RED
NI
R45
6.8K
FB2 22 Ohm
J11
BND_POST
+5V
TP13
GND
BLACK
NI
J12
BND_POST
GND
R48
8.06K
C50
1uF
UG277: Si52204-EVB User's Guide
Si52204-EVB Schematic
silabs.com | Building a more connected world. Rev. 0.1 | 19
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DC Inputs/I2C Access
OE_0b
OE_1b
OE_2b
OE_3b
REF_SA
PWRGD
SS_EN
FS
LO HI
GND
SDA
SCL
VDD_AUX
VDD_AUX
OE_0b2
OE_2b2
OE_3b2
REF_SA2,6
PWRGD_PWRDNb2
OE_1b2
SS_EN2
FS2
SDA2
SCLK2
Title
Size Document Number Rev
Date: Sheet of
400 W Cesar Chavez
Austin, TX 78701
SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
DC Inputs/I2C Access
B
9 9Friday, May 05, 2017
.
Title
Size Document Number Rev
Date: Sheet of
400 W Cesar Chavez
Austin, TX 78701
SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
DC Inputs/I2C Access
B
9 9Friday, May 05, 2017
.
Title
Size Document Number Rev
Date: Sheet of
400 W Cesar Chavez
Austin, TX 78701
SI52200_32-PIN_QFN_CUSTOMER_EVB_R2P0 2.0
DC Inputs/I2C Access
B
9 9Friday, May 05, 2017
.
R52
1K
R5810K
R561K
JP7
HEADER 1x3
1
2
3
JS3
Jumper Shunt
JS9
Jumper Shunt
JS2
Jumper Shunt
R60
1K
R51
1K
JS4
Jumper Shunt
JS6
Jumper Shunt
J14
HEADER 8x3
1A
1B
1C
2A
2B
2C
3A
3B
3C
4A
4B
4C
5A
5B
5C
6A
6B
6C
7A
7B
7C
8A
8B
8C
JS8
Jumper Shunt
JS7
Jumper Shunt
R491K
R63
1K
R5510K
R501K
R61
1K
R62
1K
R5710K
R531K
JS5
Jumper Shunt
R541K
UG277: Si52204-EVB User's Guide
Si52204-EVB Schematic
silabs.com | Building a more connected world. Rev. 0.1 | 20
10. Bill of Materials
UG277: Si52204-EVB User's Guide
Bill of Materials
silabs.com | Building a more connected world. Rev. 0.1 | 21
11. Appendix: Typical Waveplots
The plots displayed in this section are provided to give the user an example of what they should expect to observe when measuring
signals on this evaluation board with a good lab setup. These plots were taken on signals probed on-board using a Keysight 5 GHz
differential probe (Ag 1132A) (for the differential waveforms), and Keysight 2 GHz high-impedance FET probe (Keysight N2796A) (for
single-ended waveforms) and an 8 GHz bandwidth oscilloscope (Keysight Ag DSA90804A).
11.1 Reference Clock Output (Differential waveform)
UG277: Si52204-EVB User's Guide
Appendix: Typical Waveplots
silabs.com | Building a more connected world. Rev. 0.1 | 22
11.2 Differential Clock (DIFF_0) Output (Differential waveform)
UG277: Si52204-EVB User's Guide
Appendix: Typical Waveplots
silabs.com | Building a more connected world. Rev. 0.1 | 23
11.3 Differential Clock (DIFF_0) Crossing Voltage (100MHz) (Single-ended waveform)
UG277: Si52204-EVB User's Guide
Appendix: Typical Waveplots
silabs.com | Building a more connected world. Rev. 0.1 | 24
11.4 Differential Clock (DIFF_0) Crossing Voltage (200MHz) (Single-ended waveform)
UG277: Si52204-EVB User's Guide
Appendix: Typical Waveplots
silabs.com | Building a more connected world. Rev. 0.1 | 25
11.5 Spread Spectrum Clock @-0.5% spread (Differential waveform)
11.6 Spread Spectrum Clock @-0.25% spread (Differential waveform)
UG277: Si52204-EVB User's Guide
Appendix: Typical Waveplots
silabs.com | Building a more connected world. Rev. 0.1 | 26
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