January 1995 3
Philips Semiconductors Product specification
Quadruple 2-input NAND gate HEF4011B
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb =25°C; CL= 50 pF; input transition times ≤20 ns
VDD
VSYMBOL TYP MAX TYPICAL EXTRAPOLATION
FORMULA
Propagation delays 5 55 110 ns 28 ns +(0,55 ns/pF) CL
In→On10 tPHL; tPLH 25 45 ns 14 ns +(0,23 ns/pF) CL
15 20 35 ns 12 ns +(0,16 ns/pF) CL
Output transition times 5 60 120 ns 10 ns +(1,0 ns/pF) CL
HIGH to LOW 10 tTHL 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
5 60 120 ns 10 ns +(1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
VDD
VTYPICAL FORMULA FOR P (µW)
Dynamic power 5 1300 fi+∑(foCL)×VDD2where
dissipation per 10 6000 fi+∑(foCL)×VDD2fi= input freq. (MHz)
package (P) 15 20 100 fi+∑(foCL)×VDD2fo= output freq. (MHz)
CL= load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)