IRL530NS/L
HEXFET® Power MOSFET
PD - 91349C
lAdvanced Process Technology
lSurface Mount (IRL530NS)
lLow-profile through-hole (IRL530NL)
l175°C Operating Temperature
lFast Switching
lFully Avalanche Rated
Absolute Maximum Ratings
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRL530NL) is available for low-
profile applications.
Description
VDSS =100V
RDS(on) = 0.10Ω
ID = 17A
2
D P a k
TO-262
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.9
RθJA Junction-to-Ambient ( PCB Mounted,steady-state)** – – – 4 0
Thermal Resistance
°C/W
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V17
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V12 A
IDM Pulsed Drain Current  60
PD @TA = 25°C Power Dissipation 3.8 W
PD @TC = 25°C Power Dissipation 79 W
Linear Derating Factor 0.53 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy  150 mJ
IAR Avalanche Current9.0 A
EAR Repetitive Avalanche Energy7.9 mJ
dv/dt Peak Diode Recovery dv/dt  5.0 V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case ) °C
S
D
G
11
1/09/04
IRL530NS/L
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) 
––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 9.0A, VGS = 0V
trr Reverse Recovery Time ––– 140 210 n s TJ = 25°C, IF = 9.0A
Qrr Reverse Recovery Charge ––– 740 1100 nC di/dt = 100A/µs 
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Starting TJ = 25°C, L = 3.7mH
RG = 25Ω, IAS = 9.0A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Notes:
ISD ≤ 9.0A, di/dt ≤ 540A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Uses IRL530N data and test conditions
** When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended soldering techniques refer to application note #AN-994.
Source-Drain Ratings and Characteristics
S
D
G
17
60 A
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 10 0 ––– –– – V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– 0.122 ––– V/°C Reference to 25°C, ID = 1mA
––– ––– 0.100 VGS = 10V, ID = 9.0A
––– ––– 0.120 ΩVGS = 5.0V, ID = 9.0A
––– ––– 0.150 VGS = 4.0V, ID = 8.0A
VGS(th) Gate Threshold Voltage 1.0 –– – 2.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 7.7 ––– ––– S VDS = 50V, ID = 9.0A
––– ––– 25 VDS = 100V, VGS = 0V
––– ––– 250 VDS = 80V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 10 0 nA VGS = 16V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V
QgTotal Gate Charge –– – –– – 34 ID = 9.0A
Qgs Gate-to-Source Charge ––– ––– 4.8 nC VDS = 80V
Qgd Gate-to-Drain ("Miller") Charge ––– – –– 20 VGS = 5.0V, See Fig. 6 and 13 
td(on) Turn-On Delay Time ––– 7.2 ––– VDD = 50V
trRise Time ––– 53 ––– ID = 9.0A
td(off) Turn-Off Delay Time ––– 30 ––– RG = 6.0Ω, VGS = 5.0V
tfFall Time ––– 26 ––– RD = 5.5Ω, See Fig. 10 
Between lead,
––– ––– and center of die contact
Ciss Input Capacitance ––– 800 ––– VGS = 0V
Coss Output Capacitance ––– 160 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 90 ––– ƒ = 1.0MHz, See Fig. 5
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
IGSS
IDSS Drain-to-Source Leakage Current
RDS(on) Static Drain-to-Source On-Resistance
LSInternal Source Inductance 7.5
ns
nH
A
IRL530NS/L
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics
0.1
1
10
100
0.1 1 10 100
I , Drain-to-Source Current (A)
D
V , Dra in -t o-So u rc e Vo lta
g
e
(
V
)
DS
A
20
µ
s PU LSE WIDTH
T = 25°C
J
VGS
TOP 15V
1 2V
1 0V
8 .0V
6 .0V
4 .0V
3 .0V
BOTTOM 2.5V
2.5V
0.1
1
10
100
0.1 1 10 100
I , Drain-to-Source Current (A)
D
V , Dra in -t o-So u rc e Vo lta
g
e
(
V
)
DS
A
20
µ
s PU LSE WIDTH
T = 175°C
VGS
TOP 15V
1 2V
1 0V
8 .0V
6 .0V
4 .0V
3 .0V
BOTTOM 2.5V
2.5V
J
0.1
1
10
100
2345678910
T = 25°C
J
GS
V , G ate -to -So u rce V olta
g
e (V)
D
I , D ra in -to-S o urc e C urr en t ( A )
V = 50 V
20µs PULSE WIDTH
T = 175°C
J
A
DS
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
J
T , J u nc tion T emp eratur e (°C )
R , D ra in-to -S o u rc e O n Re sis ta nc e
DS(on)
(Normalized)
V = 1 0V
GS
A
I = 1 5 A
D
IRL530NS/L
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
0
3
6
9
12
15
0 1020304050
Q , T o ta l G a te Ch a r
g
e
(
nC
)
G
V , Ga te -to-So u rc e Vo ltag e (V)
GS
V = 8 0 V
V = 5 0 V
V = 2 0 V
DS
DS
DS
A
FOR TEST CIRCUIT
SE E F IG U RE 1 3
I = 9 . 0A
D
1
10
100
0.4 0.6 0.8 1.0 1.2 1.4
T = 25°C
J
V = 0V
GS
V , S ourc e-to-D rain V oltage (V )
I , Re ve rs e D ra in Curre n t (A )
SD
SD
A
T = 17 5°C
J
1
10
100
1000
1 10 100 1000
V , Dra in -to -S ou rc e Vo lta
g
e
(
V
)
DS
I , Dra in C u rre nt (A)
OP ERA T IO N IN T H IS A R EA L IM IT E D
B Y R
D
DS(on)
10µs
100µs
1ms
10ms
A
T = 25 °C
T = 17 5 °C
Sin
g
le Pulse
C
J
0
200
400
600
800
1000
1200
1400
1 10 100
C , Capacitance (pF)
DS
V , Dra in -to -So u rc e Vo lt a
g
e
(
V
)
A
V = 0V, f = 1 M H z
C = C + C , C S H O RTED
C = C
C = C + C
GS
is s gs gd ds
rss gd
os s ds g d
C
iss
C
oss
C
rss
IRL530NS/L
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RGD.U.T.
5.0V
+
-
VDD
25 50 75 100 125 150 175
0
5
10
15
20
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
IRL530NS/L
Fig 12a. Unclamped Inductive Test Circuit
Fig 12b. Unclamped Inductive Waveforms
V
DS
L
D.U.T.
V
DD
I
AS
t
p
0.01Ω
R
G
+
-
t
p
V
DS
I
AS
V
DD
V
(BR)DSS
5.0 V
Q
G
Q
GS
Q
GD
V
G
Charge
Fig 13a. Basic Gate Charge Waveform
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 13b. Gate Charge Test Circuit
5.0 V
0
50
100
150
200
250
300
350
25 50 75 100 125 150 175
J
E , S in gle P ulse Avalanc he E n ergy (m J )
AS
A
Startin
g
T , Junction Tem perature
(
°C
)
V = 25 V
I
TOP 3 .7A
6 .4A
BO TTOM 9.0A
DD
D
IRL530NS/L
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFETS
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
IRL530NS/L
D2Pak Part Marking Information
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For GB Production
D2Pak Package Outline
IRL530NS/L
TO-262 Package Outline
TO-262 Part Marking Information
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IGBT
1- GATE
2- COLLEC-
TOR
IRL530NS/L
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421)
16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 01/04
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/