Preliminary Data Sheet V2.2 - Infineon Technologies

ICs for Communications

PC I I nt er face f or Telephony/Data Appl icat i on s

PITA-2

PSB 4610 Ver sion 2.2

Prel im i nar y Dat a Sheet 01.00 DS 1

For questions on technology, deliv ery and prices please contact the Infineon Technologies Offices

in Germany or the Infi neon Technologies Companies and Representatives worldwide:

see our webpage at http://www.infineon.com

PSB 4610

Revision History: Current Version: 01.00

Previous V ersion: PSB 4610 Version 2.1 (12.99)

Page

(i n previous

Version)

Page

(i n current

Version)

Subjects (major changes since last revision)

181 default value (40h) 1221 0001 changed to 1222 0001

ABM®, AO P®, A RCO FI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EP IC®-1, EPI C ®-S, ELIC®, FAL C®54,

FALC®56, F ALC ®-E1, F ALC ®-LH, IDEC®, IOM®, IO M®-1, IOM®-2, I PAT ®-2 , ISA C®-P, I SAC ®-S, ISAC®-S TE,

ISAC®-P TE , ITAC®, IWE®, M U SAC®-A, OC T AT ®-P, QUAT®-S, SI C AT ®, SICO FI®, SICOFI®-2, SICOFI®-4,

SICOFI®-4µC, SLI C OF I® are regis t ered t radem ark s of I nf ineon T ec hnologies AG.

ACE™, ASM™, ASP™, PO TSWIRE™, QuadF ALC™, SCO UT ™ are t rademark s of Inf ineon T echnologies AG.

dition 0 1.00

P ublis hed by Inf ineon Tec hnologies AG

TR,

B al anstr aß e 73,

81541 M ü n ch en

A ll Rig hts Re ser ve d.

At t ent ion plea se !

As f ar as pat ents or ot her rights of t hird part ies are c onc erned, liabilit y is only as sum ed for c om ponent s , not f or

applicat ions, proc es s es and c ircuit s im plem ent ed w it hin c om ponents or as s em blies .

T he inf ormat ion des c ribes t he t y pe of com ponent and s hall not be c ons idered as ass ured charac t erist ic s .

T erm s of deliv ery and right s t o c hange des ign res erv ed.

Due to technical requirements components may contain dangerous substances. For information on the types in

ques t ion pleas e c ont ac t y our neares t I nfineon T ec hnologies Of f ic e.

I nf ineon T ec hnologies AG is an approved C EC C manuf ac t urer.

Packing

Pleas e us e t he rec y c ling operators k now n to you. W e c an als o help y ou – get in t ouc h with your neares t s ales

of f ic e. By agreem ent w e w ill t ak e pac k ing mat erial bac k , if it is s orted. You m us t bear t he c os ts of t rans port.

For pac king material that is returned t o us unsorted or which we are not obliged to accept , we shall have t o invoic e

you for an y co sts incu rre d.

Com ponents us ed in life- support dev ic es or sy st em s m ust be e xpres sly aut horized for suc h purpos e!

Critical components 1 of t he I nf ineon Tec hnologies AG, may only be used in lif e-support devices or sy stems2 wi th

t he expres s w ritt en approv al of t he I nf ineon T ec hnologies AG.

1 A critica l co mpo ne nt is a co mpo ne nt used i n a life- supp or t de vice or system wh ose fail ure ca n re ason ab ly b e

ex pec t ed t o c aus e t he f ailure of t hat lif e-s upport dev ic e or sy s t em, or to aff ect its s af et y or eff ec tiv eness of t hat

de vice or system.

2 Life su ppo rt devi ce s o r syste ms a re i nten ded (a) to b e imp lan te d in the human b ody, or (b ) to sup por t a nd/o r

maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be en-

dangered.

PSB 4610

Preliminary Data Sheet III 01.00

Organizat ion of thi s Data Sheet

•Chap ter 1, Feat ures

Descr ibes t he general feat ures of the PIT A- 2.

•Chap ter 2, Typical Applications with the PITA-2

Des c ribes ty pic al applic ations that c an be r ealiz ed with the PITA -2.

•Chap ter 3, Con stru c ti on of th e PIT A-2

S hows a block diagr am and des c ribes the interfac es and their func tions .

•Chap ter 4, Communicatio n w ith the P IT A-2

Des c ribes the P CI bus inter face of the P ITA- 2.

•Chap ter 5, Communicatio n w ith Ext ern al Co mponen ts

Giv es a general des cription of the loc al bus interfaces of the PITA -2.

•Chapter 6, Power Management

Descr ibes t he power managem ent functions ( inc luding D3cold) of the PIT A- 2.

•Chapt er 7, Reset and Int errupt s

Des c ribes the r equir ement s for r eset and the behaviour of the PIT A-2.

•C ha pt e r 8 , Pi nning

Descr ibes t he pins, types of pins and the charac teristics of the interfaces.

•Chap ter 9, Electrical Characterist ics

Des c ribes elec tr ic al maxim um ratings and elec tr ic al c haracteristic s.

•Chap ter 10, Package O utlines

Des c ribes the pac kage outlines.

•Chapt er 11, Co nfigu rat ion S pace Register of the P IT A- 2

Contains descr iptions of the C onfiguration Space Registers of the PIT A -2.

•Chap ter 12, Internal Register of th e P ITA

Contains descr iptions of the I nternal Registers of the P ITA- 2.

•Chap ter 13, Abbreviatio ns

Des c ribes abbr eviations occur ing in this dat a s heet.

•Chap ter 14, Index

PSB 4610

Preliminary Data Sheet IV 01.00

Im portant Notes about this Data Sheet

________________________________________

Wha t’s New?

The organization of the struc tur e follows the guidelines of Inform ation Mapping®.

________________________________________

What is Information Mapping®?

This is a res ear c h bas ed method for the

– analysis

– structure

– presentation

of us er -orientated manuals.

________________________________________

Major Changes

Instead of the used chapter s with mono caus al desc riptions you now get

– all inform ation

– for a s cope

– under the corres ponding heading.

________________________________________

The Intention

This Data Sheet is intended to be

– easily survey ed

– increas ingly readable

– c ustomized applic able

– practice-orientated

– offering the quic kest poss ible way to the required informat ion.

________________________________________

PSB 4610
Table of  Content s Page
Semiconductor Group  V Preliminary Data Sheet 01.00
1F eatu res   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2Ty pic a l A pplic a tions with t he  PITA-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3C ons truc tion of  the PITA-2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4Co mmu n ica t io n w ith  the PI T A-2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 0
.1 PC I C o n fi g u r a t i o n  Sp a ce   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1
1.1 Inform ation about t he P CI Configur ation Spac e   .  . . .  . . . . . . . . . . . . . . .12
.1 .2 Access  to  th e  PCI C o n fi g u rati o n  Spa ce . . . . . . . . . . . . . . . . . . . . . . . . . .15
.1 .3 Ba s e  Ad d r e ss R e g i ste r  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6
1.4 Other  Regis ters  of t he P CI Configur ation Spac e .  . . .  . . . . . . . . . . . . . . .20
.2 PC I M a ste r/Ta rg e t C o n tr o l l e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2
2.1 S upported PCI Commands   . . . . . . . . . . . . . . . . . . . . . .  .  . . . . . . . . .  . . .23
2.2 Trans action Ty pe Bur st Read  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
.2 .3 Tr a n sa cti o n  Typ e  Bu rst Wr i te   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 7
2.4 Transaction Type Fast Back to Back . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3 Interr upt Contr ol Register - Retry  Counter  . . .  . .  . .  . .  . . .  . . . . . . . . . . . . . .31
5Communicat ion with  External Component s . . . . . . . . . . . . . . . . . . . . . .3 3
.1 Se r i a l D MA In te rfa c e   . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .3 4
.1 .1 D MA  C o n tro ll e r  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 6
1.2 Infor mation about the DMA  Cont roller . . . . . . . . . . . . . . . . . . . . . . . . .  . .37
.1 .3 In te rn a l Re g i ste rs o f th e  DMA  C o n tro ll e r  . . . . . . . . . . . . . . . . . . . . . . . . .4 1
1.4 IOM-2 Mode 1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
1.5 IOM-2 Mode 2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
1.6 IOM-2 Mode 3  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
1.7 IOM - 2 M odes -  S upplem entar y  Des cr iption . .  . .  . . .  . .  . . . . . . . . . . . . . .56
1.8 S ingle Modem  M ode V 2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
1.9 S ingle Modem  M ode A LIS  V3.X  . . . . . . . . . . . . . . . . . .  .  . . . . . . . . . . . .65
1.10 Dual Modem /M odem+V oice M ode  . . . . . . . . . . . . . . . . . . . . . . . . .  . . . .73
1.11 Loop Bac k M ode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .76
.2 Pa r a l le l  In te rfa ce   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 8
.2 .1 AL E  a ft e r  Syste m R e se t  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1
2.2 ALE after internal Software Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
2.3 ALE  after  set ting t he P ar allel Interface M ode Bit .  . .  . .  . . . . . . . . . . . . . .83
2.4 Non Multiplexed Mode ( Write Trans action)  .  . .  . .  . .  . . . . . . . . . . . . . . . .84
2.5 Non Multiplexed Mode ( Read Trans ac tion) . . .  . .  . .  . . . . . . . . . . . . . . . .86
2.6 Multiplexed Mode (Wr ite Transaction) .  . . .  . .  . .  . . .  . .  . . . . . . . . . . . . . .87
2.7 Multiplexed Mode (Read Tr ans act ion)  . .  . . .  . .  . .  . .  . . . . . . . . . . . . . . . .88
2.8 Tr ansaction Disc onnec t with Tar get A bort . .  . .  . . .  . .  . . . . . . . . . . . . . . .89
2.9 Transaction Termination with Retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
.2 .1 0 Ti m i n g  o f th e  Pa r a l l e l  I n te r fa ce   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4
3 General Purpose I/O I nterf ace . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .97

PSB 4610
Table of  Content s Page
Semiconductor Group  VI Preliminary Data Sheet 01.00
3.1 Infor mation about the GP I /O  Int erfac e  . . . . . . . . . . . . .  . . . . . .  . . . . . . .98
.3 .2 Ti m i n g  o f th e  GP I/O In t e r fa ce  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 0 0
.3 .3 In te rn a l Re g i ste rs o f th e  GP I/O In te rfa ce  . . . . . . . . . . . . . . . . . . . . . . .10 1
3.4 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
3.5 Output Mode   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .109
3.6 Inter rupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . .111
3.7 Usage of the GP  I /O Inter fac e as ALIS V2. 1 Control Inter face  . . . . . . .113
.4 SP I  EEP R O M In te r f a c e  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 5
4.1 Inform ation about t he S PI E E PROM Inter face   . .  . . .  . . . . . . . . . . . . . .116
.4 .2 Ti m i n g  o f th e  SP I  EEPR OM In te rfa ce   . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 9
.4 .3 In te rn a l Re g i ste rs fo r th e  SP I EE PROM Inte rfa ce  . . . . . . . . . . . . . . . . .12 1
6Powe r  M a n a ge me nt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2 3
1 Infor mation about the Power Supply Concept  . . . . . . . . . .  .  . . . . . . . . . . .124
1.1 Inform ation about t he P ower  Management  S tates   .  . .  . . . . . . . . . . . . .126
1.2 Considerations about Power  Cons umpt ion and Repor ting  . . . . . . . . . .128
1.3 Configur ation Spac e Regis ters of the Power  M anagement . . . . . . . . . .131
.1 .4 El e c trica l C h a ra c t e r i stics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4 6
.1 .5 D e si g n  H i n ts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4 7
1.6 Com patibility Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .148
7Reset and  Int errupt s  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4 9
.1 R e se t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4 9
.2 In te rru p ts   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5 2
8Pinning  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5 6
9E lectrical Ch aract eristi cs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6 6
.1 Ab s o l u te  Ma ximu m R a ti n g s  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6 7
.2 D C C h a r a cte ri sti cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6 8
P ackage O ut lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 7 2
Conf iguration Sp ace Regist er o f the PITA- 2 . . . . . . . . . . . . . . . . . . . . .1 7 3
1 .1 D e sc ri p ti o n  o f th e  R e g i s te r Ty p e s  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 7 4
1 .2 C o n fi g u r a ti o n  Sp a c e  R e g i ste rs   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 7 5
3 Regis ter s  which do not occur els ewher e in the Data S heet   . . . . . . . . . . .185
Int ernal Regist er of  th e P ITA   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 9 3
2 .1 D e sc ri p ti o n  o f th e  R e g i s te r Ty p e s  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 9 4
2 .2 In te rn a l R e g i ste r  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 9 5
3 Regis ter s  which do not occur els ewher e in the Data S heet   . . . . . . . . . . .202
Ab b reviatio ns  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 0 5
I n dex  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 0 6

PSB 4610

Preliminary Data Sheet 1 01.00

Introduction

________________________________________

What is the PITA-2?

The PITA-2 is a cost-effective PCI bridge for industrial and communication

applications. I t support s dual cards and D3cold power m anagement.

________________________________________

The PITA-2 can b e used in

•PCI ISDN cards.

•P CI hardware modem s.

•P CI software m odem s.

•Industrial PCI bridge applicat ions.

________________________________________

Inter faces of t he PITA-2

The P ITA-2 off ers the following interfac es:

Interfaces to fin d i n

P CI Mast er/Tar get Controller see chapter 4. 2 on page 22

Ser ial DM A Int erf ac e s ee chapter 5.1 on page 34

P arallel Int erfac e see chapter 5. 2 on page 78

PSB 4610

Preliminary Data Sheet 2 01.00

Gener al Purpos e I/O Interfac e s ee chapter 5.3 on page 97

SP I EEP ROM Int er face s ee chapter 5.4 on page 115

The P ITA-2 off ers the following interfac es:

Interfaces to fin d i n

PSB 4610

Features

Preliminary Data Sheet 3 01.00

1 Features

________________________________________

Comp lia nt with

•P C 99 (P CI r equir ement s)

•PCI B us Specific ation Version 2.2

•PCI P ower Managem ent Specific ation V ersion 1.1

________________________________________

Highlights

•Dual Car d suppor t (3.3V and 5V signaling environment )

•E xtensive Power Management Feat ures ( including D3c old)

•Automatic Configuration with Customer Specific V alues

________________________________________

Interfaces

•P CI Master Target Interface

–PCI 2.2 compliant

–32 bit

–33 MHz

•Ser ial Int erfac e

–Suppor ts IO M -2 M odes

–S upports s er ial inter face to the ALIS chip- set fam ily

–DMA Control le r for seri al communica ti on

–16 word F IF Os for each dir ection

•Para llel Inte rface

with chip select logic s upport ing up to t hree ex ter nal com ponents

•General P urpose I/ O Interface

with interr upt capability

•SPITM Interface

for optional E EP ROM

________________________________________

PSB 4610

Features

Preliminary Data Sheet 4 01.00

________________________________________

Compatibility

•ALI S V2.1 P SB 4596

•ALI S V3.X PSB 4596

•IS DN IOM -2 Component s , e.g.:

–IEC-Q famil y

–S BCX, SB CX- X

•Com ponents consis ting of a parallel multiplexed or non m ultiplex ed Intel/

Infineon Inter fac e, e.g:

–IPA C , IPAC -X

–ISAC-S, I SAC-SX, ISAC-SX TE

________________________________________

PSB 4610

Typ ical Applications wi th the PITA- 2

Preliminary Data Sheet 5 01.00

2 Typical Applications with the PITA-2

________________________________________

Overview

Besides all the applications that require only a simple PCI interface there are

s ome applic ations which the PITA -2 is es pec ially suited for.

Simple applications benefit from the easy configuration of the PITA-2, the

ext ensive power managem ent support and the st andar d interfaces on the loc al

bus side.

Telecommunication applications (e.g modems) benefit from the integrated

mas ter DMA controller as well as the IOM- 2/GCI bus interface.

This allows for easy connection of most telecommunications transceivers and

subs tant ially reduces t he CPU work load.

Fur therm or e the PIT A-2 fully suppor ts D3c old state.

This allows the PC to enter a deep sleep state and still be able to react to an

inc oming c all at the same time.

________________________________________

ISDN-S Inte rf ace Ap plicatio n with the IPAC

PSB 2115

IPAC

PSB 4610

PTA-2

EEPROM

S0-Interface

PC I B u s

u C In terface

SPI

PSB 4610

Typ ical Applications wi th the PITA- 2

Preliminary Data Sheet 6 01.00

________________________________________

IS DN-U Int erface App lication with th e 3PAC and IE C-Q TE

________________________________________

PSB 2113

3PAC

PSB 4610

PTA-2

PC I B u s

uC Interface

EEPROM

SPI

U-Interface

PSB21911

IE C- Q TE

PSB 4610

Construction of the PITA- 2

Preliminary Data Sheet 7 01.00

3 Construction of the PITA-2

________________________________________

Overview

The PITA-2 provides a Peripheral Component Interconnect (PCI) bus interface

which acts as a bridge between the PCI bus and the different controllers and

interfaces:

•The Parallel Inter face Contr ol s upport s up to three ex ternal devic es .

•The S erial Int erface is cont rolled by the internal DMA Controller; s erial

c omm unic ation uses tr ans mit and r ec eiv e FI FOs .

•The EEP ROM for conf igur ation of the PITA - 2 and cust omer spec ific dat a

storage.

•The Gener al Purpos e I/O Int er face.

________________________________________

Block Diagram of the PITA-2

________________________________________

PITA-2

PCI

Controller

EEPROM

Control

Parallel

Interface

Control

Serial

Interface

Control

DMA

Controller

TX FIFO

RX FI FO

SPI-

Interface

Parallel

Microcontroller

Interface

General

Purpose

Interface

Serial

Interface

PCI-Bus

PSB 4610

Construction of the PITA- 2

Preliminary Data Sheet 8 01.00

________________________________________

Descrip tion of t he single Blocks

Name provides supports Notes

PCI Bus

Control •a 32 bit inter fac e

at speeds up to

33 MHz

•Bus Master D MA

capabi lity for data

pass ing through

the Serial

Interface

•Tar get c apability

for data passing

thr ough the

Pa ral le l Int e rfa c e

•D0

•D1

•D2

•D3hot and D3c old

•5V environm ent

•3.3V environm ent

•V aux supply

Parallel

Interface

Control

Chips with a Infineon/

Intel Standard Parallel

Interface, including:

•ISDN devices

•Modem s DSP s

•Industrial devices

Three pr ede-

coded chip s el-

ec t lines

Can be used

for pinst rap-

ping the subsy -

stem/

subsyst em

vendor ID

Serial

Interface

Control

Chips with a serial

interfac e, including:

•Analog v oic e

codecs

•Analog modem

codecs

•IOM-2 devices .

Transmit and

receive data

are held in

separate 16

word FIFOs.

PSB 4610

Construction of the PITA- 2

Preliminary Data Sheet 9 01.00

________________________________________

EEPROM

Control •additional

informati on, such

–the Subsystem

Vendor ID

–extensiv e pow-

er manage-

ment

information

Al l EEPRO Ms wi th

SPI in te rface This is an

optional

feature that

can be used to

customize the

PITA-2

configuration

at s tar t up.

General

Purpose

I/O

Interface

•GP output s

•GP inputs

•GP interrupt

inputs

It can be

configured to

ac t as

•Input pins

•Output pins

•I nterr upt

pins.

Can be used

for

pinst rapping

the s ubsys tem

Descrip tion of t he single Blocks (cont’d)

Name provides supports Notes

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 10 01.00

4 Communication with the PITA- 2

________________________________________

For communication with the PITA-2 the followin g blocks are u sed:

Components Page

P CI Configuration S pace 11

P CI Mas ter/T arget Controller 22

Inter rupt Contr ol Register - Retr y Counter 31

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 11 01.00

4. 1 PCI Configur at ion Space

________________________________________

Overview

Overview Page

Infor mat ion about the PCI Conf iguration Space 12

Ac c ess to the PCI Configur ation Space 15

B ase Address Register 16

Other Regist er s of the P CI Configuration S pac e 20

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 12 01.00

4.1.1 Inf ormat ion abo ut th e PCI Con f igu ratio n Space

________________________________________

Description

The PCI Configuration Space c ontains infor m ation about

•the P CI device

•the r eques ted address s pac e in the mem or y s pace of the P CI system.

The address s pac e includes 64 32-bit r egis ters where the firs t 16 r egis ter s build

the c onfigur ation s pac e header ( 00h- 3Ch, refer to “Conf igur ation Space Register

of the P ITA- 2” on page 173)

________________________________________

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 13 01.00

________________________________________

Construction of the PCI C onfiguration Space

De vice ID

31 23 15 7

Vendor ID

Status Command

Class Code Revision ID

BIST H eader Ty pe Latency Timer Cac h Line Size

Bas e Address R egi s ter 0 (Int er nal R egist ers)

Bas e Address R egister 1 (Paral lel Interface)

Bas e Address R egi s ter 2 (unused)

Bas e Address R egi s ter 3 (unused)

Bas e Address R egi s ter 4 (unused)

Bas e Address R egi s ter 5 (unused)

C ardBus CIS Pointer

Subsystem ID Subsys tem Vendor ID

Ex pansion R OM Bas e Address

Reserved Cap_Ptr

Reserved

Max_Lat Min_Gnt Interrupt Pin In te r r up t Lin e

Pow er M anagem ent Capabili ties Ca pab il ity IDNe xt Ite m P o i nt er

PMCSRBridge SupportData

P ower Data Register 1

P ower Data Register 2

P ower Data Register 3

U nused C onfigurat i on Spac e Regist er s

shaded fields l oaded duri ng

init ializ at ion if EEPROM is connec t ed

58h

54h

50h

4Ch

48h

44h

40h

3Ch

38h

34h

30h

2Ch

28h

24h

20h

1Ch

18h

14h

10h

0Ch

08h

04h

00h

081624

CardB us CI S

5Ch

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 14 01.00

________________________________________

Descrip tion of Register Types

Type Description

PE •r ead only via P CI

•thes e bits ar e initialized by pins trapping dur ing PCI r eset

or by the optional E EPROM

H•r ead only via P CI

•hardwired

RC •read clear via P CI

•thes e bits are set by the internal logic

•thes e bits c an be r ead out and r eset by writing logical “1”

to th e m

•wri ting logical “0” does n’t influence the stat es of these bits

RW •read write via PCI

•these bits can be read out and written via t he P CI bus

E•r ead only via P CI

•thes e bits are initialized to a default value dur ing PCI

r eset or by the optional E E PROM

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 15 01.00

4.1.2 Access to th e PCI Configu ration Space

________________________________________

Description

The PITA-2 supports single 32 bit data transactions for the access to the PCI

Configurat ion Space.

________________________________________

Spe c ial Qualities

Name Description

Subsystem ID •lower 4 bit s c an be set via pins tr apping if no

EEPR O M is u sed

•with external E EPROM the c omplet e 16 bit

v alue can be loaded for the Subsyst em ID

Subs y stem Vendor ID •16 bit ID of the car d manuf ac turer

•has to be applied for at the PCI Spec ial Interes t

Group

•c an be set via pins tr apping dur ing r es et if no

EEPR O M is u sed

•c an be loaded fr om ex ternal EEPROM

CardBus CIS Pointer is not supported by the PITA-2, although it is

implemented in the PCI Configuration Space

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 16 01.00

4.1.3 Base Addr ess Register

________________________________________

Base Add ress Reg isters 0 - 5

Base Ad dress Reg ister Description

B ase Address Register 0 •the lower 12 bits are hardwired t o “0”

•occ upies an address space of 4K

•allows acc es s to the internal r egis ter s of

the PIT A-2

B ase Address Register 1 •the lower 12 bits are hardwired t o “0”

•allows continuous r ead and write

oper ations for acces s to the par allel

interface

•occ upies an address space of 4K

•addr es s s pace is logically s egmented in

4x 1K addr ess blocks

B ase Address Register 2 - 5 not used

Structure of the Add ress Space o f Base Add ress Register 1

Ad dress Space Access to

3FFh - 000h device 1 on the parallel interface ( CS0)

7FFh - 400h device 2 on the parallel interface ( CS1)

BFF h - 800h device 3 on the parallel interface ( CS2)

FFFh - C00h not us ed

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 17 01.00

________________________________________

Co nfig urat io n Sp ace Register: 04h

Bit 1 Memory_Access_Enable

Type RW

Defau lt Val ue 0b

Description Only if thi s bit is set to ‘1’, the PCI interface will react on

trans ac tions to the bas e addres s r egis ter s BAR ( all Bas e

Addres s Registers are defined as m emor y m apped).

Co nfig urat io n Sp ace Register: 10h

Bit 31:12 B ase A ddres s Regis ter 0

Type RW

Defau lt Val ue 0000h

Bit 11:00 B ase A ddres s Regis ter 0

Type H

Value 000h

Description BAR0 c ontains the base addr es s of an addr es s s pac e in the

P CI m ain m emory through whic h the inter nal r egis ter s of t he

PI TA -2 can be acces sed.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 18 01.00

________________________________________

Co nfig urat io n Sp ace Register: 14h

Bit 31:12 B ase A ddres s Regis ter 1

Type RW

Defau lt Val ue 0000h

Bit 11:00 B ase A ddres s Regis ter 1

Type H

Value 000h

Description BA R1 c ontains the base addr ess of a 4-k ilobyte addr ess

s pac e in the PCI main mem ory through which the parallel

m ic ro c ontroller interface of the P ITA- 2 c an be acces s ed.

Co nfig urat io n Sp ace Register: 18h

Bit 31:0 B ase A ddres s Regis ter 2

Type H

Value 0000 0000h

Description Base A ddres s Regis ter 2 is not support ed.

Co nfig urat io n Sp ace Register: 1Ch

Bit 31:0 B ase A ddres s Regis ter 3

Type H

Value 0000 0000h

Description Base A ddres s Regis ter 3 is not support ed.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 19 01.00

________________________________________

Co nfig urat io n Sp ace Register: 20h

Bit 31:0 B ase A ddres s Regis ter 4

Type H

Value 0000 0000h

Description Base A ddres s Regis ter 4 is not support ed.

Co nfig urat io n Sp ace Register: 24h

Bit 31:0 B ase A ddres s Regis ter 5

Type H

Value 0000 0000h

Description Base A ddres s Regis ter 5 is not support ed.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 20 01.00

4.1.4 Oth er Registers of th e PCI Conf igu ration Space

________________________________________

Co nfig urat io n Sp ace Register: 28h

Bit 31:0 Car dBus CIS P ointer

Type H

Value 0000 002C0h

Description Unused

Bit 31:28 ROM_Image_Number

Type H

Value 0000b

Description Unused

Bit 27:3 Address_Space_Offset

Type H

Value 000054h

Description Unused

Bit 2:0 Address_Space_Indicator

Type H

Value 000b

Description Unused

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 21 01.00

________________________________________

Note T he CardB us function is not support ed in this version of the PI TA -2.

________________________________________

Co nfig urat io n Sp ace Register: 2Ch

Bit 31:20 Subs yst em ID

Type E

Defau lt Val ue 000h

Bit 19:16 Subs yst em ID

Type PE

Value Pinstrap value or EE PROM value

Description Ident ifies a spec ific board of a manufacturer on which the

PI TA -2 is used.

The 4 LSBs will be set by pins trapping GP 0-3 during PCI

r es et if no EEPRO M is us ed and the c om plete 16 bit register

c an be loaded if the optional EEP ROM is used.

Bit 15:0 Subs ystem Vendor ID

Type PE

Value Pinstrap value or EE PROM value

Description Mar ks of the Vendor of the board on which the P IT A- 2 is

us ed. This register will be set by pins trapping PA D0- 7 and

P A0- 7 dur ing PCI reset if no E EPROM is used or configur ed

from a connected EEPROM. This ID is alloc ated by the P CI

SIG.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 22 01.00

4. 2 PCI Master/ Target Cont roller

________________________________________

Introduction

The inter face of the PCI bus is repr esented by t he P CI Mas ter/Tar get Controller.

This cont r oller is par t of the PITA- 2.

The PCI M as ter /Target Cont r oller s uppor ts

•sev eral t ypes of trans actions,

•B ase Addr es s Registers 0 and 1.

The PCI M as ter /Target Cont r oller

•has a “Med iu m De vice Sel ect ” behavior,

•tr unc ates bur st tr ansac tions at the end of t he firs t dataphase.

________________________________________

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 23 01.00

4.2.1 Supported PCI Co mman ds

________________________________________

PCI Ma s te r Controller:

P CI Co mmand Transact ion Type

Mem ory Read s ingle t ransfer

Mem ory Wr ite single trans fer

PCI Targ e t Co ntroller:

P CI Co mmand Transact ion Type

Mem ory Read s ingle t ransfer

Mem ory Read Multiple m apped on Mem or y Read

Mem ory Read Line m apped on Mem or y Read

Mem ory Wr ite single trans fer

Mem ory Wr ite and

Invalidate mapped on Memor y Wr ite

Configuration Read single tr ansfer

Configuration Write single tr ansfer

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 24 01.00

________________________________________

Note T he following timing diagrams ar e m eant as an exam ple and s how trans actions

to and from the PCI c onfigur ation s pace.

________________________________________

Overview

Overview Page

Trans action Ty pe B urst Read 25

Trans action Ty pe B urst W rite 27

Trans action Ty pe Fast Bac k to Back 29

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 25 01.00

4.2.2 Tr ansaction T ype Burst Read

________________________________________

Description

•As serting IRDY and STO P at the firs t dataphase leads t o the disc onnection

(Disc onnect- B) of the burst read tr ansact ion by the PI TA -2.

•STOP is asser ted until F RAM E is deas s erted.

•Deass ertion of FRA ME means that STOP and DE VSE L together are

deasserted.

________________________________________

Timing Diagram

________________________________________

ADR DATA

1010

12345678910111213

IDSEL

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 26 01.00

________________________________________

Co nfig urat io n Sp ace Register: 04h

Bit 26:25 DEVSEL_Timing

Type H

Value 01b

Description ‘01’ = medium tim ing, i. e. the DEV SE L signal will be

as s erted f rom the PCI interface with t he s ec ond pos itive PCI

c loc k edge aft er FRA ME was as serted on the PCI bus by a

master.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 27 01.00

4.2.3 Tr ansaction T ype Burst Write

________________________________________

Description

•As serting IRDY and STO P at the firs t dataphase leads t o the disc onnection

( Dis connec t-B ) of the burs t write trans ac tion by the P ITA- 2.

•STOP is asser ted until F RAM E is deas s erted.

•Deass ertion of FRA ME means that STOP and DE VSE L together are

deasserted.

________________________________________

Timing Diagram

________________________________________

ADR DATA1 DATA2

1010

BE1 BE2

12345678910111213

IDSEL

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 28 01.00

________________________________________

Co nfig urat io n Sp ace Register: 04h

Bit 26:25 DEVSEL_Timing

Type H

Value 01b

Description ‘01’ = medium tim ing, i. e. the DEV SE L signal will be

as s erted f rom the PCI interface with t he s ec ond pos itive PCI

c loc k edge aft er FRA ME was as serted on the PCI bus by a

master.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 29 01.00

4.2.4 Tr ansaction T ype Fast Back to Back

________________________________________

Description

With the fast bac k to back trans action a P CI Mast er Controller can per form

•s ever al wr ite tr ans ac tions

•a read trans ac tion as las t tr ans ac tion

without setting the PCI bus to IDLE state in between or releasing the bus to

another master.

A t the end of a trans action:

•The Master as s erts t he FRAM E signal and at the s ame time the TRDY signal

is deasserted.

The transact ion is answered with a RE TRY s ignal by the PITA- 2

•if the parallel interf ace is included in the fas t back to back trans action

•and the par allel int erface is still busy.

________________________________________

Timing Diagram

________________________________________

ADR DATA1 ADR2 DATA2

1011

BE1 1011

BE2

12345678910111213

IDSEL

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 30 01.00

________________________________________

Co nfig urat io n Sp ace Register: 04h

Bit 23 Fast_Back_To_Back_Capability

Type H

Value 1b

Description The P ITA - 2 s uppor ts fas t back- to-bac k .

Bit 9 Fast_Back_To_Back_Enable

Type H

Value 0b

Description The P ITA - 2 its elf gener ates no fast bac k -to-back

transactions.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 31 01.00

4.3 Interr upt Cont rol Register - Ret r y Count er

________________________________________

Description

•Par t of the PCI M aster Target Controller

•Functionality:

1. Disconnec tion of the PCI M aster transac tion wit h Retry by the addres sed PCI

Slave.

2. Dec rement of the c ounter .

3. The Retry _Counter_Int bit is set.

4. An interr upt will be generated if the Ret ry_Counter_Enable bit is set.

5. The P CI Master star ts the tr ansaction again.

________________________________________

Inter nal Register: 00h

Bit 27 RETRY_Counter_Down_Int_En

Type RW

Defau lt Val ue 0b

Description Enable for the Retry _Counter _Down inter rupt bit

Bit 11 Retry_Counter_Int

Type RC

Defau lt Val ue 0b

Description I f a P CI Mas ter initiated tr ans ac tion is r etried f rom a PCI

Slave with the number of retries def ined in the

Retry _Counter r egis ter, this interr upt bit is set by the PCI

interface.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 32 01.00

________________________________________

Inter nal Register:1Ch

Bit 23:16 Retry Count Register

Type RW

Defau lt Val ue 00h

Description Hold the number of retries for a single PCI master

transaction before the PITA-2 will assert an interrupt (if

enabled).

A s an ex ample, if this r egis ter is progr amm ed with the value

4, the PITA-2 will retry a single PCI transaction up to four

tim es as a mas ter befor e it asser ts an interrupt . The PITA-2

will c ontinue to r etry the t ransact ion until it suc ceeds or the

sof tware decides to abort the whole transac tion.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 33 01.00

5 Communication with External Com ponents

________________________________________

Introduction

This c hapter descr ibes the interfaces for communication wit h dev ic es on the local

bus side ( i. e. not the PCI bus side).

________________________________________

Interfaces

Interfaces Page

Serial DMA I nterface 34

Pa ral le l Int e rf ace 78

Gener al P ur pose I/ O Int er face 97

SPI EEPROM Interface 1 1 5

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 34 01.00

5.1 Se ria l DMA Inte rfa ce

________________________________________

Introduction

The s er ial DMA interface is us ed in differ ent modes to tr ans mit and rec eiv e 16 bit/

32 bit data fr am es. These data fram es have differ ent content and s tr uc tur es :

•Data

•Data/V oice and Com mand

•Data/V oice and Com mand for two codec s

•Differ ent time slots on IOM- 2.

________________________________________

Usage of the Serial DMA In terface

The s er ial DMA interface is c loc ked by default with t he internally gener ated cloc k

(DCL = PCI cloc k divided by 40) .

The S er_Clock _S et bit m ust be s et in the Ser ial Clock Select register to ’1’ when

the inter fac e s hall work in ALIS V3. X or IOM -2 mode

Reset ting this bit can result in an unknown behavior of t he FI FOs and the s erial

controller.

The s erial DM A interface is f ully controlled by the DMA c ontroller .

________________________________________

PSB 4610
Communication with External Com ponent s
Preliminary  Data Sheet  35 01.00
 
________________________________________
________________________________________
Overview
Overview Page
DMA Contr oller 36
IOM-2 Mode 1 47
IOM-2 Mode 2 50
IOM-2 Mode 3 53
IOM-2 Modes  - Supplementary Desc ription 56
Single M odem Mode V2.1 61
Single M odem Mode ALIS V3.X 65
Dual Modem /M odem+ Voice Mode 73
Loop Bac k M ode 76

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 36 01.00

5.1.1 DMA Controller

________________________________________

Overview

Overview Page

Infor mat ion about the DMA Cont roller 37

Inter nal Regist ers of the DMA Cont roller 41

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 37 01.00

5.1.2 Inform ation about the DMA Controller

________________________________________

Description

For the control of the DMA Controller, three register are implemented in the

internal registers:

•The Cir cular B uffer S tart Addr es s is a 4- k byte aligned PCI address which

points to a 4-kby te c ir c ular buffer in the PCI main m emory . All DMA r ead/wr ite

transactions between host and PITA will be processed via this 4-kbyte address

space.

•The DM A Control register includes the 6-bit parameter DMA Selec t whic h is

us ed to define the mode for the next DMA t r ansfer. With the DMA _St ar t bit the

DM A t ransfer can be st arted and s topped.

•The c ontents of the DM A Wr ite Count Register is inter pr eted as a thr es hold for

the wr ite trans fers from the DMA c ontroller .

________________________________________

Function of the DMA Controller

Phase Function

1 DMA _Start bit is s et in the DMA Cont rol Register and a DMA

transf er is st art ed as defined in the DM A S elect Register.

2 T he DMA controller loads the Circular Buf fer Start Addres s t o its

A ct ual Circular Buffer Pointer .

3 T he DMA cont roller fills the T X FIFO by r eading 15 t imes thr ough

the PCI interface ( P CI mas ter mode) fr om the c ir cular buff er .

4 The DM A controller signals the end of the initial sequenc e.

5 The DMA controll er increments the Actual Circular Buffer Pointer by

4 each read t ransfer.

6 T he DMA cont roller loads the contents of the 12 bit DM A Wr it e

Count Regis ter to its internal 12 bit DMA wr it e c ounter.

7 After the fir s t 15 r ead tr ans fer s in the beginning of the 16th read

tr ans fer the DMA controller st ar ts the norm al DM A algorithm.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 38 01.00

________________________________________

DMA Write Coun ter

A fter each wr ite tr ans ac tion fr om t he RX FI FO t o the buf fer the int er nal DMA wr ite

count er is inc rement ed by 1. If this counter reaches ’0’ an inter rupt is generat ed

and the counter is loaded again with the contents of the DMA Write Counter

The internal DM A writ e counter is decrem ented ev ery t wo write transac tions as

long as two 16 bit values per FS C frame ar e t ransferr ed in t he following modes :

•32 bit frame mode

•dual modem m ode

•mode m+vo ice mo de

•IOM- 2 mode 2 and 3.

________________________________________

Function of the DMA Algorithm

Phase Function

1 The DM A controller reads the 16th data wor d from t he c ur r ent

addr ess in the cir c ular buffer (A c tual Circ ular B uffer Pointer) t o the

i n te rna l TX FIFO.

2 The DM A controller writes the f ir s t r eceived 16-bit data word from

the RX FI FO to the same addr es s in the c ir cular buff er .

3 The DM A controller incr ement s the Actual Buff er P ointer by 4.

4 The DM A controller reads the 17th data wor d from t he c ur r ent

addr ess in the cir c ular buffer (A c tual Circ ular B uffer Pointer) t o the

i n te rna l TX FIFO.

5 The DMA controller writes the second received 16-bit data word

from the RX FIFO t o the sam e addr ess in the circular buffer.

6 The DM A controller incr ement s the Actual Buff er P ointer by 4.

7 and so on

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 39 01.00

________________________________________

DMA_ Start bit

•The r eset of t he DM A_S tart bit st ops the DMA trans fer imm ediately.

•The ass ertion of the DMA _Start bit reset s the TX and RX FIFO’s.

This means that all FIFO data is los t when the DM A t rans fer is s topped.

________________________________________

Da ta in t he Circular Buffer

Since no data is written from the RX FIFO to the circular buffer for the first 15

addresses, the first interrupt after the DMA_Start assertion means that the

r eceived data is available in the c ir cular buffer on address

•003Ch to 003Ch + [DMA W rite Count]: 16 bit f rame modes

•003Ch t o 0003Ch + 2 x [DMA Write Count]: 32 bit fr ame modes.

Dur ing nor mal data transfer ev er y inter r upt m eans that received data is av ailable

in the circ ular buffer on addres s

•[end addr es s from las t interrupt ] to [end addr ess from last int err upt] + [DMA

Write Count] : 16 bit frame modes

•[end addr ess fr om last int er rupt] to [end addr es s fr om las t inter r upt] + 2 x [DMA

Write Count] : 32 bit frame modes

________________________________________

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 40 01.00

________________________________________

Example fo r DMA con t rolled Data Transfer via Circu lar Buf f er

The s tatus of the DMA c ontroller :

16 bit frame access mode (ALIS V2.1 mode/IOM-2 mode 1) when three data

frames are already wr it ten to the T X line.

________________________________________

RX data 1

TX data 15

TX data 14

TX data 13

TX data 12

TX data 11

TX data 10

TX data 9

TX data 8

TX data 7

TX data 6

TX data 5

TX data 4

TX data 3

TX data 2

TX data 1

RX data 4

RX data 3

RX data 2

TX data 23

TX data 22

TX data 21

TX data 20

don't care

1531

16 0

Circular Buffer

Memory

0000h

0004h

0008h

0038h

003Ch

RX data 8

RX data 9

RX data 10

RX data 11

RX data 12

RX data 13

RX data 14

RX data 15

RX data 16

RX data 17

RX data 18

RX data 19

RX data 5

RX data 6

RX data 7

RX data 20

TX data 16

TX data 15

TX data 14

TX data 13

TX data 12

TX data 11

TX data 10

TX data 9

TX data 8

TX data 7

TX data 6

TX data 5

TX data 19

TX data 18

TX data 17

TX data 4

Serial Control

DMA

Controller PITA

Actual_Circular_-

Buffer_Pointer

TX FIFO RX FIFO

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 41 01.00

5.1.3 Int ernal Registers of the DMA Con t roller

________________________________________

Inter nal Registers: 00h

Bit 26 FIFO_Overflow_Empty_Int_En

Type RW

Defau lt Val ue 0b

Description Enable for the FIFO_Over flow_Em pty inter rupt bit

Bit 25 DMA_Write_Counter_Overflow_Int_En

Type RW

Defau lt Val ue 0b

Description Enable for the DMA _Write_Counter_Overflow interr upt bit .

Bit 24 DMA_Write_Counter_Int_En

Type RW

Defau lt Val ue 0b

Description Enable for the DMA _Write_Counter interrupt bit.

Bit 10 FIFO_Overflow_Empty_Int

Type RC

Defau lt Val ue 0b

Description During a DM A trans fer the ser ial c ontroller was unable to

write received data to the RX FI FO because is was already

full or the ser ial c ontroller was unable t o send data after the

rising F SC edge because of empty T X F IFO.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 42 01.00

________________________________________

Bit 9 DMA_Write_Counter_Overflow_Int

Type RC

Defau lt Val ue 0b

Description T his bit is s et if the int ernal DM A write counter is count ed

down while the DMA_W rite_Counter_Int bit is st ill ac tive.

This m eans t hat the interr upt gener ated by t he

DM A_Write_Counter_Int bit is not y et pr ocess ed.

Bit 8 DMA_Write_Counter_Int

Type RC

Defau lt Val ue 0b

Description This bit is s et if the num ber of data, defined in the DM A Wr ite

Count Register is wr itten thr ough t he P CI interface. In the

32-bit modes (dual modem , modem+ voice, I OM -2 mode 2,

IOM- 2 mode 3) this bit is set if the number of dat a pairs

defined in the DMA Write Count Register is transf erred

through the PCI interface.

Inter nal Registers: 00h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 43 01.00

________________________________________

Inter nal Registers: 04h

Bit 31:0 DM A Control Register

Bit 31:9 Reserved

Type H

Value 0000000h

Description Reserved

Bit 8 DMA_Start

Type RW

Defau lt Val ue 0b

Description By ass erting this bit a DM A transf er between the circular

buffer and the s erial DM A int er face us ing inter nal RX/ TX

FIFOs is s tar ted. This bit is res et by the host if the DMA

tr ansfer is to be finished.

Bit 7:6 Reserved

Type H

Value 00b

Description Reserved

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 44 01.00

________________________________________

Bit 5:0 DMA Se lect

Type RW

Defau lt Val ue 000000b

Description Used to define the m ode for the next DMA transfer:

–Mode 1 ( ’000001’): Single M odem Mode V2. 1

–Mode 2 ( ’000010’): Single M odem Mode V3. X

–Mode 3 ( ’000100’): Dual M odem/ Modem+ Voice Mode

V3.X

–Mode 4 ( ’001000’): I OM-2 Mode 1

–Mode 5 ( ’010000’): I OM-2 Mode 2

–Mode 6 ( ’100000’): I OM-2 Mode 3

With the DMA _St art bit the DMA tr ansfer can be s tarted or

stopped.

Inter nal Registers: 04h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 45 01.00

________________________________________

Inter nal Registers: 08h

Bit 31:12 Circular Buffer St art Addres s

Type RW

Defau lt Val ue 000000h

Bit 11:0 Circular Buffer St art Addres s

Type H

Value 000h

Description •4-k byte aligned PCI address which points to a 4-k by te

circular buff er in the PCI m ain memory .

•A ll DM A read/write trans actions between the hos t and the

P ITA are proc ess ed via this 4- kby te addres s space.

Inter nal Register: 0Ch

Bit 31:02 A ctual Circular Buf fer Pointer

Type R

Value 31-12 equal to 31-12 of Regis ter 08, 11-02 ac tual address

Bit 1:0 A ctual Circular Buf fer Pointer

Type H

Value 00b

Description By r eading t his r egis ter the s oft ware has ac c ess to the PCI

address in t he DM A circular buffer address pointer.

The bits 31-12 are equal the cont ents of the Circular Buffer

St art Addr ess Regis ter. The bits 11-0 r epresent the act ual

dwor d addres s in the c ir cular buff er .

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 46 01.00

________________________________________

Inter nal Register: 1Ch

Bit 11:0 DM A Write Count Regis ter

Type RW

Defau lt Val ue 000h

Description

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 47 01.00

5.1.4 IOM-2 Mode 1

________________________________________

T ransmissio n and Recep tion of Data in the Circular Buf fer

________________________________________

Don´t care B1

31 B2

RX data 1

TX data 15

TX data 14

TX data 13

TX data 12

TX data 11

TX data 10

TX data 9

TX data 8

TX data 7

TX data 6

TX data 5

TX data 4

TX data 3

TX data 2

TX data 1

RX data 4

RX data 3

RX data 2

TX data 23

TX data 22

TX data 21

TX data 20

don't care

1531

16 0

Circular Buffer

Memory

0000h

0004h

0008h

0038h

003Ch

15 716 8 0

Data in Circu lar Buff er and on Serial DMA In terface

Direction Dat a in Circu lar Bu ffer Data o n Serial DMA

Interface

Tr ansmit Bits fr om circ ular buff er:

[31:16] = don’t care

[15:8] = B1 [7: 0]

[7:0] = B2 [7:0]

Wr ite to s er ial DM A inter face:

B1 [7:0]

B2 [7:0]

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 48 01.00

________________________________________

Timing Diagram

________________________________________

Receive B its to circular buff er:

[31:16] = don’t care

[15:8] = B1 [7: 0]

[7:0] = B2 [7:0]

Read from s erial DMA

interface:

B1 [7:0]

B2 [7:0]

Data in Circu lar Buff er and on Serial DMA In terface (cont’d)

Direction Dat a in Circu lar Bu ffer Data o n Serial DMA

Interface

8 bit B1 channel DU 8 bit B2 channel DU

8 bit B1 channel DD 8 bit B2 channel DD

125 us

16 bit B1, B2 frame, double clock

FSC (i)

DCL (i)

TXD (o)

RXD (i)

Inter nal Registers: 04h

Bit 5:0 DMA Se lect

Type RW

Defau lt Val ue 000000b

Description The DMA Cont r ol Register includes the 6 bit par am eter DM A

Select.

Used to define the m ode for the next DMA transf er:

Mode 4 (’001000’): IOM-2 Mode 1

With the DMA_S tar t bit t he DM A trans fer can be started or

stopped.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 49 01.00

________________________________________

Inter nal Register: 20h

Bit 1 DCL_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 1=’0’: The DCL signal is configur ed as input, i.e. not

dr iv en by the PITA .

Bit 0 Serial_Clock_Select

Type RW

Defau lt Val ue 0b

Description Bit 0=’1’: The s er ial c ontr oller is dr iven with the exter nal DCL

input clock.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 50 01.00

5.1.5 IOM-2 Mode 2

________________________________________

T ransmissio n and Recep tion of Data in the Circular Buf fer

________________________________________

Don´t care B1

31 B2

RX data 1

TX data 15

TX data 14

TX data 13

TX data 12

TX data 11

TX data 10

TX data 9

TX data 8

TX data 7

TX data 6

TX data 5

TX data 4

TX data 3

TX data 2

TX data 1

RX data 4

RX data 3

RX data 2

TX data 23

TX data 22

TX data 21

TX data 20

don't care

1531

16 0

Circular Buffer

Memory

0000h

0004h

0008h

0038h

003Ch

15 716 8 0

Don´t care Monitor 0

31 D, C/I, MR, MX

15 716 8 0

Data in Circu lar Buff er and on Serial DMA In terface

Direction Buffer

Offset Dat a in Circu lar Buff er Data on Serial DMA

Interface

Trans mit 0, 2, 4,

... Bits f rom circular buff er:

[31:16] = don’t ca re

[15:8] = B1 [7: 0]

[7:0] = B2 [7:0]

Wr ite to ser ial DM A

interface:

B1 [7:0]

B2 [7:0]

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 51 01.00

________________________________________

Timing Diagram

________________________________________

Trans mit 1, 3, 5,

... Bits f rom circular buff er:

[31:16] = don’t ca re

[15:8] = Monitor 0 [7:0]

[7:0] =

D,C/I0,M R,M X [7:0]

Wr ite to ser ial DM A

interface:

M onitor 0 [ 7:0]

D,C/I0,M R,M X [7: 0]

Receive 0, 2, 4,

... Bits to c ir cular buff er :

[31:16] = don’t ca re

[15:8] = B1 [7: 0]

[7:0] = B2 [7:0]

Read from s erial DM A

interface:

B1 [7:0]

B2 [7:0]

1, 3, 5,

... Bits to c ir cular buff er :

[31:16] = don’t ca re

[15:8] = Monitor 0 [7:0]

[7:0] =

D,C/I0,M R,M X [7:0]

Read from s erial DM A

interface:

M onitor 0 [ 7:0]

D,C/I0,M R,M X [7: 0]

Data in Circu lar Buff er and on Serial DMA In terface (cont’d)

Direction Buffer

Offset Dat a in Circu lar Buff er Data on Serial DMA

Interface

8 bit B1 channel DU 8 bit B2 channel DU

8 bit B1 channel DD 8 bit B2 channel DD

125 us

16 bit B1, B2 frame, double clock

FSC (i)

DCL (i)

TXD (o)

RXD (i)

8 bit Monitor 0 channel DU

8 bit Monitor 0 channel DD

2 bit D

4 bit C/I 0 MR

MR4 bit C/I 0

16 bit MON0, D, C/I0, MR, MX frame

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 52 01.00

________________________________________

Inter nal Registers: 04h

Bit 5:0 DMA Se lect

Type RW

Defau lt Val ue 000000b

Description The DMA Control Regist er inc ludes the 6 bit parameter DMA

Select.

Used to define the m ode for the next DMA transf er:

Mode 5 (’010000’): IOM-2 Mode 2

With the DMA _St art bit the DMA tr ansfer can be s tarted or

stopped.

Inter nal Register: 20h

Bit 1 DCL_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 1=’0’: The DCL signal is configur ed as input, i.e. not

dr iv en by the PITA .

Bit 0 Serial_Clock_Select

Type RW

Defau lt Val ue 0b

Description Bit 0=’1’: The s er ial c ontr oller is dr iven with the exter nal DCL

input clock.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 53 01.00

5.1.6 IOM-2 Mode 3

________________________________________

T ransmissio n and Recep tion of Data in the Circular Buf fer

________________________________________

Don´t care B1

31 B2

RX data 1

TX data 15

TX data 14

TX data 13

TX data 12

TX data 11

TX data 10

TX data 9

TX data 8

TX data 7

TX data 6

TX data 5

TX data 4

TX data 3

TX data 2

TX data 1

RX data 4

RX data 3

RX data 2

TX data 23

TX data 22

TX data 21

TX data 20

don't care

1531

16 0

Circular Buffer

Memory

0000h

0004h

0008h

0038h

003Ch

15 716 8 0

Don´t care IC1

31 IC2

15 716 8 0

Data in Circu lar Buff er and on Serial DMA In terface

Directio n Bu ffer

Offset Dat a in Circular Buf f er Data o n Serial DMA

Interface

Transmit 0, 2, 4,

... Bits from circular buff er:

[31:16] = don’t ca re

[15:8] = B1 [7: 0]

[7:0] = B2 [7:0]

Bits to serial DMA

interface:

B1 [7:0]

B2 [7:0]

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 54 01.00

________________________________________

Timing Diagram

________________________________________

Transmit 1, 3, 5,

... Bits from circular buff er:

[31:16] = don’t ca re

[15:8] = IC1 [7:0]

[7 :0 ] = IC2 [7 :0]

Write to serial DMA

interface:

IC 1 [7 :0 ]

IC 2 [7 :0 ]

Receive 0, 2, 4,

... B its to c ir cular buffer :

[31:16] = don’t care

[15:8] = B1 [7: 0]

[7:0] = B2 [7:0]

Read from s erial DMA

interface:

B1 [7:0]

B2 [7:0]

1, 3, 5,

... Write to circ ular buff er:

[31:16] = don’t care

[15:8] = IC1 [7:0]

[7 :0 ] = IC2 [7 :0]

Read from s erial DMA

interface:

IC 1 [7 :0 ]

IC 2 [7 :0 ]

Data in Circu lar Buff er and on Serial DMA In terface (cont’d)

Directio n Bu ffer

Offset Dat a in Circular Buf f er Data o n Serial DMA

Interface

8 bit B1 channel DU 8 bit B2 channel DU

8 bit B1 channel DD 8 bit B2 channel DD

125 us

16 bit B1, B2 frame, double clock

FSC (i)

DCL (i)

TXD (o)

RXD (i)

8 bit IC1 channel DU

8 bit IC1 channel DD

16 bit IC1, IC2 frame

8 bit IC2 channel DU

8 bit IC2 channel DD

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 55 01.00

________________________________________

Inter nal Registers: 04h

Bit 5:0 DMA Se lect

Type RW

Defau lt Val ue 000000b

Description The DMA Control Regist er inc ludes the 6 bit parameter DMA

Select.

Used to define the m ode for the next DMA transf er:

Mode 6 (’100000’): IOM-2 Mode 3

With the DMA _St art bit the DMA tr ansfer can be s tarted or

stopped.

Inter nal Register: 20h

Bit 1 DCL_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 1=’0’: The DCL signal is configur ed as input, i.e. not

dr iv en by the PITA .

Bit 0 Serial_Clock_Select

Type RW

Defau lt Val ue 0b

Description Bit 0=’1’: The s er ial c ontr oller is dr iven with the exter nal DCL

input clock.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 56 01.00

5.1.7 IOM-2 Modes - Supplementary Descrip tion

________________________________________

Selection of IOM-2 Time Slots

The MI SC regis ter contains four bit s . They ar e used for mas k ing the tim e slot on

IOM-2.

If Bx_MSK (x := [1,4]) is set:

•The cor responding v alue fr om the TX FIFO is not writ ten to the DU line.

•FFh is written to th is time slo t.

•In IOM -2 m ode 1 the bits B3_M SK and B4_MS K have no effect .

•Data is alway s transferr ed from the IOM -2 time slot to the RX- FIFO.

________________________________________

T iming Diagram f or all IOM-2 Modes

________________________________________

FSS

FSH

FSW

FSH

CYC

IOD

FSC (i)

DCL (i)

RXD (i)

TXD (o)

FSS

IIH

IIS

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 57 01.00

________________________________________

Figu re of the M ISC Register B1 - B4 Mask Bits

________________________________________

Ab breviation s fo r the T iming Diag ram

Parameter Symbol Limit Values Unit

min. max.

FSC pulse width tFSW 40 ns

FSC setup time tFSS 40 ns

FSC hold time tFSH 40 ns

DCL cycle time t CYC 244 ns

DCL HIGH ti me tWH 100 ns

DCL LOW tim e tWL 100 ns

IOM output data

delay tIOD 100 ns

IOM input data

setup tIIS 20 ns

IOM input data hold tIIH 20 ns

IOM-2

Mode 1

IOM-2

Mode 2

B2 Monitor 0

D,C/I0,MR,MX

IOM-2

Mode 3

B2 IC1

IC2

MISC

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 58 01.00

________________________________________

Ma s king of IOM -2 Time slot s ( Example for IOM-2 Mode 2 )

________________________________________

RXD (i)

TXD (0)

B2 Monitor 0

Previous IOM-2 frame

Don't care B1 B2

Don't care Monitor 0 D,C/I0,MR,MX

D,C/I0,MR,MX

Next IOM-2 frame

MON0

D,C/I0,

MR,MX

MON0

D,C/I0,

MR,MX

'FFh' 'FFh''FFh' 'FFh'

RX FIFO

TX FIFO

IOM-2 DD line

IOM-2 DU line

B1_MSK B3_MSK B4_MSK B2_MSK

Data 1

Data 2

Data 3

Circular Buffer

Memory

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 59 01.00

________________________________________

Inter nal Register: 1Ch

Bit 31:0 MI SC (Mis cellaneous Register)

Bit 31 IOM_B1_masking

Type RW

Defau lt Val ue 0b

Description Bit 31=’0’: B yt e B 1 is gener ated out of the circular buffer.

B it 31= ’1’: FFh is t ransm itt ed on the B1 time slot.

Bit 30 IOM_B3_masking

Type RW

Defau lt Val ue 0b

Description Bit 30=’0’: B yt e B 2 is gener ated out of the circular buffer.

B it 30= ’1’: FFh is t ransm itt ed on the B2 time slot.

Bit 29 IOM_M onitor_0 / IC1_m as king

Type RW

Defau lt Val ue 0b

Description Bit 29=’0’: B yt e M onitor 0 or IC1 is generated out of the

circular buff er.

B it 29= ’1’: FFh is t ransm itt ed on the Monitor /I C1 tim e s lot.

Monit or is used in IO M -2 m ode 2.

IC1 is used in IOM- 2 m ode 3.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 60 01.00

________________________________________

Bit 28 IOM_S upl_m asking / IC2_m as king

Type RW

Defau lt Val ue 0b

Description Address:=’0’: Byte D, C/I0, M R, M X or IC2 is generated out

of the circular buff er.

Address:=’1’: FFh is trans mitt ed on the D, C/ I0, MR, MX or

IC 2 ti me s l o t .

D, C/I 0, MR, MX : Us ed in I OM-2 mode 2.

IC2: Used in IOM -2 mode 3

Inter nal Register: 1Ch (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 61 01.00

5.1.8 Sin gle Modem Mode V2.1

________________________________________

Timing diagrams

________________________________________

Da ta in Circular Buffer and on Seri al DMA Interfac e

Direction Dat a in Circu lar Buff er Data o n Serial DMA

Interface

Trans mit B its fr om circular buffer:

[31:16] = don’t c a re

[15:0] = data fr ame [15: 0]

Write to serial DMA

interface:

data fr am e [15:0]

Receive B its to circular buff er:

[31:16] = don’t c a re

[15:0] = data fr ame [15: 0]

Read from s erial DMA

interface:

data fr am e [15:0]

16 bit data

125 us

16 bit data frame

FSC (i)

DCL (o)

TXD (o)

RXD (i)

FSW

DCD

CYC

DCI

ISU

IHO

high-Z

FSC (i)

DCL (o)

RXD (i)

TXD (o)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 62 01.00

________________________________________

Configuration of the Single Modem Mode V2.1 aft e r a Sys te m/Soft Rese t

•The configuration of the PS B4596 V 2.1 in single m odem mode is r ealized by

sof twar e using the 4-bit Gener al Purpos e I/O Inter face of the PIT A ( See

“Gener al Purpos e I/O Interface” on page 97.).

•After a system/soft reset the FSC is an input pin both for

–the P ITA

–th e ALIS V2 .1

•Af ter a syst em re set t h e D CL_Out _ En b it must be se t t o ’1’ by the host.

________________________________________

Ab breviation s fo r the T iming Diag ram

Parameter Symbol PCI

Clo ck

Cycles

Limit Values Unit

min. typ. max.

FSC pulse width tFSW 40 ns

DCL delay tDCD 16 480 ns

DCL idle time tDCI 105 µs

DCL cycle time t CYC 40 1200 ns

DCL HIGH ti me tWH 20 600 ns

DCL LOW tim e tWL 20 600 ns

DCL duty cy c le 45 50 55 %

Input data setup t ISU 10 ns

Input data hold tIHO 10 ns

Output data delay tOD 10 ns

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 63 01.00

________________________________________

Note A Pull Down res is tor is requir ed on the board to avoid a floating FS C signal in t his

situation.

________________________________________

PITA Conf igu ration for ALIS V2.1 after a Syst em Reset

Seri al DMA Interface

Mode Ser_Clock_S el ( clock

i n pu t to Se ri a l D MA

interface)

DCL_Out_E n (DCL

Direction)

ALI S V2.1 0 PCI clock/

40 1 DCL

output

Inter nal Registers: 04h

Bit 5:0 DMA Se lect

Type RW

Defau lt Val ue 000000b

Description The DMA Control Regist er inc ludes the 6 bit parameter DMA

Select.

Used to define the m ode for the next DMA transf er:

Mode 1 (’000001’): Si ng l e Mo d e m Mo de V2 . 1

With the DMA _St art bit the DMA tr ansfer can be s tarted or

stopped.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 64 01.00

________________________________________

Inter nal Register: 20h

Bit 1 DCL_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 1=’1’: The DCL signal is output (open drain) and driven

by the PITA .

Bit 0 Serial_Clock_Select

Type RW

Defau lt Val ue 0b

Description Bit 0=’0’: The ser ial controller is driv en wit h the clock s ignal

generat ed by the internal clock div ider.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 65 01.00

5.1.9 Sin gle Modem Mode AL IS V3.X

________________________________________

5.1.9.1 Infor mation about the S ingle Modem Mode ALIS V3.X

________________________________________

Timing Diagram

________________________________________

Overview

Overview Page

Inform ation about t he S ingle Modem Mode ALIS V3.X 65

Inter nal Registers of the Single Modem M ode V 3.X 67

Da ta in Circular Buffers, on Se rial DMA Interface

Direction Dat a i n Circular Buf f er Dat a on Seri al DMA In terface

Tr ansmit Read fr om c ir cular buffer :

[31:16]= don’t ca re

[15:0] = data fr ame [15:0]

Write to serial DMA interface:

data fr am e [15:0]

Receive Write to circular buffer:

[31:16]= don’t ca re

[15:0] = data fr ame [15:0]

Read from s erial DMA interfac e:

data fr am e [15:0]

FSC (i)

16 bit data

DCL (i)

TXD (o) 8 bit CMD 8 bit write data

16 bit data 8 bit read dataRXD (i)

125 us

32 bit data / command frame

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 66 01.00

________________________________________

Note The timing characteristics of the serial DMA interface in Single modem mode

V3.X mode are identical to the IOM-2 modes with the only difference that the DCL

signal is not a double bit clock, but a single bit clock, similar to Single Modem

mode V2.1.

________________________________________

Configuration of the Single Modem Mode V3.X a fter a Syst e m/Soft Reset

•Realiz ed by starting the DMA trans fer.

– S eparate from this transf er the command by te and comm and data by te are

writ ten to the ALIS Com mand Registers in the PITA on address es 10h.

•After a system/soft reset the single modem mode V3.X is in the multiplexed

m ode becaus e t he non multiplexed mode is not suppor ted.

•The A LIS V3.X needs some tim e af ter an ex ternal r eset until it has st abiliz ed

FS C and DCL. Fur ther m ore as the PIT A-2 does not autom atically as serts

S RST as a respons e to a P CI r es et the following proc edur e is r ecom mended

to start the com municat ion with the ALI S V3.X:

–Assert SRST by r eset ting bit 25 of internal regis ter 025h

–Deass ert SRS T by setting bit 25 of int ernal regis ter 025h

–Wait 500ms

•A fter this pr ocedur e the ALIS V 3.X is ready for r ec eiv ing the fir s t command

________________________________________

PITA Configurat ion for ALIS V3.X afte r a System Rese t

Seri al DMA Interface

Mode Ser_Clock_S el ( clock

i n pu t to Se ri a l D MA

interface

DCL_Out_E n (DCL

Direction)

ALIS V3.X 1 DCL input

clock

0DCL_Out

_En

2×ALIS V3.X 1 0

A LIS V3.X + second

codec 10

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 67 01.00

5.1.9.2 Internal Registers of the Single Modem Mode V3.X

________________________________________

Inter nal Registers: 04h

Bit 5:0 DMA Se lect

Type RW

Defau lt Val ue 000000b

Description The DMA Control Regist er inc ludes the 6 bit parameter DMA

Select.

Used to define the m ode for the next DMA transf er:

Mode 2 (’000010’): Si ng l e Mo d e m Mo de V3 . X

With the DMA _St art bit the DMA tr ansfer can be s tarted or

stopped.

Inter nal Register: 10h

Bit 31:0 ALIS Comm and Register 1

Description T his com mand register is used for the firs t comm and

st ructure in the FS C t ime slot by t he serial controller .

Bit 31:25 Reserved

Type H

Value 0b

Description Reserved

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 68 01.00

Bit 24 New_ALIS_Command_1

Type RW

Defau lt Val ue 0b

Description Bit 24=’1’: The host has wr itt en a new c ommand to the ALIS

Com mand Resister 1.

Bit 24=’0’: Last command written to the ALIS Command

Regis ter 1 by t he hos t is pr oces s ed and t he receiv ed data is

av ailable in the ALI S Received Data 1 r egis t er.

This bit is set by soft ware if there is a new com mand in the

ALIS Command 1 Register. After the serial DMA interface

has tr ansmitted the new com mand and t he received data is

wr itten to the ALIS_Rec eiv ed_Data_1 bits , this bit is r es et by

the serial DMA interface.

Bit 23:16 ALIS_Received_Data_1

Type RW

Defau lt Val ue 00h

Description During a DMA transfer in mode 2 or 3 every time a new

command is transferred through the serial DMA interface,

the received data is fetc hed and saved in t his regist er.

New c omm and means : The comm and was written through

the PCI interface to the A LIS c omm and r egis ter.

Tr ans fer r ing a NOP c ommand ( FFh or 00h) leads to skipping

of the received data.

Inter nal Register: 10h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 69 01.00

________________________________________

Bit 15:8 ALIS_Command_1

Type RW

Defau lt Val ue 00h

Description During a DMA transfer in mode 2 or 3 the contents of this

r egis ter ar e trans ferr ed as c omm and through the s erial DMA

interface.

After tr ans ferr ing the new com mand through the serial DM A

interface, the r egis ter is s et to NOP ( FFh).

Bit 7:0 ALIS_Transmit_Data_2

Type RW

Defau lt Val ue 00h

Description During a DMA tr ans fer in A LIS V 3.x m ode 2 or 3 the c ontents

of this register are transferred as data through the serial

DM A interface.

Inter nal Register: 10h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 70 01.00

________________________________________

Inter nal Register: 14h

Bit 31:0 ALIS Comm and Register 2

Defau lt Val ue 00000000h

Bit 31:25 Reserved

Type H

Defau lt Val ue 000h

Description Reserved

Bit 24 New_ALIS_Command_2

Type RW

Defau lt Val ue 0b

Description Bit 24=’1’: The hos t has wr itten a new c om mand t o the ALIS

Com mand 2 Regis ter .

B it 24= ’0’: Last c ommand written to the ALIS Com mand 2

Regist er by the host is proces sed and the received data is

av ailable in the ALI S Received Data 2 Register .

This bit is s et by soft ware if there is a new c ommand in t he

ALIS Comm and 2 Register . Aft er the serial controller has

trans m itted the new command and the receiv ed data is

wr itten in the A LIS Rec eiv ed Data 2 Register, this bit is res et

by the serial controller.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 71 01.00

________________________________________

Bit 23:16 ALIS_Received_Data_2

Type RW

Defau lt Val ue 00h

Description During a DMA transfer in mode 3 ev ery time a new

com mand is t ransferred through the serial DM A interface,

the received data is fetc hed and saved in t his regist er.

New com mand means : The comm and was wr itten thr ough

the PCI interface to the A LIS V 3.X c ommand regist er .

If only a N OP com mand (F Fh or 00h) is tr ansfer red t he

received data is s kipped.

Bit 15:8 ALIS_Command_2

Type RW

Defau lt Val ue 00h

Description During a DMA transfer in mode 3 the c ontents of this r egis ter

are trans ferred as comm and through the serial DM A

interface.

A fter tr ans fer r ing the new com mand t hrough t he s erial DMA

interface, the r egis ter is s et to NOP ( FFh).

Bit 7:0 ALIS_Transmit_Data_2

Type RW

Defau lt Val ue 00h

Description During a DMA transfer in mode 3 the c ontents of this r egis ter

are trans ferred as data through the serial interfac e.

Inter nal Register: 14h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 72 01.00

________________________________________

Inter nal Register: 20h

Bit 1 DCL_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 1=’0’: The DCL signal is input and driven by the PIT A .

Bit 0 Serial_Clock_Select

Type RW

Defau lt Val ue 0b

Description Bit 0=’1’: The s er ial c ontr oller is dr iven with the exter nal DCL

input clock.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 73 01.00

5.1.10 Dual Mod em/Modem+Voice Mod e

________________________________________

Description

•The PI TA transm its and r ece ives two 32 bit fr ames per FSC tim e slot.

•E ach 32 bit fr ames cons is ts of 16 bit data and 16 bit command/ data

information.

•For each of the 32 bit fr ames the 16 bit t r ansmitted data is r ead out of t he TX

FIFO.

•The 16 bit tr ans mit ted data is wr itten to the RX FIFO.

•The command read/write dat a for the f ir s t 32 bit frame is r ead out/ wr itt en to the

ALIS Comm and Register 1 (10h)

•The command read/write data for the sec ond 32 bit frame is read out/ written to

the A LIS Com mand Regis ter 2 ( 14h).

•The internal DM A write counter is inc rem ented every second write tr ans fer to

the c ir cular buff er .

•A new fr ame trans miss ion starts if the FSC is sam pled ’1’ at a negat iv e edge

of the DCL s ignal.

•The P ITA s tarts dr iv ing the TX D line with the fir st bit of the tr ans mitted dat a at

the nex t positiv e DCL edge.

•Dur ing the tr ans miss ion the ris ing DCL edge indicates the star t of a bit on t he

TXD while the falling edge of the DCL is used to lat ch the RXD signal.

•The P ITA s tops dr iv ing the TX D signal with t he positiv e DCL edge when bit 32

of the firs t or s econd transm itt ed f rame is on the T XD line.

________________________________________

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 74 01.00

________________________________________

Data Organization in the Circular Buffer

________________________________________

Timin g Diagram for the Du al Modem M ode

________________________________________

RX data 1

TX data 15

TX data 14

TX data 13

TX data 12

TX data 11

TX data 10

TX data 9

TX data 8

TX data 7

TX data 6

TX data 5

TX data 4

TX data 3

TX data 2

TX data 1

RX data 4

RX data 3

RX data 2

TX data 23

TX data 22

TX data 21

TX data 20

don't care

1531

16 0

Circular Buffer

Memory

0000h

0004h

0008h

0038h

003Ch

Don´t care TX Data 1 Modem 1

31 15 716 8 0

Don´t care TX Data 1 Modem 2

31 15 716 8 0

16 bit data 8 bit CMD 8 bit write data 16 bit data 8 bit CMD 8 bit write data

16 bit data 8 bit read data 16 bit data 8 bit read data

125 us

32 bit data / command frame 32 bit data / command frame

FSC (i)

DCL (i)

TXD (o)

RXD (i)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 75 01.00

________________________________________

Timin g Diagram for the Du al Modem+Voice M ode

________________________________________

Descrip tion of t he T iming Diagram

•The sec ond 32 bit fram e only consists of the 16 bit voice data.

•The v oice data is r ead out the TX FI FO.

•The v oice data is tr ansm itted thr ough t he s er ial DMA inter fac e ( MSB fir s t) .

•Dur ing this tr ans m ission the rec eiv ed 16 bit v oic e data ( MSB firs t) is wr itten to

th e R X FIFO.

________________________________________

16 bit data 8 bit CMD 8 bit write data 16 bit data stuffing pattern 'FFh'

16 bit data 8 bit read data 16 bit data

125 us

32 bit data / command frame 32 bit data frame

FSC (i)

DCL (i)

TXD (o)

RXD (i)

16 bit stuffing 'FFh'

Inter nal Registers: 04h

Bit 5:0 DMA Se lect

Type RW

Defau lt Val ue 000000b

Description The DMA Control Regist er inc ludes the 6 bit parameter DMA

Select.

Used to define the m ode for the next DMA transf er:

Mode 3 (’000100’): Single Dual Modem/Modem + Voice

Mode V3 .X

With the DMA _St art bit the DMA tr ansfer can be s tarted or

stopped.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 76 01.00

5.1.11 Lo op Back M ode

________________________________________

Description

If Loop_Back_Mode is set to ’1’ transmit data is transferred from the TX FIFO

bac k to the RX FI FO.

________________________________________

Mode Diagram

________________________________________

PITA

DMA

Controller

TX FIFO

RX FIFO

Loop

closed

Data 1

Data 2

Data 3

Circular Buffer

Memory

Serial Controller

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 77 01.00

________________________________________

Inter nal Register: 28h

Bit 0 Loop_Back_Mode

Type RW

Defau lt Val ue 0b

Description •Bit 0=’0’: The s er ial c ontroller tr ans mits and r ec eiv es data/

c omm ands through the serial DM A int erf ac e ( nor mal

operat ion mode).

•Bit 0=’1’: T he ser ial contr oller is in loop back m ode.

–The ser ial DMA inter face reads the data in t he

trans m itting FIFO and writes them in the r eceiving

FIFO.

–No data/com mand tr ans mission will take place on the

s er ial DMA inter fac e.

–The s erial DM A interface is clock ed with the defined

Ser_Clock_ Sel bit .

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 78 01.00

5.2 Pa ra lle l In te rfac e

________________________________________

Description

The PI TA has an 8 bit par allel inter face to suppor t three ex ternal c omponents .

This par allel inter face is implem ented in mult iplex ed and non multiplexed m ode.

It works in I nfineon/I ntel bus m ode.

The par allel inter face is by default in t he non mult iplex ed m ode.

________________________________________

Inter nal Register: 1Ch

Bit 26 Parallel_interface_mode

Type RW

Defau lt Val ue 0b

Description 0: non mult iplex ed mode

1: multiplexed mode

Bit 24 Softreset_parallel_mode

Type RW

Defau lt Val ue 0b

Description 0: Deactivates the res et signal PRS T to the application.

1: Activates the high active reset signal PRST to the

application.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 79 01.00

________________________________________

Mapp ing bet ween PCI Data and Parallel Interface Data

Data on the

P CI b us AD31-0 PCI B yte

Enables

C/BE3-0

Data on the

Parall el Interface Data bu s

PAD7-0

AD[31-8] = Don’t C a re

AD[7 -0] = Para llel

Inter face Data

“XXX0”PAD[7-0] = AD[7-0]

AD[31-8] = Don’t C a re

AD[7 -0] = Para llel

Inter face Data

“XXX1”No tr ans act ion, PCI interface

disc onnec ts with Tar get Abor t.

Ad dress M apping of the 4-kbyte PCI Add ress Space to th e Parallel

Interface

Address on

the

PCI ad dress

bus A D 1 1 -0

Chip Sel ect on

the

parallel in terface

Address on th e

parallel in terface address bus

PAD7-0 = AD9-2 (mux mode)

PA7-0 = AD9-2 ( non-mux mod e)

3FFh - 000h CS0 FFh - 00h

7FFh - 400h CS1 FFh - 00h

B FFh - 800h CS2 F Fh - 00h

FFFh - C00h none ( not used)

PSB 4610
Communication with External Com ponent s
Preliminary  Data Sheet  80 01.00
 
________________________________________
________________________________________
Modes an d T iming of the Parallel Interf ace
M odes and  Ti ming Page
AL E aft er Syst em Re set 81
ALE after  inter nal Sof tware Reset 82
A LE aft er s ett ing the Par allel I nter face Mode Bit 83
Non Multiplexed Mode ( Write Trans action) 84
Non Multiplexed Mode ( Read Tr ans ac tion) 86
M ultiplexed Mode (Write Trans act ion) 87
M ultiplexed Mode (Read Transac tion) 88
Tr ansaction Dis c onnec t with Target Abor t 89
Trans action Ter mination wit h R etry 92
Timing of the Parallel Interf ace 94

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 81 01.00

5.2.1 ALE af t er System Reset

________________________________________

Timing Diagram

________________________________________

Description

Both ALE and PRS T are high during RST and rem ain high for a m aximum of 4

cycles after RST goes deasserted.

________________________________________

12345678910111213

RST

PRST

ALE

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 82 01.00

5.2.2 ALE af t er internal Sof t ware Reset

________________________________________

Timing Diagram

________________________________________

Description

•A fter the inter nal Sof t Reset is deasser ted t he s am e behavior as in „ALE after

System Reset “ gener ated.

•The s oft reset bit in the int e rnal regis ters c an only be set or res et if the parallel

interface is in idle st ate.

•If A LE is high before PA R_RS T is ass er ted, it goes to low one cy c le after PRST

and tak es the new v alue depending on the PAR_MOD bit in the 6th cy c le aft er

P RST is deas s er ted.

________________________________________

PRST

ALE

12345678910111213

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 83 01.00

5.2.3 ALE af t er setting th e Parallel Interface Mode Bit

________________________________________

Timing Diagram

________________________________________

Description

•The par allel inter face is in non multiplexed mode by default .

•To s et the parallel interface into multiplexed mode:

The Parallel_Int er face_Mode bit has t o be s et to ’1’ after reset.

•Two P CI clocks after finishing this data phase t he A LE signal is asserted.

________________________________________

123456789101112

ADR DATAADR1 DATA

CMD1 0000 CMD 0000

______

FRAME

____

IRDY

_____

TRDY

_______

DEVSEL

AD31-0

_______

C/BE3-0

_____

STOP

ALE

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 84 01.00

5.2.4 Non M ultiplexed Mode ( Write Transact io n)

________________________________________

Timing Diagram

________________________________________

Description

•A fter the addres s phase on the P CI bus ( clock 3) and the C/B E0=0 veri ficati on

the address dec oding phase of the target (c locks 3 to 4) is act ive.

•The by te addr ess for the t rans ac tion on the par allel int er face is gener ated out

of the P CI addres s AD9- 2 by mapping it to the par allel inter face addres s bus

PA7-0.

•One PCI c loc k af ter the PCI data phase is finished the data fr om t he P CI bus

is plac ed on the data bus P AD7-0 (cloc k 5) and t he write trans action star ts.

•The data is plac ed fr om t he P CI bus on P AD7-0 asser ting the WR signal and

a CS 2- 0 signal.

•A new acc es s to the par allel interfac e could be ac cepted with an addres s

phase at clock 9. Any acc ess before would be cancelled wit h Retry because

the PCI Inter face is process ing the last acc es s.

________________________________________

ADR DATA

CMD XXX0

XXXX PCI-ADR[9-2] XXXX

PCI-DATA[7-0]

12345678910111213

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

CS2-0

ALE

PA7-0

PAD7-0

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 85 01.00

________________________________________

Example

As an example the value 0A4h shall be written at address 005h of the device

connected to CS1. In this example the Base Address Register 1 (BAR1) shall

c ontain the addr ess 20004000h.

•CS1 is activated for the address space 400h to 7FFh. Ther efore the device’s

addr es s space starts at PCI address BA R1+400h= 20004400h.

•Only the lower by te of eac h 32bit word trans ferr ed to and f rom the PITA - 2 ov er

the P CI bus is us ed for the parallel interface. Therefore the r elative PCI

addr es s is four times the relativ e dev ic e addr es s: r el. PCI address = four times

005h = 014h.

•The abs olute PCI addr es s for the data trans fer is

BAR1+400h+014h=20004414h.

•Only the low by te of a 32 bit dat a wor d matt er s , the upper thr ee byt es ar e

ignor ed by the PITA - 2. In order to write the value 0A 4h the data word

000000A4 can be written to PCI addres s 20004414h.

________________________________________

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 86 01.00

5.2.5 Non M ultiplexed Mode ( Read Transaction)

________________________________________

Timing Diagram

________________________________________

Description

•A fter the addres s phase on the P CI bus ( clock 3) and the C/B E0=0 veri ficati on

the address dec oding phase of the target (c locks 3 to 4) is act ive.

•The by te addr ess for the t rans ac tion on the par allel int er face is gener ated out

of the P CI addres s AD9- 2 by mapping it to the par allel inter face addres s bus

P A7- 0 (c lock 5) .

•The following P CI c loc k ass er ts the signals RD and CS 2-0.

•A fter 5 c loc k s the RD signal is deassert ed.

•The data from P AD7- 0 is fetc hed.

•With t he nex t cloc k the data is placed on t he P CI bus and the data phase is

finished by deasserting the TRDY signal.

•The 8 bit data fr om the par allel interfac e is placed an the last s ignific ant by te

of the P CI data bus AD7-0.

________________________________________

ADR DATA

CMD XXX0

XXXX PCI-ADR[9-2] XXXX

DATA[7-0]

12345678910111213

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

CS2-0

ALE

PA7-0

PAD7-0

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 87 01.00

5.2.6 Multiplexed Mo de ( Write Tran saction)

________________________________________

Timing Diagram

________________________________________

Description

•A fter the addres s phase on the PCI bus (cloc k 3) and the C/ BE0=0 verification

the address dec oding phase of the target (c locks 3 to 4) is act ive.

•The by te address for t he trans ac tion on the parallel interface addr ess is

gener ated out of the PCI address A D9- 2 by mapping it t o the parallel interface

addr es s bus PA7- 0.

•One PCI c loc k af ter the PCI data phase is finished the data fr om t he P CI bus

is plac ed on the data bus P AD7-0 (cloc k 5) and t he write trans action star ts.

•The data is plac ed fr om t he P CI bus on P AD7-0 asser ting the CS2- 0 signal.

•The ALE signal is deasser ted.

•With the following P CI clock the data from t he P CI bus is placed on P AD7-0

(clock5).

•The WR signal is asserted.

•A new acc es s to the par allel interfac e could be ac cepted with an addres s

phas e at clock 11. Any ac ces s bef or e would be c ancelled with Retr y bec aus e

the PCI Inter face is process ing the last acc es s.

________________________________________

ADR DATA1

CMD XXX0

PCI-ADR[9-2] PCI-DATA1[7-0]

12345678910111213

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

CS2-0

ALE

PAD7-0

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 88 01.00

5.2.7 Multiplexed Mo de ( Read Transactio n)

________________________________________

Timing Diagram

________________________________________

Description

•A fter the addres s phase on the PCI bus (cloc k 3) and the C/ BE0=0 verification

the address dec oding phase of the target (c locks 3 to 4) is act ive.

•The by te addr ess for the t rans ac tion on the par allel int er face is gener ated out

of the P CI addres s AD9- 2 by mapping it to the par allel inter face addres s bus

P A7- 0 (c lock 5) .

•The following P CI c loc k ass er ts the ALE s ignal.

•A fter 2 c loc k s the ALE signal is deasser ted.

•The addr ess is held for one m ore c lock.

•A fter 5 c loc k s the RD signal is deassert ed.

•At the s ame time the data is lat ched in die P CI output regist ers.

•TRDY is as sert ed on the PCI bus to finish the data phase.

•At the nex t clock the CS2-0 and ALE s ignals are deas ser t ed.

________________________________________

ADR(00)

DATA1

CMD XXX0

PCI-ADR[9-2] DATA1[23-16]

1 2 3 4 5 6 7 8 9 10 11 12 13 14

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

CS2-0

ALE

PAD7-0

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 89 01.00

5.2.8 Tr ansaction Discon nect with Targ et Abor t

________________________________________

Timing Diagram

________________________________________

ADR DATA ADR DATA

CMD XXX1 CMD XXX1

12345678910111213

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

CS2-0

ALE

PAD7-0

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 90 01.00

________________________________________

Description

C/BE0 = 1: No transaction is started on selected parallel interface, due to the

wr ong by te enable. The P CI M ast er Target Controller disc onnec ts the trans ac tion

with tar get abort.

________________________________________

Co nfig urat io n Sp ace Register: 04h

Bit 30 System_Error_Signaled

Type RC

Defau lt Val ue 0b

Description This bit is set by the PITA’s PCI M ast er , if t he m ast er as s ert s

the sy st em error signal on the P CI bus . This oc curs if a

trans ac tion initiated by the PIT A is disc onnec ted wit h target

abort.

Bit 29 Master_Abort_Detected

Type RC

Defau lt Val ue 0b

Description I f no fast /m edium /slow or subtrac tive s lav e reacts to a P CI

tr ansact ion initiated by the PCI Mas ter, the m aster will

discard the tr ansaction and s et this bit.

Bit 28 Master_Abort_Detected

Type RC

Defau lt Val ue 0b

Description I f a P CI trans act ion initiated by the P CI Master is

dis c onnected with Tar get A bort , t he P CI master will set this

bit. The PCI M aster is not allowed to st ar t a new PCI

trans ac tion, until this bit is deasser ted.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 91 01.00

________________________________________

Bit 27 Target_Abort_Signaled

Type RC

Defau lt Val ue 0b

Description T his bit is s et by the PCI interface if a t ransaction was

dis c onnected with Tar get Abor t. The PI TA will disc onnect

trans ac tions with Tar get A bor t if illegal by te enables ar e

detected.

Bit 8 System_Error_Enable

Type RW

Defau lt Val ue 0b

Description I f this bit is ass erted, the P CI M as ter will ass er t the Sy s tem

Error Sig nal (SERR) if it rec eiv es a t arget abort during a

tr ansact ion initiated by it self.

Bit 2 Master_Enable

Type RW

Defau lt Val ue 0b

Description If this bi t is set to ’0’ the PCI Master is not allowed to start any

trans ac tion on the PCI B us.

Co nfig urat io n Sp ace Register: 04h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 92 01.00

5.2.9 Transact ion Terminat ion with Retry

________________________________________

Description’

Retry means that the PITA finishes a transaction without a data transfer by

asserting the signal STOP, because the parallel interface processes another

transaction.

The PCI Master Target Controller has to repeat the transaction until a slave

accepts the transaction with data transfer or target abort. This sequence is

inv is ible for the sof tware.

________________________________________

Timing Diagram

________________________________________

ADR1 DATA1 ADR2 DATA2

CMD1 XXX0 CMD2 XXX0

PCI-ADR[9-2] PCI-DATA1[7-0]

12345678910111213

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

CS2-0

ALE

PAD7-0

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 93 01.00

________________________________________

Expl anati on of ADR/CMD and ADR2/CMD2

A DR/ CMD: The PCI Mas ter Tar get Controller acc epts the wr ite trans ac tion

ADR2/CM D2: The second tr ansaction is retried.

________________________________________

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 94 01.00

5.2.10 Timing of the Pa rallel In te rfa c e

________________________________________

Read Tim ing

________________________________________

W rite Timing

________________________________________

Mu lt ip lexed Address Timing

________________________________________

RD x CS

AD0-AD7

Data

WR x CS

AD0-AD7

Data

ALE

WR x CS or

RD x CS

AD0-AD7

ALS

Address

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 95 01.00

________________________________________

Non M ultiplex e d Addre ss Timing

________________________________________

Appl ication Re set and Int err u pt T im ing

________________________________________

Address

A0-A7

WR x CS or

RD x CS

valid state

PRST, SRST

Host wri te

access to

the register

ROD

previous state

IN T O (i)

IO D

INTA (o)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 96 01.00

________________________________________

Ab breviation s of th e Timin g Diagrams

Parameter Sym-

bol PCI

Clo ck

Cycles

Lim it

Values Unit

min. max

A LE puls e widt h tAA 5 150 ns

Addr es s setup tim e t o A LE tAL 130 ns

Addr es s hold tim e f r om ALE tLA 130 ns

Address latch setup time to WR,

RD tALS 130 ns

Addr es s setup tim e tAS 130 ns

Addr es s hold tim e tAH 130 ns

A LE guard t ime tAD 130 ns

RD pulse width t RR 5 150 ns

Data output delay from RD tRD 5 150 ns

Data float from RD tDF 130ns

RD control interv al tRI 5 150 ns

W pulse widt h tWW 390 ns

Data setup time to W x CS tDW 260 ns

Data hold time W x CS tWD 130 ns

W cont rol inter val tWI 390 ns

Re se t Ou tp u t D e l a y tROD 390ns

Inter rupt O utput Delay tIOD 260ns

PSB 4610
Communication with External Com ponent s
Preliminary  Data Sheet  97 01.00
 
5 .3 Gene ra l Purpo se I/O Inte rfac e
________________________________________
________________________________________
Overview
Overview Page
Infor mat ion about the GP I/ O Interfac e 98
Timing of the GP  I/O Interfac e 100
Inter nal Regist ers of the GP  I/O Interface 101
Input Mode 107
Output Mode 109
Inter rupt Mode 111
Usage of the GP  I /O Inter fac e as ALIS V2. 1 Control Inter face 113

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 98 01.00

5.3.1 Inf ormat ion abo ut th e GP I/O Interface

________________________________________

Description

For additional ac cess to ext ernal devices with a slow int erfac e behavior a 4 bit

General P urpose I/ O interface is im plem ented in the PITA.

________________________________________

Appl ication Interr up t

•The PCI inter fac e supports a separ ate int errupt input with progr am mable

polarity.

•The four pins of t he gener al purpos e I/ O inter fac e can be us ed as additional

interr upt input s.

•E ach of thes e fiv e interr upts has an I nterr upt_Enable bit and an

Interrupt_Contr ol_S tat us bit .

•For the separate input t he enable an polarity bits are located in t he Inter r upt

Contr ol Regis ter .

•For the Gener al P ur pose I/ O the enable bit s ar e located in t he Interface Control

________________________________________

Pinning

Pin Pi n N am e Ge ne r a l P u r pos e I/O

Function SPI EEPR O M

Function

2 GP0 I/O/Int. SO

3 GP1 I/O/Int. SI

4 GP2 I/O/Int. SCK

5 GP3 I/O/Int. –

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 99 01.00

________________________________________

Co ntrol Registers fo r GPx Pins

Interrupt Control Register

- ICR GPx_I NT GP Int errupt Status

GP I/O In te rface C o n trol

GPx_INT_En GP Interrupt Enable

GPx_OUT_En GP Output Enable

GPx_OUT GP Output Value

GPx_I N GP Input V alue

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 100 01.00

5.3.2 Timing of the GP I/O Interfac e

________________________________________

Timing Diagram

________________________________________

valid state

Host write

access

GP0-3 (o)

GPx configured

as output

ISU

IHO

valid state

Host read

access

GP0-3 (i)

GPx configured

as input

IOD

GPx configured

as interrupt input

GP0-3 (i)

INTA (o)

Ab breviation s of th e Timin g Diagram

Parameter Symbol Limit Values Unit

min. max.

GPx Output Data Delay tOD 90 ns

GP x Input Data Setup tISU 30 ns

GP x Input Data Hold tIHO 30 ns

GPx In te rru p t Ou tp u t

Delay tIOD 90 ns

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 101 01.00

5.3.3 Int e rnal Regist e rs of the GP I/O Int erf ace

________________________________________

Inter nal Register: 00h

Bit 5 GP3_INT

Type RC

Defau lt Val ue 0b

Description T he G P3 pin can be us ed as ’active lo w’ inter rupt input if

GP3_Int_En=’1’ and GP 3_Out_En= ’0’.

Th e b it i s set to ’1’ if bot h ar e tr ue and low is detec ted at this

pin.

Bit 4 GP2_INT

Type RC

Defau lt Val ue 0b

Description T he G P2 pin can be us ed as ’active lo w’ inter rupt input if

GP2_Int_En=’1’ and GP 2_Out_En= ’0’.

Th e b it i s set to ’1’ if bot h ar e tr ue and low is detec ted at this

pin.

Bit 3 GP1_INT

Type RC

Defau lt Val ue 0b

Description T he G P1 pin can be us ed as ’active lo w’ inter rupt input if

GP1_Int_En=’1’ and GP 1_Out_En= ’0’.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 102 01.00

________________________________________

Bit 2 GP0_INT

Type RC

Defau lt Val ue 0b

Description T he G P0 pin can be us ed as ’active lo w’ inter rupt input if

GP0_Int_En=’1’ and GP 0_Out_En= ’0’.

Inter nal Register: 00h (cont’d)

Inter nal Register: 18h

Bit 27 GP3_Int_En

Type RW

Defau lt Val ue 0b

Description Bit 27=’1’: GP 3 is conf igured as input, the pin is used as an

interr upt input with GP 3_Int _en as corres ponding bit in the

Inter r upt Contr ol Regis ter.

B it 27= ’1’: GP3 is not used as an interrupt pin.

Bit 26 GP2_Int_En

Type RW

Defau lt Val ue 0b

Description Bit 26=’1’: GP 2 is conf igured as input, the pin is used as an

interr upt input with GP 2_Int _en as corres ponding bit in the

Inter r upt Contr ol Regis ter.

B it 26= ’0’: GP2 is not used as an interrupt pin.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 103 01.00

Bit 25 GP1_Int_En

Type RW

Defau lt Val ue 0b

Description Bit 25=’1’: GP 1 is conf igured as input, the pin is used as an

interr upt input with GP 1_Int _en as corres ponding bit in the

Inter r upt Contr ol Regis ter.

B it 25= ’0’: GP1 is not used as an interrupt pin.

Bit 24 GP0_Int_En

Type RW

Defau lt Val ue 0b

Description Bit 24=’1’: GP 0 is conf igured as input, the pin is used as an

interr upt input with GP 0_Int _en as corres ponding bit in the

Inter r upt Contr ol Regis ter.

B it 24= ’0’: GP0 is not used as an interrupt pin.

Bit 19 GP3_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 19=’1’: GP _3 is configured as output pin.

B it 19= ’0’: GP _3 is configur ed as input pin.

Bit 18 GP2_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 18=’1’: GP _2 is configured as output pin.

B it 18= ’0’: GP _2 is configur ed as input pin.

Inter nal Register: 18h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 104 01.00

Bit 17 GP1_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 17=’1’: GP _1 is configured as output pin.

B it 17= ’0’: GP _1 is configur ed as input pin.

Bit 16 GP0_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 16=’1’: GP _0 is configured as output pin.

B it 16= ’0’: GP _0 is configur ed as input pin.

Bit 11 GP3_IN

Type R

Description Actual Value on the GP3 pin (pin f eedback)

Bit 10 GP2_IN

Type R

Description Actual Value on the GP2 pin (pin f eedback)

Bit 9 GP1_IN

Type R

Description Actual Value on the GP1 pin (pin f eedback)

Inter nal Register: 18h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 105 01.00

Bit 8 GP0_IN

Type R

Description Actual Value on the GP0 pin (pin f eedback)

Bit 3 GP3_OUT

Type RW

Defau lt Val ue 0b

Description The GP3 pin is driven with the value written to this output

r egis ter if the GP3_OUT_E n is set to ’1’.

Bit 2 GP2_OUT

Type RW

Defau lt Val ue 0b

Description The GP2 pin is driven with the value written to this output

r egis ter if the GP2_OUT_E n is set to ’1’.

Bit 1 GP1_OUT

Type RW

Defau lt Val ue 0b

Description The GP1 pin is driven with the value written to this output

r egis ter if the GP1_OUT_E n is set to ’1’.

Inter nal Register: 18h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 106 01.00

________________________________________

Bit 0 GP0_OUT

Type RW

Defau lt Val ue 0b

Description The GP0 pin is driven with the value written to this output

r egis ter if the GP0_OUT_E n is set to ’1’.

Inter nal Register: 18h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 107 01.00

5.3.4 Input Mode

________________________________________

Description

For using a general purpose I/O pin as input pin, the control register must be

c onfigur ed as follows:

GPx_OUT_En = ‘0’(Out put disabled)

GPx_INT_En = ‘0’(Interr upt dis abled)

(x := [0, 3 ])

Des cr iption of the inter nal r egis ter 18h on page 102.

The GP x_O UT and GPx _INT bit s can be tr eated as don’t care in this mode. The

cur rent signal value at the pin G Px can be read from r egis ter bit GP x_IN.

________________________________________

Inter nal Structure of a GPx Inp ut Pin

________________________________________

Timing Diagram

________________________________________

GPx_IN

GPx

ISU

IHO

valid state

Host read

access

GP0-3 (i)

GPx configured

as input

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 108 01.00

________________________________________

Ab breviation s of th e Timin g Diagram

Parameter Symbol Limit Values Unit

min. max.

GP x Input Data Setup tISU 30 ns

GP x Input Data Hold tIHO 30 ns

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 109 01.00

5.3.5 Output Mode

________________________________________

Description

For us ing a general purpos e I/O pin as output pin, the contr ol register mus t be

c onfigur ed as follows:

GPx_OUT_En = ‘1’(Out put enabled)

GPx_INT_En = ‘don’t c a re ’

(x := [0, 3 ])

Des cr iption of the inter nal r egis ter 18h on page 102.

The GPx _IN and G Px_INT regist er bits c an be treated as don’t car e in this m ode.

The GPx pin will drive the connected signal line with the value defined in the

GP x _OUT r egis ter bit, whic h is progr am med by the hos t.

________________________________________

Inter nal Structure of a GPx Output Pin

________________________________________

GPx_Out

GPx

GPx_Out_En

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 110 01.00

________________________________________

Timing Diagram

________________________________________

valid state

Host write

access

GP0-3 (o)

GPx configured

as output

Ab breviation of t he Timing Diagram

Parameter Symbol Limit Values Unit

min. max.

GPx Output Data Delay tOD 90 ns

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 111 01.00

5.3.6 Int errupt M ode

________________________________________

Description

For us ing a general purpos e I/O pin as output pin, the contr ol register mus t be

c onfigur ed as follows:

GPx_OUT_En = ‘1’(Out put disabled)

GPx_INT_En = ‘1’(Interr upt enabled)

(x := [0, 3 ])

Des cr iption of the inter nal r egis ter 18h on page 102.

The GPx _OUT regis ter bit c an be tr eated as don’t car e in this m ode. The GPx pin

ac ts as an active low inter r upt input pin.

If the dev ice detects ’0’ at the G P x pin

•the GP x _INT register is set to ’1’

•an interrupt on the PCI bus is gener ated

•the curr ent state of the GP x pin c an be read from GPx _IN bit or c an be treated

as don’t ca re.

________________________________________

Inter nal Structure of a GPx Inter rupt Inp ut pin

________________________________________

Timing Diagram

________________________________________

GPx_IN

GPx

>=1

INTA

IOD

GPx configured

as interrupt input

GP0-3 (i)

INTA (o)