Low Jitter Clock Generator with
6 LVPECL/LVDS/HSTL/13 LVCMOS Outputs
AD9524
Rev. C
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FEATURES
Output frequency: <1 MHz to 1 GHz
Start-up frequency accuracy: <±100 ppm (determined by
VCXO reference accuracy)
Zero delay operation
Input-to-output edge timing: <±150 ps
6 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
6 dedicated output dividers with jitter-free adjustable delay
Adjustable delay: 63 resolution steps of ½ period of VCO
output divider
Output-to-output skew: <±50 ps
Duty-cycle correction for odd divider settings
Automatic synchronization of all outputs on power-up
Absolute output jitter: <200 fs at 122.88 MHz
Integration range: 12 kHz to 20 MHz
Distribution phase noise floor: −160 dBc/Hz
Digital lock detect
Nonvolatile EEPROM stores configuration settings
SPI- and I²C-compatible serial control port
Dual PLL architecture
PLL1
Low bandwidth for reference input clock cleanup with
external VCXO
Phase detector rate of 300 kHz to 75 MHz
Redundant reference inputs
Auto and manual reference switchover modes
Revertive and nonrevertive switching
Loss of reference detection with holdover mode
Low noise LVCMOS output from VCXO used for RF/IF
synthesizers
PLL2
Phase detector rate of up to 250 MHz
Integrated low noise VCO
APPLICATIONS
LTE and multicarrier GSM base stations
Wireless and broadband infrastructure
Medical instrumentation
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
High performance wireless transceivers
ATE and high performance instrumentation
FUNCTIONAL BLOCK DIAGRAM
PLL1
REFA,
REFA OUT0,
OUT0
OUT1,
OUT1
OUT4,
OUT4
OUT5,
OUT5
OSC
REFB,
REFB
REF_TEST
SCLK/SCL
SDIO/SDA
SDO
ZD_IN, ZD_IN
CONTROL
INTERFACE
(SPI AND I2C)
EEPROM
PLL2
ZERO
DELAY
AD9524
6-CLOCK
DISTRIBUTION
09081-001
Figure 1.
GENERAL DESCRIPTION
The AD9524 provides a low power, multi-output, clock
distribution function with low jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to
4.0 GHz.
The AD9524 is defined to support the clock requirements for
long term evolution (LTE) and multicarrier GSM base station
designs. It relies on an external VCXO to provide the reference
jitter cleanup to achieve the restrictive low phase noise require-
ments necessary for acceptable data converter SNR performance.
The input receivers, oscillator, and zero delay receiver provide
both single-ended and differential operation. When connected
to a recovered system reference clock and a VCXO, the device
generates six low noise outputs with a range of 1 MHz to 1 GHz
and one dedicated buffered output from the input PLL (PLL1).
The frequency and phase of one clock output relative to another
clock output can be varied by means of a divider phase select
function that serves as a jitter-free coarse timing adjustment in
increments that are equal to one-half the period of the signal
coming out of the VCO.
An in-package EEPROM can be programmed through the serial
interface to store user-defined register settings for power-up
and chip reset.
AD9524
Rev. C | Page 2 of 56
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Conditions ..................................................................................... 4
Supply Current.............................................................................. 4
Power Dissipation......................................................................... 6
REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, and ZD_IN,
ZD_IN Input Characteristics...................................................... 6
OSC_CTRL Output Characteristics .......................................... 7
REF_TEST Input Characteristics ............................................... 7
PLL1 Output Characteristics ...................................................... 7
Distribution Output Characteristics (OUT0, OUT0 to OUT5,
OUT5)............................................................................................ 8
Timing Alignment Characteristics............................................. 9
Jitter and Noise Characteristics .................................................. 9
PLL2 Characteristics .................................................................... 9
Logic Input Pins—PD, SYNC, RESET, EEPROM_SEL,
REF_SEL...................................................................................... 10
Status Output Pins—STATUS1, STATUS0 ............................. 10
Serial Control Port—SPI Mode ................................................ 10
Serial Control Port—IC Mode ................................................ 11
Absolute Maximum Ratings.......................................................... 12
Thermal Resistance .................................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions........................... 13
Typical Performance Characteristics ........................................... 15
Input/Output Termination Recommendations.......................... 17
Terminology.................................................................................... 18
Theory of Operation ...................................................................... 19
Detailed Block Diagram ............................................................ 19
Overview ..................................................................................... 19
Component Blocks—Input PLL (PLL1).................................. 20
Component Blocks—Output PLL (PLL2) .............................. 21
Clock Distribution ..................................................................... 23
Zero Delay Operation................................................................ 25
Serial Control Port ......................................................................... 26
SPI/IC Port Selection................................................................ 26
IC Serial Port Operation.......................................................... 26
SPI Serial Port Operation.......................................................... 29
SPI Instruction Word (16 Bits)................................................. 30
SPI MSB/LSB First Transfers .................................................... 30
EEPROM Operations..................................................................... 33
Writing to the EEPROM ........................................................... 33
Reading from the EEPROM ..................................................... 33
Programming the EEPROM Buffer Segment......................... 34
Power Dissipation and Thermal Considerations ....................... 36
Clock Speed and Driver Mode ................................................. 36
Evaluation of Operating Conditions........................................ 36
Thermally Enhanced Package Mounting Guidelines............ 36
Control Registers............................................................................ 37
Control Register Map ................................................................ 37
Control Register Map Bit Descriptions................................... 41
Outline Dimensions ....................................................................... 53
Ordering Guide .......................................................................... 53
AD9524
Rev. C | Page 3 of 56
REVISION HISTORY
6/11—Rev. B to Rev. C
Changes to Table 2, Clock Output Drivers—Lower Power Mode
Off and Clock Output Drivers—Lower Power Mode On
Parameters..........................................................................................4
Changes to Table 3, Incremental Power Dissipation, Low Power
Typical Configuration Parameters..................................................6
Changes to Table 17 ........................................................................12
Changes to Overview Section, Crystal Oscillator Values ..........19
Changes to Power Dissipation and Thermal Considerations
Section ..............................................................................................36
Deleted Examples from Evaluation of Operating Conditions
Section ..............................................................................................37
Changes to Table 30, Register 0x1BB Bit Values .........................40
Changes to Table 52 Bit Values......................................................49
3/11—Rev. A to Rev. B
Added Table Summary, Table 8.......................................................7
Changes to Table 9 ............................................................................8
Changes to EEPROM Operations Section and Writing to the
EEPROM Section ............................................................................32
Changes to Addr (Hex) 0x01A, Bits[4:3], Table 30.....................37
Changes to Bits[4:3], Table 40 .......................................................43
1/11—Rev. 0 to Rev. A
Changes to General Description Section .......................................1
Changes to Specifications Summary Statement............................4
Changes to Test Conditions/Comments for VDD3_PLL1,
Supply Voltage for PLL1 Parameter, Table 2..................................4
Changes to Typical Configuration and Low Power Typical
Configuration Parameters, Table 3 .................................................5
Changes to Input High Voltage and Input Low Voltage
Parameters; Added Input Threshold Voltage Parameter,
Table 4.................................................................................................5
Changed Differential Output Voltage Swing Parameters to
Differential Output Voltage Magnitude; Changes to Test
Conditions/Comments, Table 8 ......................................................7
Changed Junction Temperature Parameter from 150°C to
115°C, Table 16................................................................................11
Added Figure 14; Renumbered Sequentially...............................15
Changes to Figure 15, Figure 17, and Figure 19; Change to
Caption of Figure 21 .......................................................................16
Added PLL1 Lock Detect Section.................................................19
Changes to VCO Calibration Section...........................................21
Changed Output Mode Section to Multimode Output
Drivers; Changes to Multimode Output Drivers Section..........22
Changes to Figure 29 ......................................................................24
Changes to SPI/I2C Port Selection Section .................................25
Change to SPI Instruction Word (16 Bits) Section.....................29
Added Power Dissipation and Thermal Considerations
Section ..............................................................................................35
Changes to Table 34 to Table 36 and Table 38.............................42
Change to Register 0x0F3, Bit 1 Description, Table 47..............45
Change to Register 0x198, Bits[7:2], Table 50.............................47
Changes to Table 52 ........................................................................48
Changes to Register 0x230 and Register 0x231, Table 54..........49
7/10—Revision 0: Initial Version
AD9524
Rev. C | Page 4 of 56
SPECIFICATIONS
fVCXO = 122.88 MHz single-ended, REFA and REFB on differential at 30.72 MHz, fVCO = 3932.16 MHz, doubler is off, channel control low
power mode off, divider phase =1, unless otherwise noted. Typical is given for VDD = 3.3 V ± 5%, and TA = 25°C, unless otherwise
noted. Minimum and maximum values are given over the full VDD and TA (−40°C to +85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY VOLTAGE
VDD3_PLL1, Supply Voltage for PLL1 3.3 V 3.3 V ± 5%
VDD3_PLL2, Supply Voltage for PLL2 3.3 V 3.3 V ± 5%
VDD3_REF, Supply Voltage Clock Output Drivers Reference 3.3 V 3.3 V ± 5%
VDD1.8_PLL2, Supply Voltage for PLL2 1.8 V 1.8 V ± 5%
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 3.3 V 3.3 V ± 5%
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers 1.8 V 1.8 V ± 5%
TEMPERATURE RANGE, TA −40 +25 +85 °C
1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 41 and Pin 40,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 38 and Pin 37, respectively).
SUPPLY CURRENT
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS
VDD3_PLL1, Supply Voltage for PLL1 22 25.2 mA Decreases by 9 mA typical if REFB is turned off
VDD3_PLL2, Supply Voltage for PLL2 67 77.7 mA
VDD3_REF, Supply Voltage Clock Output Drivers Reference
LVPECL Mode 5 6 mA Only one output driver turned on; for each
additional output that is turned on, the current
increments by 1.2 mA maximum
LVDS Mode 4 4.8 mA Only one output driver turned on; for each
additional output that is turned on, the current
increments by 1.2 mA maximum
HSTL Mode 3 3.6 mA Values are independent of the number of
outputs turned on
CMOS Mode 3 3.6 mA Values are independent of the number of
outputs turned on
VDD1.8_PLL2, Supply Voltage for PLL2 15 18 mA
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers2 3.5 4.2 mA Current for each divider: f = 245.76 MHz
CLOCK OUTPUT DRIVERS—LOWER POWER MODE OFF Channel x control register, Bit 4 = 0
LVDS Mode, 7 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 11.5 13.2 mA f = 122.88 MHz
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 40 45 mA f = 983.04 MHz
LVDS Mode, 3.5 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 6.5 7.5 mA f = 122.88 MHz
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 23 26.3 mA f = 983.04 MHz
LVPECL Mode
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 13 14.4 mA f = 122.88 MHz
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 41 46.5 mA f = 983.04 MHz
HSTL Mode, 8 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 14 16.3 mA f = 122.88 MHz
CMOS Mode (Single-Ended)
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 2 2.4 mA f = 15.36 MHz, 10 pF load
AD9524
Rev. C | Page 5 of 56
Parameter Min Typ Max Unit Test Conditions/Comments
CLOCK OUTPUT DRIVERS—LOWER POWER MODE ON Channel x control register, Bit 4 = 1
LVDS Mode, 7 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 10 10.8 mA f = 122.88 MHz
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 27 29.8 mA f = 983.04 MHz
LVDS Mode, 3.5 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 6.5 7.5 mA f = 122.88 MHz
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 23 26.3 mA f = 983.04 MHz
LVPECL Mode
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 11 12.4 mA f = 122.88 MHz
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 28 31.2 mA f = 983.04 MHz
HSTL Mode, 16 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 20 24.3 mA f = 122.88 MHz
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 50 59.1 mA f = 983.04 MHz
HSTL Mode, 8 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 11 12.7 mA f = 122.88 MHz
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 27 31.8 mA f = 983.04 MHz
1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 41 and Pin 40,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 38 and Pin 37, respectively).
2 The current for Pin 34 (VDD1.8_OUT[0:3]) is 2× that of the other VDD1.8_OUT[x:y] pairs.
AD9524
Rev. C | Page 6 of 56
POWER DISSIPATION
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER DISSIPATION Does not include power dissipated in termination resistors
Typical Configuration 571 680 mW Clock distribution outputs running as follows: four LVPECL outputs
at 122.88 MHz, two LVDS outputs (3.5 mA) at 122.88 MHz,
one differential input reference at 30.72 MHz; fVCXO = 122.88 MHz,
fVCO = 3932.16 MHz; PLL2 BW = 530 kHz; doubler is off
PD, Power-Down 101 132.2 mW
PD pin pulled low, with typical configuration conditions
INCREMENTAL POWER DISSIPATION
Low Power Typical Configuration 367 428.4 mW Absolute total power with clock distribution; one LVPECL output
running at 122.88 MHz; one differential input reference at
30.72 MHz; fVCXO = 122.88 MHz, fVCO = 3932.16 MHz; doubler is off
Switched to One Input,
Reference Single-Ended Mode
−28.5 −8 mW Running at 30.72 MHz
Switched to Two Inputs,
Reference Differential Mode
26 44.6 mW Running at 30.72 MHz
Switched to Two Inputs,
Reference Single-Ended Mode
−27.5 −5.1 mW Running at 30.72 MHz
Output Distribution, Driver On Incremental power increase (OUT1) from low power typical (3.3 V)
LVDS 15.3 18.4 mW Single 3.5 mA LVDS output at 245.76 MHz
47.8 55.4 mW Single 7 mA LVDS output at 61.44 MHz
LVPECL 50.1 54.9 mW Single LVPECL output at 122.88 MHz
HSTL 40.2 46.3 mW Single 8 mA HSTL output at 122.88 MHz
43.7 50.3 mW Single 16 mA HSTL output at 122.88 MHz
CMOS 6.6 7.9 mW Single 3.3 V CMOS output at 15.36 MHz
9.9 11.9 mW Dual complementary 3.3 V CMOS output at 15.36 MHz
9.9 11.9 mW Dual in-phase 3.3 V CMOS output at 15.36 MHz
REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, AND ZD_IN, ZD_IN INPUT CHARACTERISTICS
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
DIFFERENTIAL MODE
Input Frequency Range 400 MHz
Input Slew Rate (OSC_IN) 400 V/µs Minimum limit imposed for jitter performance
Common-Mode Internally
Generated Input Voltage
0.6 0.7 0.8 V
Input Common-Mode Range 1.025 1.475 V For dc-coupled LVDS (maximum swing)
Differential Input Voltage,
Sensitivity Frequency < 250 MHz
100 mV p-p
Capacitive coupling required; can accommodate single-ended
input by ac grounding of unused input; the instantaneous voltage
on either pin must not exceed the 1.8 V dc supply rails
Differential Input Voltage,
Sensitivity Frequency > 250 MHz
200 mV p-p
Capacitive coupling required; can accommodate single-ended
input by ac grounding of unused input; the instantaneous voltage
on either pin must not exceed the 1.8 V dc supply rails
Differential Input Resistance 4.8 kΩ
Differential Input Capacitance 1 pF
Duty Cycle Duty cycle bounds are set by pulse width high and pulse width low
Pulse Width Low 1 ns
Pulse Width High 1 ns
CMOS MODE SINGLE-ENDED INPUT
Input Frequency Range 250 MHz
Input High Voltage 1.6 V
Input Low Voltage 0.52 V
Input Threshold Voltage 1.0 V When ac coupling to the input receiver, the user must dc bias the
input to 1 V; the single-ended CMOS input is 3.3 V compatible
AD9524
Rev. C | Page 7 of 56
Input Capacitance 1 pF
Duty Cycle Duty cycle bounds are set by pulse width high and pulse width low
Pulse Width Low 1.6 ns
Pulse Width High 1.6 ns
OSC_CTRL OUTPUT CHARACTERISTICS
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
OUTPUT VOLTAGE
High VDD3_PLL1 − 0.15 V RLOAD > 20 kΩ
Low 150 mV
REF_TEST INPUT CHARACTERISTICS
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
REF_TEST INPUT
Input Frequency Range 250 MHz
Input High Voltage 2.0 V
Input Low Voltage 0.8 V
PLL1 OUTPUT CHARACTERISTICS
Table 7.
Parameter1 Min Typ Max Unit Test Conditions/Comments
MAXIMUM OUTPUT FREQUENCY 250 MHz
Rise/Fall Time (20% to 80%) 387 665 ps 15 pF load
Duty Cycle 45 50 55 % f = 250 MHz
OUTPUT VOLTAGE HIGH Output driver static
VDD3_PLL1 − 0.25 V Load current = 10 mA
VDD3_PLL1 − 0.1 V Load current = 1 mA
OUTPUT VOLTAGE LOW Output driver static
0.2 V Load current = 10 mA
0.1 V Load current = 1 mA
1 CMOS driver strength = strong (see Table 51).
AD9524
Rev. C | Page 8 of 56
DISTRIBUTION OUTPUT CHARACTERISTICS (OUT0, OUT0 TO OUT5, OUT5)
Duty cycle performance is specified with the invert divider bit set to 1, and the divider phase bits set to 0.5. (For example, for Channel 0,
0x196[7] = 1 and 0x198[7:2] = 000001.)
Table 8.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL MODE
Maximum Output Frequency 1 GHz Minimum VCO/maximum dividers
Rise Time/Fall Time (20% to 80%) 117 147 ps 100 Ω termination across output pair
Duty Cycle 47 50 52 % f < 500 MHz
43 48 52 % f = 500 MHz to 800 MHz
40 49 54 % f = 800 MHz to 1 GHz
Differential Output Voltage Magnitude 643 775 924 mV Voltage across pins; output driver static
Common-Mode Output Voltage VDD – 1.5 VDD − 1.4 VDD − 1.25 V Output driver static
SCALED HSTL MODE, 16 mA
Maximum Output Frequency 1 GHz Minimum VCO/maximum dividers
Rise Time/Fall Time (20% to 80%) 112 141 ps 100 Ω termination across output pair
Duty Cycle 47 50 52 % f < 500 MHz
44 48 51 % f = 500 MHz to 800 MHz
40 49 54 % f = 800 MHz to 1 GHz
Differential Output Voltage Magnitude 1.3 1.6 1.7 mV Voltage across pins, output driver static;
nominal supply
Supply Sensitivity 0.6 mV/mV Change in output swing vs. VDD3_OUT[x:y]
(∆VOD/∆VDD3)
Common-Mode Output Voltage VDD − 1.76 VDD − 1.6 VDD − 1.42 V
LVDS MODE, 3.5 mA
Maximum Output Frequency 1 GHz
Rise Time/Fall Time (20% to 80%) 138 161 ps 100 Ω termination across output pair
Duty Cycle 48 51 53 % f < 500 MHz
43 49 53 % f = 500 MHz to 800 MHz
41 49 55 % f = 800 MHz to 1 GHz
Differential Output Voltage Magnitude
Balanced 247 454 mV Voltage across pins; output driver static
Unbalanced 50 mV
Absolute difference between voltage
magnitude of normal pin and inverted pin
Common-Mode Output Voltage 1.125 1.375 V Output driver static
Common-Mode Difference 50 mV Voltage difference between output pins;
output driver static
Short-Circuit Output Current 3.5 24 mA Output driver static
CMOS MODE
Maximum Output Frequency 250 MHz
Rise Time/Fall Time (20% to 80%) 387 665 ps 15 pF load
Duty Cycle 45 50 55 % f = 250 MHz
Output Voltage High Output driver static
VDD − 0.25 V Load current = 10 mA
VDD − 0.1 V Load current = 1 mA
Output Voltage Low Output driver static
0.2 V Load current = 10 mA
0.1 V Load current = 1 mA
AD9524
Rev. C | Page 9 of 56
TIMING ALIGNMENT CHARACTERISTICS
Table 9.
Parameter Min Typ Max Unit Test Conditions/Comments
OUTPUT TIMING SKEW Delay off on all outputs; maximum deviation
between rising edges of outputs; all outputs are on,
unless otherwise noted.
Between LVPECL, HSTL, and LVDS Outputs 38 164 ps
Between CMOS Outputs 100 300 ps Single-ended true phase high-Z mode
Adjustable Delay 0 63 Steps Resolution step; for example, 8 × 0.5/1 GHz
Resolution Step 500 ps ½ period of 1 GHz
Zero Delay
Between Input Clock Edge on REFA or
REFB to ZD_IN Input Clock Edge,
External Zero Delay Mode
150 500 ps
PLL1 settings: PFD = 7.68 MHz, ICP = 63.5 µA, RZERO = 10 kΩ,
antibacklash pulse width is at maximum, BW = 40 Hz,
REFA and ZD_IN are set to differential mode
JITTER AND NOISE CHARACTERISTICS
Table 10.
Parameter Min Typ Max Unit Test Conditions/Comments
OUTPUT ABSOLUTE RMS TIME JITTER Application example based on a typical setup
(see Table 3); f = 122.88 MHz
LVPECL Mode, HSTL Mode, LVDS Mode
125 fs Integrated BW = 200 kHz to 5 MHz
136 fs Integrated BW = 200 kHz to 10 MHz
169 fs Integrated BW = 12 kHz to 20 MHz
212 fs Integrated BW = 10 kHz to 61 MHz
223 fs Integrated BW = 1 kHz to 61 MHz
PLL2 CHARACTERISTICS
Table 11.
Parameter Min Typ Max Unit Test Conditions/Comments
VCO (ON CHIP)
Frequency Range 3600 4000 MHz
Gain 45 MHz/V
PLL2 FIGURE OF MERIT (FOM) −226 dBc/Hz
MAXIMUM PFD FREQUENCY
Antibacklash Pulse Width
Minimum and Low 250 MHz
Maximum and High 125 MHz
AD9524
Rev. C | Page 10 of 56
LOGIC INPUT PINS—PD, SYNC, RESET, EEPROM_SEL, REF_SEL
Table 12.
Parameter Min Typ Max Unit Test Conditions/Comments
VOLTAGE
Input High 2.0 V
Input Low 0.8 V
INPUT LOW CURRENT ±80 ±250 µA The minus sign indicates that, due to the
internal pull-up resistor, current is flowing
out of the AD9524
CAPACITANCE 3 pF
RESET TIMING
Pulse Width Low 50 ns
Inactive to Start of Register Programming 100 ns
SYNC TIMING
Pulse Width Low 1.5 ns High speed clock is CLK input signal
STATUS OUTPUT PINS—STATUS1, STATUS0
Table 13.
Parameter Min Typ Max Unit Test Conditions/Comments
VOLTAGE
Output High 2.94 V
Output Low 0.4 V
SERIAL CONTROL PORT—SPI MODE
Table 14.
Parameter Min Typ Max Unit Test Conditions/Comments
CS (INPUT)
CS has an internal 40 kΩ pull-up resistor
Voltage
Input Logic 1 2.0 V
Input Logic 0 0.8 V
Current
Input Logic 1 30 µA
Input Logic 0 −110 µA The minus sign indicates that, due to the
internal pull-up resistor, current is flowing out
of the AD9524
Input Capacitance 2 pF
SCLK (INPUT) IN SPI MODE SCLK has an internal 40 kΩ pull-down resistor
in SPI mode but not in I2C mode
Voltage
Input Logic 1 2.0 V
Input Logic 0 0.8 V
Current
Input Logic 1 240 µA
Input Logic 0 1 µA
Input Capacitance 2 pF
SDIO (WHEN INPUT IS IN BIDIRECTIONAL MODE)
Voltage
Input Logic 1 2.0 V
Input Logic 0 0.8 V
Current
Input Logic 1 1 µA
Input Logic 0 1 µA
Input Capacitance 2 pF
AD9524
Rev. C | Page 11 of 56
Parameter Min Typ Max Unit Test Conditions/Comments
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage 2.7 V
Output Logic 0 Voltage 0.4 V
TIMING
Clock Rate (SCLK, 1/tSCLK) 25 MHz
Pulse Width High, tHIGH 8 ns
Pulse Width Low, tLOW 12 ns
SDIO to SCLK Setup, tDS 3.3 ns
SCLK to SDIO Hold, tDH 0 ns
SCLK to Valid SDIO and SDO, tDV 14 ns
CS to SCLK Setup, tS 10 ns
CS to SCLK Setup and Hold, tS, tC 0 ns
CS Minimum Pulse Width High, tPWH 6 ns
SERIAL CONTROL PORT—I²C MODE
VDD = VDD3_REF, unless otherwise noted.
Table 15.
Parameter Min Typ Max Unit Test Conditions/Comments
SDA, SCL (WHEN INPUTTING DATA)
Input Logic 1 Voltage 0.7 × VDD V
Input Logic 0 Voltage 0.3 × VDD V
Input Current with an Input Voltage Between
0.1 × VDD and 0.9 × VDD
−10 +10 µA
Hysteresis of Schmitt Trigger Inputs 0.015 × VDD V
Pulse Width of Spikes That Must Be
Suppressed by the Input Filter, tSPIKE
50 ns
SDA (WHEN OUTPUTTING DATA)
Output Logic 0 Voltage at 3 mA Sink Current 0.4 V
Output Fall Time from VIHMIN to VILMAX with
a Bus Capacitance from 10 pF to 400 pF
20 + 0.1 CB1 250 ns
TIMING
Note that all I2C timing values are referred to
VIHMIN (0.3 × VDD) and VILMAX levels (0.7 × VDD)
Clock Rate (SCL, fI2C) 400 kHz
Bus Free Time Between a Stop and Start
Condition, tIDLE
1.3 µs
Setup Time for a Repeated Start Condition,
tSET; STR
0.6 µs
Hold Time (Repeated) Start Condition, tHLD; STR 0.6 µs After this period, the first clock pulse is
generated
Setup Time for Stop Condition, tSET; STP 0.6 µs
Low Period of the SCL Clock, tLOW 1.3 µs
High Period of the SCL Clock, tHIGH 0.6 µs
SCL, SDA Rise Time, tRISE 20 + 0.1 CB1 300 ns
SCL, SDA Fall Time, tFALL 20 + 0.1 CB1 300 ns
Data Setup Time, tSET; DAT 100 ns
Data Hold Time, tHLD; DAT 100 880 ns
This is a minor deviation from the original I²C
specification of 0 ns minimum2
Capacitive Load for Each Bus Line, CB1 400 pF
1 CB is the capacitance of one bus line in picofarads (pF).
2 According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL
falling edge.
AD9524
Rev. C | Page 12 of 56
ABSOLUTE MAXIMUM RATINGS
Table 16.
Parameter Rating
VDD3_PLL1, VDD3_PLL2, VDD3_REF,
VDD3_OUT, LDO_VCO to GND
−0.3 V to +3.6 V
REFA, REFA, REFIN, REFB, REFB to GND −0.3 V to +3.6 V
SCLK/SCL, SDIO/SDA, SDO, CS to GND −0.3 V to +3.6 V
OUT0, OUT0, OUT1, OUT1, OUT2, OUT2,
OUT3, OUT3, OUT4, OUT4, OUT5, OUT5,
to GND
−0.3 V to +3.6 V
SYNC, RESET, PD to GND −0.3 V to +3.6 V
STATUS0, STATUS1 to GND −0.3 V to +3.6 V
SP0, SP1, EEPROM to GND −0.3 V to +3.6 V
VDD1.8_PLL2, VDD1.8_OUT, LDO_PLL1,
LDO_PLL2 to GND
2 V
Junction Temperature1 115°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (10 sec) 300°C
1 See Table 17 for θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 17. Thermal Resistance
Package Type
Airflow
Velocity
(m/sec) θJA1, 2 θJC1, 3 θJB1, 4 ΨJT1, 2 Unit
0 26.1 1.7 13.8 0.2 °C/W
1.0 22.8 0.2 °C/W
48-Lead LFCSP,
7 mm ×
7 mm 2.5 20.4 0.3 °C/W
1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-Std 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
For information about power dissipation, refer to the Power
Dissipation and Thermal Considerations section.
ESD CAUTION
AD9524
Rev. C | Page 13 of 56
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
24
23
22
21
20
19
18
17
16
15
14
13
44
45
46
47
48
43
42
41
40
39
38
37
TOP
VIEW
(Not to Scale)
AD9524
25
26
27
28
29
30
31
32
33
34
35
36
8
9
10
11
12
09081-002
REFA
REFA
REFB
REFB
LF1_EXT_CAP
OSC_CTRL
OSC_IN
OSC_IN
LF2_EXT_CAP
LDO_PLL2
VDD3_PLL2
LDO_VCO
SYNC
VDD3_REF
CS
SCLK/SCL
SDIO/SDA
SDO
OUT5
OUT5
VDD3_OUT[4:5]
OUT4
OUT4
VDD1.8_OUT[4:5]
VDD1.8_OUT[0:3]
OUT2
OUT2
VDD3_OUT[2:3]
OUT3
OUT3
EEPROM_SEL
PD
RESET
REF_TEST
PLL1_OUT
LDO_PLL1
VDD3_PLL1
REF_SEL
ZD_IN
ZD_IN
VDD1.8_PLL2
OUT0
OUT0
VDD3_OUT[0:1]
OUT1
OUT1
STATUS0/SP0
STATUS1/SP1
NOTES
1. THE EXPOSED PADDLE IS A GROUND CONNECTION ON THE CHIP. IT MUST BE SOLDERED
TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY
AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.
Figure 2. Pin Configuration
Table 18. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1 REFA I
Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
2 REFA I Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for
the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3V CMOS input.
3 REFB I
Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
4 REFB I Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for
the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
5 LF1_EXT_CAP O PLL1 External Loop Filter Capacitor. Connect this pin to ground.
6 OSC_CTRL O Oscillator Control Voltage. Connect to the voltage control pin of the external oscillator.
7 OSC_IN I
PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
8 OSC_IN I Complementary PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the
PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
9 LF2_EXT_CAP O PLL2 External Loop Filter Capacitor. Connect this pin to the LDO_VCO pin.
10 LDO_PLL2 P/O
LDO Decoupling Pin for PLL2 1.8 V Internal Regulator. Connect a 0.47 F decoupling capacitor
from this pin to ground. Note that for best performance, the LDO bypass capacitor must be
placed in close proximity to the device.
11 VDD3_PLL2 P 3.3 V Supply for PLL2.
12 LDO_VCO P/O
2.5 V LDO Internal Regulator Decoupling Pin for VCO. Connect a 0.47 µF decoupling capacitor
from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be
placed in close proximity to the device.
13 SYNC I Manual Synchronization. This pin initiates a manual synchronization and has an internal
40 kΩ pull-up resistor.
14 VDD3_REF P 3.3 V Supply for Output Clock Drivers Reference.
15 CS I Serial Control Port Chip Select, Active Low. This pin has an internal 40 kΩ pull-up resistor.
16 SCLK/SCL I
Serial Control Port Clock Signal for SPI Mode (SCLK) or I2C Mode (SCL). Data clock for serial programming.
This pin has an internal 40 kΩ pull-down resistor in SPI mode but is high impedance in I²C mode.
17 SDIO/SDA I/O Serial Control Port Bidirectional Serial Data In/Out for SPI Mode (SDIO) or I²C Mode (SDA).
AD9524
Rev. C | Page 14 of 56
Pin No. Mnemonic Type1 Description
18 SDO O
Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode).
There is no internal pull-up/pull-down resistor on this pin.
19 OUT5 O
Complementary Clock Output 5. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
20 OUT5 O
Clock Output 5. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output
or as a single-ended CMOS output.
21 VDD3_OUT[4:5] P 3.3 V Supply for Output 4 and Output 5 Clock Drivers.
22 OUT4 O
Complementary Clock Output 4. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
23 OUT4 O
Clock Output 4. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output
or as a single-ended CMOS output.
24 VDD1.8_OUT[4:5] P 1.8 V Supply for Output 4 and Output 5 Clock Dividers.
25 REF_TEST I Test Input to PLL1 Phase Detector.
26 RESET I
Digital Input, Active Low. Resets internal logic to default states. This pin has an internal
40 kΩ pull-up resistor.
27 PD Chip Power-Down, Active Low. This pin has an internal 40 kΩ pull-up resistor.
28 EEPROM_SEL I
EEPROM Select. Setting this pin high selects the register values stored in the internal EEPROM to
be loaded at reset and/or power-up. Setting this pin low causes the AD9524 to load the hard-
coded default register values at power-up/reset. This pin has an internal 40 kΩ pull-down resistor.
29 OUT3 O
Complementary Clock Output 3. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
30 OUT3 O
Square Wave Clocking Output 3. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
31 VDD3_OUT[2:3] P 3.3 V Supply Output 2 and Supply Output 3 Clock Drivers.
32 OUT2 O
Complementary Clock Output 2. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
33 OUT2 O
Clock Output 2. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output
or as a single-ended CMOS output.
34 VDD1.8_OUT[0:3] P 1.8 V Supply for Output 0, Output 1, Output 2, and Output 3 Clock Dividers.
35 STATUS1/SP1 I/O Lock Detect and Other Status Signals (STATUS1)/I2C Address (SP1).
36 STATUS0/SP0 I/O Lock Detect and Other Status Signals (STATUS0)/I2C Address (SP0).
37 OUT1 O
Complementary Clock Output 1. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
38 OUT1 O
Clock Output 1. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output
or as a single-ended CMOS output.
39 VDD3_OUT[0:1] P 3.3 V Supply Output 0 and Supply Output 1 Clock Drivers.
40 OUT0 O
Complementary Clock Output 0. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
41 OUT0 O
Clock Output 0. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output
or as a single-ended CMOS output.
42 VDD1.8_PLL2 P 1.8 V Supply for PLL2.
43 ZD_IN I External Zero Delay Clock Input. Along with ZD_IN, this pin is the differential input for the PLL
reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
44 ZD_IN I
Complementary External Zero Delay Clock Input. Along with ZD_IN, this pin is the differential input
for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
45 REF_SEL I Reference Input Select. This pin has an internal 40 kΩ pull-down resistor.
46 PLL1_OUT O
Single-Ended CMOS Output from PLL1. This pin has settings for weak and strong in
Register 0x1BA, Bit 4 (see Table 51).
47 LDO_PLL1 P/O
1.8 V Internal LDO Regulator Decoupling Pin for PLL1. Connect a 0.47 µF decoupling capacitor
from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be
placed in close proximity to the device.
48 VDD3_PLL1 P 3.3 V Supply PLL1. Use the same supply as VCXO.
EP EP, GND GND
Exposed Paddle. The exposed paddle is the ground connection on the chip. It must be soldered
to the analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and
mechanical strength benefits.
1 P = power, I = input, O = output, I/O = input/output, P/O = power/output, GND = ground.
AD9524
Rev. C | Page 15 of 56
TYPICAL PERFORMANCE CHARACTERISTICS
fVCXO = 122.88 MHz, REFA differential at 30.72 MHz, fVCO = 3686.4 MHz, and doubler is off, unless otherwise noted.
0
10
20
30
40
50
60
0 200 400 600 800 1000 1200
CURRENT (mA)
FREQUENCY (MHz)
HSTL = 16mA
HSTL = 8mA
09081-003
Figure 3. VDD3_OUT[x:y] Current (Typical) vs. Frequency;
HSTL Mode, 16 mA and 8 mA
0
5
10
15
20
25
30
35
40
45
0 200 400 600 800 1000 1200
CURRENT (mA)
FREQUENCY (MHz)
LVDS = 3.5mA
LVDS = 7m A
09081-004
Figure 4. VDD3_OUT[x:y] Current (Typical) vs. Frequency;
LVDS Mode, 7 mA and 3.5 mA
0
5
10
15
20
25
30
35
40
45
0 200 400 600 800 1000 1200
CURRENT (mA)
FREQUENCY (MHz)
09081-005
Figure 5. VDD3_OUT[x:y] Current (Typical) vs. Frequency, LVPECL Mode
0 100 200 300 400 500
CURRENT (mA)
FREQUENCY (MHz)
10pF
20pF
0
5
10
15
20
25
30
35
09081-006
2pF
Figure 6. VDD3_OUT[x:y] Current (Typical) vs. Frequency;
CMOS Mode, 20 pF, 10 pF, and 2 pF Load
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0 200 400 600 800 1000 1200
DIFFERENTIAL SWING (V p-p)
FREQUENCY (MHz)
HSTL = 8mA
HSTL = 16mA
09081-007
Figure 7. Differential Voltage Swing vs. Frequency;
HSTL Mode, 16 mA and 8 mA
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0 200 400 600 800 1000 1200
DIFFERENTIAL SWING (V p-p)
FREQUENCY (MHz)
09081-008
Figure 8. Differential Voltage Swing vs. Frequency,
LVPECL Mode
AD9524
Rev. C | Page 16 of 56
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0200
400 600 800 1000 1200
DIFFERENTI
A
L SWING (V p-p)
FREQUENCY (MHz)
LVDS = 3.5mA
LVDS = 7m A
09081-009
Figure 9. Differential Voltage Swing vs. Frequency;
LVDS Mode, 7 mA and 3.5 mA
0 100 200 300 400 500
AMPLITUDE (V)
FREQUENCY (MHz)
20pF
2pF
10pF
09081-010
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
Figure 10. Amplitude vs. Frequency and Capacitive Load;
CMOS Mode, 2 pF, 10 pF, and 20 pF
CH1 200mV 2.5ns/DIV
40.0GS/s
A CH1 104mV
1
09081-013
Figure 11. Output Waveform (Differential), LVPECL at 122.88 MHz
–
70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
100 1k 10k 100k 1M 10M
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
1: 100Hz, –85.0688dBc/Hz
2: 1kHz, –113.3955dBc/Hz
3: 8kHz, –125.8719dBc/Hz
4: 16kHz, –129.5942dBc/Hz
5: 100kHz, –134.5017dBc/Hz
6: 1MHz, –145.2872dBc/Hz
7: 10MHz, –156.2706dBc/Hz
8: 40MHz, –157.4153dBc/Hz
x: START 12kHz
STOP 80MHz
CENTER 40.006MHz
SPAN 79.988MHz
NOISE:
ANALYSIS RANGE X: BAND MARKER
ANALYSIS RANGE Y: BAND MARKER
INTG NOISE: –75.94595dBc/39.99MHz
RMS NOISE: 225.539µRAD
12.9224mdeg
RMS JITTER: 194.746fsec
RESIDUAL FM: 2.81623kHz
1
3
5
7
09081-015
Figure 12. Phase Noise, Output = 184.32 MHz
(VCXO = 122.88 MHz, Crystek VCXO CVHD-950)
–
70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
100 1k 10k 100k 1M 10M
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
1: 100Hz, –89.0260dBc/Hz
2: 1kHz, –116.9949dBc/Hz
3: 8kHz, –129.5198dBc/Hz
4: 16kHz, –133.3916dBc/Hz
5: 100kHz, –137.7680dBc/Hz
6: 1MHz, –148.3519dBc/Hz
7: 10MHz, –158.3307dBc/Hz
8: 40MHz, 159.1629–dBc/Hz
x: START 12kHz
STOP 80MHz
CENTER 40.006MHz
SPAN 79.988MHz
NOISE:
ANALYSIS RANGE X: BAND MARKER
ANALYSIS RANGE Y: BAND MARKER
INTG NOISE: –78.8099dBc/39.99MHz
RMS NOISE: 162.189µRAD
9.29276mdeg
RMS JITTER: 210.069fsec
RESIDUAL FM: 2.27638kHz
1
3
5
7
09081-016
Figure 13. Phase Noise, Output = 122.88 MHz
(VCXO = 122.88 MHz, Crystek VCXO CVHD-950; Doubler Is Off)
CH1 500mV Ω 2.5ns/DIV
40.0GS/s
A CH1 80mV
1
09081-017
Figure 14. Output Waveform (Differential), HSTL at 16 mA, 122.88 MHz
AD9524
Rev. C | Page 17 of 56
INPUT/OUTPUT TERMINATION RECOMMENDATIONS
100Ω
0.1µF
0.1µF
DOWNSTREAM
DEVICE
LVDS
OUTPUT
HIGH
IMPEDANCE
INPUT
AD9524
09081-142
Figure 15. AC-Coupled LVDS Output Driver
100ΩDOWNSTREAM
DEVICE
LVDS
OUTPUT
AD9524
HIGH
IMPEDANCE
INPUT
09081-143
Figure 16. DC-Coupled LVDS Output Driver
100Ω
0.1µF
0.1µF
DOWNSTREAM
DEVICE
LVPECL-
COMPATIBLE
OUTPUT
HIGH
IMPEDANCE
INPUT
09081-044
AD9524
Figure 17. AC-Coupled LVPECL Output Driver
100ΩDOWNSTREAM
DEVICE
LVPECL-
COMPATIBLE
OUTPUT
HIGH
IMPEDANCE
INPUT
AD9524
09081-045
Figure 18. DC-Coupled LVPECL Output Driver
100Ω
0.1µF
0.1µF
DOWNSTREAM
DEVICE
HSTL
OUTPUT
HIGH
IMPEDANCE
INPUT
09081-046
AD9524
Figure 19. AC-Coupled HSTL Output Driver
100ΩDOWNSTREAM
DEVICE
HSTL
OUTPUT
HIGH
IMPEDANCE
INPUT
AD9524
09081-047
Figure 20. DC-Coupled HSTL Output Driver
100Ω
(OPTIONAL
1
)
1
RESISTOR VALUE DEPENDS UPON
REQUIRED TERMINATION OF SOURCE.
0.1µF
0.1µF
SELF-BIASED
REF, VCXO,
ZERO DELAY
INPUTS
AD9524
09081-048
Figure 21. REF, VCXO, and Zero Delay Input, Differential Mode (When In
CMOS Single-Ended Input Mode, the Unused Input Can Be Left Unconnected)
AD9524
Rev. C | Page 18 of 56
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for
each cycle. Actual signals, however, display a certain amount
of variation from ideal phase progression over time. This
phenomenon is called phase jitter. Although many causes can
contribute to phase jitter, one major cause is random noise,
which is characterized statistically as being Gaussian (normal)
in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a
series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in decibels) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency interval.
Phase noise has a detrimental effect on the performance of ADCs,
DACs, and RF mixers. It lowers the achievable dynamic range of
the converters and mixers, although they are affected in somewhat
different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When observing
a sine wave, the time of successive zero crossings varies. In a square
wave, the time jitter is a displacement of the edges from their
ideal (regular) times of occurrence. In both cases, the variations in
timing from the ideal are the time jitter. Because these variations
are random in nature, the time jitter is specified in seconds root
mean square (rms) or 1 sigma (Σ) of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the signal-to-noise ratio (SNR) and dynamic
range of the converter. A sampling clock with the lowest possible
jitter provides the highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that can be
attributed to the device or subsystem being measured. The phase
noise of any external oscillators or clock sources is subtracted.
This makes it possible to predict the degree to which the device
impacts the total system phase noise when used in conjunction
with the various oscillators and clock sources, each of which
contributes its own phase noise to the total. In many cases, the
phase noise of one element dominates the system phase noise.
When there are multiple contributors to phase noise, the total
is the square root of the sum of squares of the individual
contributors.
Additive Time Jitter
Additive time jitter is the amount of time jitter that can be
attributed to the device or subsystem being measured. The time
jitter of any external oscillators or clock sources is subtracted.
This makes it possible to predict the degree to which the device
impacts the total system time jitter when used in conjunction with
the various oscillators and clock sources, each of which contributes
its own time jitter to the total. In many cases, the time jitter of the
external oscillators and clock sources dominates the system time
jitter.
AD9524
Rev. C | Page 19 of 56
THEORY OF OPERATION
DETAILED BLOCK DIAGRAM
CHARGE
PUMP
×2
÷D1
VCXO
SWITCH-
OVER
CONTROL
RESYNCH
÷M1
STATUS MONITOR
LOCK DETECT/
SERIAL PORT
ADDRESS
CONTROL
INTERFACE
(SPI AND I2C)
SCLK/SCL
SDO
SDIO/SDA
÷N2
PLL2
LDO_PLL2
LOOP
FILTER
TO SYNC
LOOP
FILTER
CHARGE
PUMP
PLL1
LOCK
DETECT
LOCK
DETECT
P
F
D
ZD_IN
ZD_IN
PD
RESET
SYNC
÷D ∆t
EDGE
÷D ∆t
EDGE
÷D ∆t
EDGE
÷D ∆t
EDGE
÷D ∆t
EDGE
÷D ∆t
EDGE
SYNC
SIGNAL
PLL1_OUT VDD1.8_OUT[X:Y]
REFA
REFA
REFB
REFB
AD9524
REF_SEL
STATUS0/
SP0
STATUS1/
SP1
EEPROM
EEPROM_SEL
LF2_EXT_CAPLF1_EXT_CAP
REF_TEST
OSC_CTRL OSC_IN
CS
÷R
÷R
÷R
÷N1
LDO_PLL1 LDO_VCO VDD3_OUT[X:Y]
VDD3_PLL1
VDD3_PLL2 VDD1.8_PLL2
VCO
P
F
D
OUT5
OUT5
OUT4
OUT4
OUT3
OUT3
OUT2
OUT2
OUT1
OUT1
OUT0
OUT0
09081-020
Figure 22. Top Level Diagram
OVERVIEW
The AD9524 is a clock generator that employs integer-N-based
phase-locked loops (PLL). The device architecture consists of
two cascaded PLL stages. The first stage, PLL1, consists of an
integer division PLL that uses an external voltage-controlled
crystal oscillator (VCXO) of up to 250 MHz. PLL1 has a narrow-
loop bandwidth that provides initial jitter cleanup of the input
reference signal. The second stage, PLL2, is a frequency
multiplying PLL that translates the first stage output frequency
to a range of 3.6 GHz to 4.0 GHz. PLL2 incorporates an integer-
based feedback divider that enables integer frequency multipli-
cation. Programmable integer dividers (1 to 1024) follow PLL2,
establishing a final output frequency of 1 GHz or less.
The AD9524 includes reference signal processing blocks that
enable a smooth switching transition between two reference
inputs. This circuitry automatically detects the presence of the
reference input signals. If only one input is present, the device
uses it as the active reference. If both are present, one becomes
the active reference and the other becomes the backup reference.
If the active reference fails, the circuitry automatically switches
to the backup reference (if available), making it the new active
reference. A register setting determines what action to take if the
failed reference is once again available: either stay on Reference B
or revert to Reference A. In the event that neither reference is
usable, the AD9524 supports a holdover mode. A reference
select pin (REF_SEL, Pin 45) is available to manually select
which input reference is active (see Table 42). The accuracy of
the holdover is dependent on the external VCXO frequency
stability at half supply voltage.
Any of the divider settings are programmable via the serial
programming port, enabling a wide range of input/output
frequency ratios under program control. The dividers also
include a programmable delay to adjust timing of the output
signals, if required.
The output is compatible with LVPECL, LVDS, or HSTL logic
levels (see the Input/Output Termination Recommendations
section); however, the AD9524 is implemented only in CMOS.
The loop filters of each PLL are integrated and programmable.
Only a single external capacitor for each of the two PLL loop
filters is required.
The AD9524 operates over the extended industrial temperature
range of −40°C to +85°C.
AD9524
Rev. C | Page 20 of 56
COMPONENT BLOCKS—INPUT PLL (PLL1)
PLL1 General Description
Fundamentally, the input PLL (referred to as PLL1) consists of
a phase-frequency detector (PFD), charge pump, passive loop
filter, and an external VCXO operating in a closed loop, as
shown in Figure 23.
R
ZERO
C
POLE1
R
POLE2
LF1_EXT_CAP
SWITCH-
OVER
CONTROL
REFA
REFB
REFA
REFB
REF_SEL
REF_TEST
DIVIDE BY
1, 2, ...1024
CHARGE
PUMP
7 BITS,
0.5µA LSB
VDD3_PLL1 LDO_PLL1
1.8V LDO
3.3V CMOS
OR 1.8V
DIFFERENTIAL
OSC_CTRL
OSC_IN
DIVIDE BY
1, 2, ...1024
DIVIDE BY
1, 2, ...1024
DIVIDE BY
1, 2, ...63
P
F
DVCXO
C
POLE2
AD9524
09081-021
Figure 23. Input PLL (PLL1) Block Diagram
PLL1 has the flexibility to operate with a loop bandwidth of
approximately 10 Hz to 100 Hz. This relatively narrow loop
bandwidth gives the AD9524 the ability to suppress jitter that
appears on the input references (REFA and REFB). The output
of PLL1 then becomes a low jitter phase-locked version of the
reference input system clock.
PLL1 Lock Detect
PLL1 lock detect issues an unlock condition when the
frequency error is greater than the threshold of the lock
detector. Due to the random phase relationship that exists
between a VCXO and a reference clock that are not locked to
each other, this unlock condition can occur as soon as a 16 ppm
frequency error occurs, to as much as a 32 ppm error.
PLL1 Reference Clock Inputs
The AD9524 features two separate differential reference clock
inputs, REFA and REFB. These inputs can be configured to
operate in full differential mode or single-ended CMOS mode.
In differential mode, these pins are internally self-biased. If
REFA or REFB is driven single-ended, the unused side (REFA,
REFB) should be decoupled via a suitable capacitor to a quiet
ground. shows the equivalent circuit of REFA or REFB.
It is possible to dc-couple to these inputs, but the dc operation
point should be set as specified in the tables.
Figure 21
Specifications
To operate either the REFA or the REFB inputs in 3.3 V CMOS
mode, the user must set Bit 5 or Bit 6, respectively, in Register
0x01A (see Table 40). The single-ended inputs can be driven by
either a dc-coupled CMOS level signal or an ac-coupled sine
wave or square wave.
The differential reference input receiver is powered down when
the differential reference input is not selected, or when the PLL
is powered down. The single-ended buffers power down when
the PLL is powered down, when their respective individual power-
down registers are set, or when the differential receiver is selected.
The REFB R divider uses the same value as the REFA R divider
unless Bit 7, the enable REFB R divider independent division
control bit in Register 0x01C, is programmed as shown in Table 42 .
PLL1 Loop Filter
The PLL1 loop filter requires the connection of an external
capacitor from LF1_EXT_CAP (Pin 5) to ground. The value of the
external capacitor depends on the use of an external VCXO, as
well as such configuration parameters as input clock rate and
desired bandwidth. Normally, a 0.3 µF capacitor allows the loop
bandwidth to range from 10 Hz to 100 Hz and ensures loop
stability over the intended operating parameters of the device
(see Table 43 for RZERO values).
R
ZERO
C
POLE1
R
POLE2
C
POLE2
CHARGE
PUMP
LF1_EXT_CAP LDO_PLL1
BUFFER
1kΩ0.3µF
OSC_CTRL
AD9524
09081-022
Figure 24. PLL1 Loop Filter
Table 19. PLL1 Loop Filter Programmable Values
RZERO
(kΩ)
CPOLE1
(nF)
RPOLE2
(kΩ)
CPOLE2
(nF)
LF1_EXT_CAP1
(μF)
883 1.5 fixed 165 fixed 0.337 fixed 0.3
677
341
135
10
External
1 External loop filter capacitor.
An external R-C low-pass filter should be used at the OSC_CTRL
output. The values shown in Figure 24 add an additional low-pass
pole at ~530 Hz. This R-C network filters the noise associated with
the OSC_CTRL buffer to achieve the best noise performance at the
1 kHz offset region.
PLL1 Input Dividers
Each reference input feeds a dedicated reference divider block.
The input dividers provide division of the reference frequency
in integer steps from 1 to 1023. They provide the bulk of the
frequency prescaling that is necessary to reduce the reference
frequency to accommodate the bandwidth that is typically
desired for PLL1.
AD9524
Rev. C | Page 21 of 56
PLL1 Reference Switchover mode, and PLL1 resynchronizes with the active reference. In
addition to tristate, the charge pump can be forced to VCC/2
during holdover (see Table 42, Bit 6 in Register 0x01C).
The reference monitor verifies the presence/absence of the
prescaled REFA and REFB signals (that is, after division by the
input dividers). The status of the reference monitor guides the
activity of the switchover control logic. The AD9524 supports
automatic and manual PLL reference clock switching between
REFA (the REFA and REFA pins) and REFB (the REFB and
REFB pins). This feature supports networking and infrastructure
applications that require redundant references.
COMPONENT BLOCKS—OUTPUT PLL (PLL2)
PLL2 General Description
The output PLL (referred to as PLL2) consists of an optional input
reference doubler, phase-frequency detector (PFD), a partially
integrated analog loop filter (see Figure 25), an integrated
voltage-controlled oscillator (VCO), and a feedback divider.
The VCO produces a nominal 3.8 GHz signal with an output
divider that is capable of division ratios of 4 to 11.
There are several configurable modes of reference switchover.
The manual switchover is achieved either through a program-
ming register setting or by using the REF_SEL pin. The automatic
switchover occurs when REFA disappears and there is a reference
on REFB.
The PFD of the output PLL drives a charge pump that increases,
decreases, or holds constant the charge stored on the loop filter
capacitors (both internal and external). The stored charge results
in a voltage that sets the output frequency of the VCO. The
feedback loop of the PLL causes the VCO control voltage to
vary in a way that phase locks the PFD input signals.
The reference automatic switchover can be set to work as follows:
• Nonrevertive: stay on REFB. Switch from REFA to REFB
when REFA disappears, but do not switch back to REFA
if it reappears. If REFB disappears, then go back to REFA. The gain of PLL2 is proportional to the current delivered by the
charge pump. The loop filter bandwidth is chosen to reduce noise
contributions from PLL sources that could degrade phase noise
requirements.
• Revert to REFA. Switch from REFA to REFB when REFA
disappears. Return to REFA from REFB when REFA returns.
See Table 42 for the PLL1 miscellaneous control register bit
settings. The output PLL has a VCO with multiple bands spanning a
range of 3.6 GHz to 4.0 GHz. However, the actual operating
frequency within a particular band depends on the control
voltage that appears on the loop filter capacitor. The control
voltage causes the VCO output frequency to vary linearly within
the selected band. This frequency variability allows the control
loop of the output PLL to synchronize the VCO output signal
with the reference signal applied to the PFD. Typically, the
device automatically selects the appropriate band as part of its
calibration process (invoked via the VCO control register at
Address 0x0F3).
PLL1 Holdover
In the absence of both input references, the device enters holdover
mode. Holdover is a secondary function that is provided by PLL1.
Because PLL1 has an external VCXO available as a frequency
source, it continues to operate in the absence of the input reference
signals. When the device switches to holdover, the charge pump
tristates. The device continues operating in this mode until a
reference signal becomes available. Then the device exits holdover
N DIVIDER
TO DIST/
RESYNC
×2
PLL1_OUT
LDO LDO
PLL_1.8V
LDO_PLL2VDD3_PLL2
LDO_VCO
DIVIDE BY
1, 2, 4, 8, 16
DIVIDE BY
4, 5, 6, ...11
DIVIDE-BY-4
PRESCALER
A/B
COUNTERS
CHARGE PUMP
8 BITS, 3.5µA LSB
PFD
R
ZERO
R
POLE2
C
POLE1
C
POLE2
LF2_EXT_CAP
AD9524
09081-023
Figure 25. Output PLL (PLL2) Block Diagram
AD9524
Rev. C | Page 22 of 56
Input 2× Frequency Multiplier
The 2× frequency multiplier provides the option to double
the frequency at the PLL2 input. This allows the user to take
advantage of a higher frequency at the input to the PLL (PFD),
and, thus, allows for reduced in-band phase noise and greater
separation between the frequency generated by the PLL and the
modulation spur associated with PFD. However, increased
reference spur separation results in harmonic spurs introduced
by the frequency multiplier that increase as the duty cycle deviates
from 50% at the OSC_IN inputs. As such, beneficial use of the
frequency multiplier is application-specific. Typically, a VCXO
with proper interfacing has a duty cycle that is approximately
50% at the OSC_IN inputs. Note that the maximum output
frequency of the 2× frequency multipliers must not exceed the
maximum PFD rate that is specified in Table 11.
PLL2 Feedback Divider
PLL2 has a feedback divider (N divider) that enables it to provide
integer frequency up-conversion. The PLL2 N divider is a com-
bination of a prescaler (P) and two counters, A and B. The total
divider value is
N = (P × B) + A
where P = 4.
The feedback divider is a dual modulus prescaler architecture,
with a nonprogrammable P that is equal to 4. The value of the B
counter can be from 4 to 63, and the value of the A counter can
be from 0 to 3. However, due to the architecture of the divider,
there are constraints, as listed in Table 45.
PLL2 Loop Filter
The PLL2 loop filter requires the connection of an external
capacitor from LF2_EXT_CAP (Pin 9) to LDO_VCO (Pin 12),
as illustrated in Figure 25. The value of the external capacitor
depends on the operating mode and the desired phase noise
performance. For example, a loop bandwidth of approximately
500 kHz produces the lowest integrated jitter. A lower bandwidth
produces lower phase noise at 1 MHz but increases the total
integrated jitter.
Table 20. PLL2 Loop Filter Programmable Values
RZERO
(Ω)
CPOLE1
(pF)
RPOLE2
(Ω)
CPOLE2
(pF)
LF2_EXT_CAP1
(pF)
3250 48 900 Fixed at 16 Typical at 1000
3000 40 450
2750 32 300
2500 24 225
2250 16
2100 8
2000 0
1850
1 External loop filter capacitor.
VCO Divider
The VCO divider provides frequency division between the internal
VCO and the clock distribution. The VCO divider can be set to
divide by 4, 5, 6, 7, 8, 9, 10, or 11.
VCO Calibration
The AD9524 on-chip VCO must be manually calibrated to ensure
proper operation over process and temperature. This is accom-
plished by setting the calibrate VCO bit (Bit 1 in Register 0x0F3)
to 1. (This bit is not self-clearing.) The setting can be performed as
part of the initial setup before executing the IO_Update bit
(Register 0x234, Bit 0 = 1). A readback bit, VCO calibration in
progress (see Table 53, Bit 0 in Register 0x22D), indicates when
a VCO calibration is in progress by returning a logic true (that is,
Bit 0 = 1). If the EEPROM is in use, setting the calibrate VCO bit
(Bit 1 in Register 0x0F3) to 1 before saving the register settings
to the EEPROM ensures that the VCO calibrates automatically
after the EEPROM has loaded. After calibration, it is recommended
that a sync be initiated (for more information, see the Clock
Distribution Synchronization section).
Note that the calibrate VCO bit defaults to 0. This bit must
change from 0 to 1 to initiate a calibration sequence. Therefore,
any subsequent calibrations require the following sequence:
1. Register 0x0F3, Bit 1 (calibrate VCO bit) = 0
2. Register 0x234, Bit 0 (IO_Update bit) = 1
3. Register 0x0F3, Bit 1 (calibrate VCO bit) = 1
4. Register 0x234, Bit 0 (IO_Update bit) = 1
VCO calibration is controlled by a calibration controller that runs
off the VCXO input clock. The calibration requires that PLL2 be
set up properly to lock the PLL2 loop and that the VCXO clock
be present.
During power-up or reset, the distribution section is
automatically held in sync until the first VCO calibration is
finished. Therefore, no outputs can occur until VCO calibration is
complete and PLL2 is locked.
Initiate a VCO calibration under the following conditions:
• After changing any of the PLL2 B counter and A counter
settings, or after a change in the PLL2 reference clock
frequency. This means that a VCO calibration is initiated
any time that a PLL2 register or reference clock changes
such that a different VCO frequency is the result.
• Whenever system calibration is desired. The VCO is designed
to operate properly over extremes of temperature even when
it is first calibrated at the opposite extreme. However, a VCO
calibration can be initiated at any time, if desired.
AD9524
Rev. C | Page 23 of 56
CLOCK DISTRIBUTION
The clock distribution block provides an integrated solution for
generating multiple clock outputs based on frequency dividing
the PLL2 VCO divider output. The distribution output consists
of six channels (OUT0 to OUT5). Each of the output channels
has a dedicated divider and output driver, as shown in Figure 25.
The AD9524 also has the capability to route the VCXO output
to two of the outputs (OUT0 and OUT1).
Clock Dividers
The output clock distribution dividers are referred to as D0 to D5,
corresponding to output channels OUT0 through OUT5,
respectively. Each divider is programmable with 10 bits of division
depth that is equal to 1 to 1024. Dividers have duty cycle correction
to always give 50% duty cycle, even for odd divides.
Output Power-Down
Each of the output channels offers independent control of the
power-down functionality via the Channel 0 to Channel 5 control
registers (see Table 50). Each output channel has a dedicated
power-down bit for powering down the output driver. However,
if all six outputs are powered down, the entire distribution output
enters a deep sleep mode. Although each channel has a channel
power-down control signal, it may sometimes be desirable to
power down an output driver while maintaining the divider’s
synchronization with the other channel dividers. This is
accomplished by placing the output in tristate mode (this works
in CMOS mode, as well).
Multimode Output Drivers
The user has independent control of the operating mode of each of
the fourteen output channels via the Channel 0 to Channel 5
control registers (see Table 50). The operating mode control
includes the following:
• Logic family and pin functionality
• Output drive strength
• Output polarity
The four least significant bits (LSBs) of each of the six Channel 0 to
Channel 5 control registers comprise the driver mode bits. The
mode value selects the desired logic family and pin functionality
of an output channel, as listed in Table 50. This driver design
allows a common 100 Ω external resistor for all the different
driver modes of operation that are illustrated in Figure 26.
If the output channel is ac-coupled to the circuit to be clocked,
changing the mode varies the voltage swing to determine sensi-
tivity to the drive level. For example, in LVDS mode, a current of
3.5 mA causes a 350 mV peak voltage. Likewise, in LVPECL mode,
a current of 8 mA causes an 800 mV peak voltage at the 100 Ω load
resistor.
In addition to the four mode bits, each of the six Channel 0 to
Channel 5 control registers includes the following control bits:
• Invert divider output. Enables the user to choose between
normal polarity and inverted polarity. Normal polarity is the
default state. Inverted polarity reverses the representation of
Logic 0 and Logic 1, regardless of the logic family.
• Ignore sync. Makes the divider ignore the SYNC signal
from any source.
• Power down channel. Powers down the entire channel.
• Lower power mode.
• Driver mode.
• Channel divider.
• Divider phase.
3.5mA/8mA
LVDS/LVPECL
ENABLED
HSTL
ENABLED
HSTL
ENABLED
50Ω
50Ω
P
N
N
P
100Ω LOAD
CM
V
DD3_OUT[x:y]
1.25V LVDS
VDD – 1.3V LVPECL
CM
COMMON-MODE
CIRCUIT
+–
08439-031
Figure 26. Multimode Driver
AD9524
Rev. C | Page 24 of 56
Clock Distribution Synchronization As indicated, the primary synchronization signal originates
from one of the following sources:
A block diagram of the clock distribution synchronization
functionality is shown in Figure 27. The synchronization
sequence begins with the primary synchronization signal,
which ultimately results in delivery of a synchronization strobe
to the clock distribution logic.
• Direct synchronization source via the sync dividers bit (see
Register 0x232, Bit 0 in Table 54)
• Device pin, SYNC (Pin 13)
An automatic synchronization of the divider is initiated the first
time that PLL2 locks after a power-up or reset event. Subsequent
lock/unlock events do not initiate a resynchronization of the
distribution dividers unless they are preceded by a power-down
or reset of the part.
FAN OUT
VCO OUTPUT DIVIDER
S
YNC (PIN 13)
SYNC
DIVIDER
DRIVER
OUTx
OUTx
OUT
SYNC
PHASE
DIVIDE
SYNC DIVIDERS BIT
09081-025
Figure 27. Clock Output Synchronization Block Diagram
DIVIDE = 2, PHASE = 0
DIVIDE = 2, PHASE = 6
VCO DIVIDER OUTPUT CLOCK
SYNC
CONTROL
6 × 0.5 PERIODS
0
8439-026
Figure 28. Clock Output Synchronization Timing Diagram
AD9524
Rev. C | Page 25 of 56
Both sources of the primary synchronization signal are logic OR’d;
therefore, any one of them can synchronize the clock distribution
output at any time. When using the sync dividers bit, the user
first sets and then clears the bit.
The synchronization event is the clearing operation (that is, the
Logic 1 to Logic 0 transition of the bit). The dividers are all
automatically synchronized to each other when PLL2 is ready.
The dividers support programmable phase offsets from 0 to 63
steps, in half periods of the input clock (for example, the VCO
divider output clock). The phase offsets are incorporated in the
dividers through a preset for the first output clock period of each
divider. Phase offsets are supported only by programming the
initial phase and divide value and then issuing a sync to the
distribution (automatically at startup or manually, if desired).
In normal operation, the phase offsets are already programmed
through the EEPROM or the SPI/I2C port before the AD9524
starts to provide outputs. Although the user cannot adjust the
phase offsets while the dividers are operating, it is possible to
adjust the phase of all the outputs together without powering
down PLL1 and PLL2. This is accomplished by programming
the new phase offset, using Bits[7:2] in Register 0x198 (see
Table 50) and then issuing a divide sync signal by using the
SYNC pin or the sync dividers bit (Register 0x232, Bit 0).
All outputs that are not programmed to ignore the sync are
disabled temporarily while the sync is active. Note that, if an
output is used for the zero delay path, it also disappears
momentarily. However, this is desirable because it ensures that
all the synchronized outputs have a deterministic phase relation-
ship with respect to the zero delay output and, therefore, also
with respect to the input.
ZERO DELAY OPERATION
Zero delay operation aligns the phase of the output clocks with
the phase of the external PLL reference input. The OUT0 output
is designed to be used as the output for zero delay. There are
two zero delay modes on the AD9524: internal and external
(see Figure 29). Note that the external delay mode provides
better matching than the internal delay mode because the
output drivers are included in the zero delay path. Setting the
anitbacklash pulse width control of PLL1 to maximum gives the
best zero delay matching.
Internal Zero Delay Mode
The internal zero delay function of the AD9524 is achieved
by feeding the output of Channel Divider 0 back to the PLL1
N divider. Bit 5 in Register 0x01B is used to select internal zero
delay mode (see Table 41). In the internal zero delay mode, the
output of Channel Divider 0 is routed back to the PLL1 (N divider)
through a mux. PLL1 synchronizes the phase/edge of the output
of Channel Divider 0 with the phase/edge of the reference input.
Because the channel dividers are synchronized to each other,
the outputs of the channel divider are synchronous with the
reference input.
External Zero Delay Mode
The external zero delay function of the AD9524 is achieved by
feeding OUT0 back to the ZD_IN input and, ultimately, back to
the PLL1 N divider. In Figure 29, the change in signal routing
for external zero delay is external to the AD9524.
Bit 5 in Register 0x01B is used to select the external zero delay
mode. In external zero delay mode, OUT0 must be routed back
to PLL1 (the N divider) through the ZD_IN and ZD_IN pins.
PLL1 synchronizes the phase/edge of the feedback output clock
with the phase/edge of the reference input. Because the channel
dividers are synchronized to each other, the clock outputs are
synchronous with the reference input. Both the reference path
delay and the feedback delay from ZD_IN are designed to have
the same propagation delay from the output drivers and PLL
components to minimize the phase offset between the clock
output and the reference input to achieve zero delay.
INTERNAL FB
ZD_IN
REFA
REFA
AD9523
FEEDBACK
DELAY
REF
DELAY
ENB
PFD
OUT0OUT0ZD_IN
09081-027
Figure 29. Zero Delay Function
AD9524
Rev. C | Page 26 of 56
SERIAL CONTROL PORT
The AD9524 serial control port is a flexible, synchronous serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. The
AD9524 serial control port is compatible with most synchronous
transfer formats, including Philips IC®, Motorola® SPI, and
Intel® SSR protocols. The AD9524 IC implementation deviates
from the classic IC specification in two specifications, and
these deviations are documented in Table 15 of this data sheet.
The serial control port allows read/write access to all registers
that configure the AD9524.
SPI/I²C PORT SELECTION
The AD9524 has two serial interfaces, SPI and IC. Users can
select either the SPI or IC, depending on the states (logic high,
logic low) of the two logic level input pins, SP1 and SP0, when
power is applied or after a RESET (each pin has an internal 40 kΩ
pull-down resistor). When both SP1 and SP0 are low, the SPI
interface is active. Otherwise, I2C is active with three different
I2C slave address settings (seven bits wide), as shown in .
The five MSBs of the slave address are hardware coded as
11000, and the two LSBs are determined by the logic levels
of the SP1 and SP0 pins.
Table 21
Table 21. Serial Port Mode Selection
SP1 SP0 Address
Low Low SPI
Low High I2C: 1100000
High Low I2C: 1100001
High High I2C: 1100010
I²C SERIAL PORT OPERATION
The AD9524 IC port is based on the IC fast mode standard.
The AD9524 supports both IC protocols: standard mode
(100 kHz) and fast mode (400 kHz).
The AD9524 IC port has a 2-wire interface consisting of a serial
data line (SDA) and a serial clock line (SCL). In an IC bus system,
the AD9524 is connected to the serial bus (data bus SDA and clock
bus SCL) as a slave device, meaning that no clock is generated by
the AD9524. The AD9524 uses direct 16-bit (two bytes) memory
addressing instead of traditional 8-bit (one byte) memory
addressing.
I2C Bus Characteristics
Table 22. I2C Bus Definitions
Abbreviation Definition
S Start
Sr Repeated start
P Stop
A Acknowledge
A No acknowledge
W Write
R Read
One pulse on the SCL clock line is generated for each data bit
that is transferred.
The data on the SDA line must not change during the high period
of the clock. The state of the data line can change only when the
clock on the SCL line is low.
SDA
SCL
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
0
9081-160
Figure 30. Valid Bit Transfer
A start condition is a transition from high to low on the SDA
line while SCL is high. The start condition is always generated
by the master to initialize the data transfer.
A stop condition is a transition from low to high on the SDA
line while SCL is high. The stop condition is always generated
by the master to end the data transfer.
START
CONDITION
S
STOP
CONDITION
P
SD
A
SCL
09081-161
Figure 31. Start and Stop Conditions
A byte on the SDA line is always eight bits long. An acknowledge
bit must follow every byte. Bytes are sent MSB first.
AD9524
Rev. C | Page 27 of 56
S
D
A
MSB
ACKNOWLEDGE FROM
SLAVE-RECEIVER
ACKNOWLEDGE FROM
SLAVE-RECEIVER
SCL
SP
1 2 8 9 1 2 83 TO 73 TO 7 910
09081-162
Figure 32. Acknowledge Bit
S
D
A
MSB = 0
ACKNOWLEDGE FROM
SLAVE-RECEIVER
ACKNOWLEDGE FROM
SLAVE-RECEIVER
SCL
SP
1 2 8 9 1 2 83 TO 73 TO 7 910
09081-163
Figure 33. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration)
S
D
A
ACKNOWLEDGE FROM
MASTER-RECEIVER
NO ACKNOWLEDGE
FROM
SLAVE-RECEIVER
SCL
SP
1 2 8 9 1 2 83 TO 73 TO 7 910
MSB = 1
09081-164
Figure 34. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration)
The acknowledge bit is the ninth bit attached to any 8-bit data byte.
An acknowledge bit is always generated by the receiving device
(receiver) to inform the transmitter that the byte has been received.
It is accomplished by pulling the SDA line low during the ninth
clock pulse after each 8-bit data byte.
The no acknowledge bit is the ninth bit attached to any 8-bit data
byte. A no acknowledge bit is always generated by the receiving
device (receiver) to inform the transmitter that the byte has not
been received. It is accomplished by leaving the SDA line high
during the ninth clock pulse after each 8-bit data byte.
Data Transfer Process
The master initiates data transfer by asserting a start condition.
This indicates that a data stream follows. All IC slave devices
connected to the serial bus respond to the start condition.
The master then sends an 8-bit address byte over the SDA line,
consisting of a 7-bit slave address (MSB first), plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device
(0 = write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by sending an acknowledge bit. All other
devices on the bus remain idle while the selected device waits
for data to be read from or written to it. If the R/W bit is 0, the
master (transmitter) writes to the slave device (receiver). If the R/W
bit is 1, the master (receiver) reads from the slave device (trans-
mitter). The format for these commands is described in the
section. Data Transfer Format
Data is then sent over the serial bus in the format of nine clock
pulses: one data byte (eight bits) from either master (write mode)
or slave (read mode), followed by an acknowledge bit from the
receiving device. The number of bytes that can be transmitted per
transfer is unrestricted. In write mode, the first two data bytes
immediately after the slave address byte are the internal memory
(control registers) address bytes with the high address byte first.
This addressing scheme gives a memory address of up to 216 − 1 =
65,535. The data bytes after these two memory address bytes are
register data written into the control registers. In read mode, the
data bytes after the slave address byte are register data read from
the control registers. A single I2C transfer can contain multiple data
bytes that can be read from or written to control registers whose
address is automatically incremented starting from the base
memory address.
When all the data bytes are read or written, stop conditions are
established. In write mode, the master (transmitter) asserts a stop
condition to end data transfer during the 10th clock pulse following
the acknowledge bit for the last data byte from the slave device
(receiver). In read mode, the master device (receiver) receives the
last data byte from the slave device (transmitter) but does not pull
it low during the ninth clock pulse. This is known as a no acknowl-
edge bit. Upon receiving the no acknowledge bit, the slave device
knows that the data transfer is finished and releases the SDA line.
The master then takes the data line low during the low period
before the 10th clock pulse and high during the 10th clock pulse
to assert a stop condition.
A repeated start (Sr) condition can be used in place of a stop
condition. Furthermore, a start or stop condition can occur at
any time, and partially transferred bytes are discarded.
For an I2C data write transfer containing multiple data bytes,
the peripheral drives a no acknowledge for the data byte that
follows a write to Register 0x234, thereby ending the I2C transfer.
For an I2C data read transfer containing multiple data bytes,
the peripheral drives data bytes of 0x00 for subsequent reads that
follow a read from Register 0x234.
AD9524
Rev. C | Page 28 of 56
Data Transfer Format
Send byte format. The send byte protocol is used to set up the register address for subsequent commands.
S Slave Address W A RAM Address High Byte A RAM Address Low Byte A P
Write byte format. The write byte protocol is used to write a register address to the RAM, starting from the specified RAM address.
S Slave Address W A
RAM Address
High Byte A
RAM Address
Low Byte A
RAM
Data 0 A
RAM
Data 1 A
RAM
Data 2 A P
Receive byte format. The receive byte protocol is used to read the data byte(s) from the RAM, starting from the current address.
S Slave Address R A RAM Data 0 A RAM Data 1 A RAM Data 2 A P
Read byte format. The combined format of the send byte and the receive byte.
S
Slave
Address W A
RAM Address
High Byte A
RAM Address
Low Byte A Sr
Slave
Address R A
RAM
Data 0 A
RAM
Data 1 A
RAM
Data 2 A P
I²C Serial Port Timing
SDA
SCL
SSr P S
t
FALL
t
SET; DAT
t
LOW
t
RISE
t
HLD; STR
t
HLD; DAT
t
HIGH
t
FALL
t
SET; STR
t
HLD; STR
t
SPIKE
t
SET; STP
t
RISE
t
IDLE
09081-165
Figure 35. I²C Serial Port Timing
Table 23. IC Timing Definitions
Parameter Description
fI2C I²C clock frequency
tIDLE Bus idle time between stop and start conditions
tHLD; STR Hold time for repeated start condition
tSET; STR Setup time for repeated start condition
tSET; STP Setup time for stop condition
tHLD; DAT Hold time for data
tSET; DAT Setup time for data
tLOW Duration of SCL clock low
tHIGH Duration of SCL clock high
tRISE SCL/SDA rise time
tFALL SCL/SDA fall time
tSPIKE Voltage spike pulse width that must be suppressed by the input filter
AD9524
Rev. C | Page 29 of 56
SPI SERIAL PORT OPERATION
Pin Descriptions
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and writes.
Write data bits are registered on the rising edge of this clock,
and read data bits are registered on the falling edge. This pin
is internally pulled down by a 40 kΩ resistor to ground.
SDIO (serial data input/output) is a dual-purpose pin and acts
either as an input only (unidirectional mode) or as an input/
output (bidirectional mode). The AD9524 defaults to the
bidirectional I/O mode.
SDO (serial data out) is used only in the unidirectional I/O mode
as a separate output pin for reading back data. SDO is always
active; therefore, the unidirectional I/O mode should not be
used in a multislave environment.
CS (chip select bar) is an active low control that gates the read and
write cycles. When CS is high, SDIO is in a high impedance state.
This pin is internally pulled up by a 40 kΩ resistor to VDD3_REF.
AD9524
SERIAL
CONTROL
PORT
CS
SCLK/SCL
SDIO/SDA
SDO
09081-034
Figure 36. Serial Control Port
SPI Mode Operation
In SPI mode, single or multiple byte transfers are supported,
as well as MSB first or LSB first transfer formats. The AD9524
serial control port can be configured for a single bidirectional
I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/
SDO). By default, the AD9524 is in bidirectional mode. Short
instruction mode (8-bit instructions) is not supported. Only
long (16-bit) instruction mode is supported.
A write or a read operation to the AD9524 is initiated by pulling
CS low.
The CS stalled high mode is supported in data transfers where
three or fewer bytes of data (plus instruction data) are transferred
(see ). In this mode, the Table 24 CS pin can temporarily return
high on any byte boundary, allowing time for the system controller
to process the next byte. CS can go high only on byte boundaries;
however, it can go high during either phase (instruction or data)
of the transfer.
During this period, the serial control port state machine enters
a wait state until all data is sent. If the system controller decides
to abort the transfer before all of the data is sent, the state machine
must be reset either by completing the remaining transfers or by
returning CS low for at least one complete SCLK cycle (but
fewer than eight SCLK cycles). Raising the CS pin on a nonbyte
boundary terminates the serial transfer and flushes the buffer.
In streaming mode (see Table 24), any number of data bytes can
be transferred in a continuous stream. The register address is
automatically incremented or decremented (see the SPI MSB/LSB
First Transfers section). CS must be raised at the end of the last
byte to be transferred, thereby ending streaming mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the AD9524.
The first part writes a 16-bit instruction word into the AD9524,
coincident with the first 16 SCLK rising edges. The instruction
word provides the AD9524 serial control port with information
regarding the data transfer, which is the second part of the
communication cycle. The instruction word defines whether
the upcoming data transfer is a read or a write, the number of
bytes in the data transfer, and the starting register address for
the first byte of the data transfer.
Write
If the instruction word is for a write operation, the second part
is the transfer of data into the serial control port buffer of the
AD9524. Data bits are registered on the rising edge of SCLK.
The length of the transfer (one, two, or three bytes or streaming
mode) is indicated by two bits (W1, W0) in the instruction byte.
When the transfer is one, two, or three bytes, but not streaming, CS
can be raised after each sequence of eight bits to stall the bus
(except after the last byte, where it ends the cycle). When the bus
is stalled, the serial transfer resumes when CS is lowered. Raising
the CS pin on a nonbyte boundary resets the serial control port.
During a write, streaming mode does not skip over reserved or
blank registers, and the user can write 0x00 to the reserved
register addresses.
Because data is written into a serial control port buffer area, and
not directly into the actual control registers of the AD9524, an
additional operation is needed to transfer the serial control port
buffer contents to the actual control registers of the AD9524,
thereby causing them to become active. The update registers
operation consists of setting the self-clearing IO_Update bit,
Bit 0 of Register 0x234 (see Tabl e 56). Any number of data bytes
can be changed before executing an update registers operation.
The update registers simultaneously actuates all register changes
that have been written to the buffer since any previous update.
Read
The AD9524 supports only the long instruction mode. If the
instruction word is for a read operation, the next N × 8 SCLK
cycles clock out the data from the address specified in the
instruction word, where N is 1 to 3 as determined by Bits[W1:W0].
If N = 4, the read operation is in streaming mode, continuing
until CS is raised. Streaming mode does not skip over reserved
or blank registers. The readback data is valid on the falling
edge of SCLK.
AD9524
Rev. C | Page 30 of 56
SPI MSB/LSB FIRST TRANSFERS
The default mode of the AD9524 serial control port is the
bidirectional mode. In bidirectional mode, both the sent data
and the readback data appear on the SDIO pin. It is also possible to
set the AD9524 to unidirectional mode. In unidirectional mode,
the readback data appears on the SDO pin.
The AD9524 instruction word and byte data can be MSB first
or LSB first. Any data written to Register 0x000 must be mirrored:
Bit 7 is mirrored to Bit 0, Bit 6 to Bit 1, Bit 5 to Bit 2, and Bit 4 to
Bit 3. This makes it irrelevant whether LSB first or MSB first is
in effect. The default for the AD9524 is MSB first.
A readback request reads the data that is in the serial control port
buffer area or the data that is in the active registers (see Figure 37). When LSB first is set by Register 0x000, Bit 1 and Register 0x000,
Bit 6, it takes effect immediately because it affects only the
operation of the serial control port and does not require that
an update be executed.
SERIAL
CONTROL
PORT
BUFFER
REGISTERS
UPDATE
REGISTERS
ACTIVE
REGISTERS
SCLK/SCL
SDO
SDIO/SDA
CS
0
9081-035
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from the high address to the
low address. In MSB first mode, the serial control port internal
address generator decrements for each data byte of the multibyte
transfer cycle.
Figure 37. Relationship Between Serial Control Port Buffer Registers and
Active Registers
SPI INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/W, which indicates
whether the instruction is a read or a write. The next two bits
([W1:W0]) indicate the length of the transfer in bytes. The final
13 bits are the address ([A12:A0]) at which to begin the read or
write operation.
When LSB first mode is active, the instruction and data bytes
must be written from LSB to MSB. Multibyte data transfers in
LSB first format start with an instruction byte that includes the
register address of the least significant data byte, followed by
multiple data bytes. In a multibyte transfer cycle, the internal
byte address generator of the serial port increments for each byte.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits[W1:W0] (see Table 24).
Table 24. Byte Transfer Count
W1
The AD9524 serial control port register address decrements
from the register address just written toward 0x000 for multibyte
I/O operations if the MSB first mode is active (default). If the
LSB first mode is active, the register address of the serial control
port increments from the address just written toward 0x234 for
multibyte I/O operations. Unused addresses are not skipped for
these operations.
W0 Bytes to Transfer
0 0 1
0 1 2
1 0 3
1 1 Streaming mode
For multibyte accesses that cross Address 0x234 or Address 0x000
in MSB first mode, the SPI internally disables writes to subsequent
registers and returns zeros for reads to subsequent registers.
Bits[A12:A0] select the address within the register map that is
written to or read from during the data transfer portion of the
communications cycle. Only Bits[A11:A0] are needed to cover
the range of the 0x234 registers used by the AD9524. Bit A12
must always be 0. For multibyte transfers, this address is the
starting byte address. In MSB first mode, subsequent bytes
decrement the address.
Streaming mode always terminates when crossing address
boundaries (as shown in Table 25).
Table 25. Streaming Mode (No Addresses Are Skipped)
Write Mode Address Direction Stop Sequence
MSB First Decrement …, 0x001, 0x000, stop
Table 26. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB LSB
I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
R/W W1 W0 A12 = 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
AD9524
Rev. C | Page 31 of 56
CS
SCLK
DON'T CARE
SDIO A12W0W1R/W A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE
DON'T CARE
DON'T CARE
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA
09081-038
Figure 38. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data
CS
SCLK
SDIO
SDO
REGISTER (N) DATA16-BIT INSTRUCTION HEADER REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA
A12W0W1R/W A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
DON'T CARE
DON'T CARE
DON'T CARE
DON'T
CARE
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
09081-039
Figure 39. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data
t
S
DON'T CARE
DON'T CARE W1W0A12A11A10A9A8A7A6A5D4D3D2D1D0
DON'T CARE
DON'T CARE
R/W
t
DS
t
DH
t
HIGH
t
LOW
t
CLK
t
C
CS
SCLK
SDIO
09081-040
Figure 40. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
DATA BIT N – 1DATA BIT N
CS
SCLK
SDIO
SDO
tDV
09081-041
Figure 41. Timing Diagram for Serial Control Port Register Read
CS
SCLK
DON'T CARE
DON'T CARE
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA
SDIO DON'T CARE
DON'T CARE
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 D1D0R/WW1W0 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
09081-042
Figure 42. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data
AD9524
Rev. C | Page 32 of 56
CS
SCLK
SDIO
t
HIGH
t
LOW
t
CLK
t
S
t
DS
t
DH
t
C
BIT N BIT N + 1
0
9081-043
Figure 43. Serial Control Port Timing—Write
Table 27. Serial Control Port Timing
Parameter Description
tDS Setup time between data and rising edge of SCLK
tDH Hold time between data and rising edge of SCLK
tCLK Period of the clock
Setup time between the CS falling edge and SCLK rising edge (start of communication cycle)
tS
Setup time between the SCLK rising edge and CS rising edge (end of communication cycle)
tC
tHIGH Minimum period that SCLK should be in a logic high state
tLOW Minimum period that SCLK should be in a logic low state
tDV SCLK to valid SDIO and SDO (see Figure 41)
AD9524
Rev. C | Page 33 of 56
EEPROM OPERATIONS
The AD9524 contains an internal EEPROM (nonvolatile memory).
The EEPROM can be programmed by users to create and store
a user-defined register setting file when the power is off. This
setting file can be used for power-up and chip reset as a default
setting. The EEPROM size is 512 bytes. Descriptions of the
EEPROM registers that control EEPROM operation can be found
in Table 57 and Table 58.
During the data transfer process, the write and read registers are
generally not available via the serial port, except for one readback
bit: Status_EEPROM (Register 0xB00, Bit 0).
To determine the data transfer state through the serial port in
SPI mode, users can read the value of the Status_EEPROM bit
(1 = data transfer in process and 0 = data transfer complete).
In IC mode, the user can address the AD9524 slave port with
the external IC master (send an address byte to the AD9524). If
the AD9524 responds with a no acknowledge bit, the data transfer
was not received. If the AD9524 responds with an acknowledge bit,
the data transfer process is complete. The user can monitor the
Status_EEPROM bit or use Register 0x232, Bit 4 to program the
STATUS0 pin to monitor the status of the data transfer (see Table 54).
To transfer all 512 bytes to the EEPROM, it takes approximately
46 ms, and to transfer the contents of the EEPROM to the active
register, it takes approximately 40 ms.
RESET, a hard reset (an asynchronous hard reset is executed by
briefly pulling RESET low), restores the chip either to the setting
stored in EEPROM (the EEPROM pin = 1) or to the on-chip
setting (the EEPROM pin = 0). A hard reset also executes a SYNC
operation that brings the outputs into phase alignment according
to the default settings. When EEPROM is inactive (the EEPROM
pin = 0), it takes ~2 µs for the outputs to begin toggling after
RESET is issued. When EEPROM is active (the EEPROM pin = 1),
it takes ~40 ms for the outputs to toggle after RESET is brought high.
WRITING TO THE EEPROM
The EEPROM cannot be programmed directly through the serial
port interface. To program the EEPROM and store a register
setting file, follow these steps:
1. Program the AD9524 registers to the desired circuit state.
If the user wants the PLL2 to lock automatically after power-
up, the calibrate VCO bit (Bit 1, Register 0x0F3) must be set
to 1. This allows VCO calibration to start automatically
after register loading. Note that a valid input reference
signal must be present during VCO calibration.
2. Set the IO_Update bit (Bit 0, Register 0x234) to 1.
3. Program the EEPROM buffer registers, if necessary (see
the Programming the EEPROM Buffer Segment section).
This step is necessary only if users want to use the EEPROM
to control the default settings of some (but not all) of the
AD9523 registers, or if they want to control the register
setting update sequence during power-up or chip reset.
4. Set the enable EEPROM write bit (Bit 0, Register 0xB02)
to 1 to enable the EEPROM.
5. Set the REG2EEPROM bit (Bit 0, Register 0xB03) to 1. This
starts the process of writing data into the EEPROM to create
the EEPROM setting file. This enables the EEPROM
controller to transfer the current register values, as well as the
memory address and instruction bytes from the EEPROM
buffer segment, into the EEPROM. After the write process
is completed, the internal controller sets bit REG2EEPROM
back to 0.
Bit 0 of the Status_EEPROM register (Register 0xB00) is used
to indicate the data transfer status between the EEPROM and
the control registers (1 = data transfer in process, and 0 = data
transfer complete). At the beginning of the data transfer, the
Status_EEPROM bit is set to 1 by the EEPROM controller and
cleared to 0 at the end of the data transfer. The user can access
Status_EEPROM via the STATUS0 pin when the STATUS0
pin is programmed to monitor the Status_EEPROM bit.
Alternatively, the user can monitor the Status_EEPROM bit
directly.
6. When the data transfer is complete (Status_EEPROM = 0),
set the enable EEPROM write bit (Bit 0 in Register 0xB02)
to 1. Clearing the enable EEPROM write bit to 0 disables
writing to the EEPROM.
To ensure that the data transfer has completed correctly, verify
that the EEPROM data error bit (Bit 0 in Register 0xB01) = 0.
A value of 1 in this bit indicates a data transfer error.
READING FROM THE EEPROM
The following reset-related events can start the process of
restoring the settings stored in the EEPROM to the control
registers. When the EEPROM_SEL pin is set high, do any of
the following to initiate an EEPROM read:
• Power up the AD9524.
• Perform a hardware chip reset by pulling the RESET pin
low and then releasing RESET.
• Set the self-clearing soft reset bit (Bit 5, Register 0x000) to 1.
When the EEPROM_SEL pin is set low, set the self-clearing
Soft_EEPROM bit (Bit 1, Register 0xB02) to 1. The AD9524 then
starts to read the EEPROM and loads the values into the AD9524
registers. If the EEPROM_SEL pin is low during reset or power-up,
the EEPROM is not active, and the AD9524 default values are
loaded instead.
When using the EEPROM to automatically load the AD9524
register values and lock the PLL, the calibrate VCO bit (Bit 1,
Register 0x0F3) must be set to 1 when the register values are
written to the EEPROM. This allows VCO calibration to start
automatically after register loading. A valid input reference
signal must be present during VCO calibration.
AD9524
Rev. C | Page 34 of 56
To ensure that the data transfer has completed correctly, verify
that the EEPROM data error bit (Bit 0 in Register 0xB01) is set
to 0. A value of 1 in this bit indicates a data transfer error.
PROGRAMMING THE EEPROM BUFFER SEGMENT
The EEPROM buffer segment is a register space that allows the
user to specify which groups of registers are stored to the EEPROM
during EEPROM programming. Normally, this segment does not
need to be programmed by the user. Instead, the default power-up
values for the EEPROM buffer segment allow the user to store
all of the register values from Register 0x000 to Register 0x234
to the EEPROM.
For example, if the user wants to load only the output driver
settings from the EEPROM without disturbing the PLL register
settings currently stored in the EEPROM, the EEPROM buffer
segment can be modified to include only the registers that apply
to the output drivers and exclude the registers that apply to the
PLL configuration.
There are two parts to the EEPROM buffer segment: register
section definition groups and operational codes. Each register
section definition group contains the starting address and
number of bytes to be written to the EEPROM.
If the AD9524 register map were continuous from Address 0x000
to Address 0x234, only one register section definition group
would consist of a starting address of 0x000 and a length of
563 bytes. However, this is not the case. The AD9524 register
map is noncontiguous, and the EEPROM is only 512 bytes long.
Therefore, the register section definition group tells the EEPROM
controller how the AD9524 register map is segmented.
There are three operational codes: IO_Update, end-of-data, and
pseudo-end-of-data. It is important that the EEPROM buffer
segment always have either an end-of-data or a pseudo-end-of-data
operational code and that an IO_Update operation code appear at
least once before the end-of-data operational code.
Register Section Definition Group
The register section definition group is used to define a continuous
register section for the EEPROM profile. It consists of three bytes.
The first byte defines how many continuous register bytes are in
this group. If the user puts 0x000 in the first byte, it means there
is only one byte in this group. If the user puts 0x001, it means
there are two bytes in this group. The maximum number of
registers in one group is 128.
The next two bytes are the low byte and high byte of the
memory address (16 bits) of the first register in this group.
IO_Update (Operational Code 0x80)
The EEPROM controller uses this operational code to generate
an IO_Update signal to update the active control register bank
from the buffer register bank during the download process.
At a minimum, there should be at least one IO_Update operational
code after the end of the final register section definition group. This
is needed so that at least one IO_Update occurs after all of the
AD9524 registers are loaded when the EEPROM is read. If this
operational code is absent during a write to the EEPROM, the
register values loaded from the EEPROM are not transferred to
the active register space, and these values do not take effect after
they are loaded from the EEPROM to the AD9524.
End-of-Data (Operational Code 0xFF)
The EEPROM controller uses this operational code to terminate
the data transfer process between EEPROM and the control
register during the upload and download process. The last item
appearing in the EEPROM buffer segment should be either this
operational code or the pseudo-end-of-data operational code.
Pseudo-End-of-Data (Operational Code 0xFE)
The AD9524 EEPROM buffer segment has 23 bytes that can
contain up to seven register section definition groups. If users
want to define more than seven register section definition groups,
the pseudo-end-of-data operational code can be used. During
the upload process, when the EEPROM controller receives the
pseudo-end-of-data operational code, it halts the data transfer
process, clears the REG2EEPROM bit (Bit 0, Register 0xB03),
and enables the AD9524 serial port. Users can then program the
EEPROM buffer segment again and reinitiate the data transfer
process by setting the REG2EEPROM bit to 1 and the IO_Update
bit (Bit 0, Register 0x234) to 1. The internal IC master then begins
writing to the EEPROM, starting from the EEPROM address
held from the last writing.
This sequence enables more discrete instructions to be written
to the EEPROM than would otherwise be possible due to the
limited size of the EEPROM buffer segment. It also permits the
user to write to the same register multiple times with a different
value each time.
AD9524
Rev. C | Page 35 of 56
Table 28. Example of an EEPROM Buffer Segment
Register Address (Hex) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Start EEPROM Buffer Segment
0xA00 0 Number of bytes of the first group of registers (Bits[6:0])
0xA01 Address of the first group of registers (Bits[15:8])
0xA02 Address of the first group of registers (Bits[7:0])
0xA03 0 Number of bytes of the second group of registers (Bits[6:0])
0xA04 Address of the second group of registers (Bits[15:8])
0xA05 Address of the second group of registers (Bits[7:0])
0xA06 0 Number of bytes of the third group of registers (Bits[6:0])
0xA07 Address of the third group of registers (Bits[15:8])
0xA08 Address of the third group of registers (Bits[7:0])
0xA09 IO_Update operational code (0x80)
0xA0A End-of-data operational code (0xFF)
AD9524
Rev. C | Page 36 of 56
POWER DISSIPATION AND THERMAL CONSIDERATIONS
The AD9524 is a multifunctional, high speed device that targets
a wide variety of clock applications. The numerous innovative
features contained in the device each consume incremental power.
If all outputs are enabled in the maximum frequency and mode
that have the highest power, the safe thermal operating conditions
of the device may be exceeded. Careful analysis and consideration
of power dissipation and thermal management are critical
elements in the successful application of the AD9524 device.
The AD9524 device is specified to operate within the industrial
ambient temperature range of –40°C to +85°C. This
specification is conditional, however, such that the absolute
maximum junction temperature is not exceeded (as specified in
Table 16). At high operating temperatures, extreme care must be
taken when operating the device to avoid exceeding the junction
temperature and potentially damaging the device.
Many variables contribute to the operating junction temperature
within the device, including
• Selected driver mode of operation
• Output clock speed
• Supply voltage
• Ambient temperature
The combination of these variables determines the junction
temperature within the AD9524 device for a given set of
operating conditions.
The AD9524 is specified for an ambient temperature (TA).
Use the following equation to determine the junction
temperature on the application PCB:
TJ = TCASE + (ΨJT × PD)
where:
TJ is the junction temperature (°C).
TCASE is the case temperature (°C) measured by the user at the
top center of the package.
ΨJT is the junction-to-package top value from Table 17.
PD is the power dissipation of the AD9524.
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order
approximation of TJ by the equation
TJ = TA + (θJA × PD)
where TA is the ambient temperature (°C).
Values of θJC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Values of ΨJB are provided for package comparison and PCB
design considerations.
CLOCK SPEED AND DRIVER MODE
Clock speed directly and linearly influences the total power
dissipation of the device and, therefore, the junction temperature.
Two operating frequencies are listed under the incremental power
dissipation parameter in Table 3. Using linear interpretation is
a sufficient approximation for frequency not listed in the table.
When calculating power dissipation for thermal consideration,
the amount of power dissipated in the 100 Ω resistor should be
removed. If using the data in Table 2, this power is already
removed. If using the current vs. frequency graphs provided in
the Typical Performance Characteristics section, the power into
the load must be subtracted, using the following equation:
Ω100
2
SwingVoltageOutputalDifferenti
EVALUATION OF OPERATING CONDITIONS
The first step in evaluating the operating conditions is to
determine the maximum power consumption (PD) internal
to the AD9524. The maximum PD excludes power dissipated
in the load resistors of the drivers because such power is external
to the device. Use the power dissipation specifications listed in
Table 3 to calculate the total power dissipated for the desired
configuration. The base typical configuration parameter in
Table 3 lists a power of 428 mW, which includes one LVPECL
output at 122.88 MHz. If the frequency of operation is not listed
in Table 3, see the Typical Performance Characteristics section,
current vs. frequency and driver mode, to calculate the power
dissipation; then add 20% for maximum current draw. Remove
the power dissipated in the load resistor to achieve the most
accurate power dissipation internal to the AD9524. See Table 29
for a summary of the incremental power dissipation from the base
power configuration for two different examples.
Table 29. Temperature Gradient Examples
Description Mode
Frequency
(MHz)
Maximum
Power (mW)
Example 1
Base Typical
Configuration
428
Output Driver 5 × LVPECL 122.88 275
Total Power 703
Example 2
Base Typical
Configuration
428
Output Driver 5 × LVPECL 983.04 795
Total Power 1223
THERMALLY ENHANCED PACKAGE MOUNTING
GUIDELINES
Refer to the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), for more information about mounting devices with
an exposed paddle.
AD9524
Rev. C | Page 37 of 56
CONTROL REGISTERS
CONTROL REGISTER MAP
Register addresses that are not listed in Table 30 are not used, and writing to those registers has no effect. Registers that are marked as
reserved should never have their values changed. When writing to registers with bits that are marked reserved, the user should take care
to always write the default value for the reserved bits.
Table 30. Control Register Map
Addr
(Hex)
Register
Name
(MSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
Serial Port Configuration
SPI mode
serial port
configuration
SDO
active
LSB first/
address
increment
Soft reset Reserved Reserved Soft reset LSB first/
address
increment
SDO active 0x00 0x000
I2C mode
serial port
configuration
Reserved Reserved Soft reset Reserved Reserved Soft reset Reserved Reserved 0x00
0x004 Readback
control
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Read back
active registers
0x00
0x005 EEPROM customer version ID[7:0] (LSB) 0x00
0x006
EEPROM
customer
version ID EEPROM customer version ID[15:8] (MSB) 0x00
Input PLL (PLL1)
0x010 10-bit REFA R divider[7:0] (LSB) 0x00
0x011
PLL1 REFA
R divider
control Reserved 10-bit REFA R divider[9:8]
(MSB)
0x00
0x012 10-bit REFB R divider[7:0] (LSB) 0x00
0x013
PLL1 REFB
R divider
control Reserved 10-bit REFB R divider[9:8]
(MSB)
0x00
0x014 PLL1 reference
test divider
Reserved Reserved REF_TEST divider 0x00
0x015 PLL1 reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x00
0x016 10-bit PLL1 feedback divider[7:0] (LSB) 0x00
0x017
PLL1 feedback
N divider
control Reserved 10-bit PLL1 feedback
divider[9:8] (MSB)
0x00
0x018 PLL1 charge
pump control
PLL1
charge
pump
tristate
PLL1 charge pump control 0x0C
0x019 Reserved Reserved Reserved Enable SPI
control of
antibacklash
pulse width
Antibacklash pulse
width control
PLL1 charge pump mode 0x00
0x01A PLL1
input receiver
control
REF_TEST
input
receiver
enable
REFB
differential
receiver
enable
REFA
differential
receiver
enable
REFB receiver
enable
REFA
receiver
enable
Input
REFA, REFB
receiver
power-
down
control
enable
OSC_IN
single-ended
receiver
mode enable
(CMOS mode)
OSC_IN
differential
receiver
mode enable
0x00
0x01B REF_TEST,
REFA, REFB,
and ZD_IN
control
Bypass
REF_TEST
divider
Bypass
feedback
divider
Zero delay
mode
OSC_IN signal
feedback
for PLL1
ZD_IN
single-
ended
receiver
mode
enable
(CMOS
mode)
ZD_IN
differen.
receiver
mode
enable
REFB
single-ended
receiver mode
enable
(CMOS mode)
REFA
single-ended
receiver
mode enable
(CMOS mode)
0x00
0x01C PLL1
miscellaneous
control
Enable
REFB
R divider
indepen.
division
control
OSC_CTRL
control
voltage to
VCC/2
when ref
clock fails
Reserved Reference selection mode Bypass REFB
R divider
Bypass REFA
R divider
0x00
AD9524
Rev. C | Page 38 of 56
Addr
(Hex)
Register
Name
(MSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
0x01D PLL1 loop
filter zero
resistor control
Reserved Reserved Reserved Reserved PLL1 loop filter, RZERO 0x00
Output PLL (PLL2)
0x0F0 PLL2 charge
pump control
PLL2 charge pump control 0x00
0x0F1 PLL2
feedback
N divider
control
A counter B counter 0x04
0x0F2 PLL2 control PLL2 lock
detector
power-
down
Reserved Enable
frequency
doubler
Enable SPI
control of
antibacklash
pulse width
Antibacklash pulse
width control
PLL2 charge pump mode 0x03
0x0F3 VCO control Reserved Reserved Reserved Force release
of distribution
sync when
PLL2 is
unlocked
Treat
reference
as valid
Force
VCO to
midpoint
frequency
Calibrate VCO
(not auto-
clearing)
Reserved 0x00
0x0F4 VCO divider
control
Reserved Reserved Reserved Reserved VCO
divider
power-
down
VCO divider 0x00
0x0F5 Pole 2 resistor (RPOLE2) Zero resistor (RZERO) Pole 1 capacitor (CPOLE1) 0x00
0x0F6
PLL2 loop
filter control
(9 bits) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bypass internal
RZERO resistor
0x00
0x0F9 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x00
Clock Distribution
0x196 Invert
divider
output
Ignore
sync
Power
down
channel
Lower power
mode
Driver mode 0x00
0x197 10-bit channel divider[7:0] (LSB) 0x1F
0x198
Channel 0
control
Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x00
0x199 Invert
divider
output
Ignore
sync
Power
down
channel
Lower power
mode
Driver mode 0x20
0x19A 10-bit channel divider[7:0] (LSB) 0x1F
0x19B
Channel 1
control
Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x00
0x19C Invert
divider
output
Ignore
sync
Power
down
channel
Lower power
mode
Driver mode 0x00
0x19D 10-bit channel divider[7:0] (LSB) 0x1F
0x19E
Channel 2
control
Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x00
0x19F Invert
divider
output
Ignore
sync
Power
down
channel
Lower power
mode
Driver mode[3:0] 0x20
0x1A0 10-bit channel divider[7:0] (LSB) 0x1F
0x1A1
Channel 3
control
Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x00
0x1AE Invert
divider
output
Ignore
sync
Power
down
channel
Lower power
mode
Driver mode 0x00
0x1AF 10-bit channel divider[7:0] (LSB) 0x1F
0x1B0
Channel 4
control
Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x00
0x1B1 Invert
divider
output
Ignore
sync
Power
down
channel
Lower power
mode
Driver mode 0x20
0x1B2 10-bit channel divider[7:0] (LSB) 0x1F
0x1B3
Channel 5
control
Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x00
AD9524
Rev. C | Page 39 of 56
Addr
(Hex)
Register
Name
(MSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
0x1BA PLL1 output
control
Reserved Reserved Reserved PLL1 output
CMOS driver
strength
PLL1 output divider 0x00
0x1BB PLL1 output
channel
control
PLL1
output
driver
power-
down
Reserved Reserved Reserved Reserved Reserved Route VCXO
clock to Ch 1
divider input
Route VCXO
clock to Ch 0
divider input
0x80
Readback
0x22C Readback 0 Status
PLL2
reference
clock
Status
PLL2
feedback
clock
Status
VCXO
Status
REF_TEST
Status
REFB
Status
REFA
Lock detect
PLL2
Lock detect
PLL1
0x22D Readback 1 Reserved Reserved Reserved Reserved Holdover
active
Selected
reference
(in auto
mode)
Reserved VCO
calibration
in progress
Other
0x230 Reserved Reserved Status Monitor 0 control 0x00
0x231 Reserved Reserved Status Monitor 1 control 0x00
0x232
Status signals
Reserved Reserved Reserved Enable Status_
EEPROM on
STATUS0 pin
STATUS1
pin
divider
enable
STATUS0
pin
divider
enable
Reserved Sync dividers
(manual
control)
0: sync signal
inactive
1: dividers
held in sync
(same as
SYNC pin low)
0x00
0x233 Power-down
control
Reserved Reserved Reserved Reserved Reserved PLL1
power-
down
PLL2
power-down
Distribution
power-down
0x07
0x234 Update all
registers
Reserved IO_Update 0x00
EEPROM Buffer
0xA00 Instruction (data)[7:0] (serial port configuration register) 0x00
0xA01 High byte of register address (serial port configuration register) 0x00
0xA02
EEPROM
Buffer Segment
Register 1 to
EEPROM
Buffer Segment
Register 3 Low byte of register address (serial port configuration register) 0x00
0xA03 Instruction (data)[7:0] (reaback control register) 0x02
0xA04 High byte of register address (reaback control register) 0x00
0xA05
EEPROM
Buffer Segment
Register 4 to
EEPROM
Buffer Segment
Register 6 Low byte of register address (reaback control register) 0x04
0xA06 Instruction (data)[7:0] (PLL segment) 0x0E
0xA07 High byte of register address (PLL segment) 0x00
0xA08
EEPROM
Buffer Segment
Register 7 to
EEPROM
Buffer Segment
Register 9 Low byte of register address (PLL segment) 0x10
0xA09 Instruction (data)[7:0] (PECL/CMOS output segment) 0x0E
0xA0A High byte of register address (PECL/CMOS output segment) 0x00
0xA0B
EEPROM
Buffer Segment
Register 10 to
EEPROM
Buffer Segment
Register 12 Low byte of register address (PECL/CMOS output segment) 0xF0
0xA0C Instruction (data)[7:0] (divider segment) 0x2B
0xA0D High byte of register address (divider segment) 0x01
0xA0E
EEPROM
Buffer Segment
Register 13 to
EEPROM
Buffer Segment
Register 15 Low byte of register address (divider segment) 0x90
AD9524
Rev. C | Page 40 of 56
Addr
(Hex)
Register
Name
(MSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
0xA0F Instruction (data)[7:0] (clock input and REF segment) 0x01
0xA10 High byte of register address (clock input and REF segment) 0x01
0xA11
EEPROM
Buffer Segment
Register 16 to
EEPROM
Buffer Segment
Register 18 Low byte of register address (clock input and REF segment) 0xE0
0xA12 Instruction (data)[7:0] (other segment) 0x03
0xA13 High byte of register address (other segment) 0x02
0xA14
EEPROM
Buffer Segment
Register 19 to
EEPROM
Buffer Segment
Register 21 Low byte of register address (other segment) 0x30
0xA15 EEPROM
Buffer Segment
Register 22
I/O update 0x80
0xA16 EEPROM
Buffer Segment
Register 23
End-of-data 0xFF
EEPROM Control
0xB00 Status_
EEPROM
(read only)
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Status_
EEPROM
(read only)
0x00
0xB01 EEPROM error
checking
readback
(read only)
Reserved Reserved Reserved Reserved Reserved Reserved Reserved EEPROM
data error
(read only)
0x00
0xB02 EEPROM
Control 1
Reserved Reserved Reserved Reserved Reserved Reserved Soft_EEPROM Enable
EEPROM write
0x00
0xB03 EEPROM
Control 2
Reserved Reserved Reserved Reserved Reserved Reserved Reserved REG2EEPROM 0x00
AD9524
Rev. C | Page 41 of 56
CONTROL REGISTER MAP BIT DESCRIPTIONS
Serial Port Configuration (Address 0x000 to Address 0x006)
Table 31. SPI Mode Serial Port Configuration
Address Bits Bit Name Description
7 SDO active Selects unidirectional or bidirectional data transfer mode. This bit is ignored in I2C mode.
0: SDIO pin used for write and read; SDO is high impedance (default).
1: SDO used for read; SDIO used for write; unidirectional mode.
6 LSB first/
address
increment
SPI MSB or LSB data orientation. This bit is ignored in I2C mode.
0: data-oriented MSB first; addressing decrements (default).
1: data-oriented LSB first; addressing increments.
5 Soft reset Soft reset.
1 (self clearing): soft reset; restores default values to internal registers.
4 Reserved Reserved.
0x000
[3:0] Mirror[7:4] Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part is in MSB first or LSB
first mode (see Register 0x000, Bit 6). Set bits as follows:
Bit 0 = Bit 7.
Bit 1 = Bit 6.
Bit 2 = Bit 5.
Bit 3 = Bit 4.
0x004 0 Read back
active registers
For buffered registers, serial port readback reads from actual (active) registers instead of from the buffer.
0 (default): reads values currently applied to the internal logic of the device.
1: reads buffered values that take effect on the next assertion of the I/O update.
Table 32. I2C Mode Serial Port Configuration
Address Bits Bit Name Description
[7:6] Reserved Reserved.
5 Soft reset Soft reset.
1 (self clearing): soft reset; restores default values to internal registers.
4 Reserved Reserved.
0x000
[3:0] Mirror[7:4] Bits[3:0] should always mirror Bits[7:4]. Set bits as follows:
Bit 0 = Bit 7.
Bit 1 = Bit 6.
Bit 2 = Bit 5.
Bit 3 = Bit 4.
0x004 0 Read back
active registers
For buffered registers, serial port readback reads from actual (active) registers instead of from the buffer.
0 (default): reads values currently applied to the internal logic of the device.
1: reads buffered values that take effect on the next assertion of the I/O update.
Table 33. EEPROM Customer Version ID
Address Bits Bit Name Description
0x005 [7:0]
EEPROM
customer
version ID (LSB)
16-bit EEPROM ID, Bits[7:0]. This register, along with Register 0x006, allows the user to store a unique
ID to identify which version of the AD9524 register settings is stored in the EEPROM. It does not affect
AD9524 operation in any way (default: 0x00).
0x006 [7:0]
EEPROM
customer
version ID (MSB)
16-bit EEPROM ID, Bits[15:8]. This register, along with Register 0x005, allows the user to store a unique
ID to identify which version of the AD9524 register settings is stored in the EEPROM. It does not affect
AD9524 operation in any way (default: 0x00).
AD9524
Rev. C | Page 42 of 56
Input PLL (PLL1) (Address 0x010 to Address 0x01D)
Table 34. PLL1 REFA R Divider Control
Address Bits Bit Name Description
0x010 [7:0] REFA R divider 10-bit REFA R divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.
00000000, 00000001: divide-by-1.
0x011 [1:0] 10-bit REFA R divider, Bits[9:8] (MSB)
Table 35. PLL1 REFB R Divider Control1
Address Bits Bit Name Description
0x012 [7:0] REFB R divider 10-bit REFB R divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.
00000000, 00000001: divide-by-1.
0x013 [1:0] 10-bit REFB R divider, Bits[9:8] (MSB)
1 Requires Register 0x01C, Bit 7 = 1 for division that is independent of REFA division.
Table 36. PLL1 Reference Test Divider
Address Bits Bit Name Description
[7:6] Reserved Reserved 0x014
[5:0] REF_TEST divider 6-bit reference test divider. Divide-by-1 to divide-by-63.
000000, 000001: divide-by-1.
Table 37. PLL1 Reserved
Address Bits Bit Name Description
0x015 [7:0] Reserved Reserved
Table 38. PLL1 Feedback N Divider Control
Address Bits Bit Name Description
0x016 [7:0] 10-bit feedback divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.
00000000, 00000001: divide-by-1.
0x017 [1:0]
PLL1 feedback N divider control
(N_PLL1)
10-bit feedback divider, Bits[1:0] (MSB)
Table 39. PLL1 Charge Pump Control
Address Bits Bit Name Description
7 PLL1 charge pump tristate Tristates the PLL1 charge pump. 0x018
[6:0] PLL1 charge pump control These bits set the magnitude of the PLL1 charge pump current. Granularity is ~0.5 A
with a full-scale magnitude of ~63.5 A.
[7:5] Reserved Reserved.
4 Enable SPI control of antibacklash
pulse width
Controls the functionality of Register 0x019, Bits[3:2].
0 (default): the device automatically controls the antibacklash period.
1: antibacklash period defined by Register 0x019, Bits[3:2].
[3:2] Antibacklash pulse width control Controls the PFD antibacklash period.
00 (default): minimum.
01: low.
10: high.
11: maximum.
These bits are ineffective unless Register 0x019, Bit 4 = 1.
0x019
[1:0] PLL1 charge pump mode Controls the mode of the PLL1 charge pump.
00: tristate.
01: pump up.
10: pump down.
11 (default): normal.
AD9524
Rev. C | Page 43 of 56
Table 40. PLL1 Input Receiver Control
Address Bits Bit Name Description
7 REF_TEST input receiver enable 1: enabled.
0: disabled (default).
6 REFB differential receiver enable 1: differential receiver mode.
0: single-ended receiver mode (also depends on Register 0x01B, Bit 1) (default).
5 REFA differential receiver enable 1: differential receiver mode.
0: single-ended receiver mode (also depends on Register 0x01B, Bit 0) (default).
4 REFB receiver enable REFB receiver power-down control mode only when Bit 2 = 1.
1: enable REFB receiver.
0: power-down (default).
3 REFA receiver enable REFA receiver power-down control mode only when Bit 2 = 1.
1: enable REFA receiver.
0: power-down (default).
2 Input REFA and REFB receiver
power-down control enable
Enables control over power-down of the input receivers, REFA and REFB.
1: power-down control enabled.
0: both receivers enabled (default).
1 OSC_IN single-ended receiver
mode enable (CMOS mode)
Selects which single-ended input pin is enabled when in the single-ended receiver
mode (Register 0x01A, Bit 0 = 0).
1: negative receiver from oscillator input (OSC_IN pin) selected.
0: positive receiver from oscillator input (OSC_IN pin) selected (default).
0x01A
0 OSC_IN differential receiver mode
enable
1: differential receiver mode.
0: single-ended receiver mode (also depends on Bit 1) (default).
Table 41. REF_TEST, REFA, REFB, and ZD_IN Control
Address Bits Bit Name Description
7 Bypass REF_TEST divider Puts the divider into bypass mode (same as programming the divider word to 0 or 1).
1: divider in bypass mode (divide = 1).
0: divider normal operation.
6 Bypass feedback divider Puts the divider into bypass mode (same as programming the divider word to 0 or 1).
1: divider in bypass mode (divide = 1).
0: divider normal operation.
5 Zero delay mode Selects the zero delay mode used (via the ZD_IN pin) when Register 0x01B, Bit 4 = 0.
Otherwise, this bit is ignored.
1: internal zero delay mode. The zero delay receiver is powered down. The internal
zero delay path from Distribution Divider Channel 0 is used.
0: external zero delay mode. The ZD_IN receiver is enabled.
4 OSC_IN signal feedback for PLL1 Controls the input PLL feedback path, local feedback from the OSC_IN receiver or
zero delay mode.
1: OSC_IN receiver input used for the input PLL feedback (non-zero delay mode).
0: zero delay mode enabled (also depends on Register 0x01B, Bit 4 to select the
zero delay path.
3 ZD_IN single-ended receiver
mode enable (CMOS mode)
Selects which single-ended input pin is enabled when in the single-ended receiver
mode (Register 0x01B, Bit 2 = 0).
1: ZD_IN pin enabled.
0: ZD_IN pin enabled.
2 ZD_IN differential receiver mode
enable
1: differential receiver mode.
0: single-ended receiver mode (also depends on Register 0x01B, Bit 3).
1 REFB single-ended receiver mode
enable (CMOS mode)
Selects which single-ended input pin is enabled when in single-ended receiver mode
(Register 0x01A, Bit 6 = 0).
1: REFB pin enabled.
0: REFB pin enabled.
0x01B
0 REFA single-ended receiver mode
enable (CMOS mode)
Selects which single-ended input pin is enabled when in single-ended receiver mode
(Register 0x01A, Bit 5 = 0).
1: REFA pin enabled.
0: REFA pin enabled.
AD9524
Rev. C | Page 44 of 56
Table 42. PLL1 Miscellaneous Control
Address Bits Bit Name Description
7 Enable REFB R divider
independent division control
1: REFB R divider is controlled by Register 0x012 and Register 0x013.
0: REFB R divider is set to the same setting as the REFA R divider (Register 0x010
and Register 0x011). This requires that, for the loop to stay locked, the REFA and
REFB input frequencies must be the same.
6 OSC_CTRL control voltage to
VCC/2 when reference clock fails
High permits the OSC_CTRL control voltage to be forced to midsupply when the
feedback or input clocks fail. Low tristates the charge pump output.
1: OSC_CTRL control voltage goes to VCC/2.
0: OSC_CTRL control voltage tracks the tristated (high impedance) charge pump
(through the buffer).
5 Reserved Reserved.
Programs the REFA, REFB mode selection (default = 000).
REF_SEL
Pin Bit 4 Bit 3 Bit 2 Description
X1 0 0 0 Nonrevertive: stay on REFB.
X1 0 0 1 Revert to REFA.
X1 0 1 0 Select REFA.
X1 0 1 1 Select REFB.
0 1 X1 XX
1 REF_SEL pin = 0 (low): REFA.
[4:2] Reference selection mode
1 1 X1 XX
1 REF_SEL pin = 1 (high): REFB.
1 Bypass REFB R divider Puts the divider into bypass mode (same as programming divider word to 0 or 1).
1: divider in bypass mode (divide = 1).
0: divider normal operation.
0x01C
0 Bypass REFA R divider Puts the divider into bypass mode (same as programming divider word to 0 or 1).
1: divider in bypass mode (divide = 1).
0: divider normal operation.
1 X = don’t care.
Table 43. PLL1 Loop Filter Zero Resistor Control
Address Bits Bit Name Description
[7:4] Reserved Reserved.
[3:0] PLL1 loop filter, RZERO Programs the value of the zero resistor, RZERO.
Bit 3 Bit 2 Bit 1 Bit 0 RZERO Value (kΩ)
0 0 0 0 883
0 0 0 1 677
0 0 1 0 341
0 0 1 1 135
0 1 0 0 10
0 1 0 1 10
0 1 1 0 10
0 1 1 1 10
0x01D
1 0 0 0 Use external resistor
AD9524
Rev. C | Page 45 of 56
Output PLL (PLL2) (Address 0x0F0 to Address 0x0F9)
Table 44. PLL2 Charge Pump Control
Address Bits Bit Name Description
0x0F0 [7:0] PLL2 charge pump control These bits set the magnitude of the PLL2 charge pump current. Granularity is ~3.5 A
with a full-scale magnitude of ~900 A.
Table 45. PLL2 Feedback N Divider Control
Address Bits Bit Name Description
[7:6] A counter A counter word
[5:0] B counter B counter word
Feedback Divider Constraints
A Counter (Bits[7:6])
Table 46. PLL2 Control
Address Bits Bit Name Description
7 PLL2 lock detector power-down Controls power-down of the PLL2 lock detector.
1: lock detector powered down.
0: lock detector active.
6 Reserved Default = 0; value must remain 0.
5 Enable frequency doubler Enables doubling of the PLL2 reference input frequency.
1: enabled.
0: disabled.
4 Enable SPI control of antibacklash
pulse width
Controls the functionality of Register 0x0F2, Bits[2:1].
0 (default): device automatically controls the antibacklash period.
1: antibacklash period defined by Register 0x0F2, Bits[2:1].
[3:2] Antibacklash pulse width control Controls the PFD antibacklash period of PLL2.
00 (default): minimum.
01: low.
10: high.
11: maximum.
These bits are ineffective unless Register 0x0F2, Bit 4 = 1.
0x0F2
[1:0] PLL2 charge pump mode Controls the mode of the PLL2 charge pump:
00: tristate.
01: pump up.
10: pump down.
11 (default): normal.
Table 47. VCO Control
Address Bits Bit Name Description
[7:5] Reserved Reserved.
4 Force release of distribution sync
when PLL2 is unlocked
0 (default): distribution is held in sync (static) until the output PLL locks. Then it is
automatically released from sync with all dividers synchronized.
1: overrides the PLL2 lock detector state; forces release of the distribution from
sync.
3 Treat reference as valid 0 (default): uses the PLL1 VCXO indicator to determine when the reference clock to
the PLL2 is valid.
1: treats the reference clock as valid even if PLL1 does not consider it to be valid.
2 Force VCO to midpoint frequency Selects VCO control voltage functionality.
0 (default): normal VCO operation.
1: forces VCO control voltage to midscale.
1 Calibrate VCO (not autoclearing) 1: initiates VCO calibration (this is not an autoclearing bit).
0: resets the VCO calibration.
0x0F3
0 Reserved Reserved.
B Counter (Bits[5:0]) Allowed N Division (4 × B + A)
A = 0 or A = 1 B = 4 16, 17
A = 0 to A = 2 B = 5 20, 21, 22
A = 0 to A = 2 B = 6 24, 25, 26
0x0F1
A = 0 to A = 3 B ≥ 7 28, 29 … continuous to 255
AD9524
Rev. C | Page 46 of 56
Table 48. VCO Divider Control
Address Bits Bit Name Description
[7:4] Reserved Reserved.
3 VCO divider power-down 1: powers down the divider.
0: normal operation.
Note that the VCO divider connects to all output channels.
0x0F4
[2:0] VCO divider
Bit 2 Bit 1 Bit 0 Divider Value
0 0 0 Divide-by-4
0 0 1 Divide-by-5
0 1 0 Divide-by-6
0 1 1 Divide-by-7
1 0 0 Divide-by-8
1 0 1 Divide-by-9
1 1 0 Divide-by-10
1 1 1 Divide-by-11
Table 49. PLL2 Loop Filter Control
Address Bits Bit Name Description
Bit 7 Bit 6
RPOLE2
(Ω)
0 0 900
0 1 450
1 0 300
[7:6] Pole 2 resistor (RPOLE2)
1 1
225
Bit 5 Bit 4 Bit 3
RZERO
(Ω)
0 0 0 3250
0 0 1 2750
0 1 0 2250
0 1 1 2100
1 0 0 3000
1 0 1 2500
1 1 0 2000
[5:3] Zero resistor (RZERO)
1 1 1 1850
Bit 2 Bit 1 Bit 0
CPOLE1
(pF)
0 0 0 0
0 0 1 8
0 1 0 16
0 1 1 24
1 0 0 24
1 0 1 32
1 1 0 40
0x0F5
[2:0] Pole 1 capacitor (CPOLE1)
1 1 1 48
[7:1] Reserved Reserved. 0x0F6
0 Bypass internal RZERO
resistor
Bypasses the internal RZERO resistor (RZERO = 0 Ω). Requires the use of a series external zero
resistor. This bit is the MSB of the loop filter control register (Address 0x0F5 and Address 0x0F6).
AD9524
Rev. C | Page 47 of 56
Clock Distribution (Address 0x196 to Address 0x1A1, Address 0x1AE to Address 0x1B3, Address 0x1BA, and Address 0x1BB)
Table 50. Channel 0 to Channel 5 Control (This same map applies to all six channels.)
Address Bits Bit Name Description
7 Invert divider output Inverts the polarity of the divider’s output clock.
6 Ignore sync 0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5 Power down channel 1: powers down the entire channel.
0: normal operation.
4 Lower power mode
(differential modes only)
Reduces power used in the differential output modes (LVDS/LVPECL/HSTL). This
reduction may result in power savings, but at the expense of performance. Note that
this bit does not affect output swing and current, just the internal driver power.
1: low strength/lower power.
0: normal operation.
Driver mode.
Bit 3 Bit 2 Bit 1 Bit 0 Driver Mode
0 0 0 0 Tristate output
0 0 0 1 LVPECL (8 mA)
0 0 1 0 LVDS (3.5 mA)
0 0 1 1 LVDS (7 mA)
0 1 0 0 HSTL-0 (16 mA)
0 1 0 1 HSTL-1 (8 mA)
0 1 1 0 CMOS (both outputs in phase)
+ Pin: true phase relative to divider output
− Pin: true phase relative to divider output
0 1 1 1 CMOS (opposite phases on outputs)
+ Pin: true phase relative to divider output
− Pin: complement phase relative to divider output
1 0 0 0 CMOS
+ Pin: true phase relative to divider output
− Pin: high-Z
1 0 0 1 CMOS
+ Pin: high-Z
− Pin: true phase relative to divider output
1 0 1 0 CMOS
+ Pin: high-Z
− Pin: high-Z
1 0 1 1 CMOS (both outputs in phase)
+ Pin: complement phase relative to divider output
− Pin: complement phase relative to divider output
1 1 0 0 CMOS (both outputs out of phase)
+ Pin: complement phase relative to divider output
− Pin: true phase relative to divider output
1 1 0 1 CMOS
+ Pin: complement phase relative to divider output
− Pin: high-Z
1 1 1 0 CMOS
+ Pin: high-Z
− Pin: complement phase relative to divider output
0x196
[3:0] Driver mode
1 1 1 1 Tristate output
0x197 [7:0] Channel divider, Bits[7:0] (LSB) Division = Channel Divider Bits[9:0] + 1. For example, [9:0] = 0 is divided by 1, [9:0] = 1
is divided by 2 … [9:0] = 1023 is divided by 1024. 10-bit channel divider, Bits[7:0] (LSB).
[7:2] Divider phase Divider initial phase after a sync is asserted relative to the divider input clock (from the
VCO divider output). LSB = ½ of a period of the divider input clock.
Phase = 0: no phase offset.
Phase = 1: ½ period offset, …
Phase = 63: 31 period offset.
0x198
[1:0] Channel divider, Bits[9:8] (MSB) 10-bit channel divider, Bits[9:8] (MSB).
AD9524
Rev. C | Page 48 of 56
Table 51. PLL1 Output Control (PLL1_OUT, Pin 46)
Address Bits Bit Name Description
[7:5] Reserved Reserved
4 PLL1 output CMOS driver
strength
CMOS driver strength
1: weak
0: strong
0x1BA
[3:0] PLL1 output divider 0000: divide-by-1
0001: divide-by-2 (default)
0010: divide-by-4
0100: divide-by-8
1000: divide-by-16
No other inputs permitted
Table 52. PLL1 Output Channel Control
Address Bits Bit Name Description
7 PLL1 output driver power-down PLL1 output driver power-down
[6:2] Reserved Reserved
1 Route VCXO clock to
Channel 1 divider input
1: channel uses VCXO clock; routes VCXO clock to divider input
0: channel uses VCO divider output clock
0x1BB
0 Route VCXO clock to
Channel 0 divider input
1: channel uses VCXO clock; routes VCXO clock to divider input
0: channel uses VCO divider output clock
Readback (Address 0x22C and Address 0x22D)
Table 53. Readback Registers (Readback 0 and Readback 1)
Address Bits Bit Name Description
7 Status PLL2 reference clock 1: OK
0: off/clocks are missing
6 Status PLL2 feedback clock 1: OK
0: off/clocks are missing
5 Status VCXO 1: OK
0: off/clocks are missing
4 Status REF_TEST 1: OK
0: off/clocks are missing
3 Status REFB 1: OK
0: off/clocks are missing
2 Status REFA 1: OK
0: off/clocks are missing
1 Lock detect PLL2 1: locked
0: unlocked
0x22C
0 Lock detect PLL1 1: locked
0: unlocked
[7:4] Reserved Reserved
3 Holdover active 1: holdover is active (both references are missing)
0: normal operation
2 Selected reference
(in auto mode)
Selected reference (applies only when the device automatically selects the reference;
for example, not in manual control mode)
1: REFB
0: REFA
1 Reserved Reserved
0x22D
0 VCO calibration in progress 1: VCO calibration in progress
0: VCO calibration not in progress
Other (Address 0x230 to Address 0x234)
Table 54. Status Signals
Address Bits Bit Name Description
0x230 [7:6] Reserved Reserved.
AD9524
Rev. C | Page 49 of 56
Address Bits Bit Name Description
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Muxout
0 0 0 0 0 0 GND
0 0 0 0 0 1 PLL1 and PLL2 locked
0 0 0 0 1 0 PLL1 locked
0 0 0 0 1 1 PLL2 locked
0 0 0 1 0 0 Both references are missing (REFA and REFB)
0 0 0 1 0 1 Both references are missing and PLL2 is locked
0 0 0 1 1 0 REFB selected (applies only to auto select mode)
0 0 0 1 1 1 REFA is OK
0 0 1 0 0 0 REFB is OK
0 0 1 0 0 1 REF_TEST is OK
0 0 1 0 1 0 VCXO is OK
0 0 1 0 1 1 PLL1 feedback is OK
0 0 1 1 0 0 PLL2 reference clock is OK
0 0 1 1 0 1 Reserved
0 0 1 1 1 0 REFA and REFB are OK
0 0 1 1 1 1 All clocks are OK (except REF_TEST)
0 1 0 0 0 0 PLL1 feedback is divide-by-2
0 1 0 0 0 1 PLL1 PFD down divide-by-2
0 1 0 0 1 0 PLL1 REF divide-by-2
0 1 0 0 1 1 PLL1 PFD up divide-by-2
0 1 0 1 0 0 GND
0 1 0 1 0 1 GND
0 1 0 1 1 0 GND
0 1 0 1 1 1 GND
[5:0] Status Monitor 0 control
Note that all bit combinations after 010111 are reserved.
AD9524
Rev. C | Page 50 of 56
Address Bits Bit Name Description
[7:6] Reserved Reserved.
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Muxout
0 0 0 0 0 0 GND
0 0 0 0 0 1 PLL1 and PLL2 locked
0 0 0 0 1 0 PLL1 locked
0 0 0 0 1 1 PLL2 locked
0 0 0 1 0 0 Both references are missing (REFA and REFB)
0 0 0 1 0 1 Both references are missing and PLL2 is locked
0 0 0 1 1 0 REFB selected (applies only to auto select mode)
0 0 0 1 1 1 REFA is OK
0 0 1 0 0 0 REFB is OK
0 0 1 0 0 1 REF_TEST is OK
0 0 1 0 1 0 VCXO is OK
0 0 1 0 1 1 PLL1 feedback is OK
0 0 1 1 0 0 PLL2 reference clock is OK
0 0 1 1 0 1 Reserved
0 0 1 1 1 0 REFA and REFB are OK
0 0 1 1 1 1 All clocks are OK (except REF_TEST)
0 1 0 0 0 0 GND
0 1 0 0 0 1 GND
0 1 0 0 1 0 GND
0 1 0 0 1 1 GND
0 1 0 1 0 0 PLL2 feedback is divide-by-2
0 1 0 1 0 1 PLL2 PFD down divide-by-2
0 1 0 1 1 0 PLL2 REF divide-by-2
0 1 0 1 1 1 PLL2 PFD up divide-by-2
0x231
[5:0] Status Monitor 1 control
Note that all bit combinations after 010111 are reserved.
[7:5] Reserved Reserved.
4 Enable Status_EEPROM
on STATUS0 pin
Enables the EEPROM status on the STATUS0 pin.
1: enable status.
3 STATUS1 pin divider
enable
Enables a divide-by-4 on the STATUS1 pin, allowing dynamic signals to be viewed at a lower
frequency (such as the PFD input clocks). Not to be used with dc states on the status pins,
which occur when the settings of Register 0x231, Bits[5:0] are in the range of 000000 to 001111.
1: enabled.
0: disabled.
2 STATUS0 pin divider
enable
Enables a divide-by-4 on the STATUS0 pin, allowing dynamic signals to be viewed at a lower
frequency (such as the PFD input clocks). Not to be used with dc states on the status pins,
which occur when the settings of Register 0x230, Bits[5:0] are in the range of 000000 to 001111.
1: enable.
0: disable.
1 Reserved Reserved.
0x232
0 Sync dividers
(manual control)
Set bit to put dividers in sync; clear bit to release. Functions like SYNC pin low.
1: sync.
0: normal.
AD9524
Rev. C | Page 51 of 56
Table 55. Power-Down Control
Address Bits Bit Name Description
[7:3] Reserved Reserved.
2 PLL1 power-down 1: power-down (default).
0: normal operation.
1 PLL2 power-down 1: power-down (default).
0: normal operation.
0x233
0 Distribution power-
down
Powers down the distribution.
1: power-down (default).
0: normal operation.
Table 56. Update All Registers
Address Bits Bit Name Description
[7:1] Reserved Reserved. 0x234
0 IO_Update This bit must be set to 1 to transfer the contents of the buffer registers into the active registers,
which happens on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to
be set back to 0.
1 (self-clearing): update all active registers to the contents of the buffer registers.
EEPROM Buffer (Address 0xA00 to Address 0xA16)
Table 57. EEPROM Buffer Segment
Address Bits Bit Name Description
0xA00
to
0xA16
[7:0] EEPROM Buffer
Segment Register 1 to
EEPROM Buffer
Segment Register 23
The EEPROM buffer segment section stores the starting address and number of bytes that are to
be stored and read back to and from the EEPROM. Because the register space is noncontiguous,
the EEPROM controller needs to know the starting address and number of bytes in the register
space to store and retrieve from the EEPROM. In addition, there are special instructions for the
EEPROM controller: operational codes (that is, IO_Update and end-of-data) that are also stored
in the EEPROM buffer segment. The on-chip default setting of the EEPROM buffer segment
registers is designed such that all registers are transferred to/from the EEPROM, and an
IO_Update is issued after the transfer (see the Programming the EEPROM Buffer Segment section).
EEPROM Control (Address 0xB00 to Address 0xB03)
Table 58. Status_EEPROM
Address Bits Bit Name Description
[7:1] Reserved Reserved. 0xB00
0 Status_EEPROM
(read only)
This read-only bit indicates the status of the data transferred between the EEPROM and the
buffer register bank during the writing and reading of the EEPROM. This signal is also available
at the STATUS0 pin when Register 0x232, Bit 4 is set.
0: data transfer is complete.
1: data transfer is not complete.
Table 59. EEPROM Error Checking Readback
Address Bits Bit Name Description
[7:1] Reserved Reserved. 0xB01
0 EEPROM data error
(read only)
This read-only bit indicates an error during the data transfer between the EEPROM and the buffer.
0: no error; data is correct.
1: incorrect data detected.
AD9524
Rev. C | Page 52 of 56
Table 60. EEPROM Control 1
Address Bits Bit Name Description
[7:2] Reserved Reserved.
1 Soft_EEPROM When the EEPROM_SEL pin is tied low, setting the Soft_EEPROM bit resets the AD9524 using
the settings saved in EEPROM.
1: soft reset with EEPROM settings (self-clearing).
0xB02
0 Enable EEPROM write Enables the user to write to the EEPROM.
0: EEPROM write protection is enabled. User cannot write to EEPROM (default).
1: EEPROM write protection is disabled. User can write to EEPROM.
Table 61. EEPROM Control 2
Address Bits Bit Name Description
[7:1] Reserved Reserved. 0xB03
0 REG2EEPROM Transfers data from the buffer register to the EEPROM (self-clearing).
1: setting this bit initiates the data transfer from the buffer register to the EEPROM (writing
process); it is reset by the I²C master after the data transfer is done.
AD9524
Rev. C | Page 53 of 56
OUTLINE DIMENSIONS
PIN 1
INDICATOR
TOP
VIEW 6.75
BSC SQ
7.00
BSC SQ
1
48
12
13
37
36
24
25
5.25
5.10 SQ
4.95
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BSC
12° MAX
0.20 REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
5.50
REF
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX PIN 1
INDICATOR
COPLANARITY
0.08
SEATING
PLANE
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
080108-A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 44. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9524BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1
AD9524BCPZ-REEL7 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1
AD9524/PCBZ Evaluation Board
1 Z = RoHS Compliant Part.
AD9524
Rev. C | Page 54 of 56
NOTES
AD9524
Rev. C | Page 55 of 56
NOTES
AD9524
Rev. C | Page 56 of 56
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09081-0-6/11(C)
