Am27LV020/Am27LV020B 2 Megabit (262,144 x 8-Bit) Low Voltage CMOS EPROM ct Advanced Micro Devices DISTINCTIVE CHARACTERISTICS @ Single 3.3 V power supply Regulated power supply 3.0 V-3.6 V Unregulated power supply 2.7 V-3.6 V (battery-operated systems) @ Low power consumption: 10 pA typical CMOS standby current 30 wW maximum standby power 20 mW typical H Fast access time 150 ns power at 5 MHz @ JEDEC-approved pinout Pin compatible with 5.0 V 2 Mbit EPROM Easy upgrade from 28-pin JEDEC EPROMs 100% Flashrite programming Typical programming time of 32 seconds Latch-up protected to 100 mA from -1 V to Veco +1 V High noise immunity Compact 32-pin DIP package requires no hardware change for upgrades to 8 Mbit Versatile features for simple interfacing Both CMOS and TTL input/output compatibility Two line control functions GENERAL DESCRIPTION The Am27LV020 is a low voltage, low power 2 Mbit, ultraviolet erasable, progammable read-only memory organized as 256K words by 8 bits per word. devices consume at least 57% less power than their 5.0 V counterparts. Due to its lower current and voltage, the Am27LV020 is well-suited for battery operated and portable systems as it extends the battery life in these The Am27LV020 operates from a single power supply of 3.3 V and is offered with two power supply tolerances. The Am27LV020 has a Vcc tolerance range of 3.3 V +0.3 V making it suitable for use in systems that have regulated power supplies. The Am27LV020B has a volt- age supply range of 2.7 V3.6 V making it an ideal part for battery operated systems. systems. Typical applications are notebook and hand- held computers as well as cellular phones. The Am27LV020 is packaged in the industry standard 32-pin windowed ceramic DIP and LCC packages, as well as one-time programmable (OTP) packages. This device is pin-compatible with the 5.0 V devices. Maximum power consumption of the Am27LV020 in standby mode is only 90 WW. If the device is constantly accessed at 5 MHz, thenthe maximum power consump- tion increases to 54 mW. These power ratings are sig- nificantly lower than typical EPROMs. Also, as power consumption is proportional to voltage squared, 3.3 V The Am27LV020 uses AMDs Flashrite programming algorithm (100 ys pulses) resulting in typical program- ming times of 32 seconds. This device is manufactured on AMD's sub-micron process technology which pro- vides high speed, low power and high noise immunity. Data Outputs BLOCK DIAGRAM o> Veo Bdo-DO7 o* Vss oa o> Vpp { t t t t t { t OE * Output Enable ce - Chip Enable Output Buffers PGM "1 ~~ Prog Logic ad Y Y-Gati s] ~sCDecoder Gating A0-A17 Address * Inputs | X ; 2,097,152-Bit Decoder e Cell Matrix : _ 17342B-1 Pubhication# 17342 Rev. B Issue Date. February 1994 Amendment/0 This document contains information on a product under developmant at Advanced Micro Devices. Inc The information 1s Intended to help you to evaluate this product AMD reserves the right to change or discontinue work on this proposed product without notice 2-23 @@ 0257525 0046656 O10zi AMD PRELIMINARY PRODUCT SELECTOR GUIDE Family Part No Am27LV020/Am27LV020B Ordering Part No: Am27LV020 (3.0 V~3.6 V) -150 +200 -250 -300 Am27LV020B (2.7 V-3.6 V) -200 -250 -300 Max Access Time (ns) 150 200 250 300 CE (EjAccess (ns) 150 200 250 300 OE (G)Access (ns) 65 75 100 120 CONNECTION DIAGRAMS Top View DIP PLCC/LCC Vee []1 321] Vcc ie Ai6 [J2 31[] PGM & Ais [I] 3 30[] A17 Al2 [| 4 207] A14 A7 Os 281] Ai3 Ay At A6 [Je 27[] Aa AG Aig As []7 267] A9 AS A8 A4 (ys 25. Att A4 AS A3[]9 24f] OF G AS AN A2 OE (G) A2 [10 od At At0 At at 22[] CE ) AO CE (E) Ao [] 12 21[] Daz Dao ba7 pao [] 13 20[] Das 0a1 [14 191) Das paz [fis 18,1] Da4 Vss []16 171] 003 | 6155.0 17342B-3 Notes: 1. JEDEC nomenciature is in parenthesis. PIN DESCRIPTION LOGIC SYMBOL AQ-A17 = Address Inputs 18 CE (E) ~ = Chip Enable Input (> AO-A17 DQ0-DQ7 = Data Input/Outputs 8 OE (G) = Output Enable Input DQo-Da7 PGM (P) = Program Enable Input CE (E) Veo = Vee Supply Voltage | PGM (P) Vpp = Program Supply Voltage ~| OE G) Vss = Ground 17342B-4 MH 0257525 OO4bbsd Te? 2-24 Am27LV020/Am27LV020BPRELIMINARY AMD & ORDERING INFORMATION EPROM Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27LV020 2150 DO Cc 30. B L_ OPTIONAL PROCESSING Blank = Standard processing B = Burn-in TEMPERATURE RANGE C = Commercial (0C to +70C) | = Industrial (-40C to +85C) PACKAGE TYPE D = 32-Pin Ceramic DIP (CDV032) L = 32-Pin Rectangular Ceramic Leadless Chip Carrier (CLV032, JEDEC Type) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27LV020 - 2 Megabit (262,144 x 8-Bit) Low Voltage CMOS EPROM with 3.0 V3.6 V Vcc Tolerance Am27LV020B - 2 Megabit (262,144 x 8-Bit) Low Voltage CMOS EPROM with 2.7 V-3.6 V Voc Tolerance Valid Combinations Valid Combinations OC. DCB. DI Valid Combinations list configurations planned to be ' Ui, supported in volume for this device. Consult the lo- AM27LV020-150 | DIB, LC, LCB, cal AMD sales office to confirm availability of specific Ll, LIB valid combinations and to check on newly released AM27LV020-200 combinations. AM27LV020-250 DC. DCB. DI AM27LV020-300_| DIB, LC. LCB, AM27LV020B-200 |__LI, LIB AM27LV020B-250 AM27LV020B-300 EPROM Products 2-25 MM 0257525 CO4bbLO 749&1 amo PRELIMINARY ORDERING INFORMATION OTP Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27LV020 150. J L OPTIONAL PROCESSING Blank = Standard processing TEMPERATURE RANGE GC = Commercial (0C to +70C) 1 = Industrial (-40C to +85C) PACKAGE TYPE J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) SPEED OPTION See Praduct Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27LV020 2 Megabit (262,144 x 8-Bit) Low Valtage CMOS OTP EPROM with 3.0 V~3.6 V Vcc Tolerance Am27LV020B 2 Megabit (262,144 x 8-Bit) Low Voltage CMOS OTP EPROM with 2.7 V3.6 V Vcc Tolerance Valid Combinations Valid Combinations Valid Combinations list configurations planned to be AM27LV020-150 supported in volume for this device. Consult the lo- AM27LV\ cal AMD sales office to confirm availability of specific 27LV020-200 valid combinations and to check on newly released AM27LV020-250 combinations. AM27LV020-300 JG, Jl AM27LV020B-200 AM27LV020B-250 AM27LV020B-300 M@ 0257525 OO4bbbL bas 2-26 Am27LV020/Am27LV020BMm 0257525 OO4bbbe 51) PRELIMINARY AMD a FUNCTIONAL DESCRIPTION Erasing the Am27LV020 In order to clear all locations of their programmed con- tents, itis necessary to expose the Am27LV020 to an ul- traviolet light source. A dosage of 15 W seconds/cm? is required to completely erase an Am27LV020. This dos- age can be obtained by exposure to an ultraviolet lamp wavelength of 2537 A with intensity of 12,000 pW/ cm? for 15 to 20 minutes. The Am27LV020 should be di- rectly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the Am27LV020, and similar devices, will erase with light sources having wave- lengths shorter than 4000 &. Although erasure times will be much longer than with UV sources at 2537 A, never- theless the exposure to fluorescent light and sunlight will eventually erase the Am27LV020 and exposure to them should be prevented to realize maximum system reli- ability. If used in such an environment, the package win- dow should be covered by an opaque label or substance. Programming the Am27LV020 Upon delivery, or after each erasure, the Am27LV020 has all 2,097,152 bits in the ONE, or HIGH state. ZEROs are loaded into the Am27LV020 through the procedure of programming. The programming mode is entered when 12.75 V + 0.25 V is applied to the Vee pin, CE and PGM are at ViL and OE is at Vin. For programming, the data to be programmed is applied 8 bits in parallel to the data output pins. The Flashrite algorithm reduces programming time by using 100 us programming pulse and by giving each ad- dress only as many pulses as are necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies orihe maximum is reached. This process is re- peated while sequencing through each address of the Am27LV020. This part of the algorithm is done at Vcc = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final ad- dress is completed, the entire EPROM memory is veri- fied at Voc = Vpp = 5.25 V. Am27LV020 can be programmed using the same algorithm as the 5 V coun- terpart Am27C020. Please refer to Section 6 for programming flow chart and characteristics. Program Inhibit Programming of multiple Am27LV020s in parallel with different data is also easily accomplished. Except for CE, all like inputs of the parallel Am27LV020 may be common. A TTL low-level program pulse applied to an Am27LV020 CE input with Vep = 12.75 + 0.25 V, PGM LOW, and OF HIGH will program that Am27LV020. A high-level CE input inhibits the other Am27LV020s from being programmed. Program Verify Averify should be performed on the programmed bits to determine that they were correctly programmed, The verify should be performed with OE and CE at Vit, PGM at Vin, and Vee between 12.5 V and 13.0 V. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C +5C ambient temperature range that is required when programming the Am27LV020. To activate this mode, the programming equipment must force 12.0 + 0.5 V on address line AQ of the Am27LV020. Two identifier bytes may then be se- quenced from the device outputs by toggling address line AO from Vit to Vin. All other address lines must be held at Vi. during auto select mode. Byte 0 (A0= ViL) represents the manufacturer code, and Byte 1 (AO = Vin), the device identifier code. For the Am27LV020, these two identifier bytes are given in the Mode Select table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. Read Mode The Am27LV020 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tacc) is equal to the delay from CE to output (Ice). Data is available at the outputs toe after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tacc tce. Standby Mode The Am27LV020 has a CMOS standby mode which re- duces the maximum Vcc current to 25 pA. It is placed in CMOS-standby when CE is at Vec + 0.3 V. The Am27LV020 also has a TTL-standby mode which re- duces the maximum Vcc current to 0.6 mA. It is placed in TTL-standby when CE is at Vin. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. Mixed Power Supply System Am27LV020 (in 3.0 V to 3.6 V regulated power supply) can be interfaced with 5 V system only when the I/O pins (DQ0-DQ7) are not driven by the 5 V system. Vitimax = Vecrv +2.2 V for address and clock pins and EPROM Products 2-27al AMD Vitmax = Vecrv +0.5 V for I/O pins should be followed to avoid CMOS latch-up condition. Output OR-Tieing To accommodate multiple memory connections, a two- line control function is provided to allow for: mw Low memory power dissipation @ Assurance that output bus contention will not occur Itis recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and con- nected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. PRELIMINARY System Applications During the switch between active and standby condi- tions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the out- put capacitance loading of the device. Ata minimum, a 0.1 pF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Vcc and Vss to minimize transient effects. in addition, to overcome the voltage drop caused by the inductive ef- fects of the printed circuit board traces on EPROM ar- rays, 44.7 yF bulk electrolytic capacitor should be used between Vcc and Vss for each eight devices. The foca- tion of the capacitor should be close to where the power supply is connected to the array. MODE SELECT TABLE Mode Pins CE OE PGM Ao AQ Vep Outputs Read VIL Vit X X xX Xx Dour Output Disable Vit ViH X X Xx X High Z Standby (TTL) Vii Xx xX X X x High Z Standby (CMOS) Vec+0.3V Xx x xX xX x High Z Program VIL Vin Vit X X VPP DIN Program Verity VIL Vit VIH x x Vpp DouT Program Inhibit Vin x xX Xx X Vpp High Z Auto Select | Manufacturer Code VIL Vit xX Vit VH x O1H (Note 3) Device Code VIL Viv x Vin VH x 97H Notes: 1. Va=12.0VL05V 2. X can be either Vit or Vin 3. Al-A8 = A10-A17 = Vit 4. See DC Programming Characteristics for Vpp voltage during programming. Mi 0257525 OO04bbbS 458 2-28 Am27LV020/Am27LV020BPRELIMINARY amp & ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature: Commercial (C) Devices OTP Products .............. 65C to +125C Case Temperature (Tc) .......... 0C to +70C All Other Products ........... -65C to +150C industrial (I) Devices Ambient Temperature Case Temperature (Tc) ........ 40C to +85C . ; BRO 2 with Power Applied ............. 55C to +125C Supply Read Voltages: Voltage with Respect to Vss: Vector AM27LV020 .......... +3.0 V 10 +3.6V All pins except A9, Vpp, and Vecfor AM27LV020B ........- +2.7 V to 43.6 V Vec (Note 1) ............ 0.6 V to Ver + 0.6 V ; AQ and Ver (Note 2) ............. 0.6 V to 13.5 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. VEO Lecce cece eee eee 0.6 Vito 7.0V Notes: 1. During transitions, the input may overshoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O may overshoot to Vcc + 2.0 V for peri- ods of up to 20 ns. 2. During transitions, AQ and Ver may overshoot Vss to -2.0 V for periods of up to 20 ns. A9 and Vpp must not exceed 13.5 V for any period of time. Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maxi- mum ratings for extended periods may affect device reliability. EPROM Products 2-29 MM 0257525 OO4bbbY 3594at AMD PRELIMINARY DC CHARACTERISTICS over operating ranges unless otherwise specified (Notes 1, 2, 3, and 4) Parameter Symbol | Parameter Description Test Conditions Min Max Unit TTL and CMOS Inputs for Am27LV020 (Vcc = 3.0 V to 3.6 V) VOH Output HIGH Voltage JoH = -2.0mA 2.4 Vv VoL Output LOW Voltage lo. = 2.0 mA 0.4 Vv VIH Input HIGH Voltage 2.0 Veco +03] V VIL Input LOW Voltage -0.3 +0.8 Vv IL Input Load Current Vin = 0 V to Vcc 1.0 pA ILo Output Leakage Current Vout = 0 V to Vcc 5.0 pA Icc1 Vcc Active Current CE = VIL, 15 mA (Note 3) f=5 MHz, louT = 0 mA (Open Outputs) lec2 Vec TTL Standby Current CE = Vin, OE = VIL TIL 0.6 mA Icca Vcc CMOS Standby Current CE = Vcc +0.3V CMOS 25 pA lpp4 Vep Current During Read CE = OF = Vit, Vpp = Vcc 1.0 pA Parameter Symbol | Parameter Description Test Conditions Min Max Unit CMOS for Am27LV020B (Vcc = 2.7 V to 3.6 V VoH Output HIGH Voltage loH = -20 pA Vec 0.1 Vv loH = -100 WA Veco 0.2 V VoL Output LOW Voltage lo. = 20 pA 0.1 Vv lot = 100 pA 0.2 Vv Vin Input HIGH Voltage 2.0 Vec + 0.3 v Vit Input LOW Voltage 0.3 0.8 v lu Input Load Current Vin = 0 Vto +Vcc 1.0 pA Lo Output Leakage Current VouT = 0 V to +Vcc 5.0 pA Iec1 Vcc Active Current CE=VIL, 15 mA (Note 3) f = 5 MHz, louT = 0 mA (Open Outputs) Icc2 Vec TTL Standby Current CE = Vin, OF = Vi TTL 0.6 mA Icca Vcc CMOS Standby Current CE = Vec40.3V 25 nA Ipp1 Vpp Supply Current (Read) CE = OE = Vil, Vpp = Voc 1.0 pA Notes: 1. Veco must be applied simultaneously or before Vep, and removed simultaneously or after Vpp. 2. Caution: The Am27LV020 must not be removed from (or inserted into) a socket when Vcc or Vpp is applied. 3. Iecs is tested with OE = Vin to simulate open outputs. 4. Minimum DC Input Voltage is -0.3 V. During transitions, the inputs may overshoot to -2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is Vec +0.3 V, which may overshoot to Vcc +2.0 V for periods less than 20 ns. 2-30 Am27LV020/Am27LV020B MH 0257525 OOvbbbS 220Pa PRELIMINARY AMD 10 10 nen 75 a 75 pened 5 . _ io) =a | e Ln ) & Pn < S 5 - = 5 a 25 H 25 0 0 1 23 4 5 6 7 8&8 9 10 -75 -50 -25 0 25 50 75 100 125 150 Frequency in MHz Temperature in C Figure 1. Typical Supply Current Figure 2. Typical Supply Current vs. Frequency vs. Temperature Vee = 3.6 V, T = 25C Vec = 3.6 V, f= 5 MHz 17342B-5 17342B-6 CAPACITANCE Parameter CDV032 CLV032 PLO32 Symbol | Parameter Description Test Conditions Typ | Max | Typ | Max | Typ | Max] Unit Cin Input Capacitance Vin= OV 10 12 10 8 10 | pF Cout Output Capacitance Vout = 0 V 12 15 12 9 12 | pF Notes: 1. This parameter is only sampled and not 100% tested. 2. Ta =+25C, f= 1 MHz. EPROM Products 2-31 Mm 02575e5 OOYLLELb 167cl AMD PRELIMINARY SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified (Notes 1, 3, and 4) PRELIMINARY Parameter Am27LV020/Am27LV020B Symbols Parameter JEDEC| Standard] Description Test Conditions 150 | -200 | -250 | -300 Unit taVaV tacc | Address to CE-DEV Min ns = OE = VIL Output Delay Max | 150 | 200 | 250 | 300 teLav tceE Chip Enable _ Min ns Output Delay OF = Vit Max | 150 | 200 | 250 | 300 taLav toe | Output Enableto | = Min Output Delay Ce = Vu Max | 65 | 75 | 100 | 120 ns tEHOZ tDF Chip Enable HIGH Min 0 0 0 0 teHaz | (Note 2) | or Output Enable HIGH, whichever ns comes first, to Max 50 60 60 60 Output Fioat taxax tou Output Hold from Min 0 0 0 0 Addresses, CE, or ns OE, whichever Max occurred first Notes: 1. 2. 3. 4 input Rise and Fall Times: 20 ns, Input Pulse Levels: 0.40 V to 2.4 V, Timing Measurement Reference Levelinputs: 0.8 V and 2.0 V, Outputs: 0.8 V and 2.0 V Mm 0257525 OO4bLL? OTS Veco must be applied simultaneously or before Vep, and removed simultaneously or after Vpp. This parameter is only sampled and not 100% tested. Caution: The Am27LV020 must not be removed from, ar inserted into a socket or board when Vep or Vcc is applied. . Output Load: 1 TTL gate and C1 = 100 pF, 2-32 Am27LV020/Am27LV020BPRELIMINARY ap SWITCHING TEST CIRCUIT Device 2.7 kQ Under 5.0V Test Diodes = IN3064 or Equivalent 17342B-7 Ci = 100 pF including jig capacitance SWITCHING TEST WAVEFORM 2.4V 2.0V 2.0V Test Points 0.8V 0.8V 0.40 V Input Output 17342B-6 AC Testing: Inputs are driven at 2.4 V for a Logic 1 and 0.40 V for a Logic 0. Input pulse rise and fall times are s 20 ns. EPROM Products 2-33 M8 0257525 OOLbbSa TITal AMD PRELIMINARY KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must Be Will Be Steady Steady May Will Be Change Changing from H to L from H toL May Will Be Change Changing from Lto H from Lto H Don't Care, Changing, Any Change State Permitted Unknown Does Net Center Apply Line is High Impedance Oft State KS000010 SWITCHING WAVEFORM 2.4 J --- Addresses X 2.0 Addresses Valid 2.0 0.40 08 -~28 /______ CE \ tte _ or OE toe oT tt N tOF 2 ote (hots ) 10H High Z F 7 - High Z Output CC Valid Output by} UC ee p E Notes: 17342B-8 1, OE may be delayed up to tacc toe after the falling edge of the addresses without impact on tacc. 2. tor is specified from OE or CE, whichever occurs first. 2-34 Am27LV020/Am27LV020B M@ 0257525 OO4LLLS 576PRELIMINARY PROGRAMMING FLOW CHART Interactive Section Verify Section Start Address = First Location Veco = 6.25 V Vep = 12.75 V Increment Address Program One 100 ys Pulse Increment X Verify Byte ? Pass Last Address? Vcc = Vpp = 5.25 V Figure 1. Flashrite Programming Flow Chart AMD al Device Failed 17342B-9 EPROM Products M@ 0257525 OO4bLb70 698oh amo PRELIMINARY DC PROGRAMMING CHARACTERISTICS (Ta = +25C +5C) (Notes 1, 2, and 3) Parameter Symbol Parameter Description Test Conditions Min Max Unit tu Input Current (All Inputs) Vin = Vit or Vin 10.0 pA Vit Input LOW Level (All Inputs) -0.3 0.8 Vv Vin Input HIGH Level 3.0 Veco + 0.5 Vv Voi Output LOW Voltage During Verify fol = 2.1 mA 0.45 Vv Vou Qutput HIGH Voltage During Verify lon = 400 pA 2.4 Vv Vu Ag Auto Select Voltage 11.5 12.5 Vv Ic Vcc Supply Current (Program & Verify) 50 mA Ipp Vee Supply Current (Program) GE = Vi, OF = Vin 30 mA Voc Flashrite Supply Voltage 6.00 6.50 Vv Vpp Flashrite Programming Voitage 12.5 13.0 v SWITCHING PROGRAMMING CHARACTERISTICS (Ta = +25C +5C) (Notes 1, 2, and 3) Parameter Symbols JEDEC Standard Parameter Description Min Max Unit tavet tas Address Setup Time 2 ps tozet toes OE Setup Time 2 ps Tove tos Data Setup Time 2 ps toHax tay Address Hold Time 0 hts tEHDx tou Data Hald Time 2 us taHoz tore Output Enable to Output Float Delay 0 130 ns tves tvps Vpp Setup Time 2 us teLeHi tew PGM Initial Program Pulse Width 95 105 ps tvcs tves Vee Setup Time 2 ps teELPL tces CE Setup Time 2 us taLav toe Data Valid from OE 150 ns Notes: 1. Vec must be applied simultaneausly or before Vpp, and removed simultaneously or after Vpp. 2. When programming the Am27LV020, a 0.1 uF capacitor is required across Vep and ground to suppress spurious voltage transients which may damage the device. 3. Programming characteristics are sampled but not 100% tested at worst-case conditions. 2-36 Am27LV020/Am27LV020B MH 0257525 O04bb71 5cuPRELIMINARY AMD eA M@@ 0257525 OO4bb7e 460 Me INTERACTIVE AND FLASHRITE PROGRAMMING ALGORITHM WAVEFORM (Notes 1 and 2) Program Program Verify VIN Addresses VIL tas Data Data In Stable Data Out Valid tos Vpp Vec PGM Notes: 17342B-10 1. The input timing reference level is 0.8 V for Vit and 3 V for Vin. 2. tO and torp are characteristics of the device, but must be accommodated by the programmer. EPROM Products 2-371 amo PRELIMINARY PHYSICAL DIMENSIONS* CDV032 32-Pin Ceramic DIP (measured in inches) Le 1.635 | | 1.680 | Ch tel 045 .100 .005 065 BSC MIN TOP VIEW || O14 026 SIDE VIEW 220 Oo 125 ' 0 .200 ao 908 018 L600 | 90 vee 5/8/63 aa BSC END VIEW 2-38 Am27LV020/Am27LV020B MM! 0257525 OO44b73 3T?PRELIMINARY awp PHYSICAL DIMENSIONS* CLV032 32-Pin Rectangular Ceramic Leadless Chip Carrier (measured in inches) .300 BSC 180 .400 BSC 006 4 .022 I~ ors 442 458 .040 X 45 REF (3x) 440 3 * MAX . 080 rc 440 | - = = UV Lens 4 re 540 530 a 580 MAX _ F _Y_ ainda y +a os4_ tt .088 Index Corner 082430 032 .020 X 45 REF PLANE 2 a 2/10/93 de PLANE 1 EPROM Products 2-39 M@ 0257525 OO4bb74 2334 amo PRELIMINARY PHYSICAL DIMENSIONS* PD 032 32-Pin Plastic DIP (measured in inches) Lee 1,640 | r 1.680 "| ) 930 580 4 + | .045 .090 .005 .065 110 MIN TOP VIEW 600 140 008 Dpg 015 po! [a =o. i | 630 | s21468 -700 PD 032 oF CJ75 PD 1/21/93 cde SIDE VIEW END VIEW MB 0257525 OO4Lb75 17T 2-40 Am27LV020/Am27LV020BPRELIMINARY amo &t PHYSICAL DIMENSIONS* PL 032 32-Pin Rectangular Plastic Leaded Chip Carrier (measured in inches) 020 042 050 MIN .048 REF -042 025 | 056 | = ash @ Bh 032 tors q 1 013 A fot 585 547 4 A 300 .390 595 553 REF .430 q HN Q iN q i q HN A COTO 1 009 447 015 | 080 453 095 cea71c 485 125 CJ79 PL 032 495 MM t40 6/22/93 ae TOP VIEW SIDE VIEW For reference only. BSC is an ANSI standard for Basic Space Centering. EPROM Products 2-41 @@ 02575e5 OO4bb?b OOL