MOTOROLA MC68030 ENHANCED 32-BIT MICROPROCESSOR USER'S MANUAL Third Edition MOTOROLA INC., 1992 PREFACE The MC68030 User's Manual describes the capabilities, operation, and programming of the MC68030 32-bit second-generation enhanced microprocessor. The manual consists of the following sections and appendix. For detailed information on the MC68030 instruction set refer to M68000PM/AD, M68000 Family Programmer's Reference Manual. Section 1. Introduction Section 2. Data Organization and Addressing Capabilities Section 3. Instruction Set Summary Section 4. Processing States Section 5. Signal Description Section 6. On-Chip Cache Memories Section 7. Bus Operation Section 8. Exception Processing Section 9. Memory Management Unit Section 10. Coprocessor Interface Description Section 11. Instruction Execution Timing Section 12. Applications Information Section 13. Electrical Characteristics Section 14. Ordering Information and Mechanical Data Appendix A. M68000 Family Summary Index NOTE In this manual, assertion and negation are used to specify forcing a signal to a particular state. In particular, assertion and assert refer to a signal that is active or true; negation and negate indicate a signal that is inactive or false. These terms are used independently of the voltage level (high or low) that they represent. The audience of this manual includes systems designers, systems programmers, and applications programmers. Systems designers need some knowledge of all sections, with particular emphasis on Sections 1, 5, 6, 7, 13, 14, and Appendix A. Designers who implement a coprocessor for their system also need a thorough knowledge of Section 10. MOTOROLA MC68030 USER'S MANUAL xxiii Systems programmers should become familiar with Sections 1, 2, 3, 4, 6, 8, 9, 11, and Appendix A. Applications programmers can find most of the information they need in Sections 1, 2, 3, 4, 9, 11, 12, and Appendix A. From a different viewpoint, the audience for this book consists of users of other M68000 Family members and those who are not familiar with these microprocessors. Users of the other family members can find references to similarities to and differences from the other Motorola microprocessors throughout the manual. However, Section 1 and Appendix A specifically identify the MC68030 within the rest of the family and contrast its differences. xxiv MC68030 USER'S MANUAL MOTOROLA TABLE OF CONTENTS Paragraph Number Title Page Number Section 1 Introduction 1.1 1.2 1.3 1.4 1.5 1.6 1.6.1 1.6.2 1.7 1.8 1.9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68030 Extensions to the M68000 Family . . . . . . . . . . . . . . . . . . . Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Types and Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtual Memory and Virtual Machine Concepts . . . . . . . . . . . . . . . . . Virtual Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtual Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Memory Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pipelined Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Cache Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1-4 1-4 1-10 1-10 1-12 1-12 1-14 1-15 1-16 1-16 Section 2 Data Organization and Addressing Capabilities 2.1 2.2 2.2.1 2.2.2 2.2.3 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 2.4.9 2.4.10 2.4.11 2.4.12 2.4.13 2.4.14 2.4.15 2.4.16 2.4.17 2.4.18 2.5 MOTOROLA Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Organization of Data in Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Organization of Data in Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Register Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Register Direct Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Register Indirect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Register Indirect with Postincrement Mode. . . . . . . . . . . . Address Register Indirect with Predecrement Mode . . . . . . . . . . . . Address Register Indirect with Displacement Mode . . . . . . . . . . . . Address Register Indirect with Index (8-Bit Displacement) Mode . . Address Register Indirect with Index (Base Displacement) Mode. . Memory Indirect Postindexed Mode . . . . . . . . . . . . . . . . . . . . . . . . Memory Indirect Preindexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . Program Counter Indirect with Displacement Mode . . . . . . . . . . . . Program Counter Indirect with Index (8-Bit Displacement) Mode . . Program Counter Indirect with Index (Base Displacement) Mode. . Program Counter Memory Indirect Postindexed Mode . . . . . . . . . . Program Counter Memory Indirect Preindexed Mode . . . . . . . . . . . Absolute Short Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Long Addressing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . Immediate Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effective Address Encoding Summary . . . . . . . . . . . . . . . . . . . . . . . . MC68030 USER'S MANUAL 2-1 2-2 2-2 2-4 2-4 2-5 2-8 2-9 2-10 2-10 2-10 2-11 2-12 2-12 2-13 2-14 2-15 2-16 2-16 2-17 2-18 2-19 2-20 2-20 2-21 2-22 xxv TABLE OF CONTENTS (Continued) Paragraph Number 2.6 2.6.1 2.6.2 2.7 2.8 2.8.1 2.8.2 2.8.3 Page Number Title Programmers View of Addressing Modes. . . . . . . . . . . . . . . . . . . . . Addressing Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Addressing Mode Summary . . . . . . . . . . . . . . . . . . . . . . . M68000 Family Addressing Compatibility . . . . . . . . . . . . . . . . . . . . . Other Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Program Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2-25 2-31 2-36 2-36 2-36 2-38 2-39 Section 3 Instruction Set Summary 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.2.10 3.2.11 3.3 3.3.1 3.3.2 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integer Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Field Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Binary-coded Decimal Instructions . . . . . . . . . . . . . . . . . . . . . . . . . Program Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Management Unit Instructions. . . . . . . . . . . . . . . . . . . . . . Multiprocessor Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integer Condition Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conditional Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the CAS and CAS2 Instructions . . . . . . . . . . . . . . . . . . . . . . Nested Subroutine Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Field Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pipeline Synchronization with the Nop Instruction. . . . . . . . . . . . . . 3-1 3-2 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-13 3-14 3-15 3-17 3-18 3-25 3-25 3-30 3-31 3-32 Section 4 Processing States 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 xxvi Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supervisor Privilege Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Privilege Level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Changing Privilege Level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Space Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68030 USER'S MANUAL 4-2 4-2 4-3 4-4 4-5 4-6 MOTOROLA TABLE OF CONTENTS (Continued) Paragraph Number 4.3.1 4.3.2 Title Page Number Exception Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Exception Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Section 5 Signal Description 5.1 5.2 5.3 5.4 5.5 5.6 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9 5.7 5.7.1 5.7.2 5.7.3 5.7.4 5.8 5.8.1 5.8.2 5.8.3 5.9 5.9.1 5.9.2 5.9.3 5.10 5.10.1 5.10.2 5.10.3 5.11 5.11.1 5.11.2 5.11.3 5.11.4 MOTOROLA Signal Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Code Signals (FC0-FC2) . . . . . . . . . . . . . . . . . . . . . . . . . . Address Bus (A0-A31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Bus (D0-D31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Size Signals (SIZ0, SIZ1). . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operand Cycle Start (OCS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Cycle Start (ECS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read/Write (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read-Modify-Write Cycle (RMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Strobe (AS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Strobe (DS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Buffer Enable (DBEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transfer and Size Acknowledge (DSACK0, DSACK1) . . . . . . Synchronous Termination (STERM) . . . . . . . . . . . . . . . . . . . . . . . . Cache Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Inhibit Input (CIIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Inhibit Output (CIOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Burst Request (CBREQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Burst Acknowledge (CBACK). . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Priority Level Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Pending (IPEND). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autovector (AVEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Arbitration Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Request (BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Grant (BG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Grant Acknowledge (BGACK) . . . . . . . . . . . . . . . . . . . . . . . . . Bus Exception Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Halt (HALT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Error (BERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Emulator Support Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Disable (CDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMU Disable (MMUDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pipeline Refill (REFILL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Microsequencer Status (STATUS) . . . . . . . . . . . . . . . . . . . MC68030 USER'S MANUAL 5-2 5-4 5-4 5-4 5-4 5-5 5-5 5-5 5-5 5-5 5-5 5-6 5-6 5-6 5-6 5-7 5-7 5-7 5-7 5-7 5-8 5-8 5-8 5-8 5-8 5-8 5-9 5-9 5-9 5-9 5-9 5-9 5-10 5-10 5-10 5-10 5-10 xxvii TABLE OF CONTENTS (Continued) Paragraph Number 5.12 5.13 5.14 Page Number Title Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Section 6 On-Chip Cache Memories 6.1 6.1.1 6.1.2 6.1.2.1 6.1.2.2 6.1.3 6.1.3.1 6.1.3.2 6.2 6.3 6.3.1 6.3.1.1 6.3.1.2 6.3.1.3 6.3.1.4 6.3.1.5 6.3.1.6 6.3.1.7 6.3.1.8 6.3.1.9 6.3.1.10 6.3.1.11 6.3.2 On-Chip Cache Organization and Operation . . . . . . . . . . . . . . . . . . . Instruction Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read-Modify-Write Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Filling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Entry Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Mode Filling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Allocate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Burst Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clear Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clear Entry in Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Freeze Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Burst Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clear Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clear Entry in Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . Freeze Instruction Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable Instruction Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6-4 6-6 6-8 6-10 6-10 6-10 6-15 6-20 6-20 6-20 6-21 6-21 6-21 6-21 6-22 6-22 6-22 6-22 6-22 6-23 6-23 6-23 Section 7 Bus Operation 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.2 7.2.1 xxviii Bus Transfer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Buffer Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Cycle Termination Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transfer Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Bus Sizing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68030 USER'S MANUAL 7-1 7-3 7-4 7-4 7-5 7-5 7-5 7-5 7-6 7-6 MOTOROLA TABLE OF CONTENTS (Continued) Paragraph Number 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.4 7.4.1 7.4.1.1 7.4.1.2 7.4.1.3 7.4.2 7.4.3 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.6 7.7 7.7.1 7.7.2 7.7.3 7.7.4 7.8 Title Misaligned Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effects of Dynamic Bus Sizing and Operand Misalignment . . . . . . Address, Size, and Data Bus Relationships . . . . . . . . . . . . . . . . . . MC68030 versus MC68020 Dynamic Bus Sizing . . . . . . . . . . . . . . Cache Filling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Interactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Operation with DSACKx . . . . . . . . . . . . . . . . . . . . . . Synchronous Operation with STERM . . . . . . . . . . . . . . . . . . . . . . . Data Transfer Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Read-Modify-Write Cycle. . . . . . . . . . . . . . . . . . . . . Synchronous Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Read-Modify-Write Cycle. . . . . . . . . . . . . . . . . . . . . . Burst Operation Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Space Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Acknowledge Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Acknowledge Cycle -- Terminated Normally . . . . . . . . Autovector Interrupt Acknowledge Cycle . . . . . . . . . . . . . . . . . . . Spurious Interrupt Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpoint Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Communication Cycles . . . . . . . . . . . . . . . . . . . . . . . Bus Exception Control Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Retry Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Halt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double Bus Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Grant Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Arbitration Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Number 7-13 7-19 7-22 7-24 7-24 7-26 7-27 7-28 7-29 7-30 7-31 7-37 7-43 7-48 7-51 7-54 7-59 7-68 7-69 7-70 7-71 7-74 7-74 7-74 7-75 7-82 7-89 7-91 7-94 7-95 7-96 7-98 7-99 7-100 7-100 7-103 Section 8 Exception Processing 8.1 8.1.1 8.1.2 MOTOROLA Exception Processing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Reset Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 Bus Error Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 MC68030 USER'S MANUAL xxix TABLE OF CONTENTS (Continued) Paragraph Number 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 8.1.10 8.1.11 8.1.12 8.1.13 8.2 8.2.1 8.2.2 8.2.3 8.3 8.4 Page Number Title Address Error Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Trap Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Illegal Instruction and Unimplemented Instruction Exceptions . . . . Privilege Violation Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trace Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Format Error Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMU Configuration Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpoint Instruction Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Return from Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Fault Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Status Word (SSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Software to Complete the Bus Cycles. . . . . . . . . . . . . . . . . . Completing the Bus Cycles with Rte . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Stack Frame Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8-9 8-9 8-11 8-12 8-14 8-14 8-21 8-22 8-23 8-24 8-27 8-28 8-29 8-31 8-32 8-32 Section 9 Memory Management Unit 9.1 9.1.1 9.1.2 9.2 9.2.1 9.2.2 9.2.3 9.3 9.4 9.5 9.5.1 9.5.1.1 9.5.1.2 9.5.1.3 9.5.1.4 9.5.1.5 9.5.1.6 9.5.1.7 9.5.1.8 9.5.1.9 9.5.1.10 9.5.1.11 xxx Translation Table Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Translation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Translation Table Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Flow for Address Translation . . . . . . . . . . . . . . . . . . . . . . . Effect of RESET On MMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effect of MMUDIS On Address Translation . . . . . . . . . . . . . . . . . . . Transparent Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Translation Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Translation Table Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Descriptor Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Descriptor Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Root Pointer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short-Format Table Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . Long-Fomat Table Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . Short-Format Early Termination Page Descriptor . . . . . . . . . . . . Long-Format Early Termination Page Descriptor . . . . . . . . . . . . Short-Format Page Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . Long-Format Page Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . Short-Format Invalid Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . Long-Format Indirect Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . Short-Format Indirect Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . MC68030 USER'S MANUAL 9-6 9-8 9-10 9-13 9-13 9-15 9-15 9-16 9-17 9-20 9-20 9-20 9-23 9-24 9-24 9-25 9-25 9-26 9-26 9-26 9-27 9-27 MOTOROLA TABLE OF CONTENTS (Concluded) Paragraph Number 9.5.1.12 9.5.2 9.5.3 9.5.3.1 9.5.3.2 9.5.3.3 9.5.3.4 9.5.3.5 9.5.4 9.5.5 9.5.5.1 9.5.5.2 9.5.5.3 9.5.5.4 9.6 9.7 9.7.1 9.7.2 9.7.3 9.7.4 9.7.5 9.7.5.1 9.7.5.2 9.7.5.3 9.8 9.9 9.9.1 9.9.2 9.9.3 9.9.3.1 9.9.3.2 9.9.3.3 9.9.3.4 9.9.3.5 9.9.3.6 9.10 9.10.1 9.10.2 9.10.3 Page Number Title Long-Format Indirect Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . General Table Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Variations in Translation Table Structure . . . . . . . . . . . . . . . . . . . . Early Termination and Contiguous Memory. . . . . . . . . . . . . . . . . Indirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table Sharing Between Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . Paging of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Allocation of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . Detail of Table Search Operations . . . . . . . . . . . . . . . . . . . . . . . . . Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Code Lookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supervisor Translation Tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supervisor Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68030 and MC68851 Mmu Differences . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Root Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Translation Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transparent Translation Registers . . . . . . . . . . . . . . . . . . . . . . . . . MMU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Programming Considerations . . . . . . . . . . . . . . . . . . . . . . Register Side Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMU Status Register Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . MMU Configuration Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . Mmu Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining and Using Page Tables in An Operating System. . . . . . . . . Root Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Task Memory Map Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Impact of MMU Features On Table Definition . . . . . . . . . . . . . . . . . Number of Table Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initial Shift Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Early Termination Page Descriptors . . . . . . . . . . . . . . . . . . . . . . Indirect Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Unused Descriptor Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . An Example of Paging Implementation in an Operating System . . . . System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Allocation Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Error Handler Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28 9-28 9-33 9-33 9-34 9-37 9-37 9-40 9-40 9-43 9-45 9-48 9-48 9-48 9-51 9-52 9-52 9-54 9-57 9-59 9-61 9-61 9-61 9-62 9-63 9-65 9-65 9-66 9-68 9-68 9-69 9-70 9-70 9-71 9-71 9-72 9-72 9-78 9-82 Section 10 Coprocessor Interface Description xxxi MC68030 USER'S MANUAL MOTOROLA TABLE OF CONTENTS (Continued) Paragraph Number 10.1 10.1.1 10.1.2 10.1.3 10.1.4 10.1.4.1 10.1.4.2 10.1.4.3 10.2 10.2.1 10.2.1.1 10.2.1.2 10.2.2 10.2.2.1 10.2.2.1.1 10.2.2.1.2 10.2.2.2 10.2.2.2.1 10.2.2.2.2 10.2.2.3 10.2.2.3.1 10.2.2.3.2 10.2.2.4 10.2.2.4.1 10.2.2.4.2 10.2.3 10.2.3.1 10.2.3.2 10.2.3.2.1 10.2.3.2.2 10.2.3.2.3 10.2.3.2.4 10.2.3.3 10.2.3.3.1 10.2.3.3.2 10.2.3.4 10.2.3.4.1 10.2.3.4.2 10.3 10.3.1 10.3.2 10.3.3 xxxii Page Number Title Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Concurrent Operation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor-Coprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Interface Register Selection. . . . . . . . . . . . . . . . . . Coprocessor Instruction Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor General Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Conditional Instructions . . . . . . . . . . . . . . . . . . . . . . . Branch On Coprocessor Condition Instruction. . . . . . . . . . . . . . . Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set On Coprocessor Condition Instruction. . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Coprocessor Condition, Decrement and Branch Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trap On Coprocessor Condition. . . . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Save and Restore Instructions . . . . . . . . . . . . . . . . . . Coprocessor Internal State Frames . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Format Words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Empty/Reset Format Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . Not Ready Format Word.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Invalid Format Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Valid Format Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Context Save Instruction . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Context Restore Instruction. . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Interface Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . Response CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Save CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68030 USER'S MANUAL 10-1 10-2 10-3 10-4 10-5 10-5 10-6 10-8 10-9 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-15 10-15 10-16 10-17 10-17 10-18 10-18 10-18 10-19 10-20 10-20 10-22 10-22 10-23 10-23 10-24 10-24 10-24 10-25 10-27 10-27 10-28 10-29 10-29 10-30 10-30 MOTOROLA TABLE OF CONTENTS (Continued) Paragraph Number 10.3.4 10.3.5 10.3.6 10.3.7 10.3.8 10.3.9 10.3.10 10.3.11 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.4.7 10.4.8 10.4.9 10.4.10 10.4.11 10.4.12 10.4.13 10.4.14 10.4.15 10.4.16 10.4.17 10.4.18 10.4.19 10.4.20 10.5 10.5.1 10.5.1.1 10.5.1.2 10.5.1.3 10.5.1.4 10.5.1.5 10.5.2 10.5.2.1 10.5.2.2 10.5.2.3 10.5.2.4 10.5.2.5 MOTOROLA Title Restore CIR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Word CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command CIR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operand CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Select CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Address CIR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operand Address CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Response Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . ScanPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Response Primitive General Format . . . . . . . . . . . . . Busy Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Null Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supervisor Check Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Operation Word Primitive . . . . . . . . . . . . . . . . . . . . . . . . . Transfer from Instruction Stream Primitive . . . . . . . . . . . . . . . . . . . Evaluate and Transfer Effective Address Primitive . . . . . . . . . . . . . Evaluate Effective Address and Transfer Data Primitive. . . . . . . . . Write to Previously Evaluated Effective Address Primitive . . . . . . . Take Address and Transfer Data Primitive . . . . . . . . . . . . . . . . . . . Transfer to/from Top of Stack Primitive . . . . . . . . . . . . . . . . . . . . . . Transfer Single Main Processor Register Primitive . . . . . . . . . . . . . Transfer Main Processor Control Register Primitive . . . . . . . . . . . . Transfer Multiple Main Processor Registers Primitive. . . . . . . . . . . Transfer Multiple Coprocessor Registers Primitive . . . . . . . . . . . . . Transfer Status Register and ScanPC Primitive . . . . . . . . . . . . . . . Take Pre-Instruction Exception Primitive. . . . . . . . . . . . . . . . . . . . . Take Mid-Instruction Exception Primitive . . . . . . . . . . . . . . . . . . . . Take Post-Instruction Exception Primitive . . . . . . . . . . . . . . . . . . . . Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor-Detected Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor-Detected Protocol Violations . . . . . . . . . . . . . . . . . Coprocessor-Detected Illegal Command or Condition Words . . . Coprocessor Data-Processing Exceptions . . . . . . . . . . . . . . . . . Coprocessor System-Related Exceptions . . . . . . . . . . . . . . . . . . Format Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main-Processor-Detected Exceptions . . . . . . . . . . . . . . . . . . . . . . . Protocol Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-Line Emulator Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Privilege Violations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cpTRAPcc Instruction Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trace Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68030 USER'S MANUAL Page Number 10-31 10-31 10-31 10-31 10-32 10-32 10-33 10-33 10-33 10-34 10-35 10-36 10-37 10-40 10-40 10-41 10-42 10-43 10-46 10-48 10-49 10-50 10-50 10-52 10-52 10-55 10-56 10-58 10-60 10-61 10-61 10-62 10-63 10-63 10-64 10-64 10-65 10-65 10-68 10-69 10-69 10-70 xxxiii TABLE OF CONTENTS (Continued) Paragraph Number 10.5.2.6 10.5.2.7 10.5.2.8 10.5.3 10.6 Page Number Title Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Format Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address and Bus Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-71 10-71 10-72 10-72 10-72 Section 11 Instruction Execution Timing 11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.5.1 11.2.5.2 11.2.5.3 11.2.6 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.5 11.6 11.6.1 11.6.2 11.6.3 11.6.4 11.6.5 11.6.6 11.6.7 11.6.8 11.6.9 11.6.10 11.6.11 11.6.12 11.6.13 11.6.14 11.6.15 xxxiv Performance Tradeoffs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resource Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microsequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Pipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Controller Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Fetch Pending Buffer . . . . . . . . . . . . . . . . . . . . . . . . . Write Pending Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Micro Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Execution Timing Calculations . . . . . . . . . . . . . . . . . . . . . Instruction-Cache Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overlap and Best Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Average No-Cache Case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Actual Instruction-Cache-Case Execution Time Calculations . . . . . Effect of Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effect of Wait States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Timing Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fetch Effective Address (fea) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fetch Immediate Effective Address (fiea) . . . . . . . . . . . . . . . . . . . . Calculate Effective Address (cea) . . . . . . . . . . . . . . . . . . . . . . . . . . Calculate Immediate Effective Address (ciea). . . . . . . . . . . . . . . . . Jump Effective Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOVE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special-Purpose Move Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetical/Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . Immediate Arithmetical/Logical Instructions . . . . . . . . . . . . . . . . . . Binary-Coded Decimal and Extended Instructions . . . . . . . . . . . . . Single Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shift/Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Field Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . Conditional Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68030 USER'S MANUAL 11-1 11-2 11-2 11-2 11-4 11-4 11-4 11-5 11-5 11-5 11-6 11-6 11-6 11-7 11-8 11-11 11-16 11-18 11-24 11-26 11-28 11-30 11-32 11-35 11-37 11-39 11-40 11-42 11-43 11-44 11-45 11-46 11-47 11-48 MOTOROLA TABLE OF CONTENTS (Continued) Paragraph Number 11.6.16 11.6.17 11.6.18 11.7 11.7.1 11.7.2 11.8 11.9 Title Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception-Related Instructions and Operations . . . . . . . . . . . . . . . Save and Restore Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Translation Tree Search Timing. . . . . . . . . . . . . . . . . . . . . . MMU Effective Address Calculation . . . . . . . . . . . . . . . . . . . . . . . . MMU Instruction Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Arbitration Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Number 11-49 11-50 11-51 11-51 11-58 11-60 11-61 11-62 Section 12 Applications Information 12.1 12.1.1 12.1.2 12.1.3 12.2 12.3 12.4 12.4.1 12.4.2 12.5 12.5.1 12.5.2 12.5.3 12.6 12.6.1 12.6.2 12.7 12.7.1 12.7.2 12.8 Adapting the MC68030 to MC68020 Designs . . . . . . . . . . . . . . . . . . Signal Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Floating-Point Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Select Logic for the MC68030 . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Access Time Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Mode Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static RAM Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A Two-Clock Synchronous Memory Bank Using SRAMS . . . . . . . . A 2-1-1-1 Burst Mode Memory Bank Using SRAMS . . . . . . . . . . . . A 3-1-1-1 Burst Mode Memory Bank Using SRAMS . . . . . . . . . . . . External Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction-Only External Cache Implementations . . . . . . . . . . . . . Debugging Aids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status and Refill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-Time Instruction Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power and Ground Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-2 12-3 12-4 12-5 12-9 12-11 12-14 12-17 12-18 12-18 12-24 12-27 12-30 12-32 12-35 12-35 12-36 12-39 12-43 Section 13 Electrical Characteristics 13.1 13.2 MOTOROLA Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Thermal Characteristics -- PGA Package . . . . . . . . . . . . . . . . . . . . . 13-1 MC68030 USER'S MANUAL xxxv TABLE OF CONTENTS (Concluded) Paragraph Number Page Number Title Section 14 Ordering Information and Mechanical Data 14.1 14.2 14.3 14.4 Standard MC68030 Ordering Information . . . . . . . . . . . . . . . . . . . . . Pin Assignments -- Pin Grid Array (RC Suffix) . . . . . . . . . . . . . . . . . Pin Assignments -- Ceramic Surface Mount (FE Suffix) . . . . . . . . . . Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14-2 14-3 14-4 Appendix A M68000 Family Summary xxxvi MC68030 USER'S MANUAL MOTOROLA LIST OF ILLUSTRATIONS Figure Number Title Page Number 1-1 1-2 1-3 1-4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supervisor Programming Model Supplement. . . . . . . . . . . . . . . . . . . . . . . Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-6 1-7 1-8 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 Memory Operand Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Data Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effective Address Specification Formats . . . . . . . . . . . . . . . . . . . . . . . . . . Using SIZE in the Index Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Absolute Address with Indexes . . . . . . . . . . . . . . . . . . . . . . . . . . . . Addressing Array Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Indirect Absolute Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . Accessing an Item in a Structure Using a Pointer . . . . . . . . . . . . . . . . . . . Indirect Addressing, Suppressed Index Register . . . . . . . . . . . . . . . . . . . . Preindexed Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Postindexed Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preindexed Indirect Addressing with Outer Displacement . . . . . . . . . . . . . Postindexed Indirect Addressing with Outer Displacement . . . . . . . . . . . . M68000 Family Address Extension Words . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-7 2-8 2-23 2-25 2-26 2-27 2-28 2-28 2-29 2-29 2-30 2-30 2-31 2-37 3-1 3-2 3-3 3-4 3-5 Instruction Word General Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linked List Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linked List Deletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Doubly Linked List Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Doubly Linked List Deletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-26 3-27 3-29 3-30 4-1 General Exception Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 5-1 Functional Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 Internal Caches and the MC68030. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Instruction Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Data Cache Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No-Write-Allocation and Write-Allocation Mode Examples . . . . . . . . . . . . Single Entry Mode Operation -- 8-Bit Port . . . . . . . . . . . . . . . . . . . . . . . . Single Entry Mode Operation -- 16-Bit Port . . . . . . . . . . . . . . . . . . . . . . . Single Entry Mode Operation -- 32-Bit Port . . . . . . . . . . . . . . . . . . . . . . . Single Entry Mode Operation -- Misaligned Long Word and 8-Bit Port. . . Single Entry Mode Operation -- Misaligned Long Word and 16-Bit Port. . Single Entry Mode Operation -- Misaligned Long Word and 32-Bit DSACKx Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOTOROLA MC68030 USER'S MANUAL 6-2 6-5 6-7 6-9 6-11 6-12 6-12 6-13 6-14 6-15 xxxvii LIST OF ILLUSTRATIONS (Continued) Figure Number Page Number Title 6-11 6-12 6-13 6-14 6-15 Burst Operation Cycles and Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Filling Wraparound Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deferred Burst Filling Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6-17 6-18 6-21 6-23 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 Relationship between External and Internal Signals . . . . . . . . . . . . . . . . . Asynchronous Input Sample Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Operand Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68030 Interface to Various Port Sizes . . . . . . . . . . . . . . . . . . . . . . . . . Example of Long-Word Transfer to Word Port . . . . . . . . . . . . . . . . . . . . . . Long-Word Operand Write Timing (16-Bit Data Port) . . . . . . . . . . . . . . . . Example of Word Transfer to Byte Port . . . . . . . . . . . . . . . . . . . . . . . . . . . Word Operand Write Timing (8-Bit Data Port) . . . . . . . . . . . . . . . . . . . . . . Misaligned Long-Word Transfer to Word Port Example. . . . . . . . . . . . . . . Misaligned Long-Word Transfer to Word Port . . . . . . . . . . . . . . . . . . . . . . Misaligned Cachable Long-Word Transfer from Word Port Example . . . . Misaligned Word Transfer to Word Port Example . . . . . . . . . . . . . . . . . . . Misaligned Word Transfer to Word Port . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of Misaligned Cachable Word Transfer from Word Bus . . . . . . . Misaligned Long-Word Transfer to Long-Word Port. . . . . . . . . . . . . . . . . . Misaligned Write Cycles to Long-Word Port. . . . . . . . . . . . . . . . . . . . . . . . Misaligned Cachable Long-Word Transfer from Long-Word Bus. . . . . . . . Byte Data Select Generation for 16- and 32-Bit Ports . . . . . . . . . . . . . . . . Asynchronous Long-Word Read Cycle Flowchart . . . . . . . . . . . . . . . . . . . Asynchronous Byte Read Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Byte and Word Read Cycles -- 32-Bit Port . . . . . . . . . . . . Long-Word Read -- 8-Bit Port with CIOUT Asserted. . . . . . . . . . . . . . . . . Long-Word Read -- 16-Bit and 32-Bit Port . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Write Cycle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Read-Write-Read Cycles -- 32-Bit Port . . . . . . . . . . . . . . . Asynchronous Byte and Word Write Cycles -- 32-Bit Port . . . . . . . . . . . . Long-Word Operand Write -- 8-Bit Port. . . . . . . . . . . . . . . . . . . . . . . . . . . Long-Word Operand Write -- 16-Bit Port. . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Read-Modify-Write Cycle Flowchart . . . . . . . . . . . . . . . . . . Asynchronous Byte Read-Modify-Write Cycle -- 32-Bit Port (TAS Instruction with CIOUT or CIIN Asserted) . . . . . . . . . . . . . . . . . . . . . Synchronous Long-Word Read Cycle Flowchart -- No Burst Allowed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Read with CIIN Asserted and CBACK Negated . . . . . . . . . . Synchronous Write Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Write Cycle with Wait States -- CIOUT Asserted . . . . . . . . 7-2 7-3 7-8 7-9 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-17 7-18 7-20 7-20 7-21 7-22 7-25 7-32 7-32 7-33 7-34 7-35 7-37 7-38 7-39 7-40 7-41 7-44 7-31 7-32 7-33 7-34 xxxviii MC68030 USER'S MANUAL 7-45 7-49 7-50 7-52 7-53 MOTOROLA LIST OF ILLUSTRATIONS (Continued) Figure Number 7-35 7-36 7-37 7-38 Title Page Number 7-55 7-56 7-62 7-42 7-43 7-44 7-45 7-46 7-47 7-48 7-49 7-50 7-51 7-52 7-53 7-54 7-55 7-56 7-57 7-58 7-59 7-60 7-61 7-62 7-63 7-64 7-65 Synchronous Read-Modify-Write Cycle Flowchart. . . . . . . . . . . . . . . . . . . Synchronous Read-Modify-Write Cycle Timing -- CIIN Asserted . . . . . . . Burst Operation Flowchart -- Four Long Words Transferred. . . . . . . . . . . Long-Word Operand Request from $07 with Burst Request and Wait Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Long-Word Operand Request from $07 with Burst Request -- CBACK Negated Early. . . . . . . . . . . . . . . . . . . . . . . . . . Long-Word Operand Request from $0E -- Burst Fill Deferred . . . . . . . . . Long-Word Operand Request from $07 with Burst Request -- CBACK and CIIN Asserted . . . . . . . . . . . . . . . . . . . . . . MC68030 CPU Space Address Encoding . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Acknowledge Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autovector Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpoint Operation Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpoint Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpoint Acknowledge Cycle Timing (Exception Signaled) . . . . . . . . . . Bus Error without DSACKx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Late Bus Error with DSACKx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Late Bus Error with STERM -- Exception Taken. . . . . . . . . . . . . . . . . . . . Long-Word Operand Request -- Late BERR on Third Access . . . . . . . . . Long-Word Operand Request -- BERR on Second Access . . . . . . . . . . . Asynchronous Late Retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Late Retry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Late Retry Operation for a Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Halt Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Synchronization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Arbitration Flowchart for Single Request. . . . . . . . . . . . . . . . . . . . . . . Bus Arbitration Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Arbitration State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Wire Bus Arbitration Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . Bus Arbitration Operation (Bus Inactive) . . . . . . . . . . . . . . . . . . . . . . . . . . Initial Reset Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor-Generated Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-2 8-3 8-4 8-5 8-6 8-7 Reset Operation Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Pending Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Recognition Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assertion of IPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Exception Processing Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . Examples of Interrupt Recognition and Instruction Boundaries . . . . . . . . . Breakpoint Instruction Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8-15 8-17 8-18 8-19 8-20 8-23 7-39 7-40 7-41 MOTOROLA MC68030 USER'S MANUAL 7-63 7-64 7-65 7-66 7-69 7-71 7-72 7-73 7-75 7-76 7-77 7-84 7-85 7-86 7-87 7-88 7-90 7-91 7-92 7-93 7-96 7-98 7-99 7-101 7-103 7-104 7-105 7-106 xxxix LIST OF ILLUSTRATIONS (Continued) Figure Number Page Number Title 8-8 8-9 RTE Instruction for Throwaway Four-Word Frame . . . . . . . . . . . . . . . . . . 8-26 Special Status Word (SSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 MMU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Translation Table Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example Translation Table Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example Translation Tree Layout in Memory. . . . . . . . . . . . . . . . . . . . . . . Derivation of Table Index Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example Translation Tree Using Different Format Descriptors . . . . . . . . . Address Translation General Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . Root Pointer Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short-Format Table Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Long-Format Table Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short-Format Page Descriptor and Short-Format Early Termination Page Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Long-Format Early Termination Page Descriptor. . . . . . . . . . . . . . . . . . . . Long-Format Page Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short-Format Invalid Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Long-Format Invalid Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short-Format Indirect Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Long-Format Indirect Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified Table Search Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Five-Level Table Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example Translation Tree Using Contiguous Memory. . . . . . . . . . . . . . . . Example Translation Tree Using Indirect Descriptors . . . . . . . . . . . . . . . . Example Translation Tree Using Shared Tables . . . . . . . . . . . . . . . . . . . . Example Translation Tree with Nonresident Tables. . . . . . . . . . . . . . . . . . Detailed Flowchart of MMU Table Search Operation. . . . . . . . . . . . . . . . . Table Search Initialization Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATC Entry Creation Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limit Check Procedure Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Flowchart of Descriptor Fetch Operation . . . . . . . . . . . . . . . . . . . Logical Address Map Using Function Code Lookup . . . . . . . . . . . . . . . . . Example Translation Tree Using Function Code Lookup. . . . . . . . . . . . . . Example Translation Tree Structure for Two Tasks . . . . . . . . . . . . . . . . . . Exmple Logical Address Map with Shared Supervisor and User Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exmple Translation Tree Using S and WP Bits to Set Protection . . . . . . . Root Pointer Register (CRP, SRP) Format . . . . . . . . . . . . . . . . . . . . . . . . Translation Control Register (TC) Format . . . . . . . . . . . . . . . . . . . . . . . . . Transparent Translation Register (TT0 and TT1) Format . . . . . . . . . . . . . 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30 9-31 9-32 9-33 9-34 9-35 9-36 9-37 xl MC68030 USER'S MANUAL 9-3 9-4 9-5 9-7 9-8 9-9 9-12 9-14 9-23 9-24 9-24 9-25 9-25 9-26 9-26 9-27 9-27 9-28 9-29 9-31 9-35 9-36 9-38 9-39 9-41 9-42 9-42 9-43 9-44 9-45 9-46 9-47 9-49 9-50 9-54 9-54 9-57 MOTOROLA LIST OF ILLUSTRATIONS (Continued) Figure Number Title Page Number 9-38 9-39 9-40 MMU Status Register (MMUSR) Format . . . . . . . . . . . . . . . . . . . . . . . . . . 9-59 MMU Status Interpretation PTEST Level 0 . . . . . . . . . . . . . . . . . . . . . . . . 9-62 MMU Status Interpretation PTEST Level 7 . . . . . . . . . . . . . . . . . . . . . . . . 9-63 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 F-Line Coprocessor Instruction Operation Word . . . . . . . . . . . . . . . . . . . . Asynchronous Non-DMA M68000 Coprocessor Interface Signal Usage . . MC68030 CPU Space Address Encodings . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Address Map in MC68030 CPU Space. . . . . . . . . . . . . . . . . Coprocessor Interface Register Set Map . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor General Instruction Format (cpGEN) . . . . . . . . . . . . . . . . . . Coprocessor Interface Protocol for General Category Instructions . . . . . . Coprocessor Interface Protocol for Conditional Category Instructions. . . . Branch on Coprocessor Condition Instruction (cpBcc.W) . . . . . . . . . . . . . Branch On Coprocessor Condition Instruction (cpBcc.L). . . . . . . . . . . . . . Set On Coprocessor Condition (cpScc) . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Coprocessor Condition, Decrement and Branch Instruction Format (cpDBcc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trap On Coprocessor Condition (cpTRAPcc) . . . . . . . . . . . . . . . . . . . . . . Coprocessor State Frame Format in Memory . . . . . . . . . . . . . . . . . . . . . . Coprocessor Context Save Instruction Format (cpSAVE) . . . . . . . . . . . . . Coprocessor Context Save Instruction Protocol. . . . . . . . . . . . . . . . . . . . . Coprocessor Context Restore Instruction Format (cpRESTORE) . . . . . . . Coprocessor Context Restore Instruction Protocol . . . . . . . . . . . . . . . . . . Control CIR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition CIR Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operand Alignment for Operand CIR Accesses. . . . . . . . . . . . . . . . . . . . . Coprocessor Response Primitive Format. . . . . . . . . . . . . . . . . . . . . . . . . . Busy Primitive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Null Primitive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supervisor Check Primitive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Operation Word Primitive Format . . . . . . . . . . . . . . . . . . . . . . . . Transfer from Instruction Stream Primitive Format . . . . . . . . . . . . . . . . . . Evaluate and Transfer Effective Address Primitive Format . . . . . . . . . . . . Evaluate Effective Address and Transfer Data Primitive . . . . . . . . . . . . . . Write to Previously Evaluated EffectiveAddress Primitive Format . . . . . . . Take Address and Transfer Data Primitive Format . . . . . . . . . . . . . . . . . . Transfer To/From Top of Stack Primitive Format . . . . . . . . . . . . . . . . . . . . Transfer Single Main Processor Register Primitive Format . . . . . . . . . . . . Transfer Main Processor Control Register Primitive Format . . . . . . . . . . . Transfer Multiple Main Processor Registers Primitive Format . . . . . . . . . . Register Select Mask Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Multiple Coprocessor Registers Primitive Format . . . . . . . . . . . . 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-31 10-32 10-33 10-34 10-35 10-36 10-37 MOTOROLA MC68030 USER'S MANUAL 10-4 10-6 10-7 10-8 10-9 10-10 10-11 10-13 10-14 10-14 10-15 10-17 10-18 10-21 10-25 10-26 10-27 10-28 10-30 10-31 10-32 10-35 10-36 10-37 10-40 10-41 10-41 10-42 10-43 10-46 10-48 10-49 10-50 10-51 10-52 10-52 10-53 xli LIST OF ILLUSTRATIONS (Concluded) Figure Number Page Number Title 10-38 10-39 10-40 10-41 10-42 10-43 10-44 10-45 Operand Format in Memory for Transfer to --(An) . . . . . . . . . . . . . . . . . . Transfer Status Register and ScanPC Primitive Format . . . . . . . . . . . . . . Take Pre-Instruction Exception Primitive Format . . . . . . . . . . . . . . . . . . . . MC68030 Pre-Instruction Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . Take Mid-Instruction Exception Primitive Format. . . . . . . . . . . . . . . . . . . . MC68030 Mid-Instruction Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . Take Post-Instruction Exception Primitive Format . . . . . . . . . . . . . . . . . . . MC68030 Post-Instruction Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . 10-54 10-55 10-56 10-57 10-58 10-59 10-60 10-60 11-1 11-2 11-3 11-4 11-5 Block Diagram - Eight Independent Resources. . . . . . . . . . . . . . . . . . . . . Simultaneous Instruction Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Derivation of Instruction Overlap Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor Activity - Even Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor Activity - Odd Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11-7 11-8 11-9 11-10 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 Signal Routing for Adapting the MC68030 to MC68020 Designs . . . . . . . 32-Bit Data Bus Coprocessor Connection . . . . . . . . . . . . . . . . . . . . . . . . . Chip-Select Generation PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PAL Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Cycle Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example MC68030 Byte Select PAL System Configuration . . . . . . . . . . . MC68030 Byte Select PAL Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . Access Time Computation Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example Two-Clock Read, Three-Clock Write Memory Bank . . . . . . . . . . Example PAL Equations for Two-Clock Memory Bank . . . . . . . . . . . . . . . Additional Memory Enable Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example Two-Clock Read and Write Memory Bank . . . . . . . . . . . . . . . . . Example PAL Equation for Two-Clock Read and Write Memory Bank . . . Example 2-1-1-1 Burst Mode Memory Bank at 20 MHz, 256K Bytes . . . . Example 3-1-1-1 Pipelined Burst Mode Memory Bank at 20 MHz, 256K Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Memory Enable Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example MC68030 Hardware Configuration with External Physical Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example Early Termination Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . Normal Instruction Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trace or Interrupt Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor Halted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trace Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PAL Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12-6 12-8 12-8 12-9 12-12 12-13 12-15 12-19 12-20 12-21 12-22 12-23 12-25 12-16 12-17 12-18 12-19 12-20 12-21 12-22 12-23 12-24 12-25 xlii MC68030 USER'S MANUAL 12-28 12-29 12-33 12-34 12-37 12-38 12-38 12-39 12-41 12-44 12-45 MOTOROLA LIST OF TABLES Table Number Title Page Number 1-1 1-2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 2-1 IS-I/IS Memory Indirection Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 Data Movement Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Integer Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Logical Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Shift and Rotate Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Bit Manipulation Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Bit Field Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 BCD Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Program Control Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 System Control Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 MMU Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Multiprocessor Operations (Read-Modify-Write) . . . . . . . . . . . . . . . . . . . . 3-13 Condition Code Computations (Sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . 3-15 Conditional Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Instruction Set Summary (Sheet 1 of 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 4-1 Address Space Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 5-1 5-2 Signal Index (Sheet 1 of 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Signal Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 DSACK Codes and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Size Signal Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 Address OffsetEncodings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 Data Bus Requirements for Read Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 MC68030 Internal to External Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 Memory Alignment and Port Size Influence on Write Bus Cycles . . . . . . . 7-19 Data Bus Write Enable Signals for Byte, Word, and Long-Word Ports . . . 7-23 DSACK, BERR, and HALT Assertion Results . . . . . . . . . . . . . . . . . . . . . . 7-79 STERM, BERR, and HALT Assertion Results . . . . . . . . . . . . . . . . . . . . . . 7-81 8-1 8-2 8-3 8-4 8-5 8-6 Exception Vector Assignments (Sheet 2 of 2) . . . . . . . . . . . . . . . . . . . . . . 8-2 Exception Vector Assignments (Sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . 8-3 Microsequencer STATUS Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Tracing Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 Interrupt Levels and Mask Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 Exception Priority Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 MOTOROLA MC68030 USER'S MANUAL xliii LIST OF TABLES (Continued) Table Number Title Page Number 9-1 9-2 9-3 Size Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 Translation Tree Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30 MMUSR Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-60 10-1 10-2 10-3 10-4 10-5 10-6 cpTRAPcc Opmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 Coprocessor Format Word Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 Null Coprocessor Response Primitive Encodings . . . . . . . . . . . . . . . . . . . 10-39 Valid EffectiveAddress Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-43 Main Processor Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-51 Exceptions Related to Primitive Processing. . . . . . . . . . . . . . . . . . . . . . . . 10-66 12-1 12-2 12-3 Data Bus Activity for Byte, Word, and Long-Word Ports . . . . . . . . . . . . . . 12-11 Memory Access Time Equations at 20 MHz . . . . . . . . . . . . . . . . . . . . . . . 12-16 Calculated tAVDV Values for Operation at Frequencies Less Than or Equal to the CPU Maximum Frequency Rating . . . . . . . . . 12-17 Microsequencer STATUS Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36 List of Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42 AS and ECSC Indicates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43 VCC and GND Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-46 12-4 12-5 12-6 12-7 xliv MC68030 USER'S MANUAL MOTOROLA SECTION 1 INTRODUCTION The MC68030 is a second-generation full 32-bit enhanced microprocessor from Motorola. The MC68030 is a member of the M68000 Family of devices that combines a central processing unit (CPU) core, a data cache, an instruction cache, an enhanced bus controller, and a memory management unit (MMU) in a single VLSI device. The processor is designed to operate at clock speeds beyond 20 MHz. The MC68030 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes. The MC68030 is upward object code compatible with the earlier members of the M68000 Family and has the added features of an on-chip MMU, a data cache, and an improved bus interface. It retains the flexible coprocessor interface pioneered in the MC68020 and provides full IEEE floating-point support through this interface with the MC68881 or MC68882 floating-point coprocessor. Also, the internal functional blocks of this microprocessor are designed to operate in parallel, allowing instruction execution to be overlapped. In addition to instruction execution, the internal caches, the on-chip MMU, and the external bus controller all operate in parallel. The MC68030 fully supports the nonmultiplexed bus structure of the MC68020, with 32 bits of address and 32 bits of data. The MC68030 bus has an enhanced controller that supports both asynchronous and synchronous bus cycles and burst data transfers. It also supports the MC68020 dynamic bus sizing mechanism that automatically determines device port sizes on a cycle-by-cycle basis as the processor transfers operands to or from external devices. A block diagram of the MC68030 is shown in Figure 1-1. The instructions and data required by the processor are supplied from the internal caches whenever possible. The MMU translates the logical address generated by the processor into a physical address utilizing its address translation cache (ATC). The bus controller manages the transfer of data between the CPU and memory or devices at the physical address. MOTOROLA MC68030 USER'S MANUAL 1-1 1-2 ADDRESS BUS ADDRESS PADS MC68030 USER'S MANUAL ADDRESS BUS PREFETCH PENDING BUFFER BUS CONTROL SIGNALS MICROBUS CONTROLLER WRITE PENDING BUFFER BUS CONTROLLER ACCESS CONTROL UNIT ADDRESS INSTRUCTION ADDRESS BUS CONTROL LOGIC CONTROL STORE DATA ADDRESS BUS PROGRAM COUNTER SECTION STAGE C CACHE HOLDING REGISTER (CAHR) DATA CACHE MISALIGNMENT MULTIPLEXER DATA SECTION INSTRUCTION CACHE STAGE B INSTRUCTION PIPE ADDRESS SECTION STAGE D EXECUTION UNIT MICROSEQUENCER AND CONTROL SIZE MULTIPLEXER INTERNAL DATA BUS DATA PADS DATA BUS Introduction Figure 1-1. Block Diagram MOTOROLA Introduction 1.1 FEATURES The features of the MC68030 microprocessor are: * Object Code Compatible with the MC68020 and Earlier M68000 Microprocessors * Complete 32-Bit Nonmultiplexed Address and Data Buses * 16 32-Bit General-Purpose Data and Address Registers * Two 32-Bit Supervisor Stack Pointers and 10 Special-Purpose Control Registers * 256-Byte Instruction Cache and 256-Byte Data Cache Can Be Accessed Simultaneously * Paged MMU that Translates Addresses in Parallel with Instruction Execution and Internal Cache Accesses * Two Transparent Segments Allow Untranslated Access to Physical Memory To Be D fined for Systems That Transfer Large Blocks of Data between Predefined Physical Addresses -- e.g., Graphics Applications * Pipelined Architecture with Increased Parallelism Allows Accesses to Internal Caches To Occur in Parallel with Bus Transfers and Instruction Execution To Be Overlapped * Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum), Synchronous Bus Cycles (two clocks minimum), and Burst Data Transfers (one clock minimum) all to the Physical Address Space * Dynamic Bus Sizing Supports 8-, 16-, 32-Bit Memories and Peripherals * Support for Coprocessors with the M68000 Coprocessor Interface -- e.g., Full IEEE Floating-Point Support Provided by the MC68881/MC68882 Floating-Point Coprocessors * 4-Gbyte Logical and Physical Addressing Range * Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (HighDensity NMOS) Gates to be Combined for Maximum Speed, Low Power, and Optimum Die Size * Processor Speeds Beyond 20 MHz Both improved performance and increased functionality result from the on-chip implementation of the MMU and the data and instruction caches. The enhanced bus controller and the internal parallelism also provide increased system performance. Finally, the improved bus interface, the reduction in physical size, and the lower power consumption combine to reduce system costs and satisfy cost/performance goals of the system designer. MOTOROLA MC68030 USER'S MANUAL 1-3 Introduction 1.2 MC68030 EXTENSIONS TO THE M68000 FAMILY In addition to the on-chip instruction cache present in the MC68020, the MC68030 has an internal data cache. Data that is accessed during read cycles may be stored in the on-chip cache, where it is available for subsequent accesses. The data cache reduces the number of external bus cycles when the data operand required by an instruction is already in the data cache. Performance is enhanced further because the on-chip caches can be internally accessed in a single clock cycle. In addition, the bus controller provides a two-clock cycle synchronous mode and burst mode accesses that can transfer data in as little as one clock per long word. The MC68030 enhanced microprocessor contains an on-chip MMU that allows address translation to operate in parallel with the CPU core, the internal caches, and the bus controller. Additional signals support emulation and system analysis. External debug equipment can disable the on-chip caches and the MMU to freeze the MC68030 internal state during breakpoint processing. In addition, the MC68030 indicates: 1. The start of a refill of the instruction pipe 2. Instruction boundaries 3. Pending trace or interrupt processing 4. Exception processing 5. Halt conditions This status and control information allows external debugging equipment to trace the MC68030 activity and interact nonintrusively with the MC68030 to effectively reduce system debug effort. 1.3 PROGRAMMING MODEL The programming model of the MC68030 consists of two groups of registers: the user model and the supervisor model. This corresponds to the user and supervisor privilege levels. User programs executing at the user privilege level use the registers of the user model. System software executing at the supervisor level uses the control registers of the supervisor level to perform supervisor functions. 1-4 MC68030 USER'S MANUAL MOTOROLA Introduction Figure 1-2 shows the user programming model, consisting of 16 32-bit general-purpose registers and two control registers: * General-Purpose 32-Bit Registers (D0-D7, A0-A7) * 32-Bit Program Counter (PC) * 8-Bit Condition Code Register (CCR) The supervisor programming model consists of the registers available to the user plus 14 control registers: * Two 32-Bit Supervisor Stack Pointers (ISP and MSP) * 16-Bit Status Register (SR) * 32-Bit Vector Base Register (VBR) * 32-Bit Alternate Function Code Registers (SFC and DFC) * 32-Bit Cache Control Register (CACR) * 32-Bit Cache Address Register (CAAR) * 64-Bit CPU Root Pointer (CRP) * 64-Bit Supervisor Root Pointer (SRP) * 32-Bit Translation Control Register (TC) * 32-Bit Transparent Translation Registers (TT0 and TT1) * 16-Bit MMU Status Register (MMUSR) The user programming model remains unchanged from previous M68000 Family microprocessors. The supervisor programming model supplements the user programming model and is used exclusively by the MC68030 system programmers who utilize the supervisor privilege level to implement sensitive operating system functions, I/O control, and memory management subsystems. The supervisor programming model contains all the controls to access and enable the special features of the MC68030. This segregation was carefully planned so that all application software is written to run at the nonprivileged user level and migrates to the MC68030 from any M68000 platform without modification. Since system software is usually modified by system programmers when ported to a new design, the control features are properly placed in the supervisor programming model. For example, the transparent translation feature of the MC68030 is new to the family supervisor programming model for the MC68030 and the two translation registers are new additions to the family supervisor programming model for the MC68030. Only supervisor code uses this feature, and user application programs remain unaffected. MOTOROLA MC68030 USER'S MANUAL 1-5 Introduction Registers D0-D7 are used as data registers for bit and bit field (1 to 32 bits), byte (8 bit), word (16 bit), long-word (32 bit), and quad-word (64 bit) operations. Registers A0-A6 and the user, interrupt, and master stack pointers are address registers that may be used as software stack pointers or base address registers. Register A7 (shown as A7' and A7'' in Figure 1-3) is a register designation that applies to the user stack pointer in the user privilege level and to either the interrupt or master stack pointer in the supervisor privilege level. In the supervisor privilege level, the active stack pointer (interrupt or master) is called the supervisor stack pointer (SSP). In addition, the address registers may be used for word and long-word operations. All of the 16 general-purpose registers (D0-D7, A0-A7) may be used as index registers. 31 16 15 8 7 0 D0 D1 D2 D3 D4 DATA REGISTERS D5 D6 D7 31 16 15 0 A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 31 16 15 0 31 A7 (USP) USER STACK POINTER PC PROGRAM COUNTER CCR CONDITION CODE REGISTER 0 15 7 0 Figure 1-2. User Programming Model 1-6 MC68030 USER'S MANUAL MOTOROLA Introduction The program counter (PC) contains the address of the next instruction to be executed by the MC68030. During instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC, as appropriate. 31 31 0 16 15 INTERRUPT STACK POINTER A7" (MSP) MASTER STACK POINTER SR STATUS REGISTER VBR VECTOR BASE REGISTER 0 16 15 15 A7' (ISP) 8 7 0 (CCR) 0 31 0 31 SFC DFC 31 ALTERNATE FUNCTION CODE REGISTERS 0 31 CACR CACHE CONTROL REGISTER CAAR CACHE ADDRESS REGISTER 0 31 0 AC0 31 0 AC1 15 0 ACUSR ACCESS CONTROL REGISTER 0 ACCESS CONTROL REGISTER 1 ACU STATUS REGISTER Figure 1-3. Supervisor Programming Model Supplement The status register, SR, (see Figure 1-4) stores the processor status. It contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. The condition codes are extend (X), negative (N), zero (Z), overflow (V), and carry (C). The user byte containing the condition codes is the only portion of the status register information available in the user privilege level, and it is referenced as the CCR in user programs. In the supervisor privilege level, software can access the full status register, including the interrupt priority mask (three bits) as well as additional control bits. These bits indicate whether the processor is in: 1. One of two trace modes (T1, T0) 2. Supervisor or user privilege level (S) 3. Master or interrupt mode (M) The vector base register (VBR) contains the base address of the exception vector table in memory. The displacement of an exception vector is added to the value in this register to access the vector table. MOTOROLA MC68030 USER'S MANUAL 1-7 Introduction Alternate function code registers, SFC and DFC, contain 3-bit function codes. Function codes can be considered extensions of the 32-bit linear address that optionally provide as many as eight 4-Gbyte address spaces. Function codes are automatically generated by the processor to select address spaces for data and program at the user and supervisor privilege levels and a CPU address space for processor functions (e.g., coprocessor communications). Registers SFC and DFC are used by certain instructions to explicitly specify the function codes for operations. USER BYTE (CONDITION CODE REGISTER) SYSTEM BYTE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T1 T0 S M 0 I2 I1 I0 0 0 0 X N Z V C TRACE ENABLE INTERRUPT PRIORITY MASK CARRY OVERFLOW SUPERVISOR/USER STATE ZERO NEGATIVE MASTER/INTERRUPT STATE EXTEND Figure 1-4. Status Register The cache control register (CACR) controls the on-chip instruction and data caches of the MC68030. The cache address register (CAAR) stores an address for cache control functions. The CPU root pointer (CRP) contains a pointer to the root of the translation tree for the currently executing task of the MC68030. This tree contains the mapping information for the task's address space. When the MC68030 is configured to provide a separate address space for supervisor routines, the supervisor root pointer (SRP) contains a pointer to the root of the translation tree describing the supervisor's address space. The translation control register (TC) consists of several fields that control address translation. These fields enable and disable address translation, enable and disable the use of SRP for the supervisor address space, and select or ignore the function codes in translating addresses. Other fields define the size of memory pages, the number of address bits used in translation, and the translation table structure. The transparent translation registers, TT0 and TT1, can each specify separate blocks of memory as directly accessible without address translation. Logical addresses in these areas become the physical addresses for memory access. Function codes and the eight most significant bits of the address can be used to define the area of memory and type of access; either read, write, or both types of memory access can be directly mapped. The transparent translation feature allows rapid movement of large blocks of data in memory or I/O space without disturbing the context of the on-chip address translation cache or incurring delays associated with translation table lookups. This feature is useful to graphics, controller, and real-time applications. 1-8 MC68030 USER'S MANUAL MOTOROLA Introduction The MMU status register (MMUSR) contains memory management status information resulting from a search of the address translation cache or the translation tree for a particular logical address. 1.4 DATA TYPES AND ADDRESSING MODES Seven basic data types are supported: 1. Bits 2. Bit Fields (Fields of consecutive bits, 1-32 bits long) 3. BCD Digits (Packed: 2 digits/byte, Unpacked: 1 digit/byte) 4. Byte Integers (8 bits) 5. Word Integers (16 bits) 6. Long-Word Integers (32 bits) 7. Quad-Word Integers (64 bits) In addition, the instruction set supports operations on other data types such as memory addresses. The coprocessor mechanism allows direct support of floating-point operations with the MC68881 and MC68882 floating-point coprocessors as well as specialized userdefined data types and functions. The 18 addressing modes, shown in Table 1-1, include nine basic types: 1. Register Direct 2. Register Indirect 3. Register Indirect with Index 4. Memory Indirect 5. Program Counter Indirect with Displacement 6. Program Counter Indirect with Index 7. Program Counter Memory Indirect 8. Absolute 9. Immediate The register indirect addressing modes can also postincrement, predecrement, offset, and index addresses. The program counter relative mode also has index and offset capabilities. As in the MC68020, both modes are extended to provide indirect reference through memory. In addition to these addressing modes, many instructions implicitly specify the use of the condition code register, stack pointer, and/or program counter. 1.5 INSTRUCTION SET OVERVIEW The instructions in the MC68030 instruction set are listed in Table 1-2. The instruction set has been tailored to support structured high-level languages and sophisticated operating systems. Many instructions operate on bytes, words, or long words, and most instructions can use any of the 18 addressing modes. MOTOROLA MC68030 USER'S MANUAL 1-9 Introduction Table 1-1. Addressing Modes Addressing Modes Register Direct Data Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement Syntax Dn An (An) (An) -(An) (d16,An) Register Indirect with Index (d8,An,Xn) Address Register Indirect with Index (8-BitDisplacement) Address Register Indirect with Index (Base Displacement) (bd,An,Xn) Memory Indirect Memory Indirect Postindexed ([bd,An],Xn,od) Memory Indirect Preindexed ([bd,An,Xn],od) (d16,PC) Program Counter Indirect with Displacement Program Cou nter Indirect with IndexPC Indirect with Index (8-Bit (d8,PC,Xn) Displacement) (bd,PC,Xn) PC Indirect with Index (Base Displacement) Program Counter Memory Indirect PC Memory Indirect Postindexed ([bd,PC],Xn,od) PC Memory Indirect Preindexed ([bd,PC,Xn],od) Absolute Absolute Short (xxx).W Absolute Long (xxx).L Immediate #(data) 1-10 NOTES: Dn An 8, d16 = = = Xn = bd od = = PC (data) () [] = = = = Data Register, D0-D7 Address Register, A0-A7 A twos-complement or sign-extended displacement; added as part of the effective address calculation; size is 8 (d8) or 16 (d16) bits; when omitted, assemblers use a value of zero. Address or data register used as an index register; form is Xn.SIZE*SCALE, where SIZE is .W or .L indicates index register size) and SCALE is 1, 2, 4, or 8 (index register is multiplied by SCALE); use of SIZE and/or SCALE is optional. A twos-complement base displacement;when present, size can be 16 or 32 bits. Outer displacement, added as part of effective address calculation after any memory indirection; use is optional with asize of 16 or 32 bits. Program Counter Immediate value of 8, 16, or 32 bits Effective Address Use as indirect access to long-word address. MC68030 USER'S MANUAL MOTOROLA Introduction 1.6 VIRTUAL MEMORY AND VIRTUAL MACHINE CONCEPTS The full addressing range of the MC68030 is 4 Gbytes (4,294,967,296 bytes) in each of eight address spaces. Even though most systems implement a smaller physical memory, the system can be made to appear to have a full 4 Gbytes of memory available to each user program by using virtual memory techniques. In a virtual memory system, a user program can be written as if it has a large amount of memory available, when the physical memory actually present is much smaller. Similarly, a system can be designed to allow user programs to access devices that are not physically present in the system, such as tape drives, disk drives, printers, terminals, and so forth. With proper software emulation, a physical system can appear to be any other M68000 computer system to a user program, and the program can be given full access to all of the resources of that emulated system. Such an emulated system is called a virtual machine. 1.6.1 Virtual Memory A system that supports virtual memory has a limited amount of high-speed physical memory that can be accessed directly by the processor and maintains an image of a much larger virtual memory on a secondary storage device such as a large-capacity disk drive. When the processor attempts to access a location in the virtual memory map that is not resident in physical memory, a page fault occurs. The access to that location is temporarily suspended while the necessary data is fetched from secondary storage and placed in physical memory. The suspended access is then either restarted or continued. The MC68030 uses instruction continuation to support virtual memory. When a bus cycle is terminated with a bus error, the microprocessor suspends the current instruction and executes the virtual memory bus error handler. When the bus error handler has completed execution, it returns control to the program that was executing when the error was detected, reruns the faulted bus cycle (when required), and continues the suspended instruction. MOTOROLA MC68030 USER'S MANUAL 1-11 Introduction Table 1-2. Instruction Set Mnemonic ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ASL, ASR Bcc BCHG BCLR BFCHG BFCLR BFEXTS BFEXTU BFFO BFINS BFSET BFTST BKPT BRA BSET BSR BTST CAS CAS 2 CHK CHK2 CLR CMP CMPA CMPI CMPM CMP2 DBcc DIVS, DIVSL DIVU, DIVUL EOR EORI EXG EXT, EXTB ILLEGAL JMP JSR LEA LINK LSL, LSR MOVE MOVEA MOVE CCR MOVE SR 1-12 Description Add Decimal with Extend Add Add Address Add Immediate Add Quick Add with Extend Logical AND Logical AND Immediate Arithmatic Shift Left and Right Branch Conditionally Test Bit and Change Test Bit and Clear Test Bit Feild and Change Test Bit Feild and Clear Signed Bit Feild Extract Unsigned Bit Feild Extract Bit Feild Find First One Bit Feild Insert Test Bit Feild and Set Test Bit Feild Breakpoint Branch Test Bit and Set Branch to Subroutine Test Bit Compare and Swap Operands Compare and Swap Dual Operands Check Register Against Bound Check Register Against Upper and Lower Bounds Clear Compare Compare Address Compare Immediate Compare Memory to Memory Compare Registre Against Upper and Lower Bounds Test Condition, Decrement and Branch Signed Divide Unsigned Divide Logical Exclusive OR Logical Exclusive OR Immediate Exchange Registers Sign Extend Take Illegal Instruction Trap Jump Jump to Subroutine Load Effective Address Link and Allocate Logical Shift Left and Right Move Move Address Move Condition Code Register Move Status Register Mnemonic MOVE USP MOVEC MOVEM MOVEP MOVEQ MOVES MULS MULU NBCD NEG NEGX NOP NOT OR ORI ORI CCR ORI SR PACK PEA PFLUSH PFLUSHA PLOADR, PLOADW PMOVE PMOVEFD Description Move User Stack Pointer Move Control Register Move Multiple Registers Move Periphral Move Quick Move Alternate Address Space Signed Multiply Unsigned Multiply Negate Decimal with Extend Negate Negate with Extend No Operation Logical Compliment Logical Inclusive OR Logical Inclusive OR Immediate Logical Inclusive OR Immediate to Condition Codes Logical Inclusive OR Immediate to Status Register Pack BCD Push Effective Address Flush Entry(ies) in the ATC Flush All Entries in the ATC Load Entry into the ATC Move to-from MMU Registers Move to-from MMU Registers with Flush Disable Test a Logical Address PTESTR PTESTW RESET ROL, ROR ROXL, ROXR RTD RTE RTR RTS SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TRAP TRAPcc TRAPV TST Reset External Devices Rotate Left and Right Rotate With Extend Left and Right Return and Deallocate Return from Exception Return and Restore Codes Return from Subroutine Subtract Decimal With Extend Set Conditionally Stop Subtract Subtract Immediate Subtract Quick Subtract with Extend Swap Register Words Test Operand and Set Trap Trap Conditionally Trap on Overflow Test on Overflow Test Operand UNLK UNPK Unlink Unpack BCD MC68030 USER'S MANUAL MOTOROLA Introduction Mnemonic cpBcc cpDBcc cpGEN Description Branch Conditionally Test Coprocessor Condition, Decrement and Branch Coprocessor General Instruction Mnemonic cpRESTORE cpSAVE cpScc cpTRAPcc Description Restore Internal State of Coprocessor Save Internal State of Coprocessor Set Conditionally Trap Conditionally 1.6.2 Virtual Machine A typical use for a virtual machine system is the development of software, such as an operating system, for a new machine also under development and not yet available for programming use. In a virtual machine system, a governing operating system emulates the hardware of the new machine and allows the new software to be executed and debugged as though it were running on the new hardware. Since the new software is controlled by the governing operating system, it is executed at a lower privilege level than the governing operating system. Thus, any attempts by the new software to use virtual resources that are not physically present (and should be emulated) are trapped to the governing operating system and performed by its software. In the MC68030 implementation of a virtual machine, the virtual application runs at the user privilege level. The governing operating system executes at the supervisor privilege level and any attempt by the new operating system to access supervisor resources or execute privileged instructions causes a trap to the governing operating system. Instruction continuation is used to support virtual I/O devices in memory-mapped input/ output systems. Control and data registers for the virtual device are simulated in the memory map. An access to a virtual register causes a fault and the function of the register is emulated by software. MOTOROLA MC68030 USER'S MANUAL 1-13 Introduction 1.7 THE MEMORY MANAGEMENT UNIT The MMU supports virtual memory systems by translating logical addresses to physical addresses using translation tables stored in memory. The MMU stores address mappings in an address translation cache (ATC) that contains the most recently used translations. When the ATC contains the address for a bus cycle requested by the CPU, a translation table search is not performed. Features of the MMU include: * Multiple Level Translation Tables with Short- and Long-Format Descriptors for Efficient Table Space Usage * Table Searches Automatically Performed in Microcode * 22-Entry Fully Associative ATC * Address Translations and Internal Instruction and Data Cache Accesses Performed in Parallel * Eight Page Sizes Available Ranging from 256 to 32K Bytes * Two Optional Transparent Blocks * User and Supervisor Root Pointer Registers * Write Protection and Supervisor Protection Attributes * Translations Enabled/Disabled by Software * Translations Can Be Disabled with External MMUDIS Signal * Used and Modified Bits Automatically Maintained in Tables and ATC * Cache Inhibit Output (CIOUT) Signal Can Be Asserted on a Page-by-Page Basis * 32-Bit Internal Logical Address with Capability To Ignore as many as 15 Upper Address Bits * 3-Bit Function Code Supports Separate Address Spaces * 32-Bit Physical Address The memory management function performed by the MMU is called demand paged memory management. Since a task specifies the areas of memory it requires as it executes, memory allocation is supported on a demand basis. If a requested access to memory is not currently mapped by the system, then the access causes a demand for the operating system to load or allocate the required memory image. The technique used by the MC68030 is paged memory management because physical memory is managed in blocks of a specified number of bytes, called page frames. The logical address space is divided into fixed-size pages that contain the same number of bytes as the page frames. Memory management assigns a physical base address to a logical page. The system software then transfers data between secondary storage and memory one or more pages at a time. 1-14 MC68030 USER'S MANUAL MOTOROLA Introduction 1.8 PIPELINED ARCHITECTURE The MC68030 uses a three-stage pipelined internal architecture to provide for optimum instruction throughput. The pipeline allows as many as three words of a single instruction or three consecutive instructions to be decoded concurrently. 1.9 THE CACHE MEMORIES Due to locality of reference, instructions and data that are used in a program have a high probability of being reused within a short time. Additionally, instructions and data operands that reside in proximity to the instructions and data currently in use also have a high probability of being utilized within a short period. To exploit these locality characteristics, the MC68030 contains two on-chip logical caches, a data cache, and an instruction cache. Each of the caches stores 256 bytes of information, organized as 16 entries, each containing a block of four long words (16 bytes). The processor fills the cache entries either one long word at a time or, during burst mode accesses, four long words consecutively. The burst mode of operation not only fills the cache efficiently but also captures adjacent instruction or data items that are likely to be required in the near future due to locality characteristics of the executing task. The caches improve the overall performance of the system by reducing the number of bus cycles required by the processor to fetch information from memory and by increasing the bus bandwidth available for other bus masters in the system. Addition of the data cache in the MC68030 extends the benefits of cache techniques to all memory accesses. During a write cycle, the data cache circuitry writes data to a cached data item as well as to the item in memory, maintaining consistency between data in the cache and that in memory. However, writing data that is not in the cache may or may not cause the data item to be stored in the cache, depending on the write allocation policy selected in the cache control register (CACR). MOTOROLA MC68030 USER'S MANUAL 1-15 SECTION 2 DATA ORGANIZATION AND ADDRESSING CAPABILITIES Most external references to memory by a microprocessor are either program references or data references; they either access instruction words or operands (data items) for an instruction. Program references are references to the program space, the section of memory that contains the program instructions and any immediate data operands that reside in the instruction stream. Refer to M68000PM/AD, M68000 Programmer's Reference Manual, for descriptions of the instructions in the program space. Data references refer to the data space, the section of memory that contains the program data. Data items in the instruction stream can be accessed with the program counter relative addressing modes, and these accesses are classified as program references. A third type of external reference used for coprocessor communications, interrupt acknowledge cycles, and breakpoint acknowledge cycles is classified as a CPU space reference. The MC68030 automatically sets the function codes to access the program space, the data space, or the CPU space for special functions as required. The function codes can be used by the memory management unit to organize separate program (read only) and data (read-write) memory areas. This section describes the data organization and addressing capabilities of the MC68030. It lists the types of operands used by instructions and describes the registers and their use as operands. Next, the section describes the organization of data in memory and the addressing modes available to access data in memory. Last, the section describes the system stack and user program stacks and queues. 2.1 INSTRUCTION OPERANDS The MC68030 supports a general-purpose set of operands to serve the requirements of a large range of applications. Operands of MC68030 instructions may reside in registers, in memory, or within the instructions themselves. An instruction operand might also reside in a coprocessor. An operand may be a single bit, a bit field of from 1 to 32 bits in length, a byte (8 bits), a word (16 bits), a long word (32 bits), or a quad word (64 bits). The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation. Coprocessors are designed to support special computation models that require very specific but widely varying data operand types and sizes. Hence, coprocessor instructions can specify operands of any size. MOTOROLA MC68030 USER'S MANUAL 2-1 Data Organization and Addressing Capabilities 2.2 ORGANIZATION OF DATA IN REGISTERS The eight data registers can store data operands of 1, 8, 16, 32, and 64 bits, addresses of 16 or 32 bits, or bit fields of 1 to 32 bits. The seven address registers and the three stack pointers are used for address operands of 16 or 32 bits. The control registers (SR, VBR, SFC, DFC, CACR, CAAR, CRP, SRP, TC, TT0, TT1, and MMUSR) vary in size according to function. Coprocessors may define unique operand sizes and support them with on-chip registers accordingly. 2.2.1 Data Registers Each data register is 32 bits wide. Byte operands occupy the low-order 8 bits, word operands the low-order 16 bits, and long-word operands the entire 32 bits. When a data register is used as either a source or destination operand, only the appropriate low-order byte or word (in byte or word operations, respectively) is used or changed; the remaining high-order portion is neither used nor changed. The least significant bit of a long-word integer is addressed as bit zero, and the most significant bit is addressed as bit 31. For bit fields, the most significant bit is addressed as bit zero, and the least significant bit is addressed as the width of the field minus one. If the width of the field plus the offset is greater than 32, the bit field wraps around within the register. The following illustration shows the organization of various types of data in the data registers. Quad-word data consists of two long words; for example, the product of 32-bit multiply or the quotient of 32-bit divide operations (signed and unsigned). Quad words may be organized in any two data registers without restrictions on order or pairing. There are no explicit instructions for the managment of this data type, although the MOVEM instruction can be used to move a quad word into or out of the registers. Binary-coded decimal (BCD) data represents decimal numbers in binary form. Although many BCD codes have been devised, the BCD instructions of the M68000 Family support formats which the four least significant bits consist of a binary number having the numeric value of the corresponding decimal number. Two BCD formats are used. In the unpacked BCD format, a byte contains one digit; the four least significant bits contain the binary value and the four most significant bits are undefined. Each byte of the packed BCD format contains two digits; the least significant four bits contain the least significant digit. 2-2 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities Bit (0 Modulo (Offset)<31, Offset of 0 = MSB) 31 30 29 1 *** MSB 0 LSB Byte 31 24 High-Order Byte 23 16 15 Middle-High Byte 8 7 Middle-Low Byte 0 Low-Order Byte 16-Bit Word 31 16 15 0 High-Order Word Low-Order Word Long Word 31 0 Long Word Quad Word 63 62 32 MSB Any Dx 31 0 Offset MSB *** LSB Bit Field (0 Offset<32, 0<Width 32) 31 0 Long Word Note: If width + offset < 32, bit filed wraps around within the register. Unpacked BCD (a = MSB) 31 8 7 6 5 4 3 2 1 0 x x x x a b c d 7 6 5 4 3 2 1 0 a b c d e f g h Packed BCD (a = MSB First Digit, e = MSB Second Digit) 31 8 Data Organization in Data Registers MOTOROLA MC68030 USER'S MANUAL 2-3 Data Organization and Addressing Capabilities 2.2.2 Address Registers Each address register and stack pointer is 32 bits wide and holds a 32-bit address. Address registers cannot be used for byte-sized operands. Therefore, when an address register is used as a source operand, either the low-order word or the entire long-word operand is used, depending upon the operation size. When an address register is used as the destination operand, the entire register is affected, regardless of the operation size. If the source operand is a word size, it is first sign-extended to 32 bits and then used in the operation to an address register destination. Address registers are used primarily for addresses and to support address computation. The instruction set includes instructions that add to, subtract from, compare, and move the contents of address registers. The following example shows the organization of addresses in address registers. 31 16 Sign-Extended 15 16-Bit Address Operand 31 0 0 Full 32-Bit Address Operand Address Organization in Address Registers 2.2.3 Control Registers The control registers described in this section contain control information for supervisor functions and vary in size. With the exception of the user portion of the status register (CCR), they are accessed only by instructions at the supervisor privilege level. The status register (SR), shown in Figure 1-4, is 16 bits wide. Only 12 bits of the status register are defined; all undefined values are reserved by Motorola for future definition. The undefined bits are read as zeros and should be written as zeros for future compatibility. The lower byte of the status register is the CCR. Operations to the CCR can be performed at the supervisor or user privilege level. All operations to the status register and CCR are wordsized operations, but for all CCR operations, the upper byte is read as all zeros and is ignored when written, regardless of privilege level. 2-4 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities The supervisor programming model (see Figure 1-3) shows the control registers. The cache control register (CACR) provides control and status information for the on-chip instruction and data caches. The cache address register (CAAR) contains the address for cache control functions. The vector base register (VBR) provides the base address of the exception vector table. All operations involving the CACR, CAAR, and VBR are long-word operations, whether these registers are used as the source or the destination operand. The alternate function code registers (SFC and DFC) are 32-bit registers with only bits 2:0 implemented that contain the address space values (FC0-FC2) for the read or write operands of MOVES, PLOAD, PFLUSH, and PTEST instructions. The MOVEC instruction is used to transfer values to and from the alternate function code registers. These are long-word transfers; the upper 29 bits are read as zeros and are ignored when written. The remaining control registers in the supervisor programming model are used by the memory management unit (MMU). The CPU root pointer (CRP) and supervisor root pointer (SRP) contain pointers to the user and supervisor address translation trees. Transfers of data to and from these 64-bit registers are quad-word transfers. The translation control register (TC) contains control information for the MMU. The MC68030 always uses longword transfers to access this 32-bit register. The transparent translation registers (TT0 and TT1) also contain 32 bits each; they identify memory areas for direct addressing without address translation. Data transfers to and from these registers are long-word transfers. The MMU status register (MMUSR) stores the status of the MMU after execution of a PTEST instruction. It is a 16-bit register, and transfers to and from the MMUSR are word transfers. Refer to Section 9 Memory Management Unit for more detail. 2.3 ORGANIZATION OF DATA IN MEMORY Memory is organized on a byte-addressable basis where lower addresses correspond to higher order bytes. The address, N, of a long-word data item corresponds to the address of the most significant byte of the highest order word. The lower order word is located at address N + 2, leaving the least significant byte at address N + 3 (refer to Figure 2-1). Notice that the MC68030 does not require data to be aligned on word boundaries (refer to Figure 2-2), but the most efficient data transfers occur when data is aligned on the same byte boundary as its operand size. However, instruction words must be aligned on word boundaries. MOTOROLA MC68030 USER'S MANUAL 2-5 Data Organization and Addressing Capabilities The data types supported in memory by the MC68030 are bit and bit field data; integer data of 8, 16, or 32 bits; 32-bit addresses; and BCD data (packed and unpacked). These data types are organized in memory as shown in Figure 2-2. Note that all of these data types can be accessed at any byte address. Coprocessors can implement any data types and lengths up to 255 bytes. For example, the MC68881/MC68882 floating-point coprocessors support memory accesses for quad-wordsized items (double-precision floating-point values). Figure 2A bit operand is specified by a base address that selects one byte in memory (the base byte) and a bit number that selects the one bit in this byte. The most significant bit of the byte is bit 7. 31 23 15 7 0 LONG WORD $00000000 WORD $00000000 BYTE $00000000 WORD $00000002 BYTE $00000001 BYTE $00000002 BYTE $00000003 LONG WORD $00000004 WORD $00000004 BYTE $00000004 WORD $00000006 BYTE $00000005 BYTE $00000006 BYTE $00000007 LONG WORD $FFFFFFFC WORD $FFFFFFFC BYTE $FFFFFFFC WORD $FFFFFFFE BYTE $FFFFFFFD BYTE $FFFFFFFE BYTE $FFFFFFFF Figure 2-1. Memory Operand Address 2-6 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities 7 BIT DATA 0 7 0 7 BYTE n - 1 7 6 5 4 3 2 1 0 BASE ADDRESS 7 0 7 BIT NUMBER BIT FIELD DATA 0 7 0 7 BYTE n - 1 0 BYTE n + 2 BYTE n + 1 BASE BIT 0 7 0 1 2 3 ...........w - 1 BYTE n OFFSET OFFSET 0 WIDTH ...3-2-1 0 1 2... BASE ADDRESS 7 BYTE INTEGER DATA 0 7 0 7 BYTE n - 1 MSB BYTE n LSB 0 7 BYTE n + 1 0 BYTE n + 2 ADDRESS WORD INTEGER DATA 0 7 0 7 0 7 7 BYTE n - 1 WORD INTEGER 0 7 BYTE n + 2 0 BYTE n + 3 ADDRESS 0 7 7 0 7 BYTE n - 1 0 7 0 7 0 7 LONG-WORD INTEGER 0 BYTE n + 4 ADDRESS ADDRESS 0 7 7 0 7 BYTE n - 1 QUAD-WORD DATA 0 7 0 7 0 7 QUAD WORD 0 BYTE n + 8 PACKED BINARY-CODED DATA 7 0 7 BYTE n - 1 4 3 MSD 0 7 LSD 0 7 BYTE n + 1 0 BYTE n + 2 ADDRESS UNPACKED BINARY-CODED DATA 7 4 3 0 7 BYTE n - 1 XX 4 3 0 7 MSD XX 0 7 LSD 0 BYTE n + 2 ADDRESS XX = USER DEFINED VALUE Figure 2-2. Memory Data Organization MOTOROLA MC68030 USER'S MANUAL 2-7 Data Organization and Addressing Capabilities A bit field operand is specified by: 1. A base address that selects one byte in memory, 2. A bit field offset that indicates the leftmost (base) bit of the bit field in relation to the most significant bit of the base byte, and 3. A bit field width that determines how many bits to the right of the base bit are in the bit field. The most significant bit of the base byte is bit field offset 0, the least significant bit of the base byte is bit field offset 7, and the least significant bit of the previous byte in memory is bit offset -1. Bit field offsets may have values in the range of -231 to 231-1, and bit field widths may range between 1 and 32 bits. 2.4 ADDRESSING MODES The addressing mode of an instruction can specify the value of an operand (with an immediate operand), a register that contains the operand (with the register direct addressing mode), or how the effective address of an operand in memory is derived. An assembler syntax has been defined for each addressing mode. Figure 2-3 shows the general format of the single effective address instruction operation word. The effective address field specifies the addressing mode for an operand that can use one of the numerous defined modes. The (eaL designation is composed of two 3-bit fields: the mode field and the register field. The value in the mode field selects one or a set of addressing modes. The register field specifies a register for the mode or a submode for modes that do not use registers. 15 14 13 12 11 10 9 8 7 6 X X X X X X X X X X 5 0 EFFECTIVE ADDRESS MODE REGISTER Figure 2-3. Single Effective Address Many instructions imply the addressing mode for one of the operands. The formats of these instructions include appropriate fields for operands that use only one addressing mode. 2-8 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities The effective address field may require additional information to fully specify the operand address. This additional information, called the effective address extension, is contained in an additional word or words and is considered part of the instruction. Refer to 2.5 Effective Address Encoding Summary for a description of the extension word formats. The notational conventions used in the addressing mode descriptions in this section are: EA An -- -- Dn -- Xn.SIZE*SCALE -- PC dn bd od L W () [] -- -- -- -- -- -- -- -- Effective address Address register n Example: A3 is address register 3 Data register n Example: D5 is data register 5 Denotes index register n (data or address), the index size (W for word, L for long word), and a scale factor (1, 2, 4, or 8 for no, word, long-word, or quad-word scaling, respectively). The program counter Displacement value, n bits wide Base displacement Outer displacement Long-word size Word size Identify an indirect address in a register Identify an indirect address in memory When the addressing mode uses a register, the register field of the operation word specifies the register to be used. Other fields within the instruction specify whether the register selected is an address or data register and how the register is to be used. 2.4.1 Data Register Direct Mode In the data register direct mode, the operand is in the data register specified by the effective address register field. GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER: DATA REGISTER: NUMBER OF EXTENSION WORDS: MOTOROLA EA = Dn Dn 000 n Dn 0 31 0 OPERAND OPERAND MC68030 USER'S MANUAL 2-9 Data Organization and Addressing Capabilities 2.4.2 Address Register Direct Mode In the address register direct mode, the operand is in the address register specified by the effective address register field. GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER: ADDRESS REGISTER: NUMBER OF EXTENSION WORDS: EA = An An 001 n An 0 31 0 OPERAND 2.4.3 Address Register Indirect Mode In the address register indirect mode, the operand is in memory, and the address of the operand is in the address register specified by the register field. GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER: ADDRESS REGISTER: EA = (An) (An) 010 n An 31 0 MEMORY ADDRESS 31 MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: 0 OPERAND 0 2.4.4 Address Register Indirect with Postincrement Mode In the address register indirect with postincrement mode, the operand is in memory, and the address of the operand is in the address register specified by the register field. After the operand address is used, it is incremented by one, two, or four depending on the size of the operand: byte, word, or long word. Coprocessors may support incrementing for any size of operand up to 255 bytes. If the address register is the stack pointer and the operand size is byte, the address is incremented by two rather than one to keep the stack pointer aligned to a word boundary. GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER: ADDRESS REGISTER: EA = (An) An = An + SIZE (An) + 011 n An 31 0 MEMORY ADDRESS + OPERAND LENGTH ( 1, 2, OR 4): 31 MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: 0 2-10 0 OPERAND MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities 2.4.5 Address Register Indirect with Predecrement Mode In the address register indirect with predecrement mode, the operand is in memory, and the address of the operand is in the address register specified by the register field. Before the operand address is used, it is decremented by one, two, or four depending on the operand size: byte, word, or long word. Coprocessors may support decrementing for any operand size up to 255 bytes. If the address register is the stack pointer and the operand size is byte, the address is decremented by two rather than one to keep the stack pointer aligned to a word boundary. GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER: ADDRESS REGISTER: An = An - SIZE EA = (An) - (An) 100 n An 31 0 MEMORY ADDRESS OPERAND LENGTH (1, 2, OR 4): 31 MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: 0 MOTOROLA 0 OPERAND MC68030 USER'S MANUAL 2-11 Data Organization and Addressing Capabilities 2.4.6 Address Register Indirect with Displacement Mode In the address register indirect with displacement mode, the operand is in memory. The address of the operand is the sum of the address in the address register plus the signextended 16-bit displacement integer in the extension word. Displacements are always signextended to 32 bits prior to being used in effective address calculations. EA = (An) + d 16 (d16,An) 101 n An GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER: ADDRESS REGISTER: 31 DISPLACEMENT: 31 0 MEMORY ADDRESS 0 15 SIGN EXTENDED + INTEGER 31 0 MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: 1 OPERAND 2.4.7 Address Register Indirect with Index (8-Bit Displacement) Mode This addressing mode requires one extension word that contains the index register indicator and an 8-bit displacement. The index register indicator includes size and scale information. In this mode, the operand is in memory. The address of the operand is the sum of the contents of the address register, the sign-extended displacement value in the low-order eight bits of the extension word, and the sign-extended contents of the index register (possibly scaled). The user must specify the displacement, the address register, and the index register in this mode. GENERATION: EA = (An) + (XN) + d 8 (d8,An,Xn.SIZE*SCALE) 110 n 31 An ASSEMBLER SYNTAX: MODE: REGISTER: ADDRESS REGISTER: 0 MEMORY ADDRESS 31 DISPLACEMENT: 0 7 0 31 INDEX REGISTER + INTEGER SIGN EXTENDED SIGN-EXTENDED VALUE 0 7 SCALE VALUE SCALE: X 31 MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: 2-12 + 0 OPERAND 1 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities 2.4.8 Address Register Indirect with Index (Base Displacement) Mode This addressing mode requires an index register indicator and an optional 16- or 32-bit signextended base displacement. The index register indicator includes size and scaling information. The operand is in memory. The address of the operand is the sum of the contents of the address register, the scaled contents of the sign-extended index register, and the base displacement. In this mode, the address register, the index register, and the displacement are all optional. If none is specified, the effective address is zero. This mode provides a data register indirect address when no address register is specified and the index register is a data register (Dn). GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER: ADDRESS REGISTER: EA = (An) + (Xn) + bd (bd,An,Xn.SIZE*SCALE) 110 31 n An 31 BASE DISPLACEMENT: 0 MEMORY ADDRESS 0 + SIGN-EXTENDED VALUE 31 INDEX REGISTER: 0 SIGN-EXTENDED VALUE 7 SCALE: 0 SCALE VALUE X 31 MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: MOTOROLA + 0 OPERAND 1,2, OR 3 MC68030 USER'S MANUAL 2-13 Data Organization and Addressing Capabilities 2.4.9 Memory Indirect Postindexed Mode In this mode, the operand and its address are in memory. The processor calculates an intermediate indirect memory address using the base register (An) and base displacement (bd). The processor accesses a long word at this address and adds the index operand (Xn.SIZE*SCALE) and the outer displacement to yield the effective address. Both displacements and the index register contents are sign-extended to 32 bits. In the syntax for this mode, brackets enclose the values used to calculate the intermediate memory address. All four user-specified values are optional. Both the base and outer displacements may be null, word, or long word. When a displacement is omitted or an element is suppressed, its value is taken as zero in the effective address calculation. GENERATION: ASSEMBLER SYNTAX: MODE: ADDRESS REGISTER: EA = (bd + An) + Xn.SIZE*SCALE + od ([bd,An],Xn.SIZE*SCALE,od) 31 110 An 31 BASE DISPLACEMENT: 0 MEMORY ADDRESS 0 + SIGN-EXTENDED VALUE 31 31 0 INDIRECT MEMORY ADDRESS POINTS TO 0 VALUE AT INDIRECT MEMORY ADDRESS 31 INDEX REGISTER: 0 SIGN-EXTENDED VALUE 7 0 SCALE VALUE SCALE: 31 OUTER DISPLACEMENT: X 0 + SIGN-EXTENDED VALUE 31 EFFECTIVE ADDRESS: NUMBER OF EXTENSION WORDS: 2-14 + 0 OPERAND 1,2, 3, 4, OR 5 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities 2.4.10 Memory Indirect Preindexed Mode In this mode, the operand and its address are in memory. The processor calculates an intermediate indirect memory address using the base register (An), a base displacement (bd), and the index operand (Xn.SIZE * SCALE). The processor accesses a long word at this address and adds the outer displacement to yield the effective address. Both displacements and the index register contents are sign-extended to 32 bits. In the syntax for this mode, brackets enclose the values used to calculate the intermediate memory address. All four user-specified values are optional. Both the base and outer displacements may be null, word, or long word. When a displacement is omitted or an element is suppressed, its value is taken as zero in the effective address calculation. GENERATION: ASSEMBLER SYNTAX: MODE: ADDRESS REGISTER: EA = (bd + An + Xn.SIZE*SCALE) + od ([bd,An,Xn.SIZE*SCALE],od) 31 110 An 31 BASE DISPLACEMENT: 0 MEMORY ADDRESS 0 + SIGN-EXTENDED VALUE 31 0 SIGN-EXTENDED VALUE 7 0 SCALE VALUE X + 31 INDEX REGISTER: 31 SCALE: 0 INDIRECT MEMORY ADDRESS POINTS TO 31 OUTER DISPLACEMENT: 0 + SIGN-EXTENDED VALUE 31 EFFECTIVE ADDRESS: NUMBER OF EXTENSION WORDS: MOTOROLA 0 VALUE AT INDIRECT MEMORY ADDRESS 0 OPERAND 1,2, 3, 4, OR 5 MC68030 USER'S MANUAL 2-15 Data Organization and Addressing Capabilities 2.4.11 Program Counter Indirect with Displacement Mode In this mode, the operand is in memory. The address of the operand is the sum of the address in the PC and the sign-extended 16-bit displacement integer in the extension word. The value in the PC is the address of the extension word. The reference is a program space reference and is only allowed for reads (refer to 4.2 Address Space Types). GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER: PROGRAM COUNTER: EA = (PC) + d 16 d 16 ,PC) 111 010 0 ADDRESS OF EXTENSION WORD 31 DISPLACEMENT: 31 0 15 SIGN EXTENDED + INTEGER 31 MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: 0 OPERAND 1 2.4.12 Program Counter Indirect with Index (8-Bit Displacement) Mode This mode is similar to the address register indirect with index (8-bit displacement) mode described in 2.4.7 Address Register Indirect with Index (8-Bit Displacement) Mode, but the PC is used as the base register. The operand is in memory. The address of the operand is the sum of the address in the PC, the sign-extended displacement integer in the lower eight bits of the extension word, and the sized, scaled, and sign-extended index operand. The value in the PC is the address of the extension word. This reference is a program space reference and is only allowed for reads. The user must include the displacement, the PC, and the index register when specifying this addressing mode. GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER: PROGRAM COUNTER: EA = (PC) + (Xn) + d 8 (d 8 , PC,Xn. SIZE*SCALE) 111 31 011 31 DISPLACEMENT: 0 ADDRESS OF EXTENSION WORD 0 7 SIGN EXTENDED 31 INDEX REGISTER + INTEGER 0 SIGN-EXTENDED VALUE 7 SCALE: 0 SCALE VALUE X 31 MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: 2-16 + 0 OPERAND 1 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities 2.4.13 Program Counter Indirect with Index (Base Displacement) Mode This mode is similar to the address register indirect with index (base displacement) mode described in 2.4.8 Address Register Indirect with Index (Base Displacement) Mode, but the PC is used as the base register. It requires an index register indicator and an optional 16- or 32-bit sign-extended base displacement. The operand is in memory. The address of the operand is the sum of the contents of the PC, the scaled contents of the sign-extended index register, and the base displacement. The value of the PC is the address of the first extension word. The reference is a program space reference and is only allowed for reads (refer to 4.2 Address Space Types). In this mode, the PC, the index register, and the displacement are all optional. However, the user must supply the assembler notation "ZPC'' (zero value is taken for the PC) to indicate that the PC is not used. This allows the user to access the program space without using the PC in calculating the effective address. The user can access the program space with a data register indirect access by placing ZPC in the instruction and specifying a data register (Dn) as the index register. GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER: PROGRAM COUNTER: EA = (PC) + (Xn) + bd (bd, PC, Xn. SIZE*SCALE) 111 31 011 0 ADDRESS OF EXTENSION WORD 31 BASE DISPLACEMENT: 0 + SIGN-EXTENDED VALUE 31 INDEX REGISTER 0 SIGN-EXTENDED VALUE 7 SCALE: 0 SCALE VALUE X 31 MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: MOTOROLA + 0 OPERAND 1, 2 OR 3 MC68030 USER'S MANUAL 2-17 Data Organization and Addressing Capabilities 2.4.14 Program Counter Memory Indirect Postindexed Mode This mode is similar to the memory indirect postindexed mode described in 2.4.9 Memory Indirect Postindexed Mode, but the PC is used as the base register. Both the operand and operand address are in memory. The processor calculates an intermediate indirect memory address by adding a base displacement (bd) to the PC contents. The processor accesses a long word at that address and adds the scaled contents of the index register and the optional outer displacement (od) to yield the effective address. The value of the PC used in the calculation is the address of the first extension word. The reference is a program space reference and is only allowed for reads (refer to 4.2 Address Space Types). In the syntax for this mode, brackets enclose the values used to calculate the intermediate memory address. All four user-specified values are optional. However, the user must supply the assembler notation ZPC (zero value is taken for the PC) to indicate that the PC is not used. This allows the user to access the program space without using the PC in calculating the effective address. Both the base and outer displacements may be null, word, or long word. When a displacement is omitted or an element is suppressed, its value is taken as zero in the effective address calculation. GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER FIELD: PROGRAM COUNTER: EA = (bd + PC) + Xn.SIZE*SCALE + od ([bd, PC], Xn.SIZE*SCALE,od) 111 31 011 0 MEMORY ADDRESS 31 BASE DISPLACEMENT: 0 + SIGN-EXTENDED VALUE 31 0 INDIRECT MEMORY ADDRESS POINTS TO 31 0 VALUE AT INDIRECT MEMORY ADDRESS IN PROGRAM SPACE 31 0 SIGN-EXTENDED VALUE INDEX REGISTER: 7 0 SCALE VALUE 31 OUTER DISPLACEMENT: X 0 + SIGN-EXTENDED VALUE 31 EFFECTIVE ADDRESS: NUMBER OF EXTENSION WORDS: 2-18 + 0 OPERAND 1,2, 3, 4, OR 5 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities 2.4.15 Program Counter Memory Indirect Preindexed Mode This mode is similar to the memory indirect preindexed mode described in 2.4.10 Memory Indirect Preindexed Mode, but the PC is used as the base register. Both the operand and operand address are in memory. The processor calculates an intermediate indirect memory address by adding the PC contents, a base displacement (bd), and the scaled contents of an index register. The processor accesses a long word at that address and adds the optional outer displacement (od) to yield the effective address. The value of the PC is the address of the first extension word. The reference is a program space reference and is only allowed for reads (refer to 4.2 Address Space Types). In the syntax for this mode, brackets enclose the values used to calculate the intermediate memory address. All four user-specified values are optional. However, the user must supply the assembler notation ZPC (zero value is taken for the PC) to indicate that the PC is not used. This allows the user to access the program space without using the PC in calculating the effective address. Both the base and outer displacements may be null, word, or long word. When a displacement is omitted or an element is suppressed, its value is taken as zero in the effective address calculation. GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER FIELD: PROGRAM COUNTER: EA = (bd + PC + Xn . SIZE * SCALE) + od ([bd, PC, Xn. SIZE*SCALE],od) 111 31 011 0 ADDRESS OF EXTENSION WORD 31 BASE DISPLACEMENT: 0 + SIGN-EXTENDED VALUE 31 0 SIGN-EXTENDED VALUE INDEX REGISTER 0 7 SCALE VALUE X + 31 0 INDIRECT MEMORY ADDRESS POINTS TO 31 0 VALUE AT INDIRECT MEMORY ADDRESS IN PROGRAM SPACE 31 OUTER DISPLACEMENT: 0 + SIGN-EXTENDED VALUE 31 EFFECTIVE ADDRESS: NUMBER OF EXTENSION WORDS: MOTOROLA 0 OPERAND 1, 2, 3, 4 OR 5 MC68030 USER'S MANUAL 2-19 Data Organization and Addressing Capabilities 2.4.16 Absolute Short Addressing Mode In this addressing mode, the operand is in memory, and the address of the operand is in the extension word. The 16-bit address is sign-extended to 32 bits before it is used. GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER FIELD: EXTENSION WORD: EA GIVEN (xxx).W 111 000 15 31 SIGN EXTENDED 0 MEMORY ADDRESS 31 MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: 0 OPERAND 1 2.4.17 Absolute Long Addressing Mode In this mode, the operand is in memory, and the address of the operand occupies the two extension words following the instruction word in memory. The first extension word contains the high-order part of the address; the low-order part of the address is the second extension word. GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER FIELD: FIRST EXTENSION WORD: EA GIVEN (xxx).L 111 001 15 0 ADDRESS HIGH 15 SECOND EXTENSION WORD: 0 ADDRESS LOW 31 0 CONCATENATION 31 MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: 2-20 0 OPERAND 2 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities 2.4.18 Immediate Data In this addressing mode, the operand is in one or two extension words: Byte Operation Operand is in the low-order byte of the extension word Word Operation Operand is in the extension word Long-Word Operation The high-order 16 bits of the operand are in the first extension word; the low-order 16 bits are in the second extension word. Coprocessor instructions can support immediate data of any size. The instruction word is followed by as many extension words as are required. Generation: Assembler Syntax: Mode Field: Register Field: Number of Extension Words: MOTOROLA Operand given #xxx 111 100 1 or 2, except for coprocessor instructions MC68030 USER'S MANUAL 2-21 Data Organization and Addressing Capabilities 2.5 EFFECTIVE ADDRESS ENCODING SUMMARY Most of the addressing modes use one of the three formats shown in Figure 2-4. The single effective address instruction is in the format of the instruction word. The encoding of the mode field of this word selects the addressing mode. The register field contains the general register number or a value that selects the addressing mode when the mode field contains "111.'' Table 2-2 shows the encoding of these fields. Some indexed or indirect modes use the instruction word followed by the brief format extension word. Other indexed or indirect modes consist of the instruction word and the full format of extension words. The longest instruction for the MC68030 contains 10 extension words. It is a MOVE instruction with full format extension words for both source and destination effective addresses and with 32-bit base displacements and 32-bit outer displacements for both addresses. However, coprocessor instructions can have any number of extension words. Refer to the coprocessor instruction formats in Section 10 Coprocessor Interface Description. For effective addresses that use the full format, the index suppress (IS) bit and the index/ indirect selection (I/IS) field determine the type of indexing and indirection. Table 2-1 lists the indexing and indirection operations corresponding to all combinations of IS and I/IS values. Table 2-1. IS-I/IS Memory Indirection Encodings IS 0 0 0 0 0 0 0 0 1 1 1 1 1 2-22 Index/Indirect 000 001 010 011 100 101 110 111 000 001 010 011 100-111 Operation No Memory Indirection Indirect Preindexed with Null Outer Displacement Indirect Preindexed with Word Outer Displacement Indirect Preindexed with Long Outer Displacement Reserved Indirect Postindexed with Mull Outer Displacement Indirect Postindexed with Word Outer Displacement Indirect Postindexed with Long Outer Displacement No Memory Indirection Memory Indirect with Mull Outer Displacement Memory Indirect with Word Outer Displacement Memory Indirect with Long Outer Displacement Reserved MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities Single Effective Address Instruction Format 15 14 13 12 11 10 9 8 7 6 X X X X X X X X X X 5 0 EFFECTIVE ADDRESS MODE REGISTER Brief Format Extension Word 15 14 D/A 12 REGISTER 11 W/L 10 9 SCALE 8 7 0 0 DISPLACEMENT Full Format Extension Word(s) 15 D/A 14 12 REGISTER Field 11 W/L 10 9 8 7 6 5 4 SCALE 1 BS IS BD SIZE BASE DISPLACEMENT (0, 1, OR 2 WORDS) OUTER DISPLACEMENT (0, 1, OR 2 WORDS) Definition Field Instruction: Register General Register Number Extensions: Register Index Register Number D/A Index Register Type 0 = Dn 1 = An W/L Word/Long-Word Index Size 0 = Sign-Extended Word 1 = Long Word Scale Scale Factor 00 =1 01 =2 10 = 4 11 = 8 3 0 2 0 I/IS Definition BS Base Register Suppress: 0 = Base Register Added 1 = Base Register Suppressed IS Index Suppress: 0 = Evaluate and Add Index Operand 1 = Suppress Index Operand BD SIZE Base Displacement Size: 00 = Reserved 01 = Null Displacement 10 = Word Displacement 11 Long Displacement I/IS Index/Indirect Selection Indirect and Indexing Operand Determined in Conjunction with Bit 6, Index Suppress Figure 2-4. Effective Address Specification Formats Effective address modes are grouped according to the use of the mode. They can be classified as follows: Data A data addressing effective address mode is one that refers to data operands. Memory A memory addressing effective address mode is one that refers to memory operands. Alterable An alterable addressing effective address mode is one that refers to alterable (writable) operands. Control A control addressing effective address mode is one that refers to memory operands without an associated size. MOTOROLA MC68030 USER'S MANUAL 2-23 Data Organization and Addressing Capabilities Table 2-2 shows the categories to which each of the effective addressing modes belong. Addressing Modes Data Register Direct Address Register Direct Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement Address Register Indirect with Index (8-Bit Displacement) Address Register Indirect with Index (Base Displacement) Memory Indirect Postindexed Memory Indirect Preindexed Absolute Short Absolute Long Program Counter Indirect with Displacement Program Counter Indirect with Index (8-Bit) Displacement Program Counter Indirect with Index (Base Displacement) PC Memory Indirect Postindexed PC Memory Indirect Preindexed Immediate Mode Register Data Memory Control Alterable 000 001 010 reg. no. reg. no. reg. no X -- X -- -- X -- -- X X X X Assembler Syntax Dn An (An) 011 reg. no. X X -- X (An)+ 100 reg. no. X X -- X -(An) 101 reg. no. X X X X (d16,An) 110 reg. no. X X X X (d8,An,Xn) 110 110 110 reg. no. reg. no reg. no. X X X X X X X X X X X X 111 111 000 001 X X X X X X X X (bd,An,Xn) ([bd,An],Xn,od) ([bd,An,Xn],od) (xxx).W (xxx).L 111 010 X X X -- (d16,PC) 111 011 X X X -- (d8,PC,Xn) 111 011 X X X -- (bd,PC,Xn) 111 011 X X X -- ([bd,PC],Xn,od) 111 011 X X X -- 111 100 X X -- -- ([bd,PC,Xn],od) #data These categories are sometimes combined, forming new categories that are more restrictive. Two combined classifications are alterable memory or data alterable. The former refers to those addressing modes that are both alterable and memory addresses, and the latter refers to addressing modes that are both data and alterable. 2.6 PROGRAMMERS VIEW OF ADDRESSING MODES Extensions to the indexed addressing modes, indirection, and full 32-bit displacements provide additional programming capabilities for both the MC68020 and the MC68030. This section describes addressing techniques that exploit these capabilities and summarizes the addressing modes from a programming point of view. 2-24 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities Several of the addressing techniques described in this section use data registers and address registers interchangeably. While the MC68030 provides this capability, its performance has been optimized for addressing with address registers. The performance of a program that uses address registers in address calculations is superior to that of a program that similarly uses data registers.The performance has been optimized for addressing registers in address calculations is superior to that of a program that similarly uses data registers. The specification of addresses with data registers should be used sparingly (if at all), particularly in programs that require maximum performance. 2.6.1 Addressing Capabilities In both the MC68020 and the MC68030, setting the base register suppress (BS) bit in the full format extension word (see Figure 2-4) suppresses use of the base address register in calculating the effective address. This allows any index register to be used in place of the base register. Since any of the data registers can be index registers, this provides a data register indirect form (Dn). The mode could be called register indirect (Rn) since either a data register or an address register can be used. This addressing mode is an extension to the M68000 Family because the MC68030 and MC68020 can use both the data registers and the address registers to address memory. The capabilities of specifying the size and scale of an index register (Xn.SIZE*SCALE) in these modes provides additional addressing flexibility. Using the SIZE parameter, either the entire contents of the index register can be used, or the least significant word can be sign-extended to provide a 32-bit index value (refer to Figure 2-5). 31 0 D1.L D1 31 16 15 D1.W 0 D1 USED IN ADDRESS CALCULATION Figure 2-5. Using SIZE in the Index Selection MOTOROLA MC68030 USER'S MANUAL 2-25 Data Organization and Addressing Capabilities For both the MC68020 and the MC68030, the register indirect modes can be extended further. Since displacements can be 32 bits wide, they can represent absolute addresses or the results of expressions that contain absolute addresses. This allows the general register indirect form to be (bd,Rn) or (bd,An,Rn) when the base register is not suppressed. Thus, an absolute address can be directly indexed by one or two registers (refer to Figure 2-6). SYNTAX (bd,An,Rn) bd An Rn Figure 2-6. Using Absolute Address with Indexes Scaling provides an optional shifting of the value in an index register to the left by zero, one, two, or three bits before using it in the effective address allocation (the actual value in the index register remains unchanged). This is equivalent to multiplying the register by one, two, four, or eight or direct subscripting into an array of elements of corresponding size using an arithmetic value residing in any of the 16 general registers. Scaling does not add to the effective address calculation time. However, when combined with the appropriate derived modes, it produces additional capabilities. Arrayed structures can be addressed absolutely and then subscripted, (bd,Rn*scale). Another variation that can be derived is (An,Rn*scale). In the first case, the array address is the sum of the contents of a register and a displacement, as shown in Figure 2-7. In the second example. An contains the address of an array and Rn contains a subscript. 2-26 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities SYNTAX: MOVE.W (A5, A6.L*SCALE),(A7) WHERE: A5 = ADDRESS OF ARRAY STRUCTURE A6 = INDEX NUMBER OF ARRAY ITEM A7 = STACK POINTER SIMPLE ARRAY (SCALE = 1) 15 RECORD OF 2 WORDS (SCALE = 2) 0 15 A6 = 1 2 A6 = 1 3 4 2 RECORD OF 4 WORDS (SCALE = 4) 15 A6 = 1 0 RECORD OF 8 WORDS (SCALE = 8) 0 15 0 A6 = 1 2 2 NOTE: Regardless of array structure, software increments index by the appropriate amount to point to next record. Figure 2-7. Addressing Array Items MOTOROLA MC68030 USER'S MANUAL 2-27 Data Organization and Addressing Capabilities The memory indirect addressing modes use a long-word pointer in memory to access an operand. Any of the modes previously described can be used to address the memory pointer. Because the base and index registers can both be suppressed, the displacement acts as an absolute address, providing indirect absolute memory addressing (refer to Figure 2-8). The outer displacement (od) available in the memory indirect modes is added to the pointer in memory. The syntax for these modes is ([bd,An],Xn,od) and ([bd,An,Xn],od). When the pointer is the address of a structure in memory and the outer displacement is the offset of an item in the structure, the memory indirect modes can access the item efficiently (refer to Figure 2-9). Memory indirect addressing modes are used with a base displacement in five basic forms: 1. [bd,An] -- Indirect, suppressed index register 2. ([bd,An,Xn]) -- Preindexed indirect 3. ([bd,An],Xn) -- Postindexed indirect 4. ([bd,An,Xn],od) -- Preindexed indirect with outer displacement 5. ([bd,An],Xn,od) -- Postindexed indirect with outer displacement SYNTAX: ([bd]) bd POINTER DATA ITEM Figure 2-8. Using Indirect Absolute Memory Addressing The indirect, suppressed index register mode (see Figure 2-10) uses the contents of register An as an index to the pointer located at the address specified by the displacement. The actual data item is at the address in the selected pointer. The preindexed indirect mode (see Figure 2-11) uses the contents of An as an index to the pointer list structure at the displacement. Register Xn is the index to the pointer, which contains the address of the data item. 2-28 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities SYNTAX: ([An],od) MEMORY An STRUCTURE POINTER od DATA ITEM Figure 2-9. Accessing an Item in a Structure Using a Pointer SYNTAX: ([bd,An]) POINTER LIST bd An POINTER DATA ITEM Figure 2-10. Indirect Addressing, Suppressed Index Register MOTOROLA MC68030 USER'S MANUAL 2-29 Data Organization and Addressing Capabilities SYNTAX: ([bd,An,Xn]) POINTER LIST bd An DATA ITEM Xn POINTER Figure 2-11. Preindexed Indirect Addressing 2-30 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities The postindexed indirect mode (see Figure 2-12) uses the contents of An as an index to the pointer list at the displacement. Register Xn is used as an index to the structure of data items located at the address specified by the pointer. Figure 2-13 shows the preindexed indirect addressing with outer displacement mode. SYNTAX: ([bd,An],Xn) POINTER LIST POSTINDEXED STRUCTURE bd An Xn DATA ITEM POINTER Figure 2-12. Postindexed Indirect Addressing SYNTAX: ([bd,An,Xn],od) POINTER LIST STRUCTURE bd An od Xn DATA ITEM POINTER Figure 2-13. Preindexed Indirect Addressing with Outer Displacement MOTOROLA MC68030 USER'S MANUAL 2-31 Data Organization and Addressing Capabilities The postindexed indirect mode with outer displacement (see Figure 2-14) uses the contents of An as an index to the pointer list at the displacement. Register Xn is used as an index to the structure of data structures at the address in the pointer. The outer displacement (od) is the displacement of the data item within the selected data structure. SYNTAX: ([bd,An],Xn,od) POINTER LIST POSTINDEXED STRUCTURE WITH OUTER DISPLACEMENT bd od An Xn POINTER DATA ITEM Figure 2-14. Postindexed Indirect Addressing with Outer Displacement 2.6.2 General Addressing Mode Summary The addressing modes described in the previous section are derived from specific combinations of options in the indexing mode or a selection of two alternate addressing modes. For example, the addressing mode called register indirect (Rn) assembles as the address register indirect if the register is an address register. If Rn is a data register, the assembler uses the address register indirect with index mode using the data register as the indirect register and suppresses the address register by setting the base suppress bit in the effective address specification. Assigning an address register as Rn provides higher performance than using a data register as Rn. Another case is (bd,An), which selects an addressing mode depending on the size of the displacement. If the displacement is 16 bits or less, the address register indirect with displacement mode (d16,An) is used. When a 32bit displacement is required, the address register indirect with index (bd,An,Xn) is used with the index register suppressed. 2-32 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities It is useful to examine the derived addressing modes available to a programmer (without regard to the MC68030 effective addressing mode actually encoded) because the programmer need not be concerned about these decisions. The assembler can choose the more efficient addressing mode to encode. In the list of derived addressing modes that follows, common programming terms are used. The following definitions apply: pointer -- long-Word value in a register or in memory which represents an address. base -- A pointer combined with a displacement to represent an address. index -- A constant or variable value added into an effective address calculation. A constant index is a displacement. A variable index is always represented by a register containing the value. disp -- Displacement, a constant index. subscript -- The use of any of the data or address registers as a variable index subscript into arrays of items 1, 2, 4 or 8 bytes in size. relative -- An address calculated from the program counter contents. The address is position independent and is in program space. All other addresses but psaddr are in data space. addr -- An absolute address. psaddr -- An absolute address in program space. All other addresses but PC relative are in data space. preindexed -- All modes from absolute address through program counter relative. postindexed-- Any of the following modes: addr -- Absolute address in data space psaddr,ZPC -- Absolute address in program space An -- Register pointer with constant displacement disp.An -- Register pointer with constant displacement addr,An -- Absolute address with single variable name disp,Pc -- Simple PC relative The addressing modes defined in programming terms, which are derivations of the addressing modes provided by the MC68030 architecture, are as follows: Immediate Data -- #data: The data is a constant located in the instruction stream. Register Direct -- Rn: The contents of a register contain the operand. Scanning Modes: (An)+ MOTOROLA MC68030 USER'S MANUAL 2-33 Data Organization and Addressing Capabilities Address register pointer automatically incremented after use. - (An) Address register pointer automatically decremented before use. Absolute Address: (addr) Absolute address in data space. (psaddr,ZPC) Absolute address in program space. Symbol ZPC suppresses the PC, but retains PC relative mode to directly access the program space. Register Pointer: (Rn) Register as a pointer. (disp,Rn) Register as a pointer with constant index (or base address). Indexing (An,Rn) Register pointer An with variable index Rn. (disp,An,Rn) Register pointer with constant and variable index (or a base address with a variable index). (addr,Rn) Absolute address with two variable indexes. Subscripting: (An,Rn*scale) Address register pointer subscript. (disp,An,Rn*scale) Address register pointer subscript with constant displacement (or base address with subscript). (addr,Rn*scale) Absolute address with subscript. (addr,An,Rn*scale) Absolute address subscript with variable index. Program Relative: 2-34 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities (disp,PC) Simple PC relative. (disp,PC,Rn) PC relative with variable index. (disp,PC,Rn*scale) PC relative with subscript. Memory Pointer: ([preindexed]) Memory pointer directly to data operand. ([preindexed],disp) Memory pointer as base with displacement to data operand. ([postindexed],Rn) Memory pointer with variable index. ([postindexed],disp,Rn) Memory pointer with constant and variable index. ([postindexed],Rn*scale) Memory pointer subscripted. ([postindexed],disp,Rn*scale) Memory pointer subscripted with constant index. MOTOROLA MC68030 USER'S MANUAL 2-35 Data Organization and Addressing Capabilities 2.7 M68000 FAMILY ADDRESSING COMPATIBILITY Programs can be easily transported from one member of the M68000 Family to another in an upward compatible fashion. The user object code of each early member of the family is upward compatible with newer members and can be executed on the newer microprocessor without change. The address extension word(s) are encoded with the information that allows the MC68020/MC68030 to distinguish the new address extension words for the early MC68000/MC68008/MC68010 microprocessors and for the newer 32-bit MC68020/ MC68030 microprocessors are shown in Figure 2-15. Notice the encoding for SCALE used by the MC68020/MC68030 is a compatible extension of the M68000 architecture. A value of zero for SCALE is the same encoding for both extension words; hence, software that uses this encoding is both upward and downward compatible across all processors in the product line. However, the other values of SCALE are not found in both extension formats; thus, while software can be easily migrated in an upward compatible direction, only nonscaled addressing is supported in a downward fashion. If the MC68000 were to execute an instruction that encoded a scaling factor, the scaling factor would be ignored and not access the desired memory address. The earlier microprocessors have no knowledge of the extension word formats implemented by newer processors; while they do detect illegal instructions, they do not decode invalid encodings of the extension words as exceptions. 2.8 OTHER DATA STRUCTURES Stacks and queues are widely used data structures. The MC68030 implements a system stack and also provides instructions that support the use of user stacks and queues. 2.8.1 System Stack Address register seven (A7) is used as the system stack pointer (SP). Any of the three system stack registers is active at any one time. The M and S bits of the status register determine which stack pointer is used. When S = 0 indicating user mode (user privilege level), the user stack pointer (USP) is the active system stack pointer, and the master and interrupt stack pointers cannot be referenced. When S = 1 indicating supervisor mode (at supervisor privilege level) and M = 1, the master stack pointer (MSP) is the active system stack pointer. When S = 1 and M = 0, the interrupt stack pointer (ISP) is the active system stack pointer. This mode is the MC68030 default mode after reset and corresponds to the MC68000, MC68008, and MC68010 supervisor mode. The term supervisor stack pointer (SSP) refers to the master or interrupt stack pointers, depending on the state of the M bit. When M = 1, the term SSP (or A7) refers to the MSP address register. When M = 0, the term is implicitly referenced by all instructions that use the system stack. Each system stack fills from high to low memory. 2-36 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities (UNABLE TO LOCATE ART. MUST BE RECREATED.) Figure 2-15. M68000 Family Address Extension Words A subroutine call saves the program counter on the active system stack, and the return restores it from the active system stack. During the processing of traps and interrupts, both the program counter and the status register are saved on the supervisor stack (either master or interrupt). Thus, the execution of supervisor code is independent of user code and the condition of the user stack; conversely, user programs use the user stack pointer independently of supervisor stack requirements. To keep data on the system stack aligned for maximum efficiency, the active stack pointer is automatically decremented or incremented by two for all byte-sized operands moved to or from the stack. In long-word-organized memory, aligning the stack pointer on a long-word address signed significantly increases the efficiency of stacking exception frames, subroutine calls and returns, and other stacking operations. MOTOROLA MC68030 USER'S MANUAL 2-37 Data Organization and Addressing Capabilities 2.8.2 User Program Stacks The user can implement stacks with the address register indirect with postincrement and predecrement addressing modes. With address register An (n = 0-6), the user can implement a stack that is filled wither from high to low memory or from low to high memory. Important considerations are: * Use the predecrement mode to decrement the register before its contents are used as the pointer to the stack. * Use the postincrement mode to increment the register after its contents are used as the pointer to the stack. * Maintain the stack pointer correctly when byte, word, and long-word items are mixed in these stacks. To implement stack growth from high to low memory, use: -(An) to push data on the stack, (An)+ to pull data from the stack. For this type of stack, after either a push or a pull operation, register An points to the top item on the stack. This is illustrated as: LOW MEMORY An (FREE) TOP OF STACK BOTTOM OF STACK HIGH MEMORY To implement stack growth from low to high memory, use: (An)+ to push data on the stack, -An to pull data from the stack. 2-38 MC68030 USER'S MANUAL MOTOROLA Data Organization and Addressing Capabilities In this case, after either a push or pull operation, register An points to the next available space on the stack. This is illustrated as: LOW MEMORY BOTTOM OF STACK TOP OF STACK An (FREE) HIGH MEMORY 2.8.3 Queues The user can implement queues with the address register indirect with postincrement or predecrement addressing modes. Using a pair of address registers (who of A0-A6), the user can implement a queue which is filled either from high to low memory or from low to high memory. Two registers are used because queues are pushed from one end and pulled from the other. One register, An, contains the "put'' pointer; the other, Am, the "get'' pointer. To implement growth of the queue from low to high memory, use: (An)+ to put data into the queue, (Am)+ to get data from the queue. After a "put'' operation, the "put'' address register points to the next available space in the queue, and the unchanged "get'' address register points to the next item to be removed from the queue. After a "get'' operation, the "get'' address register points to the next item to be removed from the queue, and the unchanged "put'' address register points to the next available space in the queue. This is illustrated as: LOW MEMORY LAST GET (FREE) GET (Am) + NEXT GET LAST PUT PUT (An) + (FREE) HIGH MEMORY To implement the queue as a circular buffer, the relevant address register should be checked and adjusted, if necessary, before performing the "put'' or "get'' operation. The address register is adjusted by subtracting the buffer length (in bytes) from the register. MOTOROLA MC68030 USER'S MANUAL 2-39 Data Organization and Addressing Capabilities To implement growth of the queue from high to low memory, use: -(An) to put data into the queue, -(Am) to get data from the queue. After a "put'' operation, the "put'' address register points to the last item place din the queue, and the unchanged "get'' address register points to the last item removed from the queue. After a "get'' operation, the "get'' address register points to the last item removed from the queue, and the unchanged "put'' address register points to the last item placed in the queue. This is illustrated as: LOW MEMORY (FREE) PUT - (An) LAST PUT GET - (Am) LAST GET (FREE) NEXT GET HIGH MEMORY To implement the queue as a circular buffer, the "get'' or "put'' operation should be performed first, and then the relevant address register should be checkout and adjusted, if necessary. The address register is adjusted by adding the buffer length (in bytes) to the register contents. 2-40 MC68030 USER'S MANUAL MOTOROLA SECTION 3 INSTRUCTION SET SUMMARY This section briefly describes the MC68030 instruction set. Refer to the MC68000PM/AD, MC68000 Programmer's Reference Manual, for complete details on the MC68030 instruction set. The following paragraphs include descriptions of the instruction format and the operands used by instructions, followed by a summary of the instruction set. The integer condition codes and floating-point details are discussed. Programming examples for selected instructions are also presented. 3.1 INSTRUCTION FORMAT All MC68030 instructions consist of at least one word; some have as many as 11 words (see Figure 3-1). The first word of the instruction, called the operation word, specifies the length of the instruction and the operation to be performed. The remaining words, called extension words, further specify the instruction and operands. These words may be floating-point command words, conditional predicates, immediate operands, extensions to the effective address mode specified in the operation word, branch displacements, bit number or bit field specifications, special register specifications, trap operands, pack/unpack constants, or argument counts. 15 0 OPERATION WORD(ONE WORD, SPECIFIES OPERATION AND MODES) SPECIAL OPERAND SPECIFIERS (IF ANY, ONE OR TWO WORDS) IMMEDIATE OPERAND OR SOURCE EFFECTIVE ADDRESS EXTENSION( IF ANY, ONE TO SIX WORDS) DESTINATION EFFECTIVE ADDRESS EXTENSION (IF ANY, ONE TO SIX WORDS) Figure 3-1. Instruction Word General Format MOTOROLA MC68030 USER'S MANUAL 3-1 Instruction Set Summary Besides the operation code, which specifies the function to be performed, an instruction defines the location of every operand for the function. Instructions specify an operand location in one of three ways: 1. Register Specification -- A register field of the instruction contains the number of the register. 2. Effective Address -- An effective address field of the instruction contains address mode information. 3. Implicit Reference -- The definition of an instruction implies the use of specific registers. The register field within an instruction specifies the register to be used. Other fields within the instruction specify whether the register selected is an address or data register and how the register is to be used. Section 1 Introduction contains register information. Effective address information includes the registers, displacements, and absolute addresses for the effective address mode. Section 2 Data Organization and Addressing Capabilities describes the effective address modes in detail. Certain instructions operate on specific registers. These instructions imply the required registers. 3.2 INSTRUCTION SUMMARY The instructions form a set of tools to perform the following operations: Data Movement Integer Arithmetic Logical Shift and Rotate Bit Manipulation Bit Field Manipulation Binary-Coded Decimal Arithmetic Program Control System Control Multiprocessor Communications Each instruction type is described in detail in the following paragraphs 3-2 MC68030 USER'S MANUAL MOTOROLA Instruction Set Summary The following notations are used in this section. In the operand syntax statements of the instruction definitions, the operand on the right is the destination operand. An Dn Rn CCR cc SR SP USP ISP MSP SSP DFC SFC Rc MRc = = = = = = = = = = = = = = = MMUSR = B, W, L = S D X P FPm, FPn PFcr = = = = = = k= d ea list #data {offset:width} label [m] [m:n] MOTOROLA = = = = = = = = any address register, A7-A0 any data register, D7-D0 any address or data register condition code register (lower byte of status register) condition codes from CCR status register active stack pointer user stack pointer supervisor/interrupt stack pointer supervisor/master stack pointer supervisor (master or interrupt) stack pointer destination function code register source function code register control register (VBR, SFC, DFC, CACR) MMU control register (SRP, URP, TC, DTT0, DTT1, ITT0, ITT1, MMUSR) MMU status register specifies a signed integer data type (twos complement) of byte, word, or long word single-precision real data format (32 bits) double-precision real data format (64 bits) extended-precision real data format (96 bits, 16 bits unused) packed BCD real data format (96 bits, 12 bytes) any floating-point data register, FP7-FP0 floating-point system control register (FPCR, FPSR, or FPIAR) a twos-complement signed integer (-64 to +17) that specifies the format of a number to be stored in the packed BCD format displacement; d16 is a 16-bit displacement effective address list of registers, for example D3 -- D0 immediate data; a literal integer bit field selection assemble program label bit m of an operand bits m through n of operand MC68030 USER'S MANUAL 3-3 Instruction Set Summary X N Z V C + - x / ~ V Dc Du Dr, Dq Dh, Dl MSW LSW MSB FC {R/W} [An] = = = = = = = = = = = = = = = = = = = = = = = extend (X) bit in CCR negative (N) bit in CCR Zero (Z) bit in CCR overflow (V) bit in CCR carry (C) bit in CCR arithmetic addition or postincrement indicator arithmetic subtraction or predecrement indicator arithmetic multiplication arithmetic division or conjunction symbol invert; operand is logically complemented logical AND logical OR logical exclusive OR data register, D7-D0 used during compare data register, D7-D0 used during update data registers, remainder or quotient of divide data registers, high or lo*order 32 bits of product most significant word least significant word most significant bit function code read or write indicator address extensions 3.2.1 Data Movement Instructions The MOVE instructions with their associated addressing modes are the basic means of transferring and storing addresses and data. MOVE instructions transfer byte, word, and long-word operands from memory to memory, memory to register, register to memory, and register to register. Address movement instructions (MOVE or MOVEA) transfer word and long-word operands and ensure that only valid address manipulations are executed. In addition to the general MOVE instructions, there are several special data movement instructions: move multiple registers (MOVEM), move peripheral data (MOVEP), move quick (MOVEQ), exchange registers (EXG), load effective address (LEA), push effective address (PEA), link stack (LINK), and unlink stack (UNLK). 3-4 MC68030 USER'S MANUAL MOTOROLA Instruction Set Summary Table 3-1 is a summary of the integer and floating-point data movement operations. Table 3-1. Data Movement Operations Instruction EXG LEA LINK MOVE MOVEA Operand Syntax Rn,Rn ea,An An,#d ea,ea,An MOVEM list,ea,list MOVEP Dn,(d16,An) Operand Size 32 32 16, 32 8, 16, 32 16, 32 32 16, 32 16, 32 32 16, 32 Operation Rn Rn ea An Sp - 4 SP; An (SP); SP An, SP + D SP source destination 8 32 32 32 immediate data destination SP -- 4 SP; ea (SP) An SP; (SP) An; SP + 4 SP (d16,An),Dn MOVEQ PEA UNLK #data,Dn ea An listed registers destination source listed registers Dn[31:24] (An + d); Dn[23:16] An + d + 2); Dn[15:8] (An + d + 4); Dn[7:0] (An + d + 6) (An + d) Dn[31:24]; (An + d + 2) Dn[23:16]; (An + d + 4) Dn[15:8]; (An + d + 6) Dn[7:0] 3.2.2 Integer Arithmetic Instructions The integer arithmetic operations include the four basic operations of add (ADD), subtract (SUB), multiply (MUL), and divide (DIV) as well as arithmetic compare (CMP, CMPM, CMP2), clear (CLR), and negate (NEG). The instruction set includes ADD, CMP, and SUB instructions for both address and data operations with all operand sizes valid for data operations. Address operands consist of 16 or 32 bits. The clear and negate instructions apply to all sizes of data operands. Signed and unsigned MUL and DIV instructions include: * Word multiply to produce a long-word product * Long-word multiply to produce and long-word or quad-word product * Division of a long word divided by a word divisor (word quotient and word remainder) * Division of a long word or quad word dividend by a long-word divisor (long-word quotient and long-word remainder) A set of extended instructions provides multiprecision and mixed-size arithmetic. These instructions are add extended (ADDX), subtract extended (SUBX), sign extended (EXT), and negate binary with extend (NEGX). Refer to Table 3-2 for a summary of the integer arithmetic operations. MOTOROLA MC68030 USER'S MANUAL 3-5 Instruction Set Summary Table 3-2. Integer Arithmetic Operations Instruction ADD ADDA ADDI ADDQ ADDX CLR CMP CMPA CMPI CMPM CMP2 DIVS/DIVU DIVSL/DIVUL EXT EXTB MULS/MULU NEG NEGX SUB SUBA SUBI SUBQ SUBX Operand Syntax Dn,ea ea,Dn ea,An #data,ea#data, ea Dn,Dn -(An),-(An) ea ea,Dn ea,An #data,ea (An) +,(An) + ea,Rn ea,Dn ea,Dr:Dq ea,Dq ea,Dr:Dq Dn Dn Dn ea,Dn ea,Dl (ea,Dh:Dl ea ea ea,Dn Dn,ea ea,An #data,ea #data,ea Dn,Dn -(An),-(An) Operand Size 8, 16, 32 8, 16, 32 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 32/16 16:16 64/32 32:32 32/32 32 32/32 32:32 8 16 16 32 8 32 16x16 32 32x32 32 32x32 64 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 Operation source + destination destination immediate data + destination destination source + destination + X destination 0 destination destination - source destination - immediate data destination - source lower bound < = Rn < = upper bound destination/source destination (signed or unsigned) sign-extended destination destination source y destination destination (signed or unsigned) 0 - destination destination 0 - destination - X destination destination = source destination destination - immediate data destination destination - source -- X destination 3.2.3 Logical Instructions The logical operation instructions (AND, OR, EOR, and NOT) perform logical operations with all sizes of integer data operands. A similar set of immediate instructions (ANDI, ORI, and EORI) provide these logical operations with all sizes of immediate data. The TST instruction compares the operand with zero arithmetically, placing the result in the condition code register. Table 3-3 summarizes the logical operations. 3-6 MC68030 USER'S MANUAL MOTOROLA Instruction Set Summary Table 3-3. Logical Operations Instruction AND ANDI EOR EORI NOT OR ORI TST Operand Syntax ea,Dn Dn,ea #data,ea Dn,data,ea #data,ea ea ea,Dn Dn,ea #data,ea #ea Operand Size 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 Operation source destination destination immediate data destination destination source destination destination immediate data x destination destination destination destination source V destination destination immediate data V destination destination source -- 0 to set condition codes 3.2.4 Shift and Rotate Instructions The arithmetic shift instructions (ASR and ASL) and logical shift instructions (LSR and LSL) provide shift operations in both directions. The ROR, ROL, ROXR, and ROXL instructions perform rotate (circular shift) operations, with and without the extend bit. All shift and rotate operations can be performed on either registers or memory. Register shift and rotate operations shift all operand sizes. The shift count may be specified in the instruction operation word (to shift from 1-8 places) or in a register (modulo 64 shift count). Memory shift and rotate operations shift word-length operands one bit position only. The SWAP instruction exchanges the 16-bit halves of a register. Performance of shift/rotate instructions is enhanced so that use of the ROR and ROL instructions with a shift count of eight allows fast byte swapping. Table 3-4 is a summary of the shift and rotate operations. MOTOROLA MC68030 USER'S MANUAL 3-7 Instruction Set Summary Table 3-4. Shift and Rotate Operations. 0 X/C X/C X/C 0 0 X/C C C C X X C MSW LSW 3.2.5 Bit Manipulation Instructions Bit manipulation operations are accomplished using the following instructions: bit test (BTST), bit test and set (BSET), bit test and clear (BCLR), and bit test and change (BCHG). All bit manipulation operations can be performed on either registers or memory. The bit number is specified as immediate data or in a data register. Register operands are 32 bits long, and memory operands are 8 bits long. In Table 3-5, the summary of the bit manipulation operations, Z refers to bit 2, the zero bit of the status register. 3-8 MC68030 USER'S MANUAL MOTOROLA Instruction Set Summary Table 3-5. Bit Manipulation Operations Instruction BCHG BCLR Operand Syntax Dn,ea #data,ea Dn,ea #data,ea BSET Dn,ea #data,ea BTST Dn,ea #data,ea Operand Size Operation 8, 32 (bit number of destination) Z bit of destination 8, 32 8, 32 (bit number of destination) Z; 8, 32 -- 0 bit of destination 8, 32 (bit number of destination) Z; 8, 32 -- 1 bit of destination 8, 32 (bit number of destination) Z 8, 32 3.2.6 Bit Field Operations The MC68030 supports variable-length bit field operations on fields of up to 32 bits. The bit field insert (BFINS) instruction inserts a value into a bit field. Bit field extract unsigned (BFEXTU) and bit field extract signed (BFEXTS) extract a value from the field. Bit field find first one (BFFFO) finds the first bit that is set in a bit field. Also included are instructions that are analogous to the bit manipulation operations; bit field test (BFTST), bit field test and set (BFSET), bit field test and clear (BFCLR), and bit field test and change (BFCHG). Table 3- 6 is a summary of the bit field operations. Table 3-6. Bit Field Operations Instruction BFCHG BFCLR BFEXTS BFEXTU BFFFO BFINS BFSET BFTST Operand Syntax ea {offset:width} ea {offset:width} ea {offset:width},Dn ea {offset:width},Dn ea {offset:width},Dn Dn,ea {offset:width} ea {offset:width} ea {offset:width} Operand Size 1 -- 32 1 -- 32 1--32 1 -- 32 1 -- 32 1 -- 32 1 -- 32 1 -- 32 Operation Field Field 0's Field Field Dn; Sign Extended Field Dn; Zero Extended Scan for first bit set in field; offset Dn Dn Field 1's Field Field MSB N; (OR of all bits in field) Z NOTE: All bit field instructions set the N and Z bits as shown for BFTST before performing the specified operation. MOTOROLA MC68030 USER'S MANUAL 3-9 Instruction Set Summary 3.2.7 Binary-coded Decimal Instructions Five instructions support operations on binary-coded decimal (BCD) numbers. The arithmetic operations on packed BCD numbers are add decimal with extend (ABCD), subtract decimal with extend (SBCD), and negate decimal with extend (NBCD). PACK and UNPACK instructions aid in the conversion of byte encoded numeric data, such as ASCII or EBCDIC strings, to BCD data and vice versa. Table 3-7 is a summary of the BCD operations. Table 3-7. BCD Operations Instruction ABCD NBCD PACK SBCD UNPK 3-10 Operand Syntax Dn,Dn -(An) ea -(An),-(An) #data Dn,Dn,# data Dn,Dn -(An),-(An) -(An) #data Dn,Dn,#data Operand Size Operation 8 source10 + destination10 + X destination 8 8 0 - destination10 -X destination 168 168 8 8 816 816 unpackaged source + immediate data packed destination destination10 - source10 - X destination packed source unpacked source unpacked source + immediate data unpacked destination MC68030 USER'S MANUAL MOTOROLA Instruction Set Summary 3.2.8 Program Control Instructions A set of subroutine call and return instructions and conditional and unconditional branch instructions perform program control operations. The no operation instruction (NOP) may be used to force synchronization of the internal pipelines. Table 3-8 summarizes these instructions. Table 3-8. Program Control Operations Instruction Bcc DBcc Operand Syntax label Dn,label Scc ea BRA BSR JMP JSR NOP label label ea ea none RTD RTR RTS #d none none Operand Size Operation Integer and Floating-Point Conditional 8, 16, 32 if condition true, then PC + d PC 16 if condition false, then Dn -- 1 Dn if Dn -1, then PC + d PC 8 if condition true, then 1's destination; else 0's destination Unconditional 8, 16, 32 PC + d PC 8, 16, 32 SP -- 4 SP; PC(SP); PC + d PC none destination PC none SP -- 4 SP; PC (SP); destination PC none PC + 2 PC Returns 16 (SP) PC; SP + 4 + d SP none (SP) CCR; SP + 2 SP; (SP) PC; SP + 4 SP none (SP) PC; SP + 4 SP Letters cc in the integer instruction mnemonics Bcc, DBcc, and Scc specify testing one of the following conditions: CC -- Carry clear GE -- Greater or equal LS -- Lower or same PL -- Plus CS -- Carry set GT -- Greater than LT -- Less than T -- Always true* EQ -- Equal HI -- Higher MI -- Minus VC -- Overflow clear F -- Never true* LE -- -Less or equal NE -- Not equal VS -- Overflow set *Not applicable to the Bcc instructions. MOTOROLA MC68030 USER'S MANUAL 3-11 Instruction Set Summary 3.2.9 System Control Instructions Privileged instructions, trapping instructions, and instructions that use or modify the condition code register (CCR) provide system control operations. Table 3-9 summarizes these instructions. The TRAPcc instruction uses the same conditional tests as the corresponding program control instructions. All of these instructions cause the processor to flush the instruction pipe. Table 3-9. System Control Operations Instruction Operand Syntax Operand Size Operation Privileged ANDI #data,SR immediate data SR SR 16 EORI #data,SR 16 immediate data x SR SR MOVE ea,SR SR,ea 16 16 source SR SR destination MOVE USP,An An,USP 32 32 USP An An USP MOVEC Rc,Rn Rn,Rc 32 32 Rc Rn Rn Rc MOVES Rn, ea ea,Rn 8, 16, 32 Rn destination using DFC source using SFC Rn immediate data V SR SR ORI #data,SR 16 RESET none none assert RESET line RTE none none (SP) SR; SP + 2 SP; (SP) PC; SP + 4 SP; Restore stack according to format #data 16 STOP immediate data SR; STOP Trap Generating BKPT #data none run breakpoint cycle, then trap as illegal instruction CHK ea,Dn 16, 32 if Dn < 0 or Dn > (ea), then CHK exception CHK2 ea,Rn 8, 16, 32 none none SSP -- 2 SSP; Vector Offset (SSP); SSP -- 4 SSP; PC (SSP); SSP -- 2 SSP; SR (SSP); Illegal Instruction Vector Address PC TRAP #data none SSP -- 2 SSP; Format and Vector Offset(SSP) SSP -- 4 SSP; PC(SSP); SSP -- 2 SSP; SR(SSP); Vector Address PC TRAPcc none #data none 16, 32 if cc true, then TRAP exception TRAPV none ILLEGAL none if Rn < -lower bound or Rn > -upper bound, then CHK exception if V, then take overflow TRAP exception Condition Code Register ANDI #data,CCR 8 immediate data CCR CCR EORI #data,CCR 8 immediate data CCR CCR MOVE ea,CCR CCR,ea 16 16 source CCR CCR destination #data,CCR 8 immediate data V CCR CCR ORI 3-12 MC68030 USER'S MANUAL MOTOROLA Instruction Set Summary 3.2.10 Memory Management Unit Instructions The PFLUSH instructions flush the address translation caches (ATCs) and can optionally select only nonglobal entries for flushing. PTEST performs a search of the address translation tables, storing results in the MMU status register and loading the entry into the ATC. Table 3-10 summarizes these instructions. Table 3-10. MMU Instructions Instruction PFLUSHA PFLUSHA.N PFLUSH PFLUSH.N PTEST Operand Syntax none none (An) (An) (An) Operand Size none none none none none Operation Invalidate all ATC entries Invalidate all nonglobal ATC entries Invalidate ATC entries at effective address Invalidate nonglobal ATC entries at effective address Information about logical address MMU status register 3.2.11 Multiprocessor Instructions The TAS, CAS, and CAS2 instructions coordinate the operations of processors in multiprocessing systems. These instructions use read-modify-write bus cycles to ensure uninterrupted updating of memory. Coprocessor instructions control the coprocessor operations. Table 3-11 lists these instructions. Table 3-11. Multiprocessor Operations (Read-Modify-Write) Instruction Operand Syntax CAS Dc,Du,ea CAS2 Dc1:Dc2,Du1:Du2,( Rn):(Rn) ea TAS cpBcc cpDBcc cpGEN cpRESTORE cpSAVE cpScc cpTRAPcc MOTOROLA label label,Dn User Defined ea ea ea none #data Operand Size Operation Read-Modify-Write 8, 16, 32 destination -- Dc CC; if Z then Du destination else destinationDc 8, 16, 32 dual operand CAS destination -- 0; set condition codes; 1 destination [7] Coprocessor 16, 32 if cpcc true, then PC + d PC 16 if cpcc false then Dn -1 Dn if Dn -1, then PC + d PC User Defined operand coprocessor none restore coprocessor state from ea none save coprocessor state at ea 8 if cpcc true, then 1's destination; else 0's destination none if cpc true, then TRAPcc exception 16, 32 8 MC68030 USER'S MANUAL 3-13 Instruction Set Summary 3.3 INTEGER CONDITION CODES The CCR portion of the SR contains five bits which indicate the results of many integer instructions. Program and system control instructions use certain combinations of these bits to control program and system flow. The first four bits represent a condition resulting from a processor operation. The X bit is an operand for multiprecision computations; when it is used, it is set to the value of the C bit. The carry bit and the multiprecision extend bit are separate in the M68000 Family to simplify programming techniques that use them (refer to Table 3-8 as an example). The condition codes were developed to meet two criteria: * Consistency across instructions, uses, and instances * Meaningful Results no change unless it provides useful information Consistency across instructions means that all instructions that are special cases of more general instructions affect the condition codes in the same way. Consistency across instances means that all instances of an instruction affect the condition codes in the same way. Consistency across uses means that conditional instructions test the condition codes similarly and provide the same results, regardless of whether the condition codes are set by a compare, test, or move instruction. In the instruction set definitions, the CCR is shown as follows: X N Z V C where: X (extend) Set to the value of the C bit for arithmetic operations. Otherwise not affected or set to a specified result. N (negative) Set if the most significant bit of the result is set. Cleared otherwise. Z (zero) Set if the result equals zero. Cleared otherwise. V (overflow) Set if arithmetic overflow occurs. This implies that the result cannot be represented in the operand size. Cleared otherwise. C (carry) Set if a carry out of the most significant bit of the operand occurs for an addition. Also set if a borrow occurs in a subtraction. Cleared otherwise. 3-14 MC68030 USER'S MANUAL MOTOROLA Instruction Set Summary 3.3.1 Condition Code Computation Most operations take a source operand and a destination operand, compute, and store the result in the destination location. Single-operand operations take a destination operand, compute, and store the result in the destination location. Table 3-12 lists each instruction and how it affects the condition code bits. Table 3-12. Condition Code Computations (Sheet 1 of 2) X N Z V C ABCD Operations * U ? U ? C =-Decimal Carry Z =-Z Rm . . . R0 ADD, ADDI, ADDQ * * * ? ? V = Sm Dm Rm V Sm Dm Rm C = Sm Dm V Rm Dm V Sm Rm ADDX * * ? ? ? V = Sm Dm Rm V Sm Dm Rm C = Sm Dm V Rm Dm V Sm Rm Z = Z Rm . . . R0 AND, ANDI, EOR, EORI, MOVEQ, MOVE, OR, ORI CLR, EXT, NOT, TAS, TST -- * * 0 0 CHK -- * U U U CHK2, CMP2 -- U ? U ? Z = (R = LB) V (R = UB) C = (LB < = UB) (IR < LB) V (R > UB)) V = (UB <LB) (R >UB) (R <LB) SUB, SUBI, SUBQ * * * ? ? V = Sm Dm Rm V Sm Dm Rm C = Sm Dm V Rm Dm V Sm Rm SUBX * * ? ? ? V = Sm Dm Rm V Sm Dm Rm C = Sm Dm V Rm Dm V Sm Rm Z = Z Rm . . . R0 CAS, CAS2, CMP, CMPI, CMPM -- * * ? ? V = Sm Dm Rm V Sm Dm Rm C = Sm Dm V Rm Dm V Sm Rm DIVS, DUVI -- * * ? 0 V = Division Overflow MULS, MULU -- * * ? 0 V = Multiplication Overflow SBCD, NBCD * U U ? C = Decimal Borrow Z = Z Rm . . . R0 NEG * * * ? ? V = Dm Rm C = Dm V Rm NEGX * * ? ? ? V = Dm Rm C = Dm V Rm Z = Z Rm . . . R0 MOTOROLA MC68030 USER'S MANUAL Special Definition 3-15 Instruction Set Summary Table 3-12. Condition Code Computations (Continued) Operations X N Z V C Special Definition BTST, BCHG, BSET, BCLR -- -- ? -- -- Z = Dn BFTST, BFCHG, BFSET, BFCLR -- ? ? 0 0 N = Dm Z = Dm DM -1 . . . D0 BFEXTS, BFEXTU, BFFFO -- ? ? 0 0 N = Sm Z = Sm Sm -1 . . . S0 BFINS -- ? ? 0 0 N = Dm Z = Dm DM-1 . . . D0 ASL * * * * * 0 0 LSL, ROXL * * * 0 ? C = Dm -r + 1 LSR (r = 0) -- * * 0 0 ROXL (r = 0) -- * * 0 ? C=X ROL -- * * 0 ? C = Dm -r + 1 ROL (r = 0) -- * * 0 0 ASR, LSR, ROXR * * * 0 ? C = Dr -1 ASR, LSR (r = 0) -- * * 0 0 ASL (R = 0) V = Dm (Dm -1 V . . . V Dm -r) V Dm (Dm -1 V . . . + Dm -r) C = Dm -r + 1 ROXR (r = 0) -- * * 0 ? C=X ROR -- * * 0 ? C = Dr -1 ROR (r = 0) -- * * 0 0 -- U ? * = = = = Sm Dm = = 3-16 Not Affected Undefined, Result Meaningless Other -- See Special Definition General Case X=C N = Rm Z = Rm . . . R0 Destination Operand -- Most Significant Bit Destination Operand -- Most Significant Bit Rm R n r LB UB V Rm = = = = = = = = = Result Operand -- Most Significant Bit Register Tested Bit Number Shift Count Lower Bound Upper Bound Boolean AND Boolean OR NOT Rm MC68030 USER'S MANUAL MOTOROLA Instruction Set Summary 3.3.2 Conditional Tests Table 3-13 lists the condition names, encodings, and tests for the conditional branch and set instructions. The test associated with each condition is a logical formula using the current states of the condition codes. If this formula evaluates to one, the condition is true. If the formula evaluates to zero, the condition is false. For example, the T condition is always true, and the EQ condition is true only if the Z bit condition code is currently true. Table 3-13. Conditional Tests Mnemonic Condition Encoding Test T* True 0000 1 F* False 0001 0 HI High 0010 C *Z LS Low or Same 0011 C+Z CC(HS) Carry Clear 0100 C CS(LO) Carry Set 0101 C NE Not Equal 0110 Z EQ Equal 0111 Z VC Overflow Clear 1000 V VS Overflow Set 1001 V PL Plus 1010 N MI Minus 1011 N GE Greater or Equal 1100 N *V + N *V LT Less Than 1101 N *V + N *V GT Greater Than 1110 N *V *Z + N * V *Z LE Less or Equal 1111 Z + N *V + N * V * = Boolean AND + = Boolean OR N = Boolean NOT N *Not available for the Bcc instruction. MOTOROLA MC68030 USER'S MANUAL 3-17 Instruction Set Summary 3.4 INSTRUCTION SET SUMMARY Table 3-14 provides a alphabetized listing of the MC68030 instruction set listed by opcode, operation, and syntax. Table 3-14 use notational conventions for the operands, the subfields and qualifiers, and the operations performed by the instructions. In the syntax descriptions, the left operand is the source operand, and the right operand is the destination operand. The following list contains the notations used in Table 3-14. Notation for operands: PC -- Program counter SR -- Status register V -- Overflow condition code Immediate Data -- Immediate data from the instruction Source -- Source contents Destination -- Destination contents Vector -- Location of exception vector + inf -- Positive infinity -inf -- Negative infinity fmt -- Operand data format: byte (B) word (W), long (L), single (S), double (D), extended (X), or packed (P) FPm -- One of eight floating-point data registers (always specifies the source register) FPn -- One of eight floating-point data registers (always specifies the destination register) Notation for subfields and qualifiers: bit of (operand -- Selects a single bit of the operand ea {offset:width} -- Selects a bit field (operand) -- The contents of the referenced location operand 10 -- The operand is binary-coded decimal; operations are performed in decimal (address register) -- The register indirect operation -(address register) -- Indicates that the operand register points to the memory (address register) + -- #xxx or #data 3-18 -- Location of the instruction operand -- the optional mode qualifiers are -, +, (d), and (d,ix) Immediate data that follows the instruction word(s) MC68030 USER'S MANUAL MOTOROLA Instruction Set Summary Notations for operations that have two operands, written operand op operand , where op is one of the following: -- The source operand is moved to the destination operand -- The two operands are exchanged + -- The operands are added - -- The destination operand is subtracted from the source operand x -- The operands are multiplied / -- The source operand is divided by the destination operand < -- Relational test, true if source operand is less than destination operand > -- Relational test, true if source operand is greater than destination operand V -- Logical OR -- Logical exclusive OR -- Logical AND shifted by, rotated by -- The source operand is shifted or rotated by the number of positions specified by the second operand Notation for single-operand operations: -- The operand is logically complemented ~operand operand sign-extended-- operand tested -- Notation for other operations: TRAP -- The operand is sign extended; all bits of the upper portion are made equal to the high-order bit of the lower portion The operand is compared to zero and the condition codes are set appropriately Equivalent to Format/Offset Word (SSP); SSP -2 SSP; PC (SSP); SSP - 4 SSP; SR (SSP); SSP-2 SSP; (vector) PC STOP -- Enter the stopped state, waiting for the interrupts If condition then -- The condition is tested. If true, the operations operations else -- after "then'' are performed. If the condition is operations -- false and the optional "else'' clause is present, the operations after "else" are performed. If the condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example. MOTOROLA MC68030 USER'S MANUAL 3-19 Instruction Set Summary Table 3-14. Instruction Set Summary (Sheet 1 of 5) Opcode ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ANDI to CCR ANDI to SR Operation Source10 + Destination10 + X Destination Source + Destination -Destination Source + Destination Destination Immediate Data + Destination Destination Immediate Data + Destination Destination Source + Destination + X Destination Source Destination Destination Immediate Data Destination Destination Source CCR CCR If supervisor state then Source SR SR else TRAP ASL,ASR Destination Shifted by count Destination If (condition true) then PC + d PC (number of Destination) Z; (number of Destination) bit number of Destination BCLR (bit number of Destination) Z; 0 bit number of Destination BFCHG (bit field of Destination) bit field of Destination BFCLR 0 bit field of Destination BFEXTS bit field of Source Dn BFEXTU (bit offset of Source Dn BFFFO (bit offset of Source Bit Scan Dn BFINS Dn bit field of Destination BFSET 1s bit field of Destination BFTST bit field of Destination BKPT Run breakpoint acknowledge cycle; TRAP as illegal instruction BRA PC + d PC BSET ~ (bit number of Destination) Z; 1 bit number of Destination BSR SP - 4 SP; PC (SP); PC + d PC BTST -(bit number of Destination) Z; Bcc BCHG 3-20 MC68030 USER'S MANUAL Syntax ABCD Dy,Dx ABCD -(Ay),-(Ax) ADD ea,Dn ADD Dn,ea ADDA ea,An ADDI #data,ea ADDQ #data,ea ADDX Dy,Dx ADDX -(Ay),-(Ax) AND ea,Dn AND Dn,ea ANDI #data,ea ANDI #data,CCR ANDI #data,SR ASd Dx,Dy ASd #data,Dy ASd ea Bcc (label BCHG Dn,eaBCHG #data,ea BCLR Dn,eaBCLR #data,ea BFCHG ea{offset:width} BFCLR ea{offset:width} BFEXTS ea{offset:width},Dn BFEXTU ea{offset:width},Dn BFFFO ea{offset:width},Dn BFINS Dn,ea{offset:width} BFSET ea{offset:width} BFTST ea{offset:width} BKPT # data BRA (label BSET Dn,eaBSET #data,ea BSR (label BTST Dn,eaBTST #data,ea MOTOROLA Instruction Set Summary Table 3-14. Instruction Set Summary (Sheet 2 of 5) Opcode CAS CAS2 CHK CHK2 CLR CMP CMPA CMPI CMPM CMP2 cpBcc cpDBcc cpGEN Operation CAS Destination Compare Operand cc; if Z, Update Operand Destination else Destination Compare Operand CAS2 Destination 1 Compare 1 cc; if Z, Destination 2 Compare cc; if Z, Update 1 Destination 1; Update 2 Destination 2 else Destination 1 Compare 1; Destination 2 Compare 2 If Dn < 0 or >-Source then TRAP If Rn < lower bound or Rn > upper bound then TRAP 0 Destination Destination -- Source cc Destination -- Source Destination -- Immediate Data Destination -- Source cc Compare Rn < lower-bound or Rn > upper-bound and Set Condition Codes If cpcc true then scanPC + d PC If cpcc false then (Dn -1 Dn; if Dn -1 then scanPC + d PC Pass Command Word to Coprocessor cpRESTORE If supervisor state then Restore Internal State of Coprocessor else TRAP cpSAVE If supervisor state the Save Internal State of Coprocessor else TRAP cpScc If cpcc true then 1s Destination else 0s Destination cpTRAPcc If cpcc true then TRAP DBcc DIVS DIVSL If condition false then (Dn-1 Dn; If Dn -1 then PC + d PC) Destination/Source Destination DIVU DIVUL Destination/Source Destination EOR EORI Source Destination Destination Immediate Data Destination Destination MOTOROLA MC68030 USER'S MANUAL Syntax CAS Dc,Du,eaCAS2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) CHK ea,Dn CHK2 ea,Rn CLR ea CMP ea,Dn CMPA ea,An CMPI #data,ea CMPM (Ay) +,(Ax) + CMP2 ea,Rn cpBcc (label cpDBcc Dn,(label cpGEN (parameters as defined by coprocessorL cpRESTORE ea cpSAVE save cpTRAPcc cpTRAPcc #data DBcc Dn,(label DIVS.W ea,Dn32/16 16r:16q DIVS.L ea,Dq 32/32 32q DIVS.L ea,Dr:Dq 64/32 32r:32q DIVSL.L ea,Dr:Dq32/32 32r:32q DIVU.W ea,Dn32/16 16r:16q DIVU.L ea,Dq 32/32 32q DIVU.L ea,Dr:Dq 64/32 32r:32q DIVUL.L ea,Dr:Dq32/32 32r:32q EOR Dn,ea EORI #data,ea 3-21 Instruction Set Summary Table 3-14. Instruction Set Summary (Sheet 3 of 5) Opcode EORI to CCR EORI to SR EXG EXT EXTB ILLEGAL JMP JSR LEA LINK LSL,LSR Operation Source CCR CCR If supervisor state then Source SR SR else TRAP Rx Ry Destination Sign-Extended Destination SSP-2 SSP; Vector Offset (SSP); SSP-4 SSP; PC (SSP); SSP-2 SSP; SR (SSP); Illegal Instruction Vector Address PC Destination Address PC SP-4 SP; PC (SP) Destination Address PC ea An SP -- 4 SP; An (SP) SP An, SP + d SP Destination Shifted by count Destination Syntax EORI #data,CCR EORI #data,SR EXG Dx,Dy EXG Ax,Ay EXG Dx,Ay EXG Ay,Dx EXT.W Dn extend byte to word EXT.L L Dn extend word to long word EXTB.L Dn extend byte to long word ILLEGAL JMP ea JSR ea LEA ea,An LINK An, #(displacement Source Destination Source Destination CCR Destination LSd5 Dx,Dy LSd5 #data,Dy LSd5 ea MOVE ea,ea MOVEA ea,An MOVE CCR,ea Source CCR MOVE ea,CCR MOVE SR,ea MOVEP If supervisor state then SR Destination else TRAP If supervisor state then Source SR else TRAP If supervisor state then USP An or An USP else TRAP If supervisor state then Rc Rn or Rn Rc else TRAP Registers Destination Source Registers Source Destination MOVEQ Immediate Data Destination MOVE MOVEA MOVE from CCR MOVE to CCR MOVE from SR MOVE to SR MOVE USP MOVEC MOVEM 3-22 MC68030 USER'S MANUAL MOVE ea,SR MOVE USP,An MOVE An,USP MOVEC Rc,Rn MOVEC Rn,Rc MOVEM register list,eaMOVEM ea,register list MOVEP Dx,(d,Ay) MOVEP (d,Ay),Dx MOVEQ #data,Dn MOTOROLA Instruction Set Summary Table 3-14. Instruction Set Summary (Sheet 4 of 5) Opcode MOVES MULS Operation If supervisor state then Rn Destination [DFC] or Source [SFC] Rn else TRAP Source y-Destination Destination MULU Source y-Destination Destination NBCD NEG NEGX NOP NOT OR 0 -- (Destination10) -- X Destination 0 -- (Destination) Destination 0 -- (Destination) -- X Destination None Destination Destination Source V Destination Destination ORI ORI to CCR ORI to SR PACK PEA PFLUSH PLOAD PMOVE PTEST RESET ROL,ROR ROXL, ROXR MOTOROLA Immediate Data V Destination Destination Source V CCR CCR If supervisor state then Source V SR SR else TRAP Source (Unpacked BCD) + adjustment Destintion (Packed BCD) Sp -4 SP; ea (SP) If supervisor state then invalidate instruction and data ATC entries for destination address else TRAP If supervisor state then entry ATC else TRAP If supervisor state then (Source) MRn or MRn (Destination) If supervisor state then logical address status MMUSR; entry ATC else TRAP If supervisor state then Assert RSTO Line else TRAP Destination Rotated by count Destination Destination Rotated with X by count Destination MC68030 USER'S MANUAL Syntax MOVES Rn,eaMOVES ea,Rn MULS.W ea,Dn MULS.L ea,Dl MULS.L ea,Dh:Dl MULU.W ea,Dn MULU.L ea,Dl MULU.L ea,Dh:Dl NBCD ea NEG ea NEGX ea NOP NOT ea OR ea,Dn OR Dn,ea ORI #data,ea ORI #data,CCR 16 x 16 32 32 x 32 32 32 x 32 64 16 x 16 32 32 x 32 32 32 x 32 64 ORI #data,SR PACK -(Ax),-(Ay),#(adjustment PACK Dx,Dy,#(adjustment PEA ea RESET ROd5 Rx,Dy ROd5 #data,Dy ROd5 ea ROXd5 Dx,Dy ROXd5 #data,Dy ROXd5 ea 3-23 Instruction Set Summary Table 3-14. Instruction Set Summary (Concluded) Opcode RTD RTE RTM RTR RTS SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX Operation (SP) PC; SP + 4 + d SP If-supervisor-state then (SP) SR; SP+2 SP; (SP) PC; SP + 4 SP; restore state and deallocate stack according to (SP) else TRAP Reload Saved Module State from Stack (SP) CCR; SP + 2 SP; (SP) PC; SP + 4 SP (SP) PC; SP + 4 SP Destination10 --Source10 -X Destination If condition true then 1s Destination else 0s Destination If supervisor state then Immediate Data SR; STOP else TRAP Destination -- Source Destination Destination -- Source Destination Destination -- Immediate Data Destination Destination -- Immediate Data Destination Destination -- Source - X Destination Register [31:16] Register [15:0] Destination Tested Condition Codes; 1 bit 7 of Destination SSP -2 SSP; Format/Offset (SSP); SSP - 4 SSP; PC (SSP); SSP - 2 SSP; SR (SSP); Vector Address PC TRAPcc If cc then TRAP SWAP TAS TRAP TRAPV TST UNLK UNPK Syntax RTD #displacement RTE RTM Rn RTR RTS SBCD Dx,Dy SBCD -(Ax),-(Ay) Scc ea STOP #data SUB ea,Dn SUB Dn,ea SUBA ea,An SUBI #data,ea SUBQ #data,ea SUBX Dx,Dy SUBX -(Ax),-(Ay) SWAP Dn TAS ea TRAP # (vector TRAPcc TRAPcc.W # dataTRAPcc.L # data If V then TRAP TRAPV Destination Tested Condition Codes TST ea An SP; (SP) An; SP + 4 SP UNLK An Source (Packed BCD) + adjustment Destination (Unpacked BCD) UNPACK -(Ax),-(Ay),#(adjustment UNPACK Dx,Dy,#(adjustment NOTES: 1. Specifies either the instruction (IC), data (DC), or IC/DC caches. 2. Where r is rounding precision, S or D. 3. A list of any combination of the eight floating-point data registers, with individual register names separated by a slash (/) and/or contiguous blocks of registers specified by the first and last register names separated by a dash ( -). 4. A list of any combination of the three floating-point system control registers (FPCR, FPSR, and FPIAR) with indvidual register names separated by a slash (/). 5. Where d is direction, L or R. 3-24 MC68030 USER'S MANUAL MOTOROLA Instruction Set Summary 3.5 INSTRUCTION EXAMPLES The following paragraphs provide examples of how to use selected instructions. 3.5.1 Using the CAS and CAS2 Instructions The CAS instruction compares the value in a memory location with the value in a data register, and copies a second data register into the memory location if the compared values are equal. This provides a means of updating system counters, history information, and globally shared pointers. The instruction uses an indivisible read-modify-write cycle; after CAS reads the memory location, no other instruction can change that location before CAS has written the new value. This provides security in single-processor systems, in multitasking environments, and in multiprocessor environments. In a single-processor system, the operation is protected from instructions of an interrupt routine. In a multitasking environment, no other task can interfere with writing the new value of a system variable. In a multiprocessor environment, the other processors must wait until the CAS instruction completes before accessing a global pointer. The following code fragment shows a routine to maintain a count, in location SYS_CNTR, of the executions of an operation that may be performed by any process or processor in a system. The routine obtains the current value of the count in register D0 and stores the new count value in register D1. The CAS instruction copies the new count into SYS_CNTR if it is valid. However, if another user has incremented the counter between the time the count was stored and the read-modify-write cycle of the CAS instruction, the write portion of the cycle copies the new count in SYS_CNTR into D0, and the routine branches to repeat the test. The following code sequence guarantees that SYS_CNTR is correctly incremented. INC_LOOP MOTOROLA MOVE.W MOVE.W ADDQ.W CAS.W BNE SYS_CNTR,D0 D0,D1 #1,D1 D0,D1,SYS_CNTR INC_LOOP get the old value of the counter make a copy of it and increment it if countr value is still the same, update it if not, try again MC68030 USER'S MANUAL 3-25 Instruction Set Summary The CAS and CAS2 instructions together allow safe operations in the manipulation of system linked lists. Controlling a single location, HEAD in the example, manages a last-infirst-out linked list (see Figure 3-2). If the list is empty, HEAD contains the NULL pointer (0); otherwise, HEAD contains the address of the element most recently added to the list. The code fragment shown in Figure 3-2 illustrates the code for inserting an element. The MOVE instructions load the address in location HEAD into D0 and into the NEXT pointer in the element being inserted, and the address of the new element into D1. The CAS instruction stores the address of the inserted element into location HEAD if the address in HEAD remains unaltered. If HEAD contains a new address, the instruction loads the new address into D0 and branches to the second MOVE instruction to try again. The CAS2 instruction is similar to the CAS instruction except that it performs two comparisons and updates two variables when the results of the comparisons are equal. If the results of both comparisons are equal, CAS2 copies new values into the destination addresses. If the result of either comparison is not equal, the instruction copies the values in the destination addresses into the compare operands. SINSERT SILOOP MOVE.L MOVE.L MOVE.L CAS.L BNE HEAD.D0 D0, (NEXT, A1) A1, D1 D0, D1, HEAD SILOOP ALLOCATE NEW ENTRY, ADDRESS IN A1 MOVE HEAD POINTER VALUE TO D0 ESTABLISH FORWARD LINK IN NEW ENTRY MOVE NEW ENTRY POINTER VALUE TO D1 IF WE STILL POINT TO TOP OF STACK, UPDATE THE HEAD POINTER IF NOT, TRY AGAIN BEFORE INSERTING AN ELEMENT: ENTRY ENTRY + NEXT ? NEW + NEXT ENTRY + NEXT HEAD AFTER INSERTING AN ELEMENT: ENTRY ENTRY + NEXT + NEXT ENTRY + NEXT HEAD NEW Figure 3-2. Linked List Insertion 3-26 MC68030 USER'S MANUAL MOTOROLA Instruction Set Summary The next code (see Figure 3-3) fragment shows the use of a CAS2 instruction to delete an element from a linked list. The first LEA instruction loads the effective address of HEAD into A0. The MOVE instruction loads the address in pointer HEAD into D0. The TST instruction checks for an empty list, and the BEQ instruction branches to a routine at label SDEMPTY if the list is empty. Otherwise, a second LEA instruction loads the address of the NEXT pointer in the newest element on the list into A1, and the following MOVE instruction loads the pointer contents into D1. The CAS2 instruction compares the address of the newest structure to the value in HEAD and the address in D1 to the pointer in the address in A1. If no element has been inserted or deleted by another routine while this routine has been executing, the results of these comparisons are equal, and the CAS2 instruction stores the new value into location HEAD. If an element has been inserted or deleted, the CAS2 instruction loads the new address in location HEAD into D0, and the BNE instruction branches to the TST instruction to try again. SDELETE SDLOOP LEA MOVE.L TST.L BEQ LEA MOVE.L CAS2.L HEAD, A0 (A0), D0 D0 SDEMPTY (NEXT, D0), A1 (A1), D1 D0:D1, D1:D1, (A0):(A1) BNE SDLOOP SDEMPTY LOAD ADDRESS OF HEAD POINTER INTO A0 MOVE VALUE OF HEAD POINTER INTO D0 CHECK FOR NULL HEAD POINTER IF EMPTY, NOTHING TO DELETE LOAD ADDRESS OF FORWARD LINK INTO A1 PUT FORWARD LINK VALUE IN D1 IF STILL POINT TO ENTRY TO BE DELETED, THEN UPDATE HEAD AND FORWARD POINTERS IF NOT, TRY AGAIN SUCCESSFUL DELETION, ADDRESS OF DELETED ENTRY IN D0 (MAY BE NULL) BEFORE DELETING AN ELEMENT: ENTRY ENTRY + NEXT + NEXT ENTRY + NEXT HEAD AFTER DELETING AN ELEMENT: ENTRY ENTRY + NEXT + NEXT ENTRY + NEXT HEAD Figure 3-3. Linked List Deletion MOTOROLA MC68030 USER'S MANUAL 3-27 Instruction Set Summary The CAS2 instruction can also be used to correctly maintain a first-in-first-out doubly linked list. A doubly linked list needs two controlled locations, LIST_PUT and LIST_GET, which contain pointers to the last element inserted in the list and the next to be removed, respectively. If the list is empty, both pointers are NULL (0). The code fragment shown in Figure 3-4 illustrates the insertion of an element in a doubly linked list. The first two instructions load the effective addresses of LIST_PUT and LIST_GET into registers A0 and A1, respectively. The next instruction moves the address of the new element into register D2. Another MOVE instruction moves the address in LIST_PUT into register D0. At label DILOOP, a TST instruction tests the value in D0, and the BEQ instruction branches to the MOVE instruction when D0 is equal to zero. Assuming the list is empty, this MOVE instruction is executed next; it moves the zero in D0 into the NEXT and LAST pointers of the new element. Then the CAS2 instruction moves the address of the new element into both LIST_PUT and LIST_GET, assuming that both of these pointers still contain zero. If not, the BNE instruction branches to the TST instruction at label DILOOP to try again. This time, the BEQ instruction does not branch, and the following MOVE instruction moves the address in D0 to the NEXT pointer of the new element. The CLR instruction clears register D1 to zero, and the MOVE instruction moves the zero into the LAST pointer of the new element. The LEA instruction loads the address of the LAST pointer of the most recently inserted element into register A1. Assuming the LIST_PUT pointer and the pointer in A1 have not been changed, the CAS2 instruction stores the address of the new element into these pointers. The code fragment to delete an element from a doubly linked list is similar (see Figure 3-5). The first two instructions load the effective addresses of pointers LIST_PUT and LIST_GET into registers A0 and A1, respectively. The MOVE instruction at label DDLOOP moves the LIST_GET pointer into register D1. The BEQ instruction that follows branches out of the routine when the pointer is zero. The MOVE instruction moves the LAST pointer of the element to be deleted into register D2. Assuming this is not the last element in the list, the Z condition code is not set, and the branch to label DDEMPTY does not occur. The LEA instruction loads the address of the NEXT pointer of the element at the address in D2 into register A2. The next instruction, a CLR instruction, clears register D0 to zero. The CAS2 instruction compares the address in D1 to the LIST-GET pointer and to the address in register A2. If the pointers have not been updated, the CAS2 instruction loads the address in D2 into the LIST_GET pointer and zero into the address in register A2. 3-28 MC68030 USER'S MANUAL MOTOROLA Instruction Set Summary DINSERT DILOOP DIEMPTY LEA LEA MOVE.L MOVE.L TST.L BEQ MOVE.L CLR.L MOVE.L LEA CAS2.L BNE BRA MOVE.L MOVE.L CAS2.L BNE LIST_PUT, A0 LIST_GET, A1 A2, D2 (A0), D0 D0 DIEMPTY D0, (NEXT, A2) D1 D1, (LAST, A2) (LAST, D0), A1 D0:D1,D2:D2,(A0):(A1) DILOOP DIDONE D0, (NEXT, A2) D0, (LAST, A2) D0:D0,D2:D2,(A0):(A1) DILOOP DIDONE (ALLOCATE NEW LIST ENTRY, LOAD ADDRESS INTO A2) LOAD ADDRESS OF HEAD POINTER INTO A0 LOAD ADDRESS OF TAIL POINTER INTO A1 LOAD NEW ENTRY POINTER INTO D2 LOAD POINTER TO HEAD ENTRY INTO D0 IS HEAD POINTER NULL, (0 ENTRIES IN LIST)? IF SO, WE NEED ONLY TO ESTABLISH POINTERS PUT HEAD POINTER INTO FORWARD POINTER OF NEW ENTRY PUT NULL POINTER VALUE INTO D1 PUT NULL POINTER IN BACKWARD POINTER OF NEW ENTRY LOAD BACKWARD POINTER OF OLD HEAD ENTRY INTO A1 IF WE STILL POINT TO OLD HEAD ENTRY, UPDATE POINTERS IF NOT, TRY AGAIN PUT NULL POINTER IN FORWARD POINTER OF NEW ENTRY PUT NULL POINTER IN BACKWARD POINTER OF NEW ENTRY IF WE STILL HAVE NO ENTRIES, SET BOTH POINTERS TO THIS ENTRY IF NOT, TRY AGAIN SUCCESSFUL LIST ENTRY INSERTION BEFORE INSERTING NEW ENTRY: ENTRY + LAST ENTRY + NEXT + LAST ENTRY + NEXT NEW ENTRY + LAST + NEXT LIST_GET LIST_PUT AFTER INSERTING NEW ENTRY: ENTRY + LAST ENTRY + NEXT + LAST + NEXT LIST_PUT ENTRY + LAST + NEXT LIST_GET Figure 3-4. Doubly Linked List Insertion When the list contains only one element, the routine branches to the CAS2 instruction at label DDEMPTY after moving a zero pointer value into D2. This instruction checks the addresses in LIST_PUT and LIST_GET to verify that no other routine has inserted another element or deleted the last element. Then the instruction moves zero into both pointers, and the list is empty. MOTOROLA MC68030 USER'S MANUAL 3-29 Instruction Set Summary DDELETE DDLOOP DDEMPTY LEA LEA MOVE.L BEQ MOVE.L BEQ LEA CLR.L CAS2.L BNE BRA CAS2.L BNE LIST_PUT, A0 LIST_GET, A1 (A1),D1 DDDONE (LAST,D1),D2 DDEMPTY (NEXT,D2),A2 D0 D1:D1,D2:D0,(A1):(A2) DDLOOP DDDONE D1:D1,D2:D2,(A1):(A0) DDLOOP DDDONE GET ADDRESS OF HEAD POINTER IN A0 GET ADDRESS OF TAIL POINTER IN A1 MOVE TAIL POINTER INTO D1 IF NO LIST, QUIT PUT BACKWARD POINTER IN D2 IF ONLY ONE ELEMENT, UPDATE POINTERS PUT ADDRESS OF FORWARD POINTER IN A2 PUT NULL POINTER VALUE IN D0 IF BOTH POINTERS STILL POINT TO THIS ENTRY , UPDATE THEM IF NOT, TRY AGAIN IF STILL FIRST ENTRY, SET HEAD AND TAIL POINTERS TO NULL IF NOT, TRY AGAIN SUCCESSFUL ENTRY DELETION, ADDRESS OF DELETED ENTRY IN D1 (MAY BE NULL) BEFORE DELETING ENTRY: ENTRY + LAST ENTRY + NEXT + LAST ENTRY + NEXT + LAST + NEXT LIST_GET LIST_PUT AFTER DELETING ENTRY: ENTRY + LAST ENTRY + NEXT + LAST LIST_PUT ENTRY + NEXT LIST_GET + LAST + NEXT DELETED ENTRY Figure 3-5. Doubly Linked List Deletion 3.5.2 Nested Subroutine Calls The LINK instruction pushes an address onto the stack, saves the stack address at which the address is stored, and reserves an area of the stack. Using this instruction in a series of subroutine calls results in a linked list of stack frames. The UNLK instruction removes a stack frame from the end of the list by loading an address into the stack pointer and pulling the value at that address from the stack. When the operand of the instruction is the address of the link address at the bottom of a stack frame, the effect is to remove the stack frame from the stack and from the linked list. 3-30 MC68030 USER'S MANUAL MOTOROLA Instruction Set Summary 3.5.3 Bit Field Operations One data type provided by the MC68030 is the bit field, consisting of as many as 32 consecutive bits. A bit field is defined by an offset from an effective address and a width value. The offset is a value in the range of 231 through 231 1 from the most significant bit (bit 7) at the effective address. The width is a positive number, 1-32. The most significant bit of a bit field is bit 0; the bits number in a direction opposite to the bits of an integer. The instruction set includes eight instructions that have bit field operands. The insert bit field (BFINS) instruction inserts a bit field stored in a register into a bit field. The extract bit field signed (BFEXTS) instruction loads a bit field into the least significant bits of a register and extends the sign to the left, filling the register. The extract bit field unsigned (BFEXTU) also loads a bit field, but zero fills the unused portion of the destination register. The set bit field (BFSET) instruction sets all the bits of a field to ones. The clear bit field (BFCLR) instruction clears a field. The change bit field (BFCHG) instruction complements all the bits in a bit field. These three instructions all test the previous value of the bit field, setting the condition codes accordingly. The test bit field (BFTST) instruction tests the value in the field, setting the condition codes appropriately without altering the bit field. The find first one in bit field (BFFFO) instruction scans a bit field from bit 0 to the right until it finds a bit set to one and loads the bit offset of the first set bit into the specified data register. If no bits in the field are set, the field offset and the field width is loaded into the register. An important application of bit field instructions is the manipulation of the exponent field in a floating-point number. In the IEEE standard format, the most significant bit is the sign bit of the mantissa. The exponent value begins at the next most significant bit position; the exponent field does not begin on a byte boundary. The extract bit field (BFEXTU) instruction and the BFTST instruction are the most useful for this application, but other bit field instructions can also be used. Programming of input and output operations to peripherals requires testing, setting, and inserting of bit fields in the control registers of the peripherals, which is another application for bit field instructions. However, control register locations are not memory locations; therefore, it is not always possible to insert or extract bit fields of a register without affecting other fields within the register. MOTOROLA MC68030 USER'S MANUAL 3-31 Instruction Set Summary Another widely used application for bit field instructions is bit-mapped graphics. Because byte boundaries are ignored in these areas of memory, the field definitions used with bit field instructions are very helpful. 3.5.4 Pipeline Synchronization with the Nop Instruction Although the no operation (NOP) instruction performs no visible operation, it serves an important purpose. It forces synchronization of the integer unit pipeline by waiting for all pending bus cycles to complete. All previous integer instructions and floating-point external operand accesses complete execution before the NOP begins. The NOP instruction does not synchronize the FPU pipeline; floating-point instructions with floating-point register operand destinations can be executing when the NOP begins. MOTOROLA MC68030 USER'S MANUAL 3-32 SECTION 4 PROCESSING STATES This section describes the processing states of the MC68030. It describes the functions of the bits in the supervisor portion of the status register and the actions taken by the processor in response to exception conditions. Unless the processor has halted, it is always in either the normal or the exception processing state. Whenever the processor is executing instructions or fetching instructions or operands, it is in the normal processing state. The processor is also in the normal processing state while it is storing instruction results or communicating with a coprocessor. NOTE Exception processing refers specifically to the transition from normal processing of a program to normal processing of system routines, interrupt routines, and other exception handlers. Exception processing includes all stacking operations, the fetch of the exception vector, and filling of the instruction pipe caused by an exception. It has completed when execution of the first instruction of the exception handler routine begins. The processor enters the exception processing state when an interrupt is acknowledged, when an instruction is traced or results in a trap, or when some other exceptional condition arises. Execution of certain instructions or unusual conditions occurring during the execution of any instructions can cause exceptions. External conditions, such as interrupts, bus errors, and some coprocessor responses, also cause exceptions. Exception processing provides an efficient transfer of control to handlers and routines that process the exceptions. A catastrophic system failure occurs whenever the processor receives a bus error or generates an address error while in the exception processing state. This type of failure halts the processor. For example, if during the exception processing of one bus error another bus error occurs, the MC68030 has not completed the transition to normal processing and has not completed saving the internal state of the machine, so the processor assumes that the system is not operational and halts. Only an external reset can restart a halted processor. (When the processor executes a STOP instruction, it is in a special type of normal processing state, one without bus cycles. It is stopped, not halted.) MOTOROLA MC68030 USER'S MANUAL 4-1 Processing States 4.1 PRIVILEGE LEVELS The processor operates at one of two levels of privilege: the user level or the supervisor level. The supervisor level has higher privileges than the user level. Not all processor or coprocessor instructions are permitted to execute in the lower privileged user level, but all are available at the supervisor level. This allows a separation of supervisor and user so the supervisor can protect system resources from uncontrolled access. The processor uses the privilege level indicated by the S bit in the status register to select either the user or supervisor privilege level and either the user stack pointer or a supervisor stack pointer for stack operations. The processor identifies a bus access (supervisor or user mode) via the function codes so that differentiation between supervisor and user can be maintained. The memory management unit uses the indication of privilege level to control and translate memory accesses to protect supervisor code, data, and resources from access by user programs. In many systems, the majority of programs execute at the user level. User programs can access only their own code and data areas and can be restricted from accessing other information. The operating system typically executes at the supervisor privilege level. It has access to all resources, performs the overhead tasks for the user level programs, and coordinates their activities. 4.1.1 Supervisor Privilege Level The supervisor level is the higher privilege level. The privilege level is determined by the S bit of the status register; if the S bit is set, the supervisor privilege level applies, and all instructions are executable. The bus cycles for instructions executed at the supervisor level are normally classified as supervisor references, and the values of the function codes on FC0-FC2 refer to supervisor address spaces. In a multitasking operating system, it is more efficient to have a supervisor stack space associated with each user task and a separate stack space for interrupt associated tasks. The MC68030 provides two supervisor stacks, master and interrupt; the M bit of the status register selects which of the two is active. When the M bit is set to one, supervisor stack pointer references (either implicit or by specifying address register A7) access the master stack pointer (MSP). The operating system sets the MSP for each task to point to a taskrelated area of supervisor data space. This separates task-related supervisor activity from asynchronous, I/O-related supervisor tasks that may be only coincidental to the currently executing task. The master stack (MSP) can separately maintain task control information for each currently executing user task, and the software updates the MSP when a task switch is performed, providing an efficient means for transferring task-related stack items. The other supervisor stack (ISP) can be used for interrupt control information and workspace area as interrupt handling routines require. 4-2 MC68030 USER'S MANUAL MOTOROLA Processing States When the M bit is clear, the MC68030 is in the interrupt mode of the supervisor privilege level, and operation is the same as in the MC68000, MC68008, and MC68010 supervisor mode. (The processor is in this mode after a reset operation.) All supervisor stack pointer references access the interrupt stack pointer (ISP) in this mode. The value of the M bit in the status register does not affect execution of privileged instructions; both master and interrupt modes are at the supervisor privilege level. Instructions that affect the M bit are MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, and RTE. Also, the processor automatically saves the M-bit value and clears it in the SR as part of the exception processing for interrupts. All exception processing is performed at the supervisor privilege level. All bus cycles generated during exception processing are supervisor references, and all stack accesses use the active supervisor stack pointer. 4.1.2 User Privilege Level The user level is the lower privilege level. The privilege level is determined by the S bit of the status register; if the S bit is clear, the processor executes instructions at the user privilege level. Most instructions execute at either privilege level, but some instructions that have important system effects are privileged and can only be executed at the supervisor level. For instance, user programs are not allowed to execute the STOP instruction or the RESET instruction. To prevent a user program from entering the supervisor privilege level, except in a controlled manner, instructions that can alter the S bit in the status register are privileged. The TRAP #n instruction provides controlled access to operating system services for user programs. MOTOROLA MC68030 USER'S MANUAL 4-3 Processing States The bus cycles for an instruction executed at the user privilege level are classified as user references, and the values of the function codes on FC0-FC2 specify user address spaces. The memory management unit of the processor, when it is enabled, uses the value of the function codes to distinguish between user and supervisor activity and to control access to protected portions of the address space. While the processor is at the user level, references to the system stack pointer implicitly, or to address register seven (A7) explicitly, refer to the user stack pointer (USP). 4.1.3 Changing Privilege Level To change from the user to the supervisor privilege level, one of the conditions that causes the processor to perform exception processing must occur. This causes a change from the user level to the supervisor level and can cause a change from the master mode to the interrupt mode. Exception processing saves the current values of the S and M bits of the status register (along with the rest of the status register) on the active supervisor stack, and then sets the S bit, forcing the processor into the supervisor privilege level. When the exception being processed is an interrupt and the M bit is set, the M bit is cleared, putting the processor into the interrupt mode. Execution of instructions continues at the supervisor level to process the exception condition. To return to the user privilege level, a system routine must execute one of the following instructions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or RTE. The MOVE, ANDI, EORI, and ORI to SR and RTE instructions execute at the supervisor privilege level and can modify the S bit of the status register. After these instructions execute, the instruction pipeline is flushed and is refilled from the appropriate address space. This is indicated externally by the assertion of the REFILL signal. The RTE instruction returns to the program that was executing when the exception occurred. It restores the exception stack frame saved on the supervisor stack. If the frame on top of the stack was generated by an interrupt, trap, or instruction exception, the RTE instruction restores the status register and program counter to the values saved on the supervisor stack. The processor then continues execution at the restored program counter address and at the privilege level determined by the S bit of the restored status register. If the frame on top of the stack was generated by a bus fault (bus error or address error exception), the RTE instruction restores the entire saved processor state from the stack. 4-4 MC68030 USER'S MANUAL MOTOROLA Processing States 4.2 ADDRESS SPACE TYPES The processor specifies a target address space for every bus cycle with the function code signals according to the type of access required. In addition to distinguishing between supervisor/user and program/data, the processor can identify special processor cycles, such as the interrupt acknowledge cycle, and the memory management unit can control accesses and translate addresses appropriately. Table 4-1 lists the types of accesses defined for the MC68030 and the corresponding values of function codes FC0-FC2. Table 4-1. Address Space Encodings FC2 0 0 0 0 1 1 1 1 FC1 0 0 1 1 0 0 1 1 FC0 0 1 0 1 0 1 0 1 Address Space (Undefined, Reserved)* User Data Space User Program Space (Undefined, Reserved)* (Undefined, Reserved)* Supervisor Data Space Supervisor Program Space CPU Space *Address space 3 is reserved for user definition; whereas, 0 and 4 are reserved for future use by Motorola. The memory locations of user program and data accesses are not predefined. Neither are the locations of supervisor data space. During reset, the first two long words beginning at memory location zero in the supervisor program space are used for processor initialization. No other memory locations are explicitly defined by the MC68030. A function code of $7 ([FC2:FC0] = 111) selects the CPU address space. This is a special address space that does not contain instructions or operands but is reserved for special processor functions. The processor uses accesses in this space to communicate with external devices for special purposes. For example, all M68000 processors use the CPU space for interrupt acknowledge cycles. The MC68020 and MC68030 also generate CPU space accesses for breakpoint acknowledge and coprocessor operations. Supervisor programs can use the MOVES instruction to access all address spaces, including the user spaces and the CPU address space. Although the MOVES instruction can be used to generate CPU space cycles, this may interfere with proper system operation. Thus, the use of MOVES to access the CPU space should be done with caution. MOTOROLA MC68030 USER'S MANUAL 4-5 Processing States 4.3 EXCEPTION PROCESSING An exception is defined as a special condition that pre-empts normal processing. Both internal and external conditions cause exceptions. External conditions that cause exceptions are interrupts from external devices, bus errors, coprocessor detected errors, and reset. Instructions, address errors, tracing, and breakpoints are internal conditions that cause exceptions. The TRAP, TRAPcc, TRAPV, cpTRAPcc, CHK, CHK2, RTE, and DIV instructions can all generate exceptions as part of their normal execution. In addition, illegal instructions, privilege violations, and coprocessor protocol violations cause exceptions. Exception processing, which is the transition from the normal processing of a program to the processing required for the exception condition, involves the exception vector table and an exception stack frame. The following paragraphs describe the vector table and a generalized exception stack frame. Exception processing is discussed in detail in Section 8 Exception Processing. Coprocessor detected exceptions are discussed in detail in Section 10 Coprocessor Interface Description. 4.3.1 Exception Vectors The vector base register (VBR) contains the base address of the 1024-byte exception vector table, which consists of 256 exception vectors. Exception vectors contain the memory addresses of routines that begin execution at the completion of exception processing. These routines perform a series of operations appropriate for the corresponding exceptions. Because the exception vectors contain memory addresses, each consists of one long word, except for the reset vector. The reset vector consists of two long words: the address used to initialize the interrupt stack pointer and the address used to initialize the program counter. The address of an exception vector is derived from an 8-bit vector number and the VBR. The vector numbers for some exceptions are obtained from an external device; others are supplied automatically by the processor. The processor multiplies the vector number by four to calculate the vector offset, which it adds to the VBR. The sum is the memory address of the vector. All exception vectors are located in supervisor data space, except the reset vector, which is located in supervisor program space. Only the initial reset vector is fixed in the processor's memory map; once initialization is complete, there are no fixed assignments. Since the VBR provides the base address of the vector table, the vector table can be located anywhere in memory; it can even be dynamically relocated for each task that is executed by an operating system. Details of exception processing are provided in Section 8 Exception Processing, and Table 8-1 lists the exception vector assignments. 4-6 MC68030 USER'S MANUAL MOTOROLA Processing States 4.3.2 Exception Stack Frame Exception processing saves the most volatile portion of the current processor context on the top of the supervisor stack. This context is organized in a format called the exception stack frame. This information always includes a copy of the status register, the program counter, the vector offset of the vector, and the frame format field. The frame format field identifies the type of stack frame. The RTE instruction uses the value in the format field to properly restore the information stored in the stack frame and to deallocate the stack space. The general form of the exception stack frame is illustrated in Figure 4-1. Refer to Section 8 Exception Processing for a complete list of exception stack frames. 15 12 SP 0 STATUS REGISTER PROGRAM COUNTER FORMAT VECTOR OFFSET ADDITIONAL PROCESSOR STATE INFORMATION (2, 6, 12, OR 42 WORDS, IF NEEDED) Figure 4-1. General Exception Stack Frame MOTOROLA MC68030 USER'S MANUAL 4-7 SECTION 5 SIGNAL DESCRIPTION This section contains brief descriptions of the input and output signals in their functional groups, as shown in Figure 5-1. Each signal is explained in a brief paragraph with reference to other sections that contain more detail about the signal and the related operations. FUNCTION CODES FC2-FC0 ADDRESS BUS A31-A0 DATA BUS D31-D0 TRANSFER SIZE SIZ0 SIZ1 ASYNCHRONOUS BUS CONTROL CACHE CONTROL OCS ECS R/W RMC AS DS DBEN DSACK0 DSACK1 CIIN CIOUT CBREQ CBACK MC68EC030 IPL0 IPL1 IPL2 IPEND AVEC INTERRUPT CONTROL BR BG BGACK BUS ARBITRATION CONTROL RESET HALT BERR BUS EXCEPTION CONTROL STERM REFILL STATUS CDIS SYNCHRONOUS BUS CONTROL EMULATOR SUPPORT CLK VCC (10) GND (14) Figure 5-1. Functional Signal Groups MOTOROLA MC68030 USER'S MANUAL 5-1 Signal Description NOTE In this section and in the remainder of the manual, assertion and negation are used to specify forcing a signal to a particular state. In particular, assertion and assert refer to a signal that is active or true; negation and negate indicate a signal that is inactive or false. These terms are used independently of the voltage level (high or low) that they represent. 5.1 SIGNAL INDEX The input and output signals for the MC68030 are listed in Table 5-1. Both the names and mnemonics are shown along with brief signal descriptions. For more detail on each signal, refer to the paragraph in this section named for the signal and the reference in that paragraph to a description of the related operations. Guaranteed timing specifications for the signals listed in Table 5-1 can be found in M68030EC/D, MC68030 Electrical Specifications. Table 5-1. Signal Index (Sheet 1 of 2) Signal Name Function Codes Mnemonic Function FC0-FC2 3-bit function code used to identify the address space of each bus cycle. Address Bus A0-A31 32-bit address bus. Data Bus D0-D31 32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus cycle. SIZ0/SIZ1 Indicates the number of bytes remaining to be transferred for this cycle. These signals, together with A0 and A1, define the active sections of the data bus. Size Operand Cycle Start OCS Identical operation to that of ECS except that OCS is asserted only during the first bus cycle of an operand transfer. External Cycle Start ECS Provides an indication that a bus cycle is beginning. Read/Write R/W Defines the bus transfer as a processor read or write. Read-Modify-Write Cycle RMC Provides an indicator that the current bus cycle is part of an indivisible read-modify-write operation. Address Strobe AS Indicates that a valid address is on the bus. Data Strobe DS Indicates that valid data is to be placed on the data bus by an external device or has been placed on the data bus by the MC68030. Data Buffer Enable 5-2 DBEN Provides an enable signal for external data buffers. MC68030 USER'S MANUAL MOTOROLA Signal Description Table 5-1. Signal Index (Sheet 2 of 2) Signal Name Data Transfer and Size Acknowledge Synchronous Termination Mnemonic Function DSACK0/ DSACK1 Bus response signals that indicate the requested data transfer operation is completed. In addition, these two lines indicate the size of the external bus port on a cycle-by-cycle basis and are used for asynchronous transfers. STERM Bus response signal that indicates a port size of 32 bits and that data may be latched on the next falling clock edge. CIIN Prevents data from being loaded into the MC68030 instruction and data caches. Cache Inhibit Out CIOUT Reflects the CI bit in ATC entries or TTx register; indicates that external caches should ignore these accesses Cache Burst Request CBREQ Indicates a burst request for the instruction or data cache. Cache Burst Acknowledge CBACK Indicates that the accessed device can operate in burst mode. Cache Inhibit In Interrupt Priority Level IPL0-IPL2 Provides an encoded interrupt level to the processor. Interrupt Pending IPEND Indicates that an interrupt is pending. Autovector AVEC Requests an autovector during an interrupt acknowledge cycle. Bus Request BR Indicates that an external device requires bus mastership. BG Indicates that an external device may assume bus mastership. Bus Grant Acknowledge BGACK Indicates that an external device has assumed bus mastership. Reset RESET System reset. Bus Grant Halt HALT Indicates that the processor should suspend bus activity. Bus Error BERR Indicates that an erroneous bus operation is being attempted. Cache Disable CDIS Dynamically disables the on-chip cache to assist emulator support. MMU Disable MMUDIS Dynamically disables the translation mechanism of the MMU. Pipe Refill REFILL Indicates when the MC68030 is beginning to fill pipeline. Microsequencer Status STATUS Indicates the state of the microsequencer Clock CLK Clock input to the processor. Power Supply VCC Power supply. Ground GND Ground connection MOTOROLA MC68030 USER'S MANUAL 5-3 Signal Description 5.2 FUNCTION CODE SIGNALS (FC0-FC2) These three-state outputs identify the address space of the current bus cycle. Table 4-1 shows the relationship of the function code signals to the privilege levels and the address spaces. Refer to 4.2 Address Space Types for more information. 5.3 ADDRESS BUS (A0-A31) These three-state outputs provide the address for the current bus cycle, except in the CPU address space. Refer to 4.2 Address Space Types for more information on the CPU address space. A31 is the most significant address signal. Refer to 7.1.2 Address Bus for information on the address bus and its relationship to bus operation. 5.4 DATA BUS (D0-D31) These three-state bidirectional signals provide the general-purpose data path between the MC68030 and all other devices. The data bus can transfer 8, 16, 24, or 32 bits of data per bus cycle. D31 is the most significant bit of the data bus. Refer to 7.1.4 Data Bus for more information on the data bus and its relationship to bus operation. 5.5 TRANSFER SIZE SIGNALS (SIZ0, SIZ1) These three-state outputs indicate the number of bytes remaining to be transferred for the current bus cycle. With A0, A1, DSACK0, DSACK1, and STERM, SIZ0 and SIZ1 define the number of bits transferred on the data bus. Refer to 7.2.1 Dynamic Bus Sizing for more information on the size signals and their use in dynamic bus sizing. 5-4 MC68030 USER'S MANUAL MOTOROLA Signal Description 5.6 BUS CONTROL SIGNALS The following signals control synchronous bus transfer operations for the MC68030. 5.6.1 Operand Cycle Start (OCS) This output signal indicates the beginning of the first external bus cycle for an instruction prefetch or a data operand transfer. OCS is not asserted for subsequent cycles that are performed due to dynamic bus sizing or operand misalignment. 7.1.1 Bus Control Signals for information about the relationship of OCS to bus operation. 5.6.2 External Cycle Start (ECS) This output signal indicates the beginning of a bus cycle of any type. 7.1.1 Bus Control Signals for information about the relationship of ECS to bus operation. 5.6.3 Read/Write (R/W) This three-state output signal defines the type of bus cycle. A high level indicates a read cycle; a low level indicates a write cycle. Refer to 7.1.1 Bus Control Signals for information about the relationship of R/W to bus operation. 5.6.4 Read-Modify-Write Cycle (RMC) This three-state output signal identifies the current bus cycle as part of an indivisible readmodify-write operation; it remains asserted during all bus cycles of the read-modify-write operation. Refer to 7.1.1 Bus Control Signals for information about the relationship of RMC to bus operation. 5.6.5 Address Strobe (AS) This three-state output indicates that a valid address is on the address bus. The function code, size, and read/write signals are also valid when AS is asserted. Refer to 7.1.3 Address Strobe for information about the relationship of AS to bus operation. MOTOROLA MC68030 USER'S MANUAL 5-5 Signal Description 5.6.6 Data Strobe (DS) During a read cycle, this three-state output indicates that an external device should place valid data on the data bus. During a write cycle, the data strobe indicates that the MC68030 has placed valid data on the bus. During two-clock synchronous write cycles, the MC68030 does not assert DS. Refer to 7.1.5 Data Strobe for more information about the relationship of DS to bus operation. 5.6.7 Data Buffer Enable (DBEN) This output is an enable signal for external data buffers. This signal may not be required in all systems. The timing of this signal may preclude its use in a system that supports twoclock synchronous bus cycles. Refer to 7.1.6 Data Buffer Enable for more information about the relationship of DBEN to bus operation. 5.6.8 Data Transfer and Size Acknowledge (DSACK0, DSACK1) These inputs indicate the completion of a requested data transfer operation. In addition, they indicate the size of the external bus port at the completion of each cycle. These signals apply only to asynchronous bus cycles. Refer to 7.1.7 Bus Cycle Termination Signals for more information on these signals and their relationship to dynamic bus sizing. 5.6.9 Synchronous Termination (STERM) This input is a bus handshake signal indicating that the addressed port size is 32 bits and that data is to be latched on the next falling clock edge for a read cycle. This signal applies only to synchronous operation. Refer to 7.1.7 Bus Cycle Termination Signals for more information about the relationship of STERM to bus operation. 5-6 MC68030 USER'S MANUAL MOTOROLA Signal Description 5.7 CACHE CONTROL SIGNALS The following signals relate to the on-chip caches. 5.7.1 Cache Inhibit Input (CIIN) This input signal prevents data from being loaded into the MC68030 instruction and data caches. It is a synchronous input signal and is interpreted on a bus-cycle-by-bus-cycle basis. CIIN is ignored during all write cycles. Refer to 6.1 On-Chip Cache Organization and Operation for information on the relationship of CIIN to the on-chip caches. 5.7.2 Cache Inhibit Output (CIOUT) This three-state output signal reflects the state of the CI bit in the address translation cache entry for the referenced logical address, indicating that an external cache should ignore the bus transfer. When the referenced logical address is within an area specified for transparent translation, the CI bit of the appropriate transparent translation register controls the state of CIOUT. Refer to Section 9 Memory Management Unit for more information about the address translation cache and transparent translation. Also, refer to Section 6 On-Chip Cache Memories for the effect of CIOUT on the internal caches. 5.7.3 Cache Burst Request (CBREQ) This three-state output signal requests a burst mode operation to fill a line in the instruction or data cache. Refer to 6.1.3 Cache Filling for filling information and 7.3.7 Burst Operation Cycles for bus cycle information pertaining to burst mode operations. 5.7.4 Cache Burst Acknowledge (CBACK) This input signal indicates that the accessed device can operate in the burst mode and can supply at least one more long word for the instruction or data cache. Refer to 7.3.7 Burst Operation Cycles for information about burst mode operation. MOTOROLA MC68030 USER'S MANUAL 5-7 Signal Description 5.8 INTERRUPT CONTROL SIGNALS The following signals are the interrupt control signals for the MC68030. 5.8.1 Interrupt Priority Level Signals These input signals provide an indication of an interrupt condition and the encoding of the interrupt level from a peripheral or external prioritizing circuitry. IPL2 is the most significant bit of the level number. For example, since the IPLn signals are active low, IPL0-IPL2 equal to $5 corresponds to an interrupt request at interrupt level 2. Refer to 8.1.9 Interrupt Exceptions for information on MC68030 interrupts. 5.8.2 Interrupt Pending (IPEND) This output signal indicates that an interrupt request has been recognized internally and exceeds the current interrupt priority mask in the status register (SR). This output is for use by external devices (coprocessors and other bus masters, for example) to predict processor operation on the following instruction boundaries. Refer to 8.1.9 Interrupt Exceptions for interrupt information. Also, refer to 7.4.1 Interrupt Acknowledge Bus Cycles for bus information related to interrupts. 5.8.3 Autovector (AVEC) This input signal indicates that the MC68030 should generate an automatic vector during an interrupt acknowledge cycle. Refer to 7.4.1.2 Autovector Interrupt Acknowledge Cycle for more information about automatic vectors. 5.9 BUS ARBITRATION CONTROL SIGNALS The following signals are the three bus arbitration control signals used to determine which device in a system is the bus master. 5.9.1 Bus Request (BR) This input signal indicates that an external device needs to become the bus master. This is typically a "wire-ORed" input (but does not need to be constructed from open-collector devices). Refer to 7.7 Bus Arbitration for more information. 5-8 MC68030 USER'S MANUAL MOTOROLA Signal Description 5.9.2 Bus Grant (BG) This output indicates that the MC68030 will release ownership of the bus master when the current processor bus cycle completes. Refer to 7.7.2 Bus Grant for more information. 5.9.3 Bus Grant Acknowledge (BGACK) This input indicates that an external device has become the bus master. Refer to 7.7.3 Bus Grant Acknowledge for more information. 5.10 BUS EXCEPTION CONTROL SIGNALS The following signals are the bus exception control signals for the MC68030. 5.10.1 Reset (RESET) This bidirectional open-drain signal is used to initiate a system reset. An external reset signal resets the MC68030 as well as all external devices. A reset signal from the processor (asserted as part of the RESET instruction) resets external devices only; the internal state of the processor is not altered. Refer to 7.8 Reset Operation for a description of reset bus operation and 8.1.1 Reset Exception for information about the reset exception. 5.10.2 Halt (HALT) The halt signal indicates that the processor should suspend bus activity or, when used with BERR, that the processor should retry the current cycle. Refer to 7.5 Bus Exception Control Cycles for a description of the effects of HALT on bus operations. 5.10.3 Bus Error (BERR) The bus error signal indicates that an invalid bus operation is being attempted or, when used with HALT, that the processor should retry the current cycle. Refer to 7.5 Bus Exception Control Cycles for a description of the effects of BERR on bus operations. MOTOROLA MC68030 USER'S MANUAL 5-9 Signal Description 5.11 EMULATOR SUPPORT SIGNALS The following signals support emulation by providing a means for an emulator to disable the on-chip caches and memory management unit and by supplying internal status information to an emulator. Refer to Section 12 Applications Information for more detailed information on emulation support. 5.11.1 Cache Disable (CDIS) The cache disable signal dynamically disables the on-chip caches to assist emulator support. Refer to 6.1 On-Chip Cache Organization and Operation for information about the caches; refer to Section 12 Applications Information for a description of the use of this signal by an emulator. CDIS does not flush the data and instruction caches; entries remain unaltered and become available again when CDIS is negated. 5.11.2 MMU Disable (MMUDIS) The MMU disable signal dynamically disables the translation of addresses by the MMU. Refer to 9.4 Address Translation Cache for a description of address translation; refer to Section 12 Applications Information for a description of the use of this signal by an emulator. The assertion of MMUDIS does not flush the address translation cache (ATC); ATC entries become available again when MMUDIS is negated. 5.11.3 Pipeline Refill (REFILL) The pipeline refill signal indicates that the MC68030 is beginning to refill the internal instruction pipeline. Refer to Section 12 Applications Information for a description of the use of this signal by an emulator. 5.11.4 Internal Microsequencer Status (STATUS) The microsequencer status signal indicates the state of the internal microsequencer. The varying number of clocks for which this signal is asserted indicates instruction boundaries, pending exceptions, and the halted condition. Refer to Section 12 Applications Information for a description of the use of this signal by an emulator. 5-10 MC68030 USER'S MANUAL MOTOROLA Signal Description 5.12 CLOCK (CLK) The clock signal is the clock input to the MC68030. It is a TTL-compatible signal. Refer to Section 12 Applications Information for suggestions on clock generation. 5.13 POWER SUPPLY CONNECTIONS The MC68030 requires connection to a VCC power supply, positive with respect to ground. The VCC connections are grouped to supply adequate current for the various sections of the processor. The ground connections are similarly grouped. Section 14 Ordering Information and Mechanical Data describes the groupings of VCC and ground connections, and Section 12 Applications Information describes a typical power supply interface. 5.14 SIGNAL SUMMARY Table 5-2 provides a summary of the electrical characteristics of the signals discussed in this section. 5-11 MC68030 USER'S MANUAL MOTOROLA Signal Description Table 5-2. Signal Summary Signal Function Signal Name Input/Output Active State Three-State Function Codes FC0-FC2 Output High Yes A0-A31 Output High Yes Address Bus Data Bus D0-D31 Input/Output High Yes SIZ0/SIZ1 Output High Yes Operand Cycle Start OCS Output Low No External Cycle Start ECS Output Low No Read/Write R/W Output High/Low Yes Read-Modify-Write Cycle RMC Output Low Yes Address Strobe AS Output Low Yes Data Strobe DS Output Low Yes Transfer Size Data Buffer Enable Data Transfer and Size Acknowledge Synchronous Termination Output Low Yes Input Low -- STERM Input Low -- CIIN Input Low -- Cache Inhibit Out CIOUT Output Low Yes Cache Burst Request CBREQ Output Low Yes Cache Burst Acknowledge CBACK Input Low -- Cache Inhibit In IPL0-IPL2 Input Low -- Interrupt Pending IPEND Output Low No Autovector AVEC Input Low -- BR Input Low -- Interrupt Priority Level Bus Request BG Output Low No Bus Grant Acknowledge BGACK Input Low -- Reset Bus Grant RESET Input/Output Low No Halt HALT Input Low -- Bus Error BERR Input Low -- Cache Disable CDIS Input Low -- MMU Disable MMUDIS Input Low -- Pipeline Refill REFILL Output Low No Microsequencer Status STATUS Output Low No CLK Input -- -- Clock 5-12 DBEN DSACK0/ DSACK1 Power Supply VCC Input -- -- Ground GND Input -- -- MC68030 USER'S MANUAL MOTOROLA SECTION 6 ON-CHIP CACHE MEMORIES The MC68030 microprocessor includes a 256-byte on-chip instruction cache and a 256-byte on-chip data cache that are accessed by logical (virtual) addresses. These caches improve performance by reducing external bus activity and increasing instruction throughput. Reduced external bus activity increases overall performance by increasing the availability of the bus for use by external devices (in systems with more than one bus master, such as a processor and a DMA device) without degrading the performance of the MC68030. An increase in instruction throughput results when instruction words and data required by a program are available in the on-chip caches and the time required to access them on the external bus is eliminated. Additionally, instruction throughput increases when instruction words and data can be accessed simultaneously. As shown in Figure 6-1, the instruction cache and the data cache are connected to separate on-chip address and data buses. The address buses are combined to provide the logical address to the memory management unit (MMU). The MC68030 initiates an access to the appropriate cache for the requested instruction or data operand at the same time that it initiates an access for the translation of the logical address in the address translation cache of the MMU. When a hit occurs in the instruction or data cache and the MMU validates the access on a write, the information is transferred from the cache (on a read) or to the cache and the bus controller (on a write). When a hit does not occur, the MMU translation of the address is used for an external bus cycle to obtain the instruction or operand. Regardless of whether or not the required operand is located in one of the on-chip caches, the address translation cache of the MMU performs logical-to-physical address translation in parallel with the cache lookup in case an external cycle is required. MOTOROLA MC68030 USER'S MANUAL 6-1 6-2 ADDRESS BUS ADDRESS PADS MC68030 USER'S MANUAL ADDRESS BUS PREFETCH PENDING BUFFER BUS CONTROL SIGNALS MICROBUS CONTROLLER WRITE PENDING BUFFER BUS CONTROLLER ACCESS CONTROL UNIT ADDRESS INSTRUCTION ADDRESS BUS CONTROL LOGIC CONTROL STORE DATA ADDRESS BUS PROGRAM COUNTER SECTION STAGE C CACHE HOLDING REGISTER (CAHR) DATA CACHE MISALIGNMENT MULTIPLEXER DATA SECTION INSTRUCTION CACHE STAGE B INSTRUCTION PIPE ADDRESS SECTION STAGE D EXECUTION UNIT MICROSEQUENCER AND CONTROL SIZE MULTIPLEXER INTERNAL DATA BUS DATA PADS DATA BUS On-Chip Cache Memories Figure 6-1. Internal Caches and the MC68030 MOTOROLA On-Chip Cache Memories 6.1 ON-CHIP CACHE ORGANIZATION AND OPERATION Both on-chip caches are 256-byte direct-mapped caches, each organized as 16 lines. Each line consists of four entries, and each entry contains four bytes. The tag field for each line contains a valid bit for each entry in the line; each entry is independently replaceable. When appropriate, the bus controller requests a burst mode operation to replace an entire cache line. The cache control register (CACR) is accessible by supervisor programs to control the operation of both caches. System hardware can assert the cache disable (CDIS) signal to disable both caches. The assertion of CDIS disables the caches, regardless of the state of the enable bits in CACR. CDIS is primarily intended for use by in-circuit emulators. Another input signal, cache inhibit in (CIIN), inhibits caching of data reads or instruction prefetches on a bus-cycle by bus-cycle basis. Examples of data that should not be cached are data for I/O devices and data from memory devices that cannot supply a full port width of data, regardless of the size of the required operand. Subsequent paragraphs describe how CIIN is used during the filling of the caches. An output signal, cache inhibit out (CIOUT), reflects the state of the cache inhibit (CI) bit from the MMU of either the address translation cache entry that corresponds to a specified logical address or the transparent translation register that corresponds to that address. Whenever the appropriate CI bit is set for either a read or a write access and an external bus cycle is required, CIOUT is asserted and the instruction and data caches are ignored for the access. This signal can also be used by external hardware to inhibit caching in external caches. Whenever a read access occurs and the required instruction word or data operand is resident in the appropriate on-chip cache (no external bus cycle is required), the MMU is completely ignored, unless an invalid translation resides in the MMU at that time (see next two paragraphs). Therefore, the state of the corresponding CI bits in the MMU are also ignored. The MMU is used to validate all accesses that require external bus cycles; an address translation must be available and valid, protections are checked, and the CIOUT signal is asserted appropriately. MOTOROLA MC68030 USER'S MANUAL 6-3 On-Chip Cache Memories An external access is defined as "cachable" for either the instruction or data cache when all the following conditions apply: * The cache is enabled with the appropriate bit in the CACR set. * The CDIS signal is negated. * The CIIN signal is negated for the access. * The CIOUT signal is negated for the access. * The MMU validates the access. Because both the data and instruction caches are referenced by logical addresses, they should be flushed during a task switch or at any time the logical-to-physical address mapping changes, including when the MMU is first enabled. In addition, if a page descriptor is currently marked as valid and is later changed to the invalid type (due to a context switch or a page replacement operation) entries in the on-chip instruction or data cache corresponding to the physical page must be first cleared (invalidated). Otherwise, if on-chip cache entries are valid for pages with descriptors in memory marked invalid, processor operation is unpredictable. Data read and write accesses to the same address should also have consistent cachability status to ensure that the data in the cache remains consistent with external memory. For example, if CIOUT is negated for read accesses within a page and the MMU configuration is changed so that CIOUT is subsequently asserted for write accesses within the same page, those write accesses do not update data in the cache, and stale data may result. Similarly, when the MMU maps multiple logical addresses to the same physical address, all accesses to those logical addresses should have the same cachability status. 6.1.1 Instruction Cache The instruction cache is organized with a line size of four long words, as shown in Figure 62. Each of these long words is considered a separate cache entry as each has a separate valid bit. All four entries in a line have the same tag address. Burst filling all four long words can be advantageous when the time spent in filling the line is not long relative to the equivalent bus-cycle time for four nonburst long-word accesses, because of the probability that the contents of memory adjacent to or close to a referenced operand or instruction is also required by subsequent accesses. Dynamic RAMs supporting fast access modes (page, nibble, or static column) are easily employed to support the MC68030 burst mode. 6-4 MC68030 USER'S MANUAL MOTOROLA On-Chip Cache Memories LONG-WORD SELECT INDEX TAG F F F CCC 2 10 A 3 1 A A A A A A A A A A A A A A A A A A A A A A A A 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 ACCESS ADDRESS 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 TAG V V V V 1 OF 16 SELECT TAG REPLACE DATA FROM INSTRUCTION CACHE DATA BUS VALID DATA TO INSTRUCTION CACHE HOLDING REGISTER ENTRY HIT COMPARATOR CACHE CONTROL LOGIC LINE HIT CACHE SIZE = 64 (LONG WORDS) LINE SIZE = 4 (LONG WORDS) SET SIZE = 1 Figure 6-2. On-Chip Instruction Cache Organization When enabled, the instruction cache is used to store instruction prefetches (instruction words and extension words) as they are requested by the CPU. Instruction prefetches are normally requested from sequential memory addresses except when a change of program flow occurs (e.g., a branch taken) or when an instruction is executed that can modify the status register, in which cases the instruction pipe is automatically flushed and refilled. The output signal REFILL indicates this condition. For more information on the operation of this signal, refer to Section 12 Applications Information. In the instruction cache, each of the 16 lines has a tag consisting of the 24 most significant logical address bits, the FC2 function code bit (used to distinguish between user and supervisor accesses), and the four valid bits (one corresponding to each long word). Refer to Figure 6-2 for the instruction cache organization. Address bits A7-A4 select one of 16 lines and its associated tag. The comparator compares the address and function code bits in the selected tag with address bits A31-A8 and FC2 from the internal prefetch request to determine if the requested word is in the cache. A cache hit occurs when there is a tag match and the corresponding valid bit (selected by A3-A2) is set. On a cache hit, the word selected by address bit A1 is supplied to the instruction pipe. When the address and function code bits do not match or the requested entry is not valid, a miss occurs. The bus controller initiates a long-word prefetch operation for the required MOTOROLA MC68030 USER'S MANUAL 6-5 On-Chip Cache Memories instruction word and loads the cache entry, provided the entry is cachable. A burst mode operation may be requested to fill an entire cache line. If the function code and address bits match and the corresponding long word is not valid (but one or more of the other three valid bits for that line are set) a single entry fill operation replaces the required long word only, using a normal prefetch bus cycle or cycles (no burst). 6.1.2 Data Cache The data cache stores data references to any address space except CPU space (FC=$7), including those references made with PC relative addressing modes and accesses made with the MOVES instruction. Operation of the data cache is similar to that of the instruction cache, except for the address comparison and cache filling operations. The tag of each line in the data cache contains function code bits FC0, FC1, and FC2 in addition to address bits A31-A8. The cache control circuitry selects the tag using bits A7-A4 and compares it to the corresponding bits of the access address to determine if a tag match has occurred. Address bits A3-A2 select the valid bit for the appropriate long word in the cache to determine if an entry hit has occurred. Misaligned data transfers may span two data cache entries. In this case, the processor checks for a hit one entry at a time. Therefore, it is possible that a portion of the access results in a hit and a portion results in a miss. The hit and miss are treated independently. Figure 6-3 illustrates the organization of the data cache. The operation of the data cache differs for read and write cycles. A data read cycle operates exactly like an instruction cache read cycle; when a miss occurs, an external cycle is initiated to obtain the operand from memory, and the data is loaded into the cache if the access is cachable. In the case of a misaligned operand that spans two cache entries, two long words are required from memory. Burst mode operation may also be initiated to fill an entire line of the data cache. Read accesses from the CPU address space and address translation table search accesses are not stored in the data cache. The data cache on the MC68030 is a writethrough cache. When a hit occurs on a write cycle, the data is written both to the cache and to external memory (provided the MMU validates the access), regardless of the operand size and even if the cache is frozen. If the MMU determines that the access is invalid, the write is aborted, the corresponding entry is invalidated, and a bus error exception is taken. Since the write to the cache completes before the write to external memory, the cache contains the new value even if the external write terminates in a bus error. The value in the data cache might be used by another instruction before the external write cycle has completed, although this should not have any adverse consequences. Refer to 7.6 Bus Synchronization for the details of bus synchronization. 6-6 MC68030 USER'S MANUAL MOTOROLA On-Chip Cache Memories LONG-WORD SELECT INDEX TAG F F F CCC 2 10 A 3 1 A A A A A A A A A A A A A A A A A A A A A A A A 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 ACCESS ADDRESS 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 TAG V V V V 1 OF 16 SELECT TAG REPLACE DATA FROM DATA CACHE DATA BUS VALID DATA TO EXECUTION UNIT ENTRY HIT COMPARATOR CACHE CONTROL LOGIC LINE HIT CACHE SIZE = 64 (LONG WORDS) LINE SIZE = 4 (LONG WORDS) SET SIZE = 1 Figure 6-3. On-Chip Data Cache Organization 6.1.2.1 WRITE ALLOCATION. The supervisor program can configure the data cache for either of two types of allocation for data cache entries that miss on write cycles. The state of the write allocation (WA) bit in the cache control register specifies either no write allocation or write allocation with partial validation of the data entries in the cache on writes. When no write allocation is selected (WA=0), write cycles that miss do not alter the data cache contents. In this mode, the processor does not replace entries in the cache during write operations. The cache is updated only during a write hit. When write allocation is selected (WA=1), the processor always updates the data cache on cachable write cycles, but only validates an updated entry that hits or an entry that is updated with long-word data that is long-word aligned. When a tag miss occurs on a write of long-word data that is long-word aligned, the corresponding tag is replaced, and only the long word being written is marked as valid. The other three entries in the cache line are invalidated when a tag miss occurs on a misaligned long-word write or on a byte or word write, the data is not written in the cache, the tag is unaltered, and the valid bit(s) are cleared. Thus, an aligned long-word data write may replace a previously valid entry; whereas, a misaligned data write or a write of data that is not long word may invalidate a previously valid entry or entries. MOTOROLA MC68030 USER'S MANUAL 6-7 On-Chip Cache Memories Write allocation eliminates stale data that may reside in the cache because of either of two unique situations: multiple mapping of two or more logical addresses to one physical address within the same task or allowing the same physical location to be accessed by both supervisor and user mode cycles. Stale data conditions can arise when operating in the nowrite-allocation mode and all the following conditions are satisfied: * Multiple mapping (object aliasing) is allowed by the operating system. * A read cycle loads a value for an "aliased" physical address into the data cache. * A write cycle occurs, referencing the same aliased physical object as above but using a different logical address, causing a cache miss and no update to the cache (has the same page offset). * The physical object is then read using the first alias, which provides stale data from the cache. In this case, the data in the cache no longer matches that in physical memory and is stale. Since the write-allocation mode updates the cache during write cycles, the data in the cache remains consistent with physical memory. Note that when CIOUT is asserted, the data cache is completely ignored, even on write cycles operating in the write-allocation mode. Also note that since the CIIN signal is ignored on write cycles, cache entries may be created for noncachable data (when CIIN is asserted on a write) when operating in the writeallocation mode. Figure 6-4 shows the manner in which each mode operates in five different situations. TAG' LOGICAL ADDRESS = FC2-FC0, A31-A8, A7-A4, A3-A2 LINE SELECT ($5) USER DATA, $000010 b0-b3, V0 = 1 b4-b7, V1 = 0 b8-bB, V2 = 1 bC-bF, V3 = 1 TAG NO WRITE ALLOCATE EXAMPLE 1: USER WORD WRITE OF b2'-b3' to $00001052 (CACHE HIT, ALWAYS UPDATE CACHE AND MEMORY) EXAMPLE 2: USER LONG-WORD WRITE OF b6'-b9' to $00001056 (TAG MATCH, LONG-WORD DATA, MISALIGNED, b6-b7 RESULT IN A CACHE MISS, b8-b9 RESULT IN A CACHE HIT) A) B) A) B) START EXTERNAL CYCLE b2-b3 b2'-b3' START EXTERNAL CYCLE b8-b9 b8'-b9' WRITE ALLOCATE A) START EXTERNAL CYCLE B) b2-b3 b2'-b3' A) START EXTERNAL CYCLE B) b8-b9 b8'-b9' Figure 6-4. No-Write-Allocation and Write-Allocation Mode Examples 6-8 MC68030 USER'S MANUAL MOTOROLA On-Chip Cache Memories 6.1.2.2 READ-MODIFY-WRITE ACCESSES. The read portion of a read-modify-write cycle is always forced to miss in the data cache. However, if the system allows internal caching of read-modify-write cycle operands (CIOUT and CIIN both negated), the processor either uses the data read from memory to update a matching entry in the data cache or creates a new entry with the read data in the case of no matching entry. The write portion of a readmodify-write operation also updates a matching entry in the data cache. In the case of a cache miss on the write, the allocation of a new cache entry for the data being written is controlled by the WA bit. Table search accesses, however, are completely ignored by the data cache; it is never updated for a table search access. 6.1.3 Cache Filling The bus controller can load either cache in either of two ways: * Single entry mode * Burst fill mode In the single entry mode, the bus controller loads a single long-word entry of a cache line. In the burst fill mode, an entire line (four long words) can be filled. Refer to Section 7 Bus Operation for detailed information about the bus cycles required for both modes. 6.1.3.1 SINGLE ENTRY MODE. When a cachable access is initiated and a burst mode operation is not requested by the MC68030 or is not supported by external hardware, the bus controller transfers a single long word for the corresponding cache entry. An entire long word is required. If the port size of the responding device is smaller than 32 bits, the MC68030 executes all bus cycles necessary to fill the long word. When a device cannot supply its entire port width of data, regardless of the size of the transfer, the responding device must consistently assert the cache inhibit input (CIIN) signal. For example, a 32-bit port must always supply 32 bits, even for 8- and 16-bit transfers; a 16bit port must supply 16 bits, even for 8-bit transfers. The MC68030 assumes that a 32-bit termination signal for the bus cycle indicates availability of 32 valid data bits, even if only 16 or 8 bits are requested. Similarly, the processor assumes that a 16-bit termination signal indicates that all 16 bits are valid. If the device cannot supply its full port width of data, it must assert CIIN for all bus cycles corresponding to a cache entry. MOTOROLA MC68030 USER'S MANUAL 6-9 On-Chip Cache Memories When a cachable read cycle provides data with both CIIN and BERR negated, the MC68030 attempts to fill the cache entry. Figure 6-5 shows the organization of a line of data in the caches. The notation b0, b1, b2, and so forth identifies the bytes within the line. For each entry in the line, a valid bit in the associated tag corresponds to a long-word entry to be loaded. Since a single valid bit applies to an entire long word, a single entry mode operation must provide a full 32 bits of data. Ports less than 32 bits wide require several read cycles for each entry. Figure 6-5 shows an example of a byte data operand read cycle starting at byte address $03 from an 8-bit port. Provided the data item is cachable, this operation results in four bus cycles. The first cycle requested by the MC68030 reads a byte from address $03. The 8-bit DSACKx response causes the MC68030 to fetch the remainder of the long word starting at address $00. The bytes are latched in the following order: b3, b0, b1, and b2. Note that during cache loading operations, devices must indicate the same port size consistently throughout all cycles for that long-word entry in the cache. Figure 6-6 shows the access of a byte data operand from a 16-bit port. This operation requires two read cycles. The first cycle requests the byte at address $03. If the device responds with a 16-bit DSACKx encoding, the word at address $02 (including the requested byte) is accepted by the MC68030. The second cycle requests the word at address $00. Since the device again responds with a 16-bit DSACKx encoding, the remaining two bytes of the long word are latched, and the cache entry is filled. (UNABLE TO LOCATE ART) Figure 6-5. Single Entry Mode Operation -- 8-Bit Port (UNABLE TO LOCATE ART) Figure 6-6. Single Entry Mode Operation -- 16-Bit Port With a 32-bit port, the same operation is shown in Figure 6-7. Only one read cycle is required. All four bytes (including the requested byte) are latched during the cycle. (UNABLE TO LOCATE ART) Figure 6-7. Single Entry Mode Operation -- 32-Bit Port If a requested access is misaligned and spans two cache entries, the bus controller attempts to fill both associated long-word cache entries. An example of this is an operand request for a long word on an odd-word boundary. The MC68030 first fetches the initial byte(s) of the operand (residing in the first long word) and then requests the remaining bytes to fill that cache entry (if the port size is less than 32 bits) before it requests the remainder of the operand and corresponding long word to fill the second cache entry. If the port size is 32 bits, the processor performs two accesses, one for each cache entry. 6-10 MC68030 USER'S MANUAL MOTOROLA On-Chip Cache Memories Figure 6-8 shows a misaligned access of a long word at address $06 from an 8-bit port requiring eight bus cycles to complete. Reading this long-word operand requires eight read cycles, since accesses to all eight addresses return 8-bit port-size encodings. These cycles fetch the two cache entries that the requested long-word spans. The first cycle requests a long word at address $06 and accepts the first requested byte (b6). The subsequent transfers of the first long word are performed in the following order: b7, b4, b5. The remaining four read cycles transfer the four bytes of the second cache entry. The sequence of access for the entire operation is b6, b7, b4, b5, b8, b9, bA, and bB. (UNABLE TO LOCATE ART) Figure 6-8. Single Entry Mode Operation -- Misaligned Long Word and 8-Bit Port The next example, shown in Figure 6-9, is a read of a misaligned long-word operand from devices that return 16-bit DSACKx encodings. The processor accepts the first portion of the operand, the word from address $06, and requests a word from address $04 to fill the cache entry. Next, the processor reads the word at address $08, the second portion of the operand, and stores it in the cache also. Finally, the processor accesses the word at $0A to fill the second long-word cache entry. (UNABLE TO LOCATE ART) Figure 6-9. Single Entry Mode Operation -- Misaligned Long Word and 16-Bit Port Two read cycles are required for a misaligned long-word operand transfer from devices that return 32-bit DSACKx encodings. As shown in Figure 6-10, the first read cycle requests the long word at address $06 and latches the long word at address $04. The second read cycle requests and latches the long word corresponding to the second cache entry at address $08. Two read cycles are also required if STERM is used to indicate a 32-bit port instead of the 32-bit DSACKx encoding. (UNABLE TO LOCATE ART) Figure 6-10. Single Entry Mode Operation -- Misaligned Long Word and 32-Bit DSACKx Port If all bytes of a long word are cachable, CIIN must be negated for all bus cycles required to fill the entry. If any byte is not cachable, CIIN must be asserted for all corresponding bus cycles. The assertion of the CIIN signal prevents the caches from being updated during read cycles. Write cycles (including the write portion of a read-modify-write cycle) ignore the assertion of the CIIN signal and may cause the data cache to be altered, depending on the state of the cache (whether or not the write cycle hits), the state of the WA bit in the CACR, and the conditions indicated by the MMU. The occurrence of a bus error while attempting to load a cache entry aborts the entry fill operation but does not necessarily cause a bus error exception. If the bus error occurs on a read cycle for a portion of the required operand (not the remaining bytes of the cache entry) to be loaded into the data cache, the processor immediately takes a bus error exception. If MOTOROLA MC68030 USER'S MANUAL 6-11 On-Chip Cache Memories the read cycle in error is made only to fill the data cache (the data is not part of the target operand), no exception occurs, but the corresponding entry is marked invalid. For the instruction cache, the processor marks the entry as invalid, but only takes an exception if the execution unit attempts to use the instruction word(s). 6.1.3.2 BURST MODE FILLING. Burst mode filling is enabled by bits in the cache control register. The data burst enable bit must be set to enable burst filling of the data cache. Similarly, the instruction burst enable bit must be set to enable burst filling of the instruction cache. When burst filling is enabled and the corresponding cache is enabled, the bus controller requests a burst mode fill operation in either of these cases: * A read cycle for either the instruction or data cache misses due to the indexed tag not matching. * A read cycle tag matches, but all long words in the line are invalid. The bus controller requests a burst mode fill operation by asserting the cache burst request signal (CBREQ). The responding device may sequentially supply one to four long words of cachable data, or it may assert the cache inhibit input signal (CIIN) when the data in a long word is not cachable. If the responding device does not support the burst mode and it terminates cycles with STERM, it should not acknowledge the request with the assertion of the cache burst acknowledge (CBACK) signal. The MC68030 ignores the assertion of CBACK during cycles terminated with DSACKx. The cache burst request signal (CBREQ) requests burst mode operation from the referenced external device. To operate in the burst mode, the device or external hardware must be able to increment the low-order address bits if required, and the current cycle must be a 32-bit synchronous transfer (STERM must be asserted) as described in Section 7 Bus Operation. The device must also assert CBACK (at the same time as STERM) at the end of the cycle in which the MC68030 asserts CBREQ. CBACK causes the processor to continue driving the address and bus control signals and to latch a new data value for the next cache entry at the completion of each subsequent cycle (as defined by STERM), for a total of up to four cycles (until four long words have been read). When a cache burst is initiated, the first cycle attempts to load the cache entry corresponding to the instruction word or data item explicitly requested by the execution unit. The subsequent cycles are for the subsequent entries in the cache line. In the case of a misaligned transfer when the operand spans two cache entries within a cache line, the first cycle corresponds to the cache entry containing the portion of the operand at the lower address. Figure 6-11 illustrates the four cycles of a burst operation and shows that the second, third, and fourth cycles are run in burst mode. A distinction is made between the first cycle of a burst operation and the subsequent cycles because the first cycle is requested by the microsequencer and the burst fill cycles are requested by the bus controller. Therefore, when data from the first cycle is returned, it is immediately available for the execution unit (EU). However, data from the burst fill cycles is not available to the EU until the burst operation is complete. Since the microsequencer makes two separate requests for misaligned data operands, only the first portion of the misaligned operand returned during a 6-12 MC68030 USER'S MANUAL MOTOROLA On-Chip Cache Memories burst operation is available to the EU after the first cycle is complete. The microsequencer must wait for the burst operation to complete before requesting the second portion of the operand. Normally, the request for the second portion results in a data cache hit unless the second cycle of the burst operation terminates abnormally. BURST OPERATION CYCLE 1 CYCLE 2 FIRST ACCESS OF BURST OPERATION REQUIRED OPERAND OR PREFETCH BURST FILL CYCLE BURST MODE REQUESTED AND ACKNOWLEDGED CYCLE 3 BURST FILL CYCLE CYCLE 4 BURST FILL CYCLE BURST MODE BEGINS HERE Figure 6-11. Burst Operation Cycles and Burst Mode The bursting mechanism allows addresses to wrap around so that the entire four long words in the cache line can be filled in a single burst operation, regardless of the initial address and operand alignment. Depending on the structure of the external memory system, address bits A2 and A3 may have to be incremented externally to select the long words in the proper order for loading into the cache. The MC68030 holds the entire address bus constant for the duration of the burst cycle. Figure 6-12 shows an example of this address wraparound. The initial cycle is a long-word access from address $6. Because the responding device returns CBACK and STERM (signaling a 32-bit port), the entire long word at base address $04 is transferred. Since the initial address is $06 when CBREQ is asserted, the next entry to be burst filled into the cache should correspond to address $08, then $0C, and last, $00. This addressing is compatible with existing nibble-mode dynamic RAMs, and can be supported by page and static column modes with an external modulo 4 counter for A2 and A3. (UNABLE TO LOCATE ART) Figure 6-12. Burst Filling Wraparound Example The MC68030 does not assert CBREQ during the first portion of a misaligned access if the remainder of the access does not correspond to the same cache line. Figure 6-13 shows an example in which the first portion of a misaligned access is at address $0F. With a 32-bit port, the first access corresponds to the cache entry at address $0C, which is filled using a single-entry load operation. The second access, at address $10 corresponding to the second cache line, requests a burst fill and the processor asserts CBREQ. During this burst operation, long words $10, $14, $18, and $1C are all filled in that order. (UNABLE TO LOCATE ART) Figure 6-13. Deferred Burst Filling Example MOTOROLA MC68030 USER'S MANUAL 6-13 On-Chip Cache Memories The processor does not assert CBREQ if any of the following conditions exist: * The appropriate cache is not enabled * Burst filling for the cache is not enabled * The cache freeze bit for the appropriate cache is set * The current operation is the read portion of a read-modify-write operation * The MMU has inhibited caching for the current page * The cycle is for the first access of an operand that spans two cache lines (crosses a modulo 16 boundary) Additionally, the assertion of CIIN and BERR and the premature negation of CBACK affect burst operation as described in the following paragraphs. The assertion of CIIN during the first cycle of a burst operation causes the data to be latched by the processor, and if the requested operand is aligned (the entire operand is latched in the first cycle), the data is passed on to the instruction pipe or execution unit. However, the data is not loaded into its corresponding cache. In addition, the MC68030 negates CBREQ, and the burst operation is aborted. If a portion of the requested operand remains to be read (due to misalignment), a second read cycle is initiated at the appropriate address with CBREQ negated. The assertion of CIIN during the second, third, or fourth cycle of a burst operation prevents the data during that cycle from being loaded into the appropriate cache and causes CBREQ to negate, aborting the burst operation. However, if the data for the cycle contains part of the requested operand, the execution unit uses that data. The premature negation of the CBACK signal during the burst operation causes the current cycle to complete normally, loading the data successfully transferred into the appropriate cache. However, the burst operation aborts and CBREQ negates. A bus error occurring during a burst operation also causes the burst operation to abort. If the bus error occurs during the first cycle of a burst (i.e., before burst mode is entered), the data read from the bus is ignored, and the entire associated cache line is marked "invalid". If the access is a data cycle, exception processing proceeds immediately. If the cycle is for an instruction fetch, a bus error exception is made pending. This bus error is processed only if the execution unit attempts to use either instruction word. Refer to 11.2.2 Instruction Pipe for more information about pipeline operation. For either cache, when a bus error occurs after the burst mode has been entered (that is, on the second cycle or later), the cache entry corresponding to that cycle is marked invalid, but the processor does not take an exception (the microsequencer has not yet requested the data). In the case of an instruction cache burst, the data from the aborted cycle is completely ignored. Pending instruction prefetches are still pending and are subsequently run by the processor. If the second cycle is for a portion of a misaligned data operand fetch and a bus error occurs, the processor terminates the burst operation and negates CBREQ. Once the burst terminates, the microsequencer requests a read cycle for the second portion. Since the burst terminated abnormally for the second cycle of the burst, the data cache 6-14 MC68030 USER'S MANUAL MOTOROLA On-Chip Cache Memories results in a miss, and a second external cycle is required. If BERR is again asserted, the MC68030 then takes an exception. On the initial access of a burst operation, a "retry'"(indicated by the assertion of BERR and HALT) causes the processor to retry the bus cycle and assert CBREQ again. However, signaling a retry with simultaneous BERR and HALT during the second, third, or fourth cycle of a burst operation does not cause a retry operation, even if the requested operand is misaligned. Assertion of BERR and HALT during burst fill cycles of a burst operation causes independent bus error and halt operations. The processor remains halted until HALT is negated, and then handles the bus error as described in the previous paragraphs. 6.2 CACHE RESET When a hardware reset of the processor occurs, all valid bits of both caches are cleared. The cache enable bits, burst enable bits, and the freeze bits in the cache control register (CACR) for both caches (refer to Figure 6-14) are also cleared, effectively disabling both caches. The WA bit in the CACR is also cleared. 6.3 CACHE CONTROL Only the MC68030 cache control circuitry can directly access the cache arrays, but the supervisor program can set bits in the CACR to exercise control over cache operations. The supervisor also has access to the cache address register (CAAR), which contains the address for a cache entry to be cleared. 6.3.1 Cache Control Register The CACR, shown in Figure 6-14, is a 32-bit register that can be written or read by the MOVEC instruction or indirectly modified by a reset. Five of the bits (4-0) control the instruction cache; six other bits (13-8) control the data cache. Each cache is controlled independently of the other, although a similar operation can be performed for both caches by a single MOVEC instruction. For example, loading a long word in which bits 3 and 11 are set into the CACR clears both caches. Bits 31-14 and 7-5 are reserved for Motorola definition. They are currently read as zeros and are ignored when written. For future compatibility, writes should not set these bits. 31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000000000000000000 WA DBE CD CED FD ED 0 0 0 IBE CI CEI FI EI WA DBE CD CED FD ED IBE CI CEI FI EI = = = = = = = = = = = Write Allocate Data Burst Enable Clear Data Cache Clear Entry in Data Cache Freeze Data Cache Freeze Data Cache Instruction Burst Enable Clear Instruction Cache Clear Entry in Instruction Cache Freeze Instruction Cache Enable Instruction Cache Figure 6-14. Cache Control Register MOTOROLA MC68030 USER'S MANUAL 6-15 On-Chip Cache Memories 6.3.1.1 WRITE ALLOCATE. Bit 13, the WA bit, is set to select the write-allocation mode (refer to 6.1.2.1 Write Allocation) for write cycles. Clearing this bit selects the no-writeallocation mode. A reset operation clears this bit. The supervisor should set this bit when it shares data with the user task or when any task maps multiple logical addresses to one physical address. If the data cache is disabled or frozen, the WA bit is ignored. 6.3.1.2 DATA BURST ENABLE. Bit 12, the DBE bit, is set to enable burst filling of the data cache. Operating systems and other software set this bit when burst filling of the data cache is desired. A reset operation clears the DBE bit. 6.3.1.3 CLEAR DATA CACHE. Bit 11, the CD bit, is set to clear all entries in the data cache. Operating systems and other software set this bit to clear data from the cache prior to a context switch. The processor clears all valid bits in the data cache at the time a MOVEC instruction loads a one into the CD bit of the CACR. The CD bit is always read as a zero. 6.3.1.4 CLEAR ENTRY IN DATA CACHE. Bit 10, the CED bit, is set to clear an entry in the data cache. The index field of the CAAR (see Figure 6-15) corresponding to the index and long-word select portion of an address specifies the entry to be cleared. The processor clears only the specified long word by clearing the valid bit for the entry at the time a MOVEC instruction loads a one into the CED bit of the CACR, regardless of the states of the ED and FD bits. The CED bit is always read as a zero. 6-16 MC68030 USER'S MANUAL MOTOROLA On-Chip Cache Memories 6.3.1.5 FREEZE DATA CACHE. Bit 9, the FD bit, is set to freeze the data cache. When the FD bit is set and a miss occurs during a read or write of the data cache, the indexed entry is not replaced. However, write cycles that hit in the data cache cause the entry to be updated even when the cache is frozen. When the FD bit is clear, a miss in the data cache during a read cycle causes the entry (or line) to be filled, and the filling of entries on writes that miss are then controlled by the WA bit. A reset operation clears the FD bit. 6.3.1.6 ENABLE DATA CACHE. Bit 8, the ED bit, is set to enable the data cache. When it is cleared, the data cache is disabled. A reset operation clears the ED bit. The supervisor normally enables the data cache, but it can clear ED for system debugging or emulation, as required. Disabling the data cache does not flush the entries. If it is enabled again, the previously valid entries remain valid and can be used. 6.3.1.7 INSTRUCTION BURST ENABLE. Bit 4, the IBE bit, is set to enable burst filling of the instruction cache. Operating systems and other software set this bit when burst filling of the instruction cache is desired. A reset operation clears the IBE bit. 6.3.1.8 CLEAR INSTRUCTION CACHE. Bit 3, the CI bit, is set to clear all entries in the instruction cache. Operating systems and other software set this bit to clear instructions from the cache prior to a context switch. The processor clears all valid bits in the instruction cache at the time a MOVEC instruction loads a one into the CI bit of the CACR. The CI bit is always read as a zero. 6.3.1.9 CLEAR ENTRY IN INSTRUCTION CACHE. Bit 2, the CEI bit, is set to clear an entry in the instruction cache. The index field of the CAAR (see Figure 6-15) corresponding to the index and long-word select portion of an address specifies the entry to be cleared. The processor clears only the specified long word by clearing the valid bit for the entry at the time a MOVEC instruction loads a one into the CEI bit of the CACR, regardless of the states of the EI and FI bits. The CEI bit is always read as a zero. MOTOROLA MC68030 USER'S MANUAL 6-17 On-Chip Cache Memories 6.3.1.10 FREEZE INSTRUCTION CACHE. Bit 1, the FI bit, is set to freeze the instruction cache. When the FI bit is set and a miss occurs in the instruction cache, the entry (or line) is not replaced. When the FI bit is cleared to zero, a miss in the instruction cache causes the entry (or line) to be filled. A reset operation clears the FI bit. 6.3.1.11 ENABLE INSTRUCTION CACHE. Bit 0, the EI bit, is set to enable the instruction cache. When it is cleared, the instruction cache is disabled. A reset operation clears the EI bit. The supervisor normally enables the instruction cache, but it can clear EI for system debugging or emulation, as required. Disabling the instruction cache does not flush the entries. If it is enabled again, the previously valid entries remain valid and may be used. 6.3.2 Cache Address Register The CAAR is a 32-bit register shown in Figure 6-15. The index field (bits 7-2) contains the address for the "clear cache entry" operations. The bits of this field correspond to bits 7-2 of addresses; they specify the index and a long word of a cache line. Although only the index field is used currently, all 32 bits of the register are implemented and are reserved for use by Motorola. 31 8 7 CACHE FUNCTION ADDRESS 2 1 0 INDEX Figure 6-15. Cache Address Register 6-18 MC68030 USER'S MANUAL MOTOROLA SECTION 7 BUS OPERATION This section provides a functional description of the bus, the signals that control it, and the bus cycles provided for data transfer operations. It also describes the error and halt conditions, bus arbitration, and the reset operation. Operation of the bus is the same whether the processor or an external device is the bus master; the names and descriptions of bus cycles are from the point of view of the bus master. For exact timing specifications, refer to Section 13 Electrical Characteristics. The MC68030 architecture supports byte, word, and long-word operands, allowing access to 8-, 16-, and 32-bit data ports through the use of asynchronous cycles controlled by the data transfer and size acknowledge inputs (DSACK0 and DSACK1). Synchronous bus cycles controlled by the synchronous termination signal (STERM) can only be used to transfer data to and from 32-bit ports. The MC68030 allows byte, word, and long-word operands to be located in memory on any byte boundary. For a misaligned transfer, more than one bus cycle may be required to complete the transfer, regardless of port size. For a port less than 32 bits wide, multiple bus cycles may be required for an operand transfer due to either misalignment or a port width smaller than the operand size. Instruction words and their associated extension words must be aligned on word boundaries. The user should be aware that misalignment of word or long-word operands can cause the MC68030 to perform multiple bus cycles for the operand transfer; therefore, processor performance is optimized if word and long-word memory operands are aligned on word or long-word boundaries, respectively. 7.1 BUS TRANSFER SIGNALS The bus transfers information between the MC68030 and an external memory, coprocessor, or peripheral device. External devices can accept or provide 8 bits, 16 bits, or 32 bits in parallel and must follow the handshake protocol described in this section. The maximum number of bits accepted or provided during a bus transfer is defined as the port width. The MC68030 contains an address bus that specifies the address for the transfer and a data bus that transfers the data. Control signals indicate the beginning of the cycle, the address space and the size of the transfer, and the type of cycle. The selected device then controls the length of the cycle with the signal(s) used to terminate the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity of the address and provide timing information for the data. MOTOROLA MC68030 USER'S MANUAL 7-1 Bus Operation The bus can operate in an asynchronous mode identical to the MC68020 bus for any port width. The bus and control input signals used for asynchronous operation are internally synchronized to the MC68030 clock, introducing a delay. This delay is the time period required for the MC68030 to sample an asynchronous input signal, synchronize the input to the internal clocks of the processor, and determine whether it is high or low. Figure 7-1 shows the relationship between the clock signal and the associated internal signal of a typical asynchronous input. CLK EXT INT SYNC DELAY Figure 7-1. Relationship between External and Internal Signals Furthermore, for all asynchronous inputs, the processor latches the level of the input during a sample window around the falling edge of the clock signal. This window is illustrated in Figure 7-2. To ensure that an input signal is recognized on a specific falling edge of the clock, that input must be stable during the sample window. If an input makes a transition during the window time period, the level recognized by the processor is not predictable; however, the processor always resolves the latched level to either a logic high or low before using it. In addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this section. 7-2 MC68030 USER'S MANUAL MOTOROLA Bus Operation t su th CLK EXT SAMPLE WINDOW Figure 7-2. Asynchronous Input Sample Window A device with a 32-bit port size can also provide a synchronous mode transfer. In synchronous operation, input signals are externally synchronized to the processor clock, and the synchronizing delay is not incurred. Synchronous inputs (STERM, CBACK, and CIIN) must remain stable during a sample window for all rising edges of the clock during a bus cycle (i.e., while address strobe (AS) is asserted), regardless of when the signals are asserted or negated, to ensure proper operation. This sample window is defined by the synchronous input setup and hold times (see MC68030EC/D, MC68030 Electrical Specifications). 7.1.1 Bus Control Signals The external cycle start (ECS) signal is the earliest indication that the processor is initiating a bus cycle. The MC68030 initiates a bus cycle by driving the address, size, function code, read/write, and cache inhibit-out outputs and by asserting ECS. However, if the processor finds the required program or data item in an on-chip cache, if a miss occurs in the address translation cache (ATC) of the memory management unit (MMU), or if the MMU finds a fault with the access, the processor aborts the cycle before asserting AS. ECS can be used to initiate various timing sequences that are eventually qualified with AS. Qualification with AS may be required since, in the case of an internal cache hit, an ATC miss, or an MMU fault, a bus cycle may be aborted after ECS has been asserted. The assertion of AS ensures that the cycle has not been aborted by these internal conditions. During the first external bus cycle of an operand transfer, the operand cycle start (OCS) signal is asserted with ECS. When several bus cycles are required to transfer the entire operand, OCS is asserted only at the beginning of the first external bus cycle. With respect to OCS, an "operand'' is any entity required by the execution unit, whether a program or data item. The function code signals (FC0-FC2) are also driven at the beginning of a bus cycle. These three signals select one of eight address spaces (refer to Table 4-1) to which the address applies. Five address spaces are presently defined. Of the remaining three, one is reserved MOTOROLA MC68030 USER'S MANUAL 7-3 Bus Operation for user definition and two are reserved by Motorola for future use. The function code signals are valid while AS is asserted. At the beginning of a bus cycle, the size signals (SIZ0 and SIZ1) are driven along with ECS and the FC0-FC2. SIZ0 and SIZ1 indicate the number of bytes remaining to be transferred during an operand cycle (consisting of one or more bus cycles) or during a cache fill operation from a device with a port size that is less than 32 bits. Table 7-2 shows the encoding of SIZ0 and SIZ1. These signals are valid while AS is asserted. The read/write (R/W) signal determines the direction of the transfer during a bus cycle. This signal changes state, when required, at the beginning of a bus cycle and is valid while AS is asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice versa. The signal may remain low for two consecutive write cycles. The read-modify-write cycle signal (RMC) is asserted at the beginning of the first bus cycle of a read-modify-write operation and remains asserted until completion of the final bus cycle of the operation. The RMC signal is guaranteed to be negated before the end of state 0 for a bus cycle following a read-modify-write operation. 7.1.2 Address Bus The address bus signals (A0-A31) define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The processor places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted. 7.1.3 Address Strobe AS is a timing signal that indicates the validity of an address on the address bus and of many control signals. It is asserted one-half clock after the beginning of a bus cycle. 7-4 MC68030 USER'S MANUAL MOTOROLA Bus Operation 7.1.4 Data Bus The data bus signals (D0-D31) comprise a bidirectional, nonmultiplexed parallel bus that contains the data being transferred to or from the processor. A read or write operation may transfer 8, 16, 24, or 32 bits of data (one, two, three, or four bytes) in one bus cycle. During a read cycle, the data is latched by the processor on the last falling edge of the clock for that bus cycle. For a write cycle, all 32 bits of the data bus are driven, regardless of the port width or operand size. The processor places the data on the data bus one-half clock cycle after AS is asserted in a write cycle. 7.1.5 Data Strobe The data strobe (DS) is a timing signal that applies to the data bus. For a read cycle, the processor asserts DS to signal the external device to place data on the bus. It is asserted at the same time as AS during a read cycle. For a write cycle, DS signals to the external device that the data to be written is valid on the bus. The processor asserts DS one full clock cycle after the assertion of AS during a write cycle. 7.1.6 Data Buffer Enable The data buffer enable signal (DBEN) can be used to enable external data buffers while data is present on the data bus. During a read operation, DBEN is asserted one clock cycle after the beginning of the bus cycle and is negated as DS is negated. In a write operation, DBEN is asserted at the time AS is asserted and is held active for the duration of the cycle. In a synchronous system supporting two-clock bus cycles, DBEN timing may prevent its use. 7.1.7 Bus Cycle Termination Signals During asynchronous bus cycles, external devices assert the data transfer and size acknowledge signals (DSACK0 and/or DSACK1) as part of the bus protocol. During a read cycle, the assertion of DSACKx signals the processor to terminate the bus cycle and to latch the data. During a write cycle, the assertion of DSACKx indicates that the external device has successfully stored the data and that the cycle may terminate. These signals also indicate to the processor the size of the port for the bus cycle just completed, as shown in Table 7-1. Refer to 7.3.1 Asynchronous Read Cycle for timing relationships of DSACK0 and DSACK1. MOTOROLA MC68030 USER'S MANUAL 7-5 Bus Operation For synchronous bus cycles, external devices assert the synchronous termination signal (STERM) as part of the bus protocol. During a read cycle, the assertion of STERM causes the processor to latch the data. During a write cycle, it indicates that the external device has successfully stored the data. In either case, it terminates the cycle and indicates that the transfer was made to a 32-bit port. Refer to 7.3.2 Asynchronous Write Cycle for timing relationships of STERM. The bus error (BERR) signal is also a bus cycle termination indicator and can be used in the absence of DSACKx or STERM to indicate a bus error condition. It can also be asserted in conjunction with DSACKx or STERM to indicate a bus error condition, provided it meets the appropriate timing described in this section and in MC68030EC/D, MC68030 Electrical Specifications. Additionally, the BERR and HALT signals can be asserted together to indicate a retry termination. Again, the BERR and HALT signals can be asserted simultaneously in lieu of or in conjunction with the DSACKx or STERM signals. Finally, the autovector (AVEC) signal can be used to terminate interrupt acknowledge cycles, indicating that the MC68030 should internally generate a vector number to locate an interrupt handler routine. AVEC is ignored during all other bus cycles. 7.2 DATA TRANSFER MECHANISM The MC68030 architecture supports byte, word, and long-word operands allowing access to 8-, 16-, and 32-bit data ports through the use of asynchronous cycles controlled by DSACK0 and DSACK1. It also supports synchronous bus cycles to and from 32-bit ports, terminated by STERM. Byte, word, and long-word operands can be located on any byte boundary, but misaligned transfers may require additional bus cycles, regardless of port size. When the processor requests a burst mode fill operation, it asserts the cache burst request (CBREQ) signal to attempt to fill four entries within a line in one of the on-chip caches. This mode is compatible with nibble, static column, or page mode dynamic RAMs. The burst fill operation uses synchronous bus cycles, each terminated by STERM, to fetch as many as four long words. 7.2.1 Dynamic Bus Sizing The MC68030 dynamically interprets the port size of the addressed device during each bus cycle, allowing operand transfers to or from 8-, 16-, and 32-bit ports. During an asynchronous operand transfer cycle, the slave device signals its port size (byte, word, or long word) and indicates completion of the bus cycle to the processor through the use of the DSACKx inputs. Refer to Table 7-1 for DSACKx encodings and assertion results. 7-6 MC68030 USER'S MANUAL MOTOROLA Bus Operation Table 7-1. DSACK Codes and Results DSACK1 DSACK0 Result H H Insert Wait States in Current Bus Cycle H L Complete Cycle -- Data Bus Port Size is 8 Bits L H Complete Cycle -- Data Bus Port Size is 16 Bits L L Complete Cycle -- Data Bus Port Size is 32 Bits For example, if the processor is executing an instruction that reads a long-word operand from a long-word aligned address, it attempts to read 32 bits during the first bus cycle. (Refer to 7.2.2 Misaligned Operands for the case of a word or byte address.) If the port responds that it is 32 bits wide, the MC68030 latches all 32 bits of data and continues with the next operation. If the port responds that it is 16 bits wide, the MC68030 latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits. The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the DSACKx signals to indicate the port width. For instance, a 32-bit device always returns DSACKx for a 32-bit port (regardless of whether the bus cycle is a byte, word, or long-word operation). Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. A 32-bit port must reside on data bus bits 0-31, a 16-bit port must reside on data bus bits 16-32, and an 8-bit port must reside on data bus bits 24-31. This requirement minimizes the number of bus cycles needed to transfer data to 8- and 16bit ports and ensures that the MC68030 correctly transfers valid data. The MC68030 always attempts to transfer the maximum amount of data on all bus cycles; for a long-word operation, it always assumes that the port is 32 bit wide when beginning the bus cycle. The bytes of operands are designated as shown in Figure 7-3. The most significant byte of a long-word operand is OP0, and OP3 is the least significant byte. The two bytes of a wordlength operand are OP2 (most significant) and OP3. The single byte of a byte-length operand is OP3. These designations are used in the figures and descriptions that follow. MOTOROLA MC68030 USER'S MANUAL 7-7 Bus Operation 31 LONG WORD OPERAND 0 OP0 OP1 OP2 OP3 15 0 WORD OPERAND OP2 OP3 7 BYTE OPERAND 0 OP3 Figure 7-3. Internal Operand Representation Figure 7-4 shows the required organization of data ports on the MC68030 bus for 8, 16, and 32-bit devices. The four bytes shown in Figure 7-4 are connected through the internal data bus and data multiplexer to the external data bus. This path is the means through which the MC68030 supports dynamic bus sizing and operand misalignment. Refer to 7.2.2 Misaligned Operands for the definition of misaligned operand. The data multiplexer establishes the necessary connections for different combinations of address and data sizes. The multiplexer takes the four bytes of the 32-bit bus and routes them to their required positions. For example, OP0 can be routed to D24-D31, as would be the normal case, or it can be routed to any other byte position to support a misaligned transfer. The same is true for any of the operand bytes. The positioning of bytes is determined by the size (SIZ0 and SIZ1) and address (A0 and A1) outputs. The SIZ0 and SIZ1 outputs indicate the remaining number of bytes to be transferred during the current bus cycle, as shown in Table 7-2. The number of bytes transferred during a write or noncachable read bus cycle is equal to or less than the size indicated by the SIZ0 and SIZ1 outputs, depending on port width and operand alignment. For example, during the first bus cycle of a long-word transfer to a word port, the size outputs indicate that four bytes are to be transferred, although only two bytes are moved on that bus cycle. Cachable read cycles must always transfer the number of bytes indicated by the port size. A0 and A1 also affect operation of the data multiplexer. During an operand transfer, A2-A31 indicate the long-word base address of that portion of the operand to be accessed; A0 and A1 indicate the byte offset from the base. Table 7-3 shows the encodings of A0 and A1 and the corresponding byte offsets from the long-word base. 7-8 MC68030 USER'S MANUAL MOTOROLA Bus Operation OP0 OP1 OP2 OP3 0 1 2 3 REGISTER MULTIPLEXER ROUTING AND DUPLICATION EXTERNAL DATA BUS D31- D24 D23-D16 D15-D8 D7-D0 ADDRESS xxxxxxxx0 BYTE 0 BYTE 1 BYTE 2 BYTE 3 xxxxxxxx0 BYTE 0 BYTE 1 2 BYTE 2 BYTE 3 INCREASING MEMORY ADDRESSES INTERNAL TO THE MC68EC030 EXTERNAL BUS 32-BIT PORT 16-BIT PORT a b xxxxxxxx0 BYTE 0 1 BYTE 1 2 BYTE 2 3 BYTE 3 8-BIT PORT FIG 7-4 Figure 7-4. MC68030 Interface to Various Port Sizes Table 7-4 lists the bytes required on the data bus for read cycles that are cachable. The entries shown as OPn are portions of the requested operand that are read or written during that bus cycle and are defined by SIZ0, SIZ1, A0, and A1 for the bus cycle. The PRn and the Nn bytes correspond to the previous and next bytes in memory, respectively, that must be valid on the data bus for the specified port size (long word or word) so that the internal caches operate correctly. (For cachable accesses, the MC68030 assumes that all portions of the data bus for a given port size are valid.) This same table applies to noncachable read cycles except that the bytes labeled PRn and Nn are not required and can be replaced by "don't cares". Table 7-2. Size Signal Encoding SIZ1 0 1 1 0 MOTOROLA SIZ0 1 0 1 0 Size Byte Word 3 Bytes Long Word Table 7-3. Address Offset Encodings A1 0 0 1 1 MC68030 USER'S MANUAL A0 0 1 0 1 Offset +0 Bytes +1 Byte +2 Bytes +3 Bytes 7-9 Bus Operation Table 7-4. Data Bus Requirements for Read Cycles. (Table did not make it over in the conversion from Word) Table 7-5 lists the combinations of SIZ0, SIZ1, A0, and A1 and the corresponding pattern of the data transfer for write cycles from the internal multiplexer of the MC68030 to the external data bus. Figure 7-5 shows the transfer of a long-word operand to a word port. In the first bus cycle, the MC68030 places the four operand bytes on the external bus. Since the address is longword aligned in this example, the multiplexer follows the pattern in the entry of Table 7-5 corresponding to SIZ0_SIZ1_A0_A1=0000. The port latches the data on bits D16-D31 of the data bus, asserts DSACK1 (DSACK0 remains negated), and the processor terminates the bus cycle. It then starts a new bus cycle with SIZ0_SIZ1_A0_A1=1010 to transfer the remaining 16 bits. SIZ0 and SIZ1 indicate that a word remains to be transferred; A0 and A1 indicate that the word corresponds to an offset of two from the base address. The multiplexer follows the pattern corresponding to this configuration of the size and address signals and places the two least significant bytes of the long word on the word portion of the bus (D16-D31). The bus cycle transfers the remaining bytes to the word-size port. Figure 76 shows the timing of the bus transfer signals for this operation. 7-10 MC68030 USER'S MANUAL MOTOROLA Bus Operation Table 7-5. MC68030 Internal to External Data Bus. (Table did not make it over in the conversion from Word) 31 LONG WORD OPERAND OP0 OP1 D31 DATA BUS 0 OP2 OP3 D16 WORD MEMORY MC68EC030 MSB LSB OP0 OP1 OP2 OP3 SIZ1 0 1 SIZ0 0 0 A1 0 1 MEMORY CONTROL A0 0 0 DSACK1 L L DSACK0 H H Figure 7-5. Example of Long-Word Transfer to Word Port MOTOROLA MC68030 USER'S MANUAL 7-11 Bus Operation S0 S2 S4 S0 S2 S4 CLK A31-A2 A1 A0 FC2-FC0 SIZ1 SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 OP0 OP2 D23-D16 OP1 OP3 WORD WRITE WORD WRITE LONG WORD OPERAND WRITE TO 16-BIT PORT Figure 7-6. Long-Word Operand Write Timing (16-Bit Data Port) Figure 7-7 shows a word transfer to an 8-bit bus port. Like the preceding example, this example requires two bus cycles. Each bus cycle transfers a single byte. The size signals for the first cycle specify two bytes; for the second cycle, one byte. Figure 7-8 shows the associated bus transfer signal timing. 7-12 MC68030 USER'S MANUAL MOTOROLA Bus Operation 15 WORD OPERAND OP2 0 OP3 D31 DATA BUS D24 BYTE MEMORY MC68EC030 OP2 MEMORY CONTROL SIZ1 1 SIZ0 0 A1 0 A0 0 DSACK1 H DSACK0 L 0 1 0 1 H L OP3 Figure 7-7. Example of Word Transfer to Byte Port 7.2.2 Misaligned Operands Since operands may reside at any byte boundaries, they may be misaligned. A byte operand is properly aligned at any address; a word operand is misaligned at an odd address; a long word is misaligned at an address that is not evenly divisible by four. The MC68000, MC68008, and MC68010 implementations allow long-word transfers on odd-word boundaries but force exceptions if word or long-word operand transfers are attempted at odd-byte addresses. Although the MC68030 does not enforce any alignment restrictions for data operands (including PC relative data addresses), some performance degradation occurs when additional bus cycles are required for long-word or word operands that are misaligned. For maximum performance, data items should be aligned on their natural boundaries. All instruction words and extension words must reside on word boundaries. Attempting to prefetch an instruction word at an odd address causes an address error exception. MOTOROLA MC68030 USER'S MANUAL 7-13 Bus Operation S0 S2 S4 S0 S2 S4 CLK A31-A2 A1 A0 FC2-FC0 SIZ1 SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 OP2 OP3 D23-D16 OP3 OP3 D15-D8 OP2 OP3 D7-D0 OP3 OP3 BYTE WRITE BYTE WRITE WORD OPERAND WRITE Figure 7-8. Word Operand Write Timing (8-Bit Data Port) 7-14 MC68030 USER'S MANUAL MOTOROLA Bus Operation Figure 7-9 shows the transfer of a long-word operand to an odd address in word-organized memory, which requires three bus cycles. For the first cycle, the size signals specify a longword transfer, and the address offset (A2:A0) is 001. Since the port width is 16 bits, only the first byte of the long word is transferred. The slave device latches the byte and acknowledges the data transfer, indicating that the port is 16 bits wide. When the processor starts the second cycle, the size signals specify that three bytes remain to be transferred with an address offset (A2:A0) of 010. The next two bytes are transferred during this cycle. The processor then initiates the third cycle, with the size signals indicating one byte remaining to be transferred. The address offset (A2:A0) is now 100; the port latches the final byte; and the operation is complete. Figure 7-10 shows the associated bus transfer signal timing. Figure 7-11 shows the equivalent operation for a cachable data read cycle. Figures 7-12 and 7-13 show a word transfer to an odd address in word-organized memory. This example is similar to the one shown in Figures 7-9 and 7-10 except that the operand is word sized and the transfer requires only two bus cycles. Figure 7-14 shows the equivalent operation for a cachable data read cycle. 31 LONG WORD OPERAND OP0 OP1 DATA BUS D31 0 OP2 OP3 D16 WORD MEMORY MSB LSB XXX OP0 OP1 OP2 OP3 XXX MC68EC030 MEMORY CONTROL SIZ1 0 SIZ0 0 A1 0 A0 0 1 0 1 1 0 1 1 0 A0 1 DSACK1 L DSACK0 H 0 0 L L H H Figure 7-9. Misaligned Long-Word Transfer to Word Port Example MOTOROLA MC68030 USER'S MANUAL 7-15 Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 S4 CLK A31-A2 A1 A0 FC2-FC0 SIZ1 SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 OP0 OP1 OP3 D23-D16 OP0 OP2 OP3 D15-D8 OP1 OP1 OP3 D7-D0 OP2 OP2 OP3 BYTE WRITE WORD WRITE BYTE WRITE LONG WORD OPERAND WRITE Figure 7-10. Misaligned Long-Word Transfer to Word Port 7-16 MC68030 USER'S MANUAL MOTOROLA Bus Operation 31 LONG WORD OPERAND (REGISTER) OP0 OP1 0 OP2 OP3 31 CACHE ENTRIES PR 0 OP0 OP1 OP2 31 0 OP3 N N1 N2 DATA BUS D31 D16 WORD MEMORY MC68EC030 MSB LSB PR OP0 OP1 OP2 OP3 N N1 N2 MEMORY CONTROL A1 0 A0 0 A0 1 DSACK1 L DSACK0 H 1 0 1 H 1 1 0 1 0 0 0 L 1 0 L L H H SIZ1 0 SIZ0 0 1 0 1 Figure 7-11. Misaligned Cachable Long-Word Transfer from Word Port Example 15 WORD OPERAND OP2 0 OP3 D31 DATA BUS D16 WORD MEMORY MEMORY CONTROL MC68030 MSB LSB SIZ1 SIZ0 XXX OP2 1 OP3 XXX 0 A2 A1 A0 DSACK1 DSACK0 0 0 0 1 L H 1 0 1 0 L H Figure 7-12. Misaligned Word Transfer to Word Port Example MOTOROLA MC68030 USER'S MANUAL 7-17 Bus Operation S0 S2 S4 S0 S4 S2 CLK A31-A2 A1 A0 FC2-FC0 SIZ1 SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 OP2 OP3 D23-D16 OP2 OP3 D15-D8 OP3 OP3 D7-D0 OP2 OP3 WORD WRITE BYTE WRITE WORD OPERAND WRITE TO A1/A0=01 Figure 7-13. Misaligned Word Transfer to Word Port 7-18 MC68030 USER'S MANUAL MOTOROLA Bus Operation Figures 7-15 and 7-16 show an example of a long-word transfer to an odd address in longword-organized memory. In this example, a long-word access is attempted beginning at the least significant byte of a long-word-organized memory. Only one byte can be transferred in the first bus cycle. The second bus cycle then consists of a three-byte access to a long-word boundary. Since the memory is long-word organized, no further bus cycles are necessary. Figure 7-17 shows the equivalent operation for a cachable data read cycle. 7.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment The combination of operand size, operand alignment, and port size determines the number of bus cycles required to perform a particular memory access. Table 7-6 shows the number of bus cycles required for different operand sizes to different port sizes with all possible alignment conditions for write cycles and noncachable read cycles. Table 7-6. Memory Alignment and Port Size Influence on Write Bus Cycles A1/A0 Instruction* Byte Operand Word Operand Long-Word Operand 00 1:2:4 1:1:1 1:1:2 1:2:4 Number of Bus Cycles 01 10 N/A N/A 1:1:1 1:1:1 1:2:2 1:1:2 2:3:4 2:2:4 11 N/A 1:1:1 2:2:2 2:3:4 Data Port Size -- 32 Bits:16 Bits:8 Bits *Instruction prefetches are always two words from a long-word boundary. This table shows that bus cycle throughput is significantly affected by port size and alignment. The MC68030 system designer and programmer should be aware of and account for these effects, particularly in time-critical applications. MOTOROLA MC68030 USER'S MANUAL 7-19 Bus Operation 15 WORD OPERAND (REGISTER) OP2 0 31 CACHE ENTRY OP3 PR OP2 0 OP3 N DATA BUS D31 D16 WORD MEMORY MC68EC030 MSB LSB SIZ1 SIZ0 XXX OP2 1 0 0 OP3 XXX 0 1 0 MEMORY CONTROL A2 A1 A0 DSACK1 DSACK0 0 1 L H 1 0 L H Figure 7-14. Example of Misaligned Cachable Word Transfer from Word Bus 15 LONG WORD OPERAND OP0 OP1 D31 OP2 0 OP3 DATA BUS D0 LONG WORD MEMORY MC68EC030 MSB UMB LMB LSB XXX XXX XXX OP0 0 OP1 OP2 OP3 XXX 1 SIZ1 SIZ0 MEMORY CONTROL A2 A1 A0 DSACK1 DSACK0 0 0 1 1 L L 1 1 0 0 L L Figure 7-15. Misaligned Long-Word Transfer to Long-Word Port Table 7-6 shows that the processor always prefetches instructions by reading a long word from a long-word address (A1:A0=00), regardless of port size or alignment. When the required instruction begins at an odd-word boundary, the processor attempts to fetch the entire 32 bits and loads both words into the instruction cache, if possible, although the second one is the required word. Even if the instruction access is not cached, the entire 32 bits are latched into an internal cache holding register from which the two instructions words can subsequently be referenced. Refer to Section 11 Instruction Execution Timing for a complete description of the cache holding register and pipeline operation. 7-20 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S2 S4 S0 S2 S4 CLK A31-A2 A1 A0 FC2-FC0 SIZ1 SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 OP0 OP1 D23-D16 OP0 OP2 D15-D8 OP1 OP3 D7-D0 OP0 OP1 BYTE WRITE 3 - BYTE WRITE LONG WORD OPERAND WRITE Figure 7-16. Misaligned Write Cycles to Long-Word Port MOTOROLA MC68030 USER'S MANUAL 7-21 Bus Operation 31 LONG WORD OPERAND (REGISTER) OP0 OP1 0 OP2 OP3 31 CACHE ENTRIES PR2 PR1 0 PR OP0 31 0 OP1 OP2 OP3 N DATA BUS D31 D0 LONG WORD MEMORY MC68EC030 MSB UMB LMB LSB PR2 PR1 PR OP0 0 OP1 OP2 OP3 N 1 SIZ1 SIZ0 MEMORY CONTROL DSACK1 DSACK0 1 L L 0 L L A2 A1 A0 0 0 1 1 1 0 Figure 7-17. Misaligned Cachable Long-Word Transfer from Long-Word Bus 7.2.4 Address, Size, and Data Bus Relationships The data transfer examples show how the MC68030 drives data onto or receives data from the correct byte sections of the data bus. Table 7-7 shows the combinations of the size signals and address signals that are used to generate byte enable signals for each of the four sections of the data bus for noncachable read cycles and all write cycles if the addressed device requires them. The port size also affects the generation of these enable signals as shown in the table. The four columns on the right correspond to the four byte enable signals. Letters B, W, and L refer to port sizes: B for 8-bit ports, W for 16-bit ports, and L for 32-bit ports. The letters B, W, and L imply that the byte enable signal should be true for that port size. A dash (--) implies that the byte enable signal does not apply. The MC68030 always drives all sections of the data bus because, at the start of a write cycle, the bus controller does not know the port size. The byte enable signals in the table apply only to read operations that are not to be internally cached and to write operations. For cachable read cycles, during which the data is cached, the addressed port must drive all sections of the bus on which it resides. 7-22 MC68030 USER'S MANUAL MOTOROLA Bus Operation Table 7-7. Data Bus Write Enable Signals for Byte, Word, and Long-Word Ports Transfer Size Byte Word 3 Byte Long Word SIZ1 SIZ0 A1 A0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Data Bus Active Sections Byte (B) - Word (W) - Long-Word (L) Ports D31:D24 D23:D16 D15:D8 D7:D0 -- -- -- BWL -- -- WL B -- L -- BW L -- W B -- -- WL BWL -- L WL B L L W BW L -- W B -- L WL BWL L L WL B L L W BW L -- W B L L WL BWL L L WL B L L W BW L -- W B The table shows that the MC68030 transfers the number of bytes specified by the size signals to or from the specified address unless the operand is misaligned or the number of bytes is greater than the port width. In these cases, the device transfers the greatest number of bytes possible for the port. For example, if the size is four bytes and the address offset (A1:A0) is 01, a 32-bit slave can only receive three bytes in the current bus cycle. A 16- or 8-bit[lz slave can only receive one byte. The table defines the byte enables for all port sizes. Byte data strobes can be obtained by combining the enable signals with the data strobe signal. Devices residing on 8-bit ports can use the data strobe by itself since there is only one valid byte for every transfer. These enable or strobe signals select only the bytes required for write cycles or for noncachable read cycles. The other bytes are not selected, which prevents incorrect accesses in sensitive areas such as I/O. Figure 7-18 shows a logic diagram for one method for generating byte data enable signals for 16- and 32-bit ports from the size and address encodings and the read/write signal. MOTOROLA MC68030 USER'S MANUAL 7-23 Bus Operation 7.2.5 MC68030 versus MC68020 Dynamic Bus Sizing The MC68030 supports the dynamic bus sizing mechanism of the MC68020 for asynchronous bus cycles (terminated with DSACKx) with two restrictions. First, for a cachable access within the boundaries of an aligned long word, the port size must be consistent throughout the transfer of each long word. For example, when a byte port resides at address $00, addresses $01, $02, and $03 must also correspond to byte ports. Second, the port must supply as much data as it signals as port size, regardless of the transfer size indicated with the size signals and the address offset indicated by A0 and A1 for cachable accesses. Otherwise, dynamic bus sizing is identical in the two processors. 7.2.6 Cache Filling The on-chip data and instruction caches, described in Section 6 On-Chip Cache Memories, are each organized as 16 lines of four long-word entries each. For each line, a tag contains the most significant bits of the logical address, FC2 (instruction cache) or FC0- FC2 (data cache), and a valid bit for each entry in the line. An entry fill operation loads an entire long word accessed from memory into a cache entry. This type of fill operation is performed when one entry of a line is not valid and an access is cachable. A burst fill operation is requested when a tag miss occurs for the current cycle or when all four entires in the cache line are invalid (provided the cache is enabled and burst filling for the cache is enabled). The burst fill operation attempts to fill all four entries in the line. To support burst filling, the slave device must have a 32-bit port and must have a burst mode capability; that is, it must acknowledge a burst request with the cache burst acknowledge (CBACK) signal. It must also terminate the burst accesses with STERM and place a long word on the data bus for each transfer. The device may continue to supply successive long words, asserting STERM with each one, until the cache line is full. For further information about filling the cache, both entry fills and burst mode fills, refer to 6.1.3 Cache Filling, 7.3.4 Synchronous Read Cycle, 7.3.5 Synchronous Write Cycle, and 7.3.7 Burst Operation Cycles, which discuss in detail the required bus cycles. 7-24 MC68030 USER'S MANUAL MOTOROLA Bus Operation 7.2.7 Cache Interactions The organization and requirements of the on-chip instruction and data caches affect the interpretation of the DSACKx and STERM signals. Since the MC68030 attempts to load all data operands and instructions that are cachable into the on-chip caches, the bus may operate differently when caching is enabled. Specifically, on cachable read cycles that terminate normally, the low-order address signals (A0 and A1) and the size signals do not apply. The slave device must supply as much aligned data on the data bus as its port size allows, regardless of the requested operand size. This means that an 8-bit port must supply a byte, a 16-bit port must supply a word, and a 32-bit port must supply an entire long word. This data is loaded into the cache. For a 32-bit port, the slave device ignores A0 and A1 and supplies the long word beginning at the long-word boundary on the data bus. For a 16-bit[lz port, the device ignores A0 and supplies the entire word beginning at the lower word boundary on D16-D31 of the data bus. For a byte port, the device supplies the addressed byte on D24-D31. If the addressed device cannot supply port-sized data or if the data should not be cached, the device must assert cache inhibit in (CIIN) as it terminates the read cycle. If the bus cycle terminates abnormally, the MC68030 does not cache the data. For details of interactions of port sizes, misalignments, and cache filling, refer to 6.1.3 Cache Filling. The caches can also affect the assertion of AS and the operation of a read cycle. The search of the appropriate cache by the processor begins when the microsequencer requires an instruction or a data item. At this time, the bus controller may also initiate an external bus cycle in case the requested item is not resident in the instruction or data cache. If the bus is not occupied with another read or write cycle, the bus controller asserts the ECS signal (and the OCS signal, if appropriate). If an internal cache hit occurs, the external cycle aborts, and AS is not asserted. This makes it possible to have ECS asserted on multiple consecutive clock cycles. Notice that there is a minimum time specified from the negation of ECS to the next assertion of ECS (refer to MC68030EC/D, MC68030 Electrical Specifications. Instruction prefetches can occur every other clock so that if, after an aborted cycle due to an instruction cache hit, the bus controller asserts ECS on the next clock, this second cycle is for a data fetch. However, data accesses that hit in the data cache can also cause the assertion of ECS and an aborted cycle. Therefore, since instruction and data accesses are mixed, it is possible to see multiple successive ECS assertions on the external bus if the processor is hitting in both caches and if the bus controller is free. Note that, if the bus controller is executing other cycles, these aborted cycles due to cache hits may not be seen externally. Also, OCS is asserted for the first external cycle of an operand transfer. Therefore, in the case of a misaligned data transfer where the first portion of the operand results in a cache hit (but the bus controller did not begin an external cycle and then abort it) and the second portion in a cache miss, OCS is asserted for the second portion of the operand. MOTOROLA MC68030 USER'S MANUAL 7-25 Bus Operation UUD UMD LMD LLD UD LD A0 A1 SIZ0 SIZ1 UUD = UPPER UPPER DATA (32-BIT PORT) UMD = UPPER MIDDLE DATA (32-BIT PORT) LMD = LOWER MIDDLE DATA (32-BIT PORT) LLD = LOWER LOWER DATA (32-BIT PORT) UD = UPPER DATA (16-BIT PORT) LD = LOWER DATA (16-BIT PORT) R/W NOTE: These select lines can be combined with the address decode circuitry or all can be generated within the same programmed array logic unit. Figure 7-18. Byte Data Select Generation for 16- and 32-Bit Ports 7-26 MC68030 USER'S MANUAL MOTOROLA Bus Operation 7.2.8 Asynchronous Operation The MC68030 bus may be used in an asynchonous manner. In that case, the external devices connected to the bus can operate at clock frequencies different from the clock for the MC68030. Asynchronous operation requires using only the handshake line (AS, DS, DSACK1, DSACK0, BERR, and HALT) to control data transfers. Using this method, AS signals the start of a bus cycle, and DS is used as a condition for valid data on a write cycle. Decoding the size outputs and lower address lines (A0 and A1) provides strobes that select the active portion of the data bus. The slave device (memory or peripheral) then responds by placing the requested data on the correct portion of the data bus for a read cycle or latching the data on a write cycle, and asserting the DSACK1/DSACK0 combination that corresponds to the port size to terminate the cycle. If no slave responds or the access is invalid, external control logic asserts the BERR or BERR and HALT signal(s) to abort or retry the bus cycle, respectively. The DSACKx signals can be asserted before the data from a slave device is valid on a read cycle. The length of time that DSACKx may precede data is given by parameter #31, and it must be met in any asynchronous system to insure that valid data is latched into the processor. (Refer to MC68030EC/D, MC68030 Electrical Specifications for timing parameters.) Notice that no maximum time is specified from the assertion of AS to the assertion of DSACKx. Although the processor can transfer data in a minimum of three clock cycles when the cycle is terminated with DSACKx, the processor inserts wait cycles in clock period increments until DSACKx is recognized. The BERR and/or HALT signals can be asserted after the DSACKx signal(s) is asserted. BERR and/or HALT must be asserted within the time given as parameter #48, after DSACKx is asserted in any asynchronous system. If this maximum delay time is violated, the processor may exhibit erratic behavior. MOTOROLA MC68030 USER'S MANUAL 7-27 Bus Operation For asynchronous read cycles, the value of CIIN is internally latched on the rising edge of bus cycle state 4. Refer to 7.3.1 Asynchronous Read Cycle for more details on the states for asynchonous read cycles. During any bus cycle terminated by DSACKx or BERR, the assertion of CBACK is completely ignored. 7.2.9 Synchronous Operation with DSACKx Although cycles terminated with the DSACKx signals are classified as asynchronous and cycles terminated with STERM are classified as synchronous, cycles terminated with DSACKx can also operate synchronously in that signals are interpreted relative to clock edges. The devices that use these cycles must synchronize the responses to the MC68030 clock to be synchronous. Since they terminate bus cycles with the DSACKx signals, the dynamic bus sizing capabilities of the MC68030 are available. In addition, the minimum cycle time for these cycles is also three clocks. To support those systems that use the system clock to generate DSACKx and other asynchronous inputs, the asynchronous input setup time (parameter #47A) and the asynchronous input hold time (parameter #47B) are given. If the setup and hold times are met for the assertion or negation of a signal, such as DSACKx, the processor can be guaranteed to recognize that signal level on that specific falling edge of the system clock. If the assertion of DSACKx is recognized on a particular falling edge of the clock, valid data is latched into the processor (for a read cycle) on the next falling clock edge provided the data meets the data setup time (parameter #27). In this case, parameter #31 for asynchronous operation can be ignored. The timing parameters referred to are described in MC68030EC/ D, MC68030 Electrical Specifications. If a system asserts DSACKx for the required window around the falling edge of S2 and obeys the proper bus protocol by maintaining DSACKx (and/or BERR/HALT) until and throughout the clock edge that negates AS (with the appropriate asynchronous input hold time specified by parameter #47B), no wait states are inserted. The bus cycle runs at its maximum speed (three clocks per cycle) for bus cycles terminated with DSACKx. 7-28 MC68030 USER'S MANUAL MOTOROLA Bus Operation To assure proper operation in a synchronous system when BERR or BERR and HALT is asserted after DSACKx, BERR (and HALT) must meet the appropriate setup time (parameter #27A) prior to the falling clock edge one clock cycle after DSACKx is recognized. This setup time is critical, and the MC68030 may exhibit erratic behavior if it is violated. When operating synchronously, the data-in setup and hold times for synchronous cycles may be used instead of the timing requirements for data relative to the DS signal. The value of CIIN is latched on the rising edge of bus cycle state 4 for all cycles terminated with DSACKx. 7.2.10 Synchronous Operation with STERM The MC68030 supports synchronous bus cycles terminated with STERM. These cycles, for 32-bit ports only, are similar to cycles terminated with DSACKx. The main difference is that STERM can be asserted (and data can be transferred) earlier than for a cycle terminated with DSACKx, causing the processor to perform a minimum access time transfer in two clock periods. However, wait cycles can be inserted by delaying the assertion of STERM appropriately. Using STERM instead of DSACKx in any bus cycle makes the cycle synchronous. Any bus cycle is synchronous if: 1. Neither DSACKx nor AVEC is recognized during the cycle. 2. The port size is 32 bits. 3. Synchronous input setup and hold time requirements (specifications #60 and #61) for STERM are met. Burst mode operation requires the use of STERM to terminate each of its cycles. The first cycle of any burst transfer must be a synchronous cycle as described in the preceding paragraph. The exact timing of this cycle is controlled by the assertion of STERM, and wait cycles can be inserted as necessary. However, the minimum cycle time is two clocks. If a burst operation is initiated and allowed to terminate normally, the second, third, and fourth cycles latch data on successive falling edges of the clock at a minimum. Again, the exact timing for these subsequent cycles is controlled by the timing of STERM for each of these cycles, and wait cycles can be inserted as necessary. MOTOROLA MC68030 USER'S MANUAL 7-29 Bus Operation Although the synchronous input signals (STERM, CIIN, and CBACK) must be stable for the appropriate setup and hold times relative to every rising edge of the clock during which AS is asserted, the assertion or negation of CBACK and CIIN is internally latched on the rising edge of the clock for which STERM is asserted in a synchronous cycle. The STERM signal can be generated from the address bus and function code value and does not need to be qualified with the AS signal. If STERM is asserted and no cycle is in progress (even if the cycle has begun, ECS is asserted and then the cycle is aborted), STERM is ignored by the MC68030. Similarly, CBACK can be asserted independently of the assertion of CBREQ. If a cache burst is not requested, the assertion of CBACK is ignored. The assertion of CIIN is ignored when the appropriate cache is not enabled or when cache inhibit out (CIOUT) is asserted. It is also ignored during write cycles or translation table searches. NOTE STERM and DSACKx should never be asserted during the same bus cycle. 7.3 DATA TRANSFER CYCLES The transfer of data between the processor and other devices involves the following signals: * Address Bus A0-A31 * Data Bus D0-D31 * Control Signals The address and data buses are both parallel nonmultiplexed buses. The bus master moves data on the bus by issuing control signals, and the asynchronous/synchronous bus uses a handshake protocol to insure correct movement of the data. In all bus cycles, the bus master is responsible for de-skewing all signals it issues at both the start and the end of the cycle. In addition, the bus master is responsible for de-skewing the acknowledge and data signals from the slave devices. The following paragraphs define read, write, and read-modify-write cycle operations. An additional paragraph describes burst mode transfers. 7-30 MC68030 USER'S MANUAL MOTOROLA Bus Operation Each of the bus cycles is defined as a succession of states. These states apply to the bus operation and are different from the processor states described in Section 4 Processing States. The clock cycles used in the descriptions and timing diagrams of data transfer cycles are independent of the clock frequency. Bus operations are described in terms of external bus states. 7.3.1 Asynchronous Read Cycle During a read cycle, the processor receives data from a memory, coprocessor, or peripheral device. If the instruction specifies a long-word operation, the MC68030 attempts to read four bytes at once. For a word operation, it attempts to read two bytes at once, and for a byte operation, one byte. For some operations, the processor requests a three-byte transfer. The processor properly positions each byte internally. The section of the data bus from which each byte is read depends on the operand size, address signals (A0-A1), CIIN and CIOUT, whether the internal caches are enabled, and the port size. Refer to 7.2.1 Dynamic Bus Sizing, 7.2.2 Misaligned Operands, and 7.2.6 Cache Filling for more information on dynamic bus sizing, misaligned operands, and cache interactions. Figure 7-19 is a flowchart of an asynchronous long-word read cycle. Figure 7-20 is a flowchart of a byte read cycle. The following figures show functional read cycle timing diagrams specified in terms of clock periods. Figure 7-21 corresponds to byte and word read cycles from a 32-bit port. Figure 7-22 corresponds to a long-word read cycle from an 8-bit port. Figure 7-23 also applies to a long-word read cycle, but from a 16-bit port. State 0 The read cycle starts in state 0 (S0). The processor drives ECS low, indicating the beginning of an external cycle. When the cycle is the first external cycle of a read operand operation, operand cycle start (OCS) is driven low at the same time. During S0, the processor places a valid address on A0-A31 and valid function codes on FC0-FC2. The function codes select the address space for the cycle. The processor drives R/W high for a read cycle and drives DBEN inactive to disable the data buffers. SIZ0-SIZ1 become valid, indicating the number of bytes requested to be transferred. CIOUT also becomes valid, indicating the state of the MMU CI bit in the address translation descriptor or in the appropriate TTx register. MOTOROLA MC68030 USER'S MANUAL 7-31 Bus Operation CONTROLLER EXTERNAL DEVICE ADDRESS DEVICE 1) 2) 3) 4) 5) 6) 7) 8) 9) ASSERT ECS/OCS FOR ONE-HALF CLOCK SET R/W TO READ DRIVE ADDRESS ON A31-A0 DRIVE FUNCTION CODE ON FC2-FC0 DRIVE SIZE (SIZ1-SIZ0) (FOUR BYTES) CACHE INHIBIT OUT (CIOUT) BECOMES VALID ASSERT ADDRESS STROBE (AS) ASSERT DATA STROBE (DS) ASSERT DATA BUFFER ENABLE (DBEN) ACQUIRE DATA 1) 2) 3) 4) PRESENT DATA 1) DECODE ADDRESS 2) PLACE DATA ON D31-D0 3) ASSERT DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACKx) SAMPLE CACHE IN (CIN) LATCH DATA NEGATE AS AND DS NEGATE DBEN TERMINATE CYCLE 1) REMOVE DATA FROM D31-D0 2) NEGATE DSACK START NEXT CYCLE Figure 7-19. Asynchronous Long-Word Read Cycle Flowchart CONTROLLER EXTERNAL DEVICE ADDRESS DEVICE 1) 2) 3) 4) 5) 6) 7) 8) 9) ASSERT ECS/OCS FOR ONE-HALF CLOCK SET R/W TO READ DRIVE ADDRESS ON A31-A0 DRIVE FUNCTION CODE ON FC2-FC0 DRIVE SIZE (SIZ1-SIZ0) (FOUR BYTES) CACHE INHIBIT OUT (CIOUT) BECOMES VALID ASSERT ADDRESS STROBE (AS) ASSERT DATA STROBE (DS) ASSERT DATA BUFFER ENABLE (DBEN) ACQUIRE DATA PRESENT DATA 1) DECODE ADDRESS 2) PLACE DATA ON D31-D324 OR D23-D16 OR D15-D8 OR D7-D0 (BASED ON A1,A0, CACHE AND BUS WIDTH) 3) ASSERT DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACKx) 1)SAMPLE CACHE INHIBIT IN (CIIN) 2) LATCH DATA 3) NEGATE AS AND DS 4) NEGATE DBEN TERMINATE CYCLE 1) REMOVE DATA FROM D31-D0 2) NEGATE DSACK START NEXT CYCLE Figure 7-20. Asynchronous Byte Read Cycle Flowchart 7-32 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 S4 CLK A31-A2 A1 A0 FC2-FC0 SIZ1 WORD BYTE SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 OP2 D23-D16 OP3 OP3 D15-D8 OP3 D7-D0 WORD READ BYTE READ BYTE READ Figure 7-21. Asynchronous Byte and Word Read Cycles -- 32-Bit Port MOTOROLA MC68030 USER'S MANUAL 7-33 Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 CLK A31-A2 A1 A0 FC2-FC0 SIZ1 LONG WORD 3-BYTE WORD BYTE SIZ0 R/W ECS OCS AS DS CIOUT DSACK1 DSACK0 DBEN D31-D24 OP0 OP1 OP2 OP3 D23-D16 D15-D8 D7-D0 BYTE READ BYTE READ BYTE READ BYTE READ LONG WORD OPERAND READ FROM 8-BIT PORT Figure 7-22. Long-Word Read -- 8-Bit Port with CIOUT Asserted MOTOROLA MC68030 USER'S MANUAL 7-35 Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 S4 CLK A31-A2 A1 A0 FC2-FC0 SIZ1 LONG WORD WORD LONG WORD SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 OP0 OP2 OP0 D23-D16 OP1 OP3 OP1 D15-D8 OP2 D7-D0 OP3 WORD READ WORD READ LONG WORD READ FROM 32- BIT PORT LONG WORD OPERAND READ FROM 16-BIT PORT Figure 7-23. Long-Word Read -- 16-Bit and 32-Bit Port 7-36 MC68030 USER'S MANUAL MOTOROLA Bus Operation State 1 One-half clock later in state 1 (S1), the processor asserts AS indicating that the address on the address bus is valid. The processor also asserts DS also during S1. In addition, the ECS (and OCS, if asserted) signal is negated during S1. State 2 During state 2 (S2), the processor asserts DBEN to enable external data buffers. The selected device uses R/W, SIZ0-SIZ1, A0-A1, CIOUT, and DS to place its information on the data bus, and drives CIIN if appropriate. Any or all of the bytes (D24-D31, D16-D23, D8-D15, and D0-D7) are selected by SIZ0-SIZ1 and A0-A1. Concurrently, the selected device asserts DSACKx. State 3 As long as at least one of the DSACKx signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), data is latched on the next falling edge of the clock, and the cycle terminates. If DSACKx is not recognized by the start of state 3 (S3), the processor inserts wait states instead of proceeding to states 4 and 5. To ensure that wait states are inserted, both DSACK0 and DSACK1 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the processor continues to sample the DSACKx signals on the falling edges of the clock until one is recognized. State 4 The processor samples CIIN at the beginning of state 4 (S4). Since CIIN is defined as a synchronous input, whether asserted or negated, it must meet the appropriate synchronous input setup and hold times on every rising edge of the clock while AS is asserted. At the end of S4, the processor latches the incoming data. State 5 The processor negates AS, DS, and DBEN during state 5 (S5). It holds the address valid during S5 to provide address hold time for memory systems. R/W, SIZ0-SIZ1, and FC0- FC2 also remain valid throughout S5. The external device keeps its data and DSACKx signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove its data and negate DSACKx within approximately one clock period after sensing the negation of AS or DS. DSACKx signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. MOTOROLA MC68030 USER'S MANUAL 7-37 Bus Operation 7.3.2 Asynchronous Write Cycle During a write cycle, the processor transfers data to memory or a peripheral device. Figure 7-24 is a flowchart of a write cycle operation for a long-word transfer. The following figures show the functional write cycle timing diagrams specified in terms of clock periods. Figure 7-25 shows two write cycles (between two read cycles with no idle time) for a 32-bit port. Figure 7-26 shows byte and word write cycles to a 32-bit port. Figure 7-27 shows a long-word write cycle to an 8-bit port. Figure 7-28 shows a long-word write cycle to a 16-bit port. CONTROLLER EXTERNAL DEVICE ADDRESS DEVICE 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) ASSERT ECS/OCS FOR ONE-HALF CLOCK DRIVE ADDRESS ON A31-A0 DRIVE FUNCTION CODE ON FC2-FC0 DRIVE SIZE (SIZ1-SIZ0) (FOUR BYTES) SET R/W TO WRITE CACHE INHIBIT OUT (CIOUT) BECOMES VALID ASSERT ADDRESS STROBE (AS) ASSERT DATA BUFFER ENABLE (DBEN) DRIVE DATA LINES D31-D0 ASSERT DATA STROBE (DS) TERMINATE OUTPUT TRANSFER ACCEPT DATA 1) DECODE ADDRSS 2) STORE DATA FROM D31-D0 3) ASSERT DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACKx) 1) NEGATE AS AND DS 2) REMOVE DATA FROM D31-D0 3) NEGATE DBEN TERMINATE CYCLE 1) NEGATE DSACKx START NEXT CYCLE Figure 7-24. Asynchronous Write Cycle Flowchart 7-38 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 Sw Sw S4 CLK A31-A2 A1 A0 FC2-FC0 SIZ1 LONG WORD SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D0 READ WRITE WRITE READ WITH WAIT STATES Figure 7-25. Asynchronous Read-Write-Read Cycles -- 32-Bit Port State 0 The write cycle starts in S0. The processor drives ECS low, indicating the beginning of an external cycle. When the cycle is the first external cycle of a write operation, OCS is driven low at the same time. During S0, the processor places a valid address on A0-A31 and valid function codes on FC0-FC2. The function codes select the address space for the cycle. The processor drives R/W low for a write cycle. SIZ0-SIZ1 become valid, indicating the number of bytes to be transferred. CIOUT also becomes valid, indicating MOTOROLA MC68030 USER'S MANUAL 7-39 Bus Operation the state of the MMU CI bit in the address translation descriptor or in the appropriate TTx register. 7-40 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 S4 CLK A31-A2 A1 A0 FC2-FC0 SIZ1 BYTE WORD SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 OP2 OP3 OP3 D23-D16 OP3 OP3 OP3 D15-D8 OP2 OP3 OP3 D7-D0 OP3 OP3 OP3 WORD WRITE BYTE WRITE BYTE WRITE Figure 7-26. Asynchronous Byte and Word Write Cycles -- 32-Bit Port MOTOROLA MC68030 USER'S MANUAL 7-41 Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 CLK A31-A2 A1 A0 FC2-FC0 SIZ1 LONG WORD 3-BYTE WORD BYTE SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 OP0 OP1 OP2 OP3 D23-D16 OP1 OP1 OP3 OP3 D15-D8 OP2 OP2 OP2 OP3 D7-D0 OP3 OP3 OP3 OP3 BYTE WRITE BYTE WRITE BYTE WRITE BYTE WRITE LONG WORD OPERAND READ TO 8-BIT PORT Figure 7-27. Long-Word Operand Write -- 8-Bit Port 7-42 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 S4 CLK A31-A2 A1 A0 FC2-FC0 SIZ1 LONG WORD LONG WORD WORD SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 OP0 OP2 OP0 D23-D16 OP1 OP3 OP1 D15-D8 OP2 OP2 OP2 D7-D0 OP3 OP3 OP3 WORD WRITE WORD WRITE LONG WORD WRITE TO 32-BIT PORT LONG WORD OPERAND WRITE TO 16-BIT PORT Figure 7-28. Long-Word Operand Write -- 16-Bit Port MOTOROLA MC68030 USER'S MANUAL 7-43 Bus Operation State 1 One-half clock later in S1, the processor asserts AS, indicating that the address on the address bus is valid. The processor also asserts DBEN during S1, which can enable external data buffers. In addition, the ECS (and OCS, if asserted) signal is negated during S1. State 2 During S2, the processor places the data to be written onto the D0-D31, and samples DSACKx at the end of S2. State 3 The processor asserts DS during S3, indicating that the data is stable on the data bus. As long as at least one of the DSACKx signals is recognized by the end of S2 meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACKx is not recognized by the start of S3, the processor inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK0 and DSACK1 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the processor continues to sample the DSACKx signals on the falling edges of the clock until one is recognized. The selected device uses R/W, DS, SIZ0-SIZ1, and A0-A1 to latch data from the appropriate byte(s) of the data bus (D24-D31, D16-D23, D8-D15, and D0-D7). SIZ0-SIZ1 and A0-A1 select the bytes of the data bus. If it has not already done so, the device asserts DSACKx to signal that it has successfully stored the data. State 4 The processor issues no new control signals during S4. State 5 The processor negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems. R/W, SIZ0-SIZ1, FC0-FC2, and DBEN also remain valid throughout S5. The external device must keep DSACKx asserted until it detects the negation of AS or DS (whichever it detects first). The device must negate DSACKx within approximately one clock period after sensing the negation of AS or DS. DSACKx signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. 7-44 MC68030 USER'S MANUAL MOTOROLA Bus Operation 7.3.3 Asynchronous Read-Modify-Write Cycle The read-modify-write cycle performs a read, conditionally modifies the data in the arithmetic logic unit, and may write the data out to memory. In the MC68030 processor, this operation is indivisible, providing semaphore capabilities for multiprocessor systems. During the entire read-modify-write sequence, the MC68030 asserts the RMC signal to indicate that an indivisible operation is occurring. The MC68030 does not issue a bus grant (BG) signal in response to a bus request (BR) signal during this operation. The read portion of a readmodify-write operation is forced to miss in the data cache because the data in the cache would not be valid if another processor had altered the value being read. However, readmodify-write cycles may alter the contents of the data cache as described in 6.1.2 Data Cache. No burst filling of the data cache occurs during a read-modify-write operation. The test and set (TAS) and compare and swap (CAS and CAS2) instructions are the only MC68030 instructions that utilize read-modify-write operations. Depending on the compare results of the CAS and CAS2 instructions, the write cycle(s) may not occur. Table search accesses required for the MMU are always read-modify-write cycles to the supervisor data space. During these cycles, a write does not occur unless a descriptor is updated. No data is internally cached for table search accesses since the MMU uses physical addresses to access the tables. Refer to Section 9 Memory Management Unit for information about the MMU. Figure 7-29 is a flowchart of the asynchronous read-modify-write cycle operation. Figure 730 is an example of a functional timing diagram of a TAS instruction specified in terms of clock periods. State 0 The processor asserts ECS and OCS in S0 to indicate the beginning of an external operand cycle. The processor also asserts RMC in S0 to identify a read-modify-write cycle. The processor places a valid address on A0-A31 and valid function codes on FC0- FC2. The function codes select the address space for the operation. SIZ0-SIZ1 become valid in S0 to indicate the operand size. The processor drives R/W high for the read cycle and sets 4 according to the value of the MMU CI bit in the address translation descriptor or in the appropriate TTx register. State 1 One-half clock later in S1, the processor asserts AS, indicating that the address on the address bus is valid. The processor asserts DS during S1. In addition, the ECS (and OCS, if asserted) signal is negated during S1. MOTOROLA MC68030 USER'S MANUAL 7-45 Bus Operation CONTROLLER EXTERNAL DRIVE LOCK BUS 1) ASSERT READ-MODIFY-WRITE CYCLE (RMC) ADDRESS DEVICE 1) 2) 3) 4) 5) 6) 7) 8) 9) ASSERT ECS/OCS FOR ONE-HALF CLOCK SET R/W TO READ DRIVE ADDRESS ON A31-A0 DRIVE FUNCTION CODE ON FC2- FC0 DRIVE SIZE (SIZ1-SIZ0) CACHE INHIBIT OUT (CIOUT) BECOMES VALID ASSERT ADDRESS STROBE (AS) ASSERT DATA STROBE (DS) ASSERT DATA BUFFER ENABLE (DBEN) ACQUIRE DATA 1) 2) 3) 4) 5) SAMPLE CACHE INHIBIT IN LATCH DATA NEGATE AS AND DS NEGATE DBEN START DATA MODIFICATION PRESENT DATA 1) DECODE ADDRESS 2) PLACE DATA ON D31-D0 3) ASSERT DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACKx) TERMINATE CYCLE 1) REMOVE DATA FROM D31-D0 2) NEGATE DSACKx START OUTPUT TRANSFER 1) 2) 3) 4) 5) 6) 7) 8) ASSERT ECS/OCS FOR ONE-HALF CLOCK DRIVE ADDRESS ON A31-A0 (IF DIFFERENT) DRIVE SIZE (SIZ1-SIZ0) SET R/W TO WRITE ASSERT AS ASSERT DBEN PLACE DATA ON D31-D0 ASSERT DS TERMINATE OUTPUT TRANSFER 1) NEGATE AS AND DS 2) REMOVE DATA FROM D31-D0 3) NEGATE DBEN A IF CAS2 INSTRUCTION AND ONLY ONE OPERAND READ, THEN GO TO A ; IF OPERANDS DO NOT MATCH, THEN GO TO C ; ELSE GO TO C B B ACCEPT DATA 1) DECODE ADDRESS 2) STORE DATA FROM D31-D0 3) ASSERT DSACKx TERMINATE CYCLE 1) NEGATE DSACKx D IF CAS2 INSTRUCTION AND ONLY ONE OPERAND WRITTEN, THEN GO TO D ; ELSE GO TO E E UNLOCK BUS 1) NEGATE RMC START NEXT CYCLE Figure 7-29. Asynchronous Read-Modify-Write Cycle Flowchart 7-46 MC68030 USER'S MANUAL MOTOROLA Bus Operation State 2 During state 2 (S2), the processor drives DBEN active to enable external data buffers. The selected device uses R/W, SIZ0-SIZ1, A0-A1, and DS to place information on the data bus. Any or all of the bytes (D24-D31, D16-D23, D8-D15, and D0-D7) are selected by SIZ0-SIZ1 and A0-A1. Concurrently, the selected device may assert the DSACKx signals. State 3 As long as at least one of the DSACKx signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), data is latched on the next falling edge of the clock, and the cycle terminates. If DSACKx is not recognized by the start of S3, the processor inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK0 and DSACK1 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the processor continues to sample the DSACKx signals on the falling edges of the clock until one is recognized. State 4 The processor samples the level of CIIN at the beginning of S4. At the end of S4, the processor latches the incoming data. State 5 The processor negates AS, DS, and DBEN during S5. If more than one read cycle is required to read in the operand(s), S0-S5 are repeated for each read cycle. When finished reading, the processor holds the address, R/W, and FC0-FC2 valid in preparation for the write portion of the cycle. The external device keeps its data and DSACKx signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove the data and negate DSACKx within approximately one clock period after sensing the negation of AS or DS. DSACKx signals that remain asserted beyond this limit may be prematurely detected for the next portion of the operation. Idle States The processor does not assert any new control signals during the idle states, but it may internally begin the modify portion of the cycle at this time. S6-S11 are omitted if no write cycle is required. If a write cycle is required, the R/W signal remains in the read mode until S6 to prevent bus conflicts with the preceding read portion of the cycle; the data bus is not driven until S8. MOTOROLA MC68030 USER'S MANUAL 7-47 Bus Operation S0 S2 S4 Si Si S6 S8 S10 S0 CLK A31-A2 A1 A0 FC2-FC0 SIZ1 SIZ0 R/W RMC ECS AS DS CIIN CIOUT DSACK1 DSACK0 DBEN D31-D24 OP3 D23-D16 OP3 D15-D8 OP3 OP3 D7-D0 OP3 BERR HALT BG INDIVISIBLE CYCLE NEXT CYCLE Figure 7-30. Asynchronous Byte Read-Modify-Write Cycle -- 32-Bit Port (TAS Instruction with CIOUT or CIIN Asserted) 7-48 MC68030 USER'S MANUAL MOTOROLA Bus Operation State 6 The processor asserts ECS and OCS in S6 to indicate that another external cycle is beginning. The processor drives R/W low for a write cycle. CIOUT also becomes valid, indicating the state of the MMU CI bit in the address translation descriptor or in a relevant TTx register. Depending on the write operation to be performed, the address lines may change during S6. State 7 In S7, the processor asserts AS, indicating that the address on the address bus is valid. The processor also asserts DBEN, which can be used to enable data buffers during S7. In addition, the ECS (and OCS, if asserted) signal is negated during S7. State 8 During S8, the processor places the data to be written onto D0-D31. State 9 The processor asserts DS during S9 indicating that the data is stable on the data bus. As long as at least one of the DSACKx signals is recognized by the end of S8 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACKx is not recognized by the start of S9, the processor inserts wait states instead of proceeding to S10 and S11. To ensure that wait states are inserted, both DSACK0 and DSACK1 must remain negated throughout the asynchronous input setup and hold times around the end of S8. If wait states are added, the processor continues to sample DSACKx signals on the falling edges of the clock until one is recognized. The selected device uses R/W, DS, SIZ0-SIZ1, and A0-A1 to latch data from the appropriate section(s) of the data bus (D24-D31, D16-D23, D8-D15, and D0-D7). SIZ0-SIZ1 and A0-A1 select the data bus sections. If it has not already done so, the device asserts DSACKx when it has successfully stored the data. State 10 The processor issues no new control signals during S10. MOTOROLA MC68030 USER'S MANUAL 7-49 Bus Operation State 11 The processor negates AS and DS during S11. It holds the address and data valid during S11 to provide address hold time for memory systems. R/W and FC0-FC2 also remain valid throughout S11. If more than one write cycle is required, S6-S11 are repeated for each write cycle. The external device keeps DSACKx asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove its data and negate DSACKx within approximately one clock period after sensing the negation of AS or DS. 7.3.4 Synchronous Read Cycle A synchronous read cycle is terminated differently from an asynchronous read cycle; otherwise, the cycles assert and respond to the same signals, in the same sequence. STERM rather than DSACKx is asserted by the addressed external device to terminate a synchronous read cycle. Since STERM must meet the synchronous setup and hold times with respect to all rising edges of the clock while AS is asserted, it does not need to be synchronized by the processor. Only devices with 32-bit ports may assert STERM. STERM is also used with the CBREQ and CBACK signals during burst mode operation. It provides a two-clock (minimum) bus cycle for 32-bit ports and single-clock (minimum) burst accesses, although wait states can be inserted for these cycles as well. Therefore, a synchronous cycle terminated with STERM with one wait cycle is a three-clock bus cycle. However, note that STERM is asserted one-half clock later than DSACKx would be for a similar asynchronous cycle with zero wait cycles (also three clocks). Thus, if dynamic bus sizing is not needed, STERM can be used to provide more decision time in an external cache design than is available with DSACKx for three-clock accesses. Figure 7-31 is a flowchart of a synchronous long-word read cycle. Byte and word operations are similar. Figure 7-32 is a functional timing diagram of a synchronous long-word read cycle. 7-50 MC68030 USER'S MANUAL MOTOROLA Bus Operation CONTROLLER EXTERNAL DEVICE ADDRESS DEVICE 1) 2) 3) 4) 5) 6) 7) 8) ASSERT ECS/OCS FOR ONE-HALF CLOCK DRIVE R/W TO READ DRIVE ADDRESS ON A31-A0 DRIVE FUNCTION ON FC2-FC0 DRIVE SIZE (SIZ1-SIZ0) (FOUR BYTES) CACHE INHIBIT OUT (CIOUT) BECOMES VALID ASSERT ADDRESS STROBE (AS) ASSERT CACHE BURST REQUEST (CBREQ) (IF BURST POSSSIBLE) 9) ASSERT DATA STROBE (DS) 10) ASSERT DATA BUFFER ENABLE (DBEN) PRESENT DATA 1) 2) 3) 4) ACQUIRE DATA DECODE ADDRESS PLACE DATA ON D31-D0 ASSERT SYNCHRONOUS TERMINATION (STERM) ASSERT CACHE BURST ACKNOWLEDGE (CBACK) 1) SAMPLE CACHE INHIBIT IN (CIIN) AND CACHE BURST ACKNOWLEDGE (CBACK) 2) LATCH DATA 3) NEGATE AS AND DS 4) NEGATE DBEN TERMINATE CYCLE 1) REMOVE DATA FROM D31-D0 2) NEGATE STERM START NEXT CYCLE Figure 7-31. Synchronous Long-Word Read Cycle Flowchart -- No Burst Allowed State 0 The read cycle starts with S0. The processor drives ECS low, indicating the beginning of an external cycle. When the cycle is the first cycle of a read operand operation, OCS is driven low at the same time. During S0, the processor places a valid address on A0-A31 and valid function codes on FC0-FC2. The function codes select the address space for the cycle. The processor drives R/W high for a read cycle and drives DBEN inactive to disable the data buffers. SIZ1-SIZ0 become valid, indicating the number of bytes to be transferred. CIOUT also becomes valid, indicating the state of the MMU CI bit in the address translation descriptor or in the appropriate TTx register. State 1 One-half clock later in S1, the processor asserts AS, indicating that the address on the address bus is valid. The processor also asserts DS during S1. If the burst mode is enabled for the appropriate on-chip cache and all four long words of the cache entry are invalid, (i.e., four long words can be read in), CBREQ is asserted. In addition, the ECS (and OCS, if asserted) signal is negated during S1. MOTOROLA MC68030 USER'S MANUAL 7-51 Bus Operation S0 S2 CLK A31-A0 FC2-FC0 SIZ1 SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 STERM CIIN CIOUT CBREQ CBACK D31-D0 DBEN Figure 7-32. Synchronous Read with CIIN Asserted and CBACK Negated State 2 The selected device uses R/W, SIZ0-SIZ1, A0-A1, and CIOUT to place its information on the data bus. Any or all of the byte sections of the data bus (D24-D31, D16-D23, D8- D15, and D0-D7) are selected by SIZ0-SIZ1 and A0-A1. During S2, the processor drives DBEN active to enable external data buffers. In systems that use two-clock synchronous bus cycles, the timing of DBEN may prevent its use. At the beginning of S2, the processor samples the level of STERM. If STERM is recognized, the processor latches the incoming data at the end of S2. If the selected data is not to be cached for the 7-52 MC68030 USER'S MANUAL MOTOROLA Bus Operation current cycle or if the device cannot supply 32 bits, CIIN must be asserted at the same time as STERM. In addition, the state of CBACK is latched when STERM is recognized. Since CIIN, CBACK, and STERM are synchronous signals, they must meet the synchronous input setup and hold times for all rising edges of the clock while AS is asserted. If STERM is negated at the beginning of S2, wait states are inserted after S2, and STERM is sampled on every rising edge thereafter until it is recognized. Once STERM is recognized, data is latched on the next falling edge of the clock (corresponding to the beginning of S3). State 3 The processor negates AS, DS, and DBEN during S3. It holds the address valid during S3 to simplify memory interfaces. R/W, SIZ0-SIZ1, and FC0-FC2 also remain valid throughout S3. The external device must keep its data asserted throughout the synchronous hold time for data from the beginning of S3. The device must remove its data within one clock after asserting STERM and negate STERM within two clocks after asserting STERM; otherwise, the processor may inadvertently use STERM for the next bus cycle. 7.3.5 Synchronous Write Cycle A synchronous write cycle is terminated differently from an asynchronous write cycle and the data strobe may not be useful. Otherwise, the cycles assert and respond to the same signal, in the same sequence. STERM is asserted by the external device to terminate a synchronous write cycle. The discussion of STERM in the preceding section applies to write cycles as well as to read cycles. DS is not asserted for two-clock synchronous write cycles; therefore, the clock (CLK) may be used as the timing signal for latching the data. In addition, there is no time from the latest assertion of AS and the required assertion of STERM for any two-clock synchronous bus cycle. The system must qualify a memory write with the assertion of AS to ensure that the write is not aborted by internal conditions within the MC68030. MOTOROLA MC68030 USER'S MANUAL 7-53 Bus Operation Figure 7-33 is a flowchart of a synchronous write cycle. Figure 7-34 is a functional timing diagram of this operation with wait states. CONTROLLER EXTERNAL DEVICE ADDRESS DEVICE 1) 2) 3) 4) 5) 6) 7) 8) ASSERT ECS/OCS FOR ONE-HALF CLOCK DRIVE ADDRESS ON A31-A0 DRIVE FUNCTION ON FC2-FC0 DRIVE SIZE (SIZ1-SIZ0) (FOUR BYTES) SET R/W TO WRITE CACHE INHIBIT OUT (CIOUT) BECOMES VALID ASSERT ADDRESS STROBE (AS) ASSERT DATA BUFFER ENABLE (DBEN) ASSERT DATA BUFFER ENABLE (DBEN) 9) DRIVE DATA LINES D31-D0 10) ASSERT DATA STROBE (DS) IF WAIT STATES) TERMINATE OUTPUT TRANSFER ACCEPT DATA 1) DECODE ADDRESS 2) STORE DATA ON D31-D0 3) ASSERT SYNCHRONOUS TERMINATION (STERM) 1) NEGATE AS AND DS 2) REMOVE DATA FROM D31-0 3) NEGATE DBEN TERMINATE CYCLE 1) NEGATE STERM START NEXT CYCLE Figure 7-33. Synchronous Write Cycle Flowchart State 0 The write cycle starts with S0. The processor drives ECS low, indicating the beginning of an external cycle. When the cycle is the first cycle of a write operation, OCS is driven low at the same time. During S0, the processor places a valid address on A0-A31 and valid function codes on FC0-FC2. The function codes select the address space for the cycle. The processor drives R/W low for a write cycle. SIZ0-SIZ1 become valid, indicating the number of bytes to be transferred. CIOUT also becomes valid, indicating the state of the MMU CI bit in the address translation descriptor or in the appropriate TTx register. State 1 One-half clock later in S1, the processor asserts AS, indicating that the address on the address bus is valid. The processor also asserts DBEN during S1, which may be used to enable the external data buffers. In addition, the ECS (and OCS, if asserted) signal is negated during S1. 7-54 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S1 S2 Sw Sw S3 CLK A31-A0 FC2-FC0 SIZ1 SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 STERM CIIN CIOUT CBREQ CBACK D31-D0 DBEN Figure 7-34. Synchronous Write Cycle with Wait States -- CIOUT Asserted State 2 During S2, the processor places the data to be written onto D0-D31. The selected device uses R/W, CLK, SIZ0-SIZ1, and A0-A1 to latch data from the appropriate section(s) of the data bus (D24-D31, D16-D23, D8-D15, and D0-D7). SIZ0-SIZ1 and A0-A1 select the data bus sections. The device asserts STERM when it has successfully stored the data. If the device does not assert STERM by the rising edge of S2, the processor inserts wait states until it is recognized. The processor asserts DS at the end of S2 if wait states are inserted. For zero-wait-state synchronous write cycles, DS is not asserted. MOTOROLA MC68030 USER'S MANUAL 7-55 Bus Operation State 3 The processor negates AS (and DS, if necessary) during S3. It holds the address and data valid during S3 to simplify memory interfaces. R/W, SIZ0-SIZ1, FC0-FC2, and DBEN also remain valid throughout S3. The addressed device must negate STERM within two clock periods after asserting it, or the processor may use STERM for the next bus cycle. 7.3.6 Synchronous Read-Modify-Write Cycle A synchronous read-modify-write operation differs from an asynchronous read-modify-write operation only in the terminating signal of the read and write cycles and in the use of CLK instead of DS latching data in the write cycle. Like the asynchronous operation, the synchronous read-modify-write operation is indivisible. Although the operation is synchronous, the burst mode is never used during read-modify-write cycles. Figure 7-35 is a flowchart of the synchronous read-modify-write operation. Timing for the cycle is shown in Figure 7-36. 7-56 MC68030 USER'S MANUAL MOTOROLA Bus Operation CONTROLLER EXTERNAL DEVICE LOCK BUS 1) ASSERT READ-MODIFY-WRITE CYCLE (RMC) START INPUT TRANSFER 1) 2) 3) 4) 5) 6) ASSERT ECS/OCS FOR ONE-HALF CLOCK DRIVE R/W TO READ DRIVE FUNCTION CODE ON FC2-FC0 DRIVE ADDRESS ON A31-A0 DRIVE SIZE (SIZ1-SIZ0) CACHE INHIBIT OUT (CIOUT) BECOMES VALID 7) ASSERT ADDRESS STROBE (AS) 8) ASSERT DATA STROBE (DS) 9) ASSERT DATA BUFFER ENABLE (DBEN) TERMINATE INPUT TRANSFER 1) 2) 3) 4) 5) SAMPLE CACHE INHIBIT IN (CIIN) LATCH DATA NEGATE AS AND DS NEGATE DBEN START DATA MODICIATION PRESENT DATA 1) DECODE ADDRESS 2) PLACE DATA ON D31-D0 3) ASSERT SYNCHRONOUS TERMINATION (STERM) A TERMINATE CYCLE 1) REMOVE DATA FROM D31-D0 2) NEGATE STERM IF CAS2 INSTRUCTION AND ONLY ONE OPERAND READ, THEN GO TO A : IF OPERANDS DO NOT MATCH, THEN GO TO C : ELSE GO TO B B START OUTPUT TRANSFER 1) 2) 3) 4) 5) 6) 7) 8) 9) ASSERT ECS/OCS FOR ONE-HALF CLOCK SET R/W TO WRITE DRIVE ADDRESS ON A31-A0 (IF DIFFERENT) DRIVE SIZE (SIZ1-SIZ0) CIOUT BECOMES VALID ASSERT AS ASSERT DBEN PLACE DATA ON D31-D0 ASSERT DS (IF WAIT STATES) TERMINATE OUTPUT TRANSFER 1) NEGATE AS (AND DS) 2) REMOVE DATA FROM D31-D0 3) NEGATE DBEN C ACCEPT DATA 1) DECODE ADDRESS 2) STORE DATA FROM D31-D0 3) ASSERT STERM TERMINATE CYCLE D IF CAS2 INSTRUCTION AND ONLY ONE OPERAND WRITTEN, THEN GO TO D : ELSE GO TO E 1) NEGATE STERM E UNLOCK BUS 1) NEGATE RMC START NEXT CYCLE Figure 7-35. Synchronous Read-Modify-Write Cycle Flowchart MOTOROLA MC68030 USER'S MANUAL 7-57 Bus Operation S0 S1 S2 S3 Si Si S4 S5 S6 S7 CLK A31-A0 FC2-FC0 SIZ1 SIZ0 R/W RMC ECS OCS AS DS DSACK1 DSACK0 STERM CIIN CIOUT CBREQ CBACK D31-D0 DBEN Figure 7-36. Synchronous Read-Modify-Write Cycle Timing -- CIIN Asserted State 0 The processor asserts ECS and OCS in S0 to indicate the beginning of an external operand cycle. The processor also asserts RMC in S0 to identify a read-modify-write cycle. The processor places a valid address on A0-A31 and valid function codes on FC0- FC2. The function codes select the address space for the operation. SIZ0-SIZ1 become valid in S0 to indicate the operand size. The processor drives R/W high for a read cycle 7-58 MC68030 USER'S MANUAL MOTOROLA Bus Operation and sets CIOUT to the value of the MMU CI bit in the address translation descriptor or in the appropriate TTx register. The processor drives DBEN inactive to disable the data buffers. State 1 One-half clock later in S1, the processor asserts AS, indicating that the address on the address bus is valid. The processor also asserts DS during S1. In addition, the ECS (and OCS, if asserted) signal is negated during S1. State 2 The selected device uses R/W, SIZ0-SIZ1, A0-A1, and CIOUT to place its information on the data bus. Any or all of the byte sections (D24-D31, D16-D23, D8-D15, and D0-D7) are selected by SIZ0-SIZ1 and A0-A1. During S2, the processor drives DBEN active to enable external data buffers. In systems that use two-clock synchronous bus cycles, the timing of DBEN may prevent its use. At the beginning of S2, the processor samples the level of STERM. If STERM is recognized, the processor latches the incoming data. If the selected data is not to be cached for the current cycle or if the device cannot supply 32 bits, CIIN must be asserted at the same time as STERM. Since CIIN and STERM are synchronous signals, they must meet the synchronous nput setup and hold times for all rising edges of the clock while AS is asserted. If STERM is negated at the beginning of S2, wait states are inserted after S2, and STERM is sampled on every rising edge thereafter until it is recognized. Once STERM is recognized, data is latched on the next falling edge of the clock (corresponding to the beginning of S3). MOTOROLA MC68030 USER'S MANUAL 7-59 Bus Operation State 3 The processor negates AS, DS, and DBEN during S3. If more than one read cycle is required to read in the operand(s), S0-S3 are repeated accordingly. When finished with the read cycle, the processor holds the address, R/W, and FC0-FC2 valid in preparation for the write portion of the cycle. The external device must keep its data asserted throughout the synchronous hold time for data from the beginning of S3. The device must remove the data within one-clock cycle after asserting STERM to avoid bus contention. It must also negate STERM within two clocks after asserting STERM; otherwise, the processor may inadvertently use STERM for the next bus cycle. Idle States The processor does not assert any new control signals during the idle states, but it may begin the modify portion of the cycle at this time. The R/W signal remains in the read mode until S4 to prevent bus conflicts with the preceding read portion of the cycle; the data bus is not driven until S6. State 4 The processor asserts ECS and OCS in S4 to indicate that an external cycle is beginning. The processor drives R/W low for a write cycle. CIOUT also becomes valid, indicating the state of the MMU CI bit in the address translation descriptor or in the appropriate TTx register. Depending on the write operation to be performed, the address lines may change during S4. State 5 In state 5 (S5), the processor asserts AS to indicate that the address on the address bus is valid. The processor also asserts DBEN during S5, which can be used to enable external data buffers. State 6 During S6, the processor places the data to be written onto the D0-D31. The selected device uses R/W, CLK, SIZ0-SIZ1, and A0-A1 to latch data from the appropriate byte(s) of the data bus (D24-D31, D16-D23, D8-D15, and D0-D7). SIZ0- SIZ1 and A0-A1 select the data bus sections. The device asserts STERM when it has successfully stored the data. If the device does not assert STERM by the rising edge of S6, the processor inserts wait states until it is recognized. The processor asserts DS at the end of S6 if wait states are inserted. Note that for zero-wait-state synchronous write cycles, DS is not asserted. 7-60 MC68030 USER'S MANUAL MOTOROLA Bus Operation State 7 The processor negates AS (and DS, if necessary) during S7. It holds the address and data valid during S7 to simplify memory interfaces. R/W and FC0-FC2 also remain valid throughout S7. If more than one write cycle is required, S8-S11 are repeated for each write cycle. The external device must negate STERM within two clock periods after asserting it, or the processor may inadvertently use STERM for the next bus cycle. 7.3.7 Burst Operation Cycles The MC68030 supports a burst mode for filling the on-chip instruction and data caches. The MC68030 provides a set of handshake control signals for the burst mode. When a miss occurs in one of the caches, the MC68030 initiates a bus cycle to obtain the required data or instruction stream fetch. If the data or instruction can be cached, the MC68030 attempts to fill a cache entry. Depending on the alignment for a data access, the MC68030 may attempt to fill two cache entries. The processor may also assert CBREQ to request a burst fill operation. That is, the processor can fill additional entries in the line. The MC68030 allows a burst of as many as four long words. The mechanism that asserts the CBREQ signal for burstable cache entries is enabled by the data burst enable (DBE) and instruction burst enable (IBE) bits of the cache control register (CACR) for the data and instruction caches, respectively. Either of the following conditions cause the MC68030 to initiate a cache burst request (and assert CBREQ) for a cachable read cycle: * The logical address and function code signals of the current instruction or data fetch do not match the indexed tag field in the respective instruction or data cache. * All four long words corresponding to the indexed tag in the appropriate cache are marked invalid. However, the MC68030 does not assert CBREQ during the first portion of a misaligned access if the remainder of the access does not correspond to the same cache line. Refer to 6.1.3.1 Single Entry Mode for details. MOTOROLA MC68030 USER'S MANUAL 7-61 Bus Operation If the appropriate cache is not enabled or if the cache freeze bit for the cache is set, the processor does not assert CBREQ. CBREQ is not asserted during the read or write cycles of any read-modify-write operation. The MC68030 allows burst filling only from 32-bit ports that terminate bus cycles with STERM and respond to CBREQ by asserting CBACK. When the MC68030 recognizes STERM and CBACK and it has asserted CBREQ, it maintains AS, DS, R/W, A0-A31, FC0- FC2, SIZ0-SIZ1 in their current state throughout the burst operation. The processor continues to accept data on every clock during which STERM is asserted until the burst is complete or an abnormal termination occurs. CBACK indicates that the addressed device can respond to a cache burst request by supplying one more long word of data in the burst mode. It can be asserted independently of the CBREQ signal, and burst mode is only initiated if both of these signals are asserted for a synchronous cycle. If the MC68030 executes a full burst operation and fetches four long words, CBREQ is negated after STERM is asserted for the third cycle, indicating that the MC68030 only requests one more long word (the fourth cycle). CBACK can then be negated, and the MC68030 latches the data for the fourth cycle and completes the cache line fill. The following conditions can abort a burst fill: * CIIN asserted, * BERR asserted, or * CBACK negated prematurely. The processing of a bus error during a burst fill operation is described in 7.5.1 Bus Errors. For the purposes of halting the processor or arbitrating the bus away from the processor with BR, a burst operation is a single cycle since AS remains asserted during the entire operation. If the HALT signal is asserted during a burst operation, the processor halts at the end of the operation. Refer to 7.5.3 Halt Operation for more information about the halt operation. An alternate bus master requesting the bus with BR may become bus master at the end of the operation provided BR is asserted early enough to be internally synchronized before another processor cycle begins. Refer to 7.7 Bus Arbitration for more information about bus arbitration. 7-62 MC68030 USER'S MANUAL MOTOROLA Bus Operation The simultaneous assertion of BERR and HALT during a bus cycle normally indicates that the cycle should be retried. However, during the second, third, or fourth cycle of a burst operation, this signal combination indicates a bus error condition, which aborts the burst operation. In addition, the processor remains in the halted state until HALT is negated. For information about bus error processing, refer to 7.5.1 Bus Errors. Figure 7-37 is a flowchart of the burst operation. The following timing diagrams show various burst operations. Figure 7-38 shows burst operations for long-word requests with two wait states inserted in the first access and one wait cycle inserted in the subsequent accesses. Figure 7-39 shows a burst operation that fails to complete normally due to CBACK negating prematurely. Figure 7-40 shows a burst operation that is deferred because the entire operand does not correspond to the same cache line. Figure 7-41 shows a burst operation aborted by CIIN. Because CBACK corresponds to the next cycle, three long words are transferred even though CBACK is only asserted for two clock periods. The burst operation sequence begins with states S0-S3, which are very similar to those states for a synchronous read cycle except that CBREQ is asserted. S4-S9 perform the final three reads for a complete burst operation. State 0 The burst operation starts with S0. The processor drives ECS low, indicating the beginning of an external cycle. When the cycle is the first cycle of a read operation, OCS is driven low at the same time. During S0, the processor places a valid address on A0- A31 and valid function codes on FC0-FC2. The function codes select the address space for the cycle. The processor drives R/W high, indicating a read cycle, and drives DBEN inactive to disable the data buffers. SIZ0-SIZ1 become valid, indicating the number of operand bytes to be transferred. CIOUT also becomes valid, indicating the state of the MMU CI bit in the address translation descriptor or in the appropriate TTx register. State 1 One-half clock later in S1, the processor asserts AS to indicate that the address on the address bus is valid. The processor also asserts DS during S1. CBREQ is also asserted, indicating that the MC68030 can perform a burst operation into one of its caches and can read in four long words. In addition, ECS (and OCS, if asserted) is negated during S1. State 2 The selected device uses R/W, SIZ0-SIZ1, A0-A1, and CIOUT to place the data on the data bus. (The first cycle must supply the long word at the corresponding long-word boundary.) All of the byte sections (D24-D31, D16-D23, D8-D15, and D0-D7) of the data bus must be driven since the burst operation latches 32 bits on every cycle. During S2, the processor drives DBEN active to enable external data buffers. In systems that use two-clock synchronous bus cycles, the timing of DBEN may prevent its use. At the beginning of S2, the processor tests the level of STERM. If STERM is recognized, the processor latches the incoming data at the end of S2. For the burst operation to proceed, CBACK must be asserted when STERM is recognized. If the data for the current cycle is MOTOROLA MC68030 USER'S MANUAL 7-63 Bus Operation CONTROLLER EXTERNAL DEVICE ADDRESS DEVICE 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) ASSERT ECS/OCS FOR ONE-HALF CLOCK DRIVE R/W TO READ DRIVE ADDRESS ON A31-A0 DRIVE FUNCTION ON FC2-FC0 DRIVE SIZE (SIZ1-SIZ0) (FOUR BYTES) CACHE INHIBIT OUT (CIOUT) BECOMES VALID ASSERT ADDRESS STROBE (AS) ASSERT CACHE BURST REQUEST (CBREQ) ASSERT DATA STROBE (DS) ASSERT DATA BUFFER ENABLE (DBEN) ACQUIRE DATA PRESENT DATA 1) 2) 3) 4) DECODE ADDRESS PLACE DATA ON D31-D0 ASSERT SYNCHRONOUS TERMINATION (STERM) ASSERT CACHE BURST ACKNOWLEDGE (CBACK) 1) SAMPLE CACHE INHIBIT IN (CIIN) AND CACHE BURST ACKNOWLEDGE (CBACK) 2) LATCH DATA TERMINATE CYCLE 1) REMOVE DATA FROM D31-D0 2) NEGATE STERM (IF NECESSARY) 3) NEGATE CBACK (IF NECESSARY) END OF BURST WHEN 4 LONG WORDS TRANSFERRED UNTIL 4 LONG WORDS TRANSFERRED 1) NEGATE AS AND DS 2) NEGATE DBEN START NEXT CYCLE Figure 7-37. Burst Operation Flowchart -- Four Long Words Transferred not to be cached, CIIN must be asserted at the same time as STERM. The assertion of CIIN also has the effect of aborting the burst operation. 7-64 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S1 S2 Sw Sw Sw Sw Sw Sw S3 Sw Sw S4 S5 Sw Sw S6 S7 Sw Sw S8 S9 CLK A31-A4 A3 A2-A0 FC2-FC0 SIZ1-SIZ0 R/W ECS OCS AS DS STERM CIIN CIOUT CBREQ CBACK D31-D0 b4-b7 b8-bB bC-bF 10 11 bC-bF DBEN 01 00 VALUE OF A3:A2 INCREMENTED BY THE SYSTEM HARDWARE Figure 7-38. Long-Word Operand Request from $07 with Burst Request and Wait Cycle MOTOROLA MC68030 USER'S MANUAL 7-65 Bus Operation S0 S2 S4 S6 CLK A31-A4 A3 A2-A0 FC2-FC0 SIZ1-SIZ0 R/W ECS OCS 3 AS DS STERM CIIN CIOUT CBREQ CBACK D31-D0 VALUE OF CBACK CONTROL NEXT CYCLE b8-bB b4-b7 bC-bF 2 1 DBEN 01 10 11 VALUE OF A3:A2 INCREMENTED BY THE SYSTEM HARDWARE NOTES: 1. Assertion of CBACK causes data to be placed on D31-D0. 2. Continued assertion of CBACK causes data to be placed on D31-D0. 3. Negation of CBACK causes AS to be negated. Figure 7-39. Long-Word Operand Request from $07 with Burst Request -- CBACK Negated Early 7-66 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S1 S2 Sw Sw S3 S0 S1 S2 Sw Sw S3 Sw Sw S4 S5 Sw Sw S6 S7 Sw Sw S8 S9 CLK A31-A5 A4 A3-A1 A0 FC2-FC0 SIZ1 SIZ0 R/W ECS OCS AS DS STERM CBREQ CBACK bC-bF D31-D0 b0-b3 b4-b7 b8-bB bC-bF DBEN PREVIOUS CACHE BLOCK NEXT CACHE BLOCK - START BURST CYCLE Figure 7-40. Long-Word Operand Request from $0E -- Burst Fill Deferred MOTOROLA MC68030 USER'S MANUAL 7-67 Bus Operation S0 S2 S4 CLK A31-A0 FC2-FC0 SIZ1 SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 STERM CIIN CIOUT CBREQ CBACK b4-b7 D31-D0 DBEN 01 10 11 BURST MODE ENDS, DATA NOT CACHED VALUE OF A3:A2 INCREMENTED BY THE SYSTEM HARDWARE Figure 7-41. Long-Word Operand Request from $07 with Burst Request -- CBACK and CIIN Asserted 7-68 MC68030 USER'S MANUAL MOTOROLA Bus Operation Since CIIN, CBACK, and STERM are synchronous signals, they must meet the synchronous input setup and hold times for all rising edges of the clock while AS is asserted. If STERM is negated at the beginning of S2, wait states are inserted after S2, and STERM is sampled on every rising edge of the clock thereafter until it is recognized. Once STERM is recognized, data is latched on the next falling edge of the clock (corresponding to the beginning of S3). State 3 The processor maintains AS, DS, and DBEN asserted during S3. It also holds the address valid during S3 for continuation of the burst. R/W, SIZ0-SIZ1, and FC0-FC2 also remain valid throughout S3. The external device must keep the data driven throughout the synchronous hold time for data from the beginning of S3. The device must negate STERM within one clock after asserting STERM; otherwise, the processor may inadvertently use STERM prematurely for the next burst access. STERM need not be negated if subsequent accesses do not require wait cycles. State 4 At the beginning of S4, the processor tests the level of STERM. This state signifies the beginning of burst mode, and the remaining states correspond to burst fill cycles. If STERM is recognized, the processor latches the incoming data at the end of S4. This data corresponds to the second long word of the burst. If STERM is negated at the beginning of S4, wait states are inserted instead of S4 and S5, and STERM is sampled on every rising edge of the clock thereafter until it is recognized. As for synchronous cycles, the states of CBACK and CIIN are latched at the time STERM is recognized. The assertion of CBACK at this time indicates that the burst operation should continue, and the assertion of CIIN indicates that the data latched at the end of S4 should not be cached and that the burst should abort. State 5 The processor maintains all the signals on the bus driven throughout S5 for continuation of the burst. The same hold times for STERM and data described for S3 apply here. State 6 This state is identical to S4 except that once STERM is recognized, the third long wordof data for the burst is latched at the end of S6. MOTOROLA MC68030 USER'S MANUAL 7-69 Bus Operation State 7 During this state, the processor negates CBREQ, and the memory device may negate CBACK. Aside from this, all other bus signals driven by the processor remain driven. The same hold times for STERM and data described for S3 apply here. State 8 This state is identical to S4 except that CBREQ is negated, indicating that the processor cannot continue to accept more data after this. The data latched at the end of S8 corresponds to the fourth long word of the burst. State 9 The processor negates AS, DS, and DBEN during S9. It holds the address, R/W, SIZ0- SIZ1, and FC0-FC2 valid throughout S9. The same hold times for data described for S3 apply here. Note that the address bus of the MC68030 remains driven to a constant value for the duration of a burst transfer operation (including the first transfer before burst mode is entered). If an external memory system requires incrementing of the long-word base address to supply successive long words of information, this function must be performed by external hardware. Additionally, in the case of burst transfers that cross a 16-byte boundary (i.e., the first long word transferred is not located at A3/A2=00), the external hardware must correctly control the continuation or termination of the burst transfer as desired. The burst may be terminated by negating CBACK during the transfer of the most significant long word of the 16-byte image (A3/A2=11) or may be continued (with CBACK asserted) by providing the long word located at A3/A2=00 (i.e., the count sequence wraps back to zero and continues as necessary). The MC68030 caches assume the higher order address lines (A4A31) remain unchanged as the long-word accesses wrap back around to A3/A2=00. 7.4 CPU SPACE CYCLES FC0-FC2 select user and supervisor program and data areas as listed in Table 4-1. The area selected by FC0-FC2=$7 is classified as the CPU space. The interrupt acknowledge, breakpoint acknowledge, and coprocessor communication cycles described in the following sections utilize CPU space. 7-70 MC68030 USER'S MANUAL MOTOROLA Bus Operation The CPU space type is encoded on A16-A19 during a CPU space operation and indicates the function that the processor is performing. On the MC68030, three of the encodings are implemented as shown in Figure 7-42. All unused values are reserved by Motorola for future additional CPU space types. FUNCTION CODE 2 0 BREAKPOINT ACKNOWLEDGE 1 1 1 ADDRESS BUS 31 23 19 16 31 COPROCESSOR COMM. 1 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 CPID 13 2 BKPT # 4 1 1 1 0 0 0 0 0 0 0 0 0 31 INTERRUPT ACKNOWLEDGE 0 0 0 CP REG 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL 0 1 CPU SPACE TYPE FIELD Figure 7-42. MC68030 CPU Space Address Encoding 7.4.1 Interrupt Acknowledge Bus Cycles When a peripheral device signals the processor (with the IPL0-IPL2 signals) that the device requires service, and the internally synchronized value on these signals indicates a higher priority than the interrupt mask in the status register (or that a transition has occurred in the case of a level 7 interrupt), the processor makes the interrupt a pending interrupt. Refer to 8.1.9 Interrupt Exceptions for details on the recognition of interrupts. The MC68030 takes an interrupt exception for a pending interrupt within one instruction boundary (after processing any other pending exception with a higher priority). The following paragraphs describe the various kinds of interrupt acknowledge bus cycles that can be executed as part of interrupt exception processing. MOTOROLA MC68030 USER'S MANUAL 7-71 Bus Operation 7.4.1.1 INTERRUPT ACKNOWLEDGE CYCLE -- TERMINATED NORMALLY. When the MC68030 processes an interrupt exception, it performs an interrupt acknowledge cycle to obtain the number of the vector that contains the starting location of the interrupt service routine. Some interrupting devices have programmable vector registers that contain the interrupt vectors for the routines they use. The following paragraphs describe the interrupt acknowledge cycle for these devices. Other interrupting conditions or devices cannot supply a vector number and use the autovector cycle described in 7.4.1.2 Autovector Interrupt Acknowledge Cycle. The interrupt acknowledge cycle is a read cycle. It differs from the asynchronous read cycle described in 7.3.1 Asynchronous Read Cycle or the synchronous read cycle described in 7.3.4 Synchronous Read Cycle in that it accesses the CPU address space. Specifically, the differences are: 1. FC0-FC2 are set to seven (FC0/FC1/FC2=111) for CPU address space. 2. A1, A2, and A3 are set to the interrupt request level (the inverted values of IPL0, iPL1, and IPL2, respectively). 3. The CPU space type field (A16-A19) is set to $F, the interrupt acknowledge code. 4. A20-A31, A4-A15, and A0 are set to one. The responding device places the vector number on the data bus during the interrupt acknowledge cycle. Beyond this, the cycle is terminated normally with either STERM or DSACKx. Figure 7-43 is the flowchart of the interrupt acknowledge cycle. 7-72 MC68030 USER'S MANUAL MOTOROLA Bus Operation CONTROLLER INTERRUPTING DEVICE ACKNOWLEDGE INTERRUPT REQUEST INTERRUPT 1) INTERRUPT PENDING (IPEND) RECOGNIZED BY CURRENT INSTRUCTION - WAIT FOR INSTRUCTION BOUNDARY 2) SET R/W TO READ 3) SET FUNCTION CODE TO CPU SPACE 4) PLACE INTERRUPT LEVEL ON A1,A2, AND A3. TYPE FIELD = INTERRUPT ACKNOWLEDGE (IACK) 5) SET SIZE TO BYTE 6) NEGATE IPEND 7) ASSERT ADDRESS STROBE (AS) AND DATA STROBE (DS) PROVIDE VECTOR INFORMATION 1) PLACE VECTOR NUMBER ON LEAST SIGNIFICANT BYTE OF DATA PORT (DEPENDS ON PORT SIZE) 2) ASSERT DATA AND SIZE ACKNOWLEDGE (DSACKx) OR ASSERT SYNCHRONOUS TERMINATION (STERM) ACQUIRE VECTOR NUMBER 1) LATCH VECTOR NUMBER 2) NEGATE AS AND DS RELEASE CONTINUE INTERRUPT EXCEPTION PROCESSING 1) REMOVE VECTOR NUMBER FROM DATA BUS 2) NEGATE DSACKx Figure 7-43. Interrupt Acknowledge Cycle Flowchart Figure 7-44 shows the timing for an interrupt acknowledge cycle terminated with DSACKx. 7.4.1.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE. When the interrupting device cannot supply a vector number, it requests an automatically generated vector or autovector. Instead of placing a vector number on the data bus and asserting DSACKx or STERM, the device asserts the autovector signal (AVEC) to terminate the cycle. Neither STERM nor DSACKx may be asserted during an interrupt acknowledge cycle terminated by AVEC. The vector number supplied in an autovector operation is derived from the interrupt level of the current interrupt. When AVEC is asserted instead of DSACK or STERM during an interrupt acknowledge cycle, the MC68030 ignores the state of the data bus and internally generates the vector number, the sum of the interrupt level plus 24 ($18). There are seven distinct autovectors that can be used, corresponding to the seven levels of interrupt available with signals IPL0-IPL2. Figure 7-45 shows the timing for an autovector operation. MOTOROLA MC68030 USER'S MANUAL 7-73 Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 CLK A31-A4 A3-A1 INTERRUPT LEVEL A0 FC2-FC0 SIZ1 SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 VECTOR # FROM 8-BIT PORT D23-D16 VECTOR # FROM 16-BIT PORT D7-D0 VECTOR # FROM 32-BIT PORT IPL2-IPL0 IPEND READ CYCLE INTERRUPT ACKNOWLEDGE WRITE STACK Figure 7-44. Interrupt Acknowledge Cycle Timing 7-74 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 CLK A31-A4 INTERRUPT LEVEL A3-A1 A0 FC2-FC0 SIZ1 SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D0 IPL2-IPL0 AVEC READ CYCLE INTERRUPT ACKNOWLEDGE AUTOVECTORED WRITE STACK Figure 7-45. Autovector Operation Timing MOTOROLA MC68030 USER'S MANUAL 7-75 Bus Operation 7.4.1.3 SPURIOUS INTERRUPT CYCLE. When a device does not respond to an interrupt acknowledge cycle with AVEC, STERM, or DSACKx, the external logic typically returns BERR. The MC68030 automatically generates the spurious interrupt vector number, 24, instead of the interrupt vector number in this case. If HALT is also asserted, the processor retries the cycle. 7.4.2 Breakpoint Acknowledge Cycle The breakpoint acknowledge cycle is generated by the execution of a breakpoint instruction (BKPT). The breakpoint acknowledge cycle allows the external hardware to provide an instruction word directly into the instruction pipeline as the program executes. This cycle accesses the CPU space with a type field of zero and provides the breakpoint number specified by the instruction on address lines A2-A4. If the external hardware terminates the cycle with DSACKx or STERM, the data on the bus (an instruction word) is inserted into the instruction pipe, replacing the breakpoint opcode, and is executed after the breakpoint acknowledge cycle completes. The breakpoint instruction requires a word to be transferred so that if the first bus cycle accesses an 8-bit port, a second cycle is required. If the external logic terminates the breakpoint acknowledge cycle with BERR (i.e., no instruction word available), the processor takes an illegal instruction exception. Figure 7-46 is a flowchart of the breakpoint acknowledge cycle. Figure 7-47 shows the timing for a breakpoint acknowledge cycle that returns an instruction word. Figure 7-48 shows the timing for a breakpoint acknowledge cycle that signals an exception. 7.4.3 Coprocessor Communication Cycles The MC68030 coprocessor interface provides instruction-oriented communication between the processor and as many as seven coprocessors. The bus communication required to support coprocessor operations uses the MC68030 CPU space with a type field of $2. Coprocessor accesses use the MC68030 bus protocol except that the address bus supplies access information rather than a 32-bit address. The CPU space type field (A16-A19) for a coprocessor operation is $2. A13-A15 contain the coprocessor identification number (CpID), and A0-A4 specify the coprocessor interface register to be accessed. Coprocessor accesses to a CpID of zero correspond to MMU instructions and are not generated by the MC68030 as a result of the coprocessor interface. These cycles can only be generated by the MOVES instruction. Refer to Section 10 Coprocessor Interface Description for further information. 7-76 MC68030 USER'S MANUAL MOTOROLA Bus Operation CONTROLLER EXTERNAL DEVICE BREAKPOINT ACKNOWLEDGE 1) 2) 3) 4) 5) 6) SET R/W TO READ SET FUNCTION CODE TO CPU SPACE PLACE CPU SPACE TYPE 0 ON A19-A16 PLACE BREAKPOINT NUMBER ON A4-A2 SET SIZE TO WORD ASSERT ADDRESS STROBE (AS) AND DATA STROBE (DS) 1) PLACE REPLACEMENT OPCODE ON DATA BUS 2) ASSERT DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACKx) SYNCHRONOUS TERMINATION (STERM) OR 1) ASSERT BUS ERRROR (BERR) TO INITIATE EXCEPTION PROCESSING IF DSACKx OR STERM 1) LATCH DATA 2) NEGATE AS AND DS 3) GO TO A IF BERR ASSERTED: 1) NEGATE AS AND DS 2) GO TO B A B 1) PLACE LATCHED DATA IN INSTRUCTION PIPELINE 2) CONTINUE PROCESSING SLAVE NEGATES DSACKx, STERM OR BERR 1) INITIATE ILLEGAL INSTRUCTION PROCESSING Figure 7-46. Breakpoint Operation Flow 7.5 BUS EXCEPTION CONTROL CYCLES The MC68030 bus architecture requires assertion of either DSACKx or STERM from an external device to signal that a bus cycle is complete. DSACKx, STERM, or AVEC is not asserted if: * The external device does not respond. * No interrupt vector is provided. * Various other application-dependent errors occur. External circuitry can provide BERR when no device responds by asserting DSACKx, STERM, or AVEC within an appropriate period of time after the processor asserts AS. This allows the cycle to terminate and the processor to enter exception processing for the error condition. The MMU can also detect an internal bus error. This occurs when the processor attempts to access an address in a protected area of memory (a user program attempts to access supervisor data, for example) or after the MMU receives a bus error while searching the address table for an address translation description. MOTOROLA MC68030 USER'S MANUAL 7-77 Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 CLK A31-A20 A19-A16 (0000) BREAKPOINT ENCODING A15-A2 BREAKPOINT NUMBER A1-A0 CPU SPACE FC2-FC0 SIZ1 WORD SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 BERR HALT READ CYCLE BREAKPOINT ACKNOWLEDGE INSTRUCTION WORD FETCH FETCHED INSTRUCTION EXECUTION Figure 7-47. Breakpoint Acknowledge Cycle Timing 7-78 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S2 Sw Sw Sw S4 S0 S2 S4 CLK A31-A0 FC2-FC0 SIZ1-SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D0 BERR HALT READ WITH BUS ERROR ASSERTED INTERNAL PROCESSING STACK WRITE Figure 7-48. Breakpoint Acknowledge Cycle Timing (Exception Signaled) Another signal that is used for bus exception control is HALT. This signal can be asserted by an external device for debugging purposes to cause single bus cycle operation or (in combination with BERR) a retry of a bus cycle in error. MOTOROLA MC68030 USER'S MANUAL 7-79 Bus Operation To properly control termination of a bus cycle for a retry or a bus error condition, DSACKx, BERR, and HALT can be asserted and negated with the rising edge of the MC68030 clock. This assures that when two signals are asserted simultaneously, the required setup time (#47A) and hold time (#47B) for both of them is met for the same falling edge of the processor clock. (Refer to MC68030EC/D, MC68030 Electrical Specifications for timing requirements.) This or some equivalent precaution should be designed into the external circuitry that provides these signals. The acceptable bus cycle terminations for asynchronous cycles are summarized in relation to DSACKx assertion as follows (case numbers refer to Table 7-8): Normal Termination: DSACKx is asserted; BERR and HALT remain negated (case 1). Halt Termination: HALT is asserted at same time or before DSACKx, and BERR remains negated (case 2). Bus Error Termination: BERR is asserted in lieu of, at the same time, or before DSACKx (case 3) or after DSACKx (case 4), and HALT remains negated; BERR is negated at the same time or after DSACKx. Retry Termination: HALT and BERR are asserted in lieu of, at the same time, or before DSACKx (case 5) or after DSACKx (case 6); BERR is negated at the same time or after DSACKx; HALT may be negated at the same time or after BERR. 7-80 MC68030 USER'S MANUAL MOTOROLA Bus Operation Table 7-8. DSACK, BERR, and HALT Assertion Results Case No. Control Signal Asserted on Rising Edge of State N N+2 Result 1 DSACKx BERR HALT A NA NA S NA X Normal cycle terminate and continue. 2 DSACKx BERR HALT A NA A/S S NA S Normal cycle terminate and halt. Continue when HALT negated. 3 DSACKx BERR HALT NA/A A NA X S NA Terminate and take bus error exception, possibly deferred. 4 DSACKx BERR HALT A NA NA X A NA Terminate and take bus error exception, possibly deferred. 5 DSACKx BERR HALT NA/A A A/S X S S Terminate and retry when HALT negated. 6 DSACKx BERR HALT A NA NA X A A Terminate and retry when HALT negated. LEGEND: N -- The number of current even bus state (e.g., S2, S4, etc.) A -- Signal is asserted in this bus state NA -- Signal is not asserted in this state X -- Don't care S -- Signal was asserted in previous state and remains asserted in this state Table 7-8 shows various combinations of control signal sequences and the resulting bus cycle terminations. To ensure predictable operation, BERR and HALT should be negated according to the specifications in MC68030EC/D, MC68030 Electrical Specifications. DSACKx, BERR, and HALT may be negated after AS. If DSACKx or BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated prematurely. The termination signal for a synchronous cycle is STERM. An analogous set of bus cycle termination cases exists in relationship to STERM assertion. Note that STERM and DSACKx must never both be asserted in the same cycle. STERM has setup time (#60) and hold time (#61) requirements relative to each rising edge of the processor clock while AS is asserted. Bus error and retry terminations during burst cycles operate as described in 6.1.3.2 Burst Mode Filling, 7.5.1 Bus Errors, and 7.5.2 Retry Operation. MOTOROLA MC68030 USER'S MANUAL 7-81 Bus Operation For STERM, the bus cycle terminations are summarized as follows (case numbers refer to Table 7-9): Normal Termination: STERM is asserted; BERR and HALT remain negated (case 1). Halt Termination: HALT is asserted before STERM, and BERR remains negated (case 2). Bus Error Termination: BERR is asserted in lieu of, at the same time, or before STERM (case 3) or after STERM (case 4), and HALT remains negated; BERR is negated at the same time or after STERM. Retry Termination: HALT and BERR are asserted in lieu of, at the same time, or before STERM (case 5) or after STERM (case 6); BERR is negated at the same time or after STERM; HALT may be negated at the same time or after BERR. 7-82 MC68030 USER'S MANUAL MOTOROLA Bus Operation Table 7-9. STERM, BERR, and HALT Assertion Results Case No. Control Signal Asserted on Rising Edge of State N N+2 Result 1 STERM BERR HALT A NA NA -- -- -- Normal cycle terminate and continue. 2 STERM BERR HALT NA NA A/S A NA S Normal cycle terminate and halt. Continue when HALT negated. 3 STERM BERR HALT NA A/S NA A S NA Terminate and take bus error exception, possibly deferred. 4 STERM BERR HALT A A N/A -- -- -- Terminate and take bus error exception, possibly deferred. 5 STERM BERR HALT NA A A/S A S S Terminate and retry when HALT negated. 6 STERM BERR HALT A A A -- -- -- Terminate and retry when HALT negated. LEGEND: N A NA X S -- --The number of current even bus state (e.g., S2, S4, etc.) --Signal is asserted in this bus state --Signal is not asserted in this state --Don't care --Signal was asserted in previous state and remains asserted in this state --State N+2 not part of bus cycle EXAMPLE A: A system uses a watchdog timer to terminate accesses to an unpopulated address space. The timer asserts BERR after timeout (case 3). MOTOROLA MC68030 USER'S MANUAL 7-83 Bus Operation EXAMPLE B: A system uses error detection and correction on RAM contents. The designer may: 1. Delay DSACKx until data is verified; assert BERR and HALT simultaneously to indicate to the processor to automatically retry the error cycle (case 5) or, if data is valid, assert DSACKx (case 1). 2. Delay DSACKx until data is verified and assert BERR with or without DSACKx if data is in error (case 3). This initiates exception processing for software handling of the condition. 3. Return DSACKx prior to data verification. If data is invalid, BERR is asserted on the next clock cycle (case 4). This initiates exception processing for software handling of the condition. 4. Return DSACKx prior to data verification; if data is invalid, assert BERR and HALT on the next clock cycle (case 6). The memory controller can then correct the RAM prior to or during the automatic retry. 7.5.1 Bus Errors The bus error signal can be used to abort the bus cycle and the instruction being executed. BERR takes precedence over DSACKx or STERM provided it meets the timing constraints described in MC68030EC/D, MC68030 Electrical Specifications. If BERR does not meet these constraints, it may cause unpredictable operation of the MC68030. If BERR remains asserted into the next bus cycle, it may cause incorrect operation of that cycle. When the bus error signal is issued to terminate a bus cycle, the MC68030 may enter exception processing immediately following the bus cycle, or it may defer processing the exception. The instruction prefetch mechanism requests instruction words from the bus controller and the instruction cache before it is ready to execute them. If a bus error occurs on an instruction fetch, the processor does not take the exception until it attempts to use that instruction word. Should an intervening instruction cause a branch or should a task switch occur, the bus error exception does not occur. 7-84 MC68030 USER'S MANUAL MOTOROLA Bus Operation The bus error signal is recognized during a bus cycle in any of the following cases: * DSACKx (or STERM) and HALT are negated and BERR is asserted. * HALT and BERR are negated and DSACKx is asserted. BERR is then asserted within one clock cycle (HALT remains negated). * BERR is asserted and recognized on the next falling clock edge following the rising clock edge on which STERM is asserted and recognized (HALT remains negated). When the processor recognizes a bus error condition, it terminates the current bus cycle in the normal way. Figure 7-49 shows the timing of a bus error for the case in which neither DSACKx nor STERM is asserted. Figure 7-50 shows the timing for a bus error that is asserted after DSACKx. Exceptions are taken in both cases. (Refer to 8.1.2 Bus Error Exception for details of bus error exception processing.) When BERR is asserted during a read cycle that supplies data to either on-chip cache, the data in the cache is marked invalid. However, when a write cycle that writes data into the data cache results in an externally generated bus error, the data in the cache is not marked invalid. In the second case, where BERR is asserted after DSACKx is asserted, BERR must be asserted within specification #48 (refer to MC68030EC/D, MC68030 Electrical Specifications) for purely asynchronous operation, or it must be asserted and remain stable during the sample window, defined by specifications #27A and #47B, around the next falling edge of the clock after DSACKx is recognized. If BERR is not stable at this time, the processor may exhibit erratic behavior. BERR has priority over DSACKx. In this case, data may be present on the bus, but may not be valid. This sequence may be used by systems that have memory error detection and correction logic and by external cache memories. The assertion of BERR described in the third case (recognized after STERM) has requirements similar to those described in the preceding paragraph. BERR must be stable throughout the sample window for the next falling edge of the clock, as defined by specifications #27A and #28A. Figure 7-51 shows the timing for this case. MOTOROLA MC68030 USER'S MANUAL 7-85 Bus Operation S0 S2 S4 S0 S2 S4 S0 S2 CLK A31-A20 A19-A16 (0000) BREAKPOINT ENCODING A15-A2 BREAKPOINT NUMBER A1-A0 FC2-FC0 CPU SPACE SIZ1 WORD SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31 -D24 D23-D16 D15-D8 D7-D0 BERR HALT READ CYCLE BREAKPOINT ACKNOWLEDGE BUS ERROR ASSERTED FETCHED INSTRUCTION EXECUTION Figure 7-49. Bus Error without DSACKx 7-86 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S2 Sw Sw S4 S0 S2 S4 CLK A31-A0 FC2-FC0 SIZ1-SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D0 IPL0-IPL2 BERR HALT WRITE WITH BUS ERROR ASSERTED INTERNAL PROCESSING STACK WRITE Figure 7-50. Late Bus Error with DSACKx A bus error occurring during a burst fill operation is a special case. If a bus error occurs during the first cycle of a burst, the data is ignored, the entire cache line is marked invalid, and the burst operation is aborted. If the cycle is for an instruction fetch, a bus error exception is made pending. This bus error is processed only if the execution unit attempts to use either of the two words latched during the bus cycle. If the cycle is for a data fetch, the bus error exception is taken immediately. Refer to Section 11 Instruction Execution Timing for more information about pipeline operation. MOTOROLA MC68030 USER'S MANUAL 7-87 Bus Operation S0 S2 Sw Sw Sw Sw S3 S0 S2 CLK A31-A0 FC2-FC0 SIZ1-SIZ0 R/W ECS OCS AS DS STERM DBEN D31-D0 BERR HALT WRITE WITH BUS ERROR ASSERTED INTERNAL PROCESSING STACK WRITE Figure 7-51. Late Bus Error with STERM -- Exception Taken When a bus error occurs after the burst mode has been entered (that is, on the second access or later), the processor terminates the burst operation, and the cache entry corresponding to that cycle is marked invalid, but the processor does not take an exception (see Figure 7-52). If the second cycle is for a portion of a misaligned operand fetch, the processor runs another read cycle for the second portion with CBREQ negated, as shown in Figure 7-53. If BERR is asserted again, the MC68030 then takes an exception. The MC68030 supports late bus errors during a burst fill operation; the timing is the same relative to STERM and the clock as for a late bus error in a normal synchronous cycle. 7-88 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S2 S4 S6 CLK A31-A4 A3 A2-A0 FC2-FC0 SIZ1-SIZ0 R/W ECS OCS AS DS STERM CIIN CIOUT CBREQ CBACK D31-D0 b4-b7 b8-bB DBEN BERR HALT 0111 1000 1100 LATE BERR ENDS BURST; NO EXCEPTION TAKEN VALUE OF A3:A0 INCREMENTED BY THE SYSTEM HARDWARE Figure 7-52. Long-Word Operand Request -- Late BERR on Third Access MOTOROLA MC68030 USER'S MANUAL 7-89 Bus Operation S0 S1 S2 Sw Sw Sw Sw Sw Sw S3 Sw Sw Sw Sw S4 S5 S0 S1 S2 S3 Sw Sw Sw Sw S4 S5 CLK A31-A0 A3:A0 = 1000 FC2-FC0 SIZ1-SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 STERM CIIN CIOUT CBREQ CBACK D31-D0 bC-bF b4-b7 DBEN BERR HALT BURST ABORTED BUS ERROR ASSERTED 0111 1000 INTERNAL PROCESSING RERUN CYCLE TO GET LAST 3 BYTES OF OPERAND VALUE OF A3:A0 INCREMENTED BY THE SYSTEM HARDWARE Figure 7-53. Long-Word Operand Request -- BERR on Second Access 7-90 MC68030 USER'S MANUAL MOTOROLA Bus Operation 7.5.2 Retry Operation When the BERR and HALT signals are both asserted by an external device during a bus cycle, the processor enters the retry sequence. A delayed retry, similar to the delayed bus error signal described previously, can also occur, both for synchronous and asynchronous cycles. The processor terminates the bus cycle, places the control signals in their inactive state, and does not begin another bus cycle until the HALT signal is negated by external logic. After a synchronization delay, the processor retries the previous cycle using the same access information (address, function code, size, etc.) The BERR signal should be negated before S2 of the read cycle to ensure correct operation of the retried cycle. Figure 7-54 shows a retry operation of an asynchronous cycle, and Figure 7-55 shows a retry operation of a synchronous cycle. The processor retries any read or write cycle of a read-modify-write operation separately; RMC remains asserted during the entire retry sequence. On the initial access of a burst operation, a retry (indicated by the assertion of BERR and HALT) causes the processor to retry the bus cycle and assert CBREQ again. Figure 7-56 shows a late retry operation that causes an initial burst operation to be repeated. However, signaling a retry with simultaneous BERR and HALT during the second, third, or fourth cycle of a burst operation does not cause a retry operation, even if the requested operand is misaligned. Assertion of BERR and HALT during a subsequent cycle of a burst operation causes independent BERR and HALT operations. The external bus activity remains halted until HALT is negated and the processor acts as previously described for the bus error during a burst operation. Asserting BR along with BERR and HALT provides a relinquish and retry operation. The MC68030 does not relinquish the bus during a read-modify-write operation, except during the first read cycle. Any device that requires the processor to give up the bus and retry a bus cycle during a read-modify-write cycle must either assert BERR and BR only (HALT must not be included) or use the single wire arbitration method discussed in 7.7.4 Bus Arbitration Control. The bus error handler software should examine the read-modify-write bit in the special status word (refer to 8.2.1 Special Status Word (SSW)) and take the appropriate action to resolve this type of fault when it occurs. MOTOROLA MC68030 USER'S MANUAL 7-91 Bus Operation S0 S1 S2 S3 Sw Sw S4 S5 S0 S2 S4 CLK A31-A0 FC2-FC0 SIZ1-SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DATA BUS NOT DRIVEN D31-D0 BERR HALT WRITE CYCLE RETRY SIGNALED HALT RETRY CYCLE Figure 7-54. Asynchronous Late Retry 7-92 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S1 S2 S3 S0 S1 S2 S3 CLK A31-A0 FC2-FC0 SIZ1-SIZ0 R/W ECS OCS AS DS STERM D31-D0 BERR HALT READ CYCLE RETRY SIGNALED HALT RETRY CYCLE Figure 7-55. Synchronous Late Retry 7.5.3 Halt Operation When HALT is asserted and BERR is not asserted, the MC68030 halts external bus activity at the next bus cycle boundary. HALT by itself does not terminate a bus cycle. Negating and reasserting HALT in accordance with the correct timing requirements provides a single-step (bus cycle to bus cycle) operation. The HALT signal affects external bus cycles only; thus, a program that resides in the instruction cache and performs no data writes (or reads that miss in the data cache) may continue executing, unaffected by the HALT signal. 7-93 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S1 S2 S3 S0 S1 S2 S3 S4 CLK A31-A0 FC2-FC0 SIZ1-SIZ0 R/W ECS OCS AS DS STERM CIIN CIOUT CBREQ CBACK D31-D0 BERR HALT READ HALT RETRY Figure 7-56. Late Retry Operation for a Burst The single-cycle mode allows the user to proceed through (and debug) external processor operations, one bus cycle at a time. Figure 7-57 shows the timing requirements for a singlecycle operation. Since the occurrence of a bus error while HALT is asserted causes a retry operation, the user must anticipate retry cycles while debugging in the single-cycle mode. The single-step operation and the software trace capability allow the system debugger to trace single bus cycles, single instructions, or changes in program flow. These processor capabilities, along with a software debugging package, give complete debugging flexibility. 7-94 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S2 S0 S4 S2 S4 CLK A31-A0 FC2-FC0 SIZ1/SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D0 BERR HALT BR BG BGACK READ HALT (ARBITRATION PERMITTED WHILE THE CONTROLLER IS HALTED) READ Figure 7-57. Halt Operation Timing 7-95 MC68030 USER'S MANUAL MOTOROLA Bus Operation When the processor completes a bus cycle with the HALT signal asserted, the data bus is placed in the high-impedance state, and bus control signals are driven inactive (not highimpedance state); the address, function code, size, and read/write signals remain in the same state. The halt operation has no effect on bus arbitration (refer to 7.7 Bus Arbitration). When bus arbitration occurs while the MC68030 is halted, the address and control signals are also placed in the high-impedance state. Once bus mastership is returned to the MC68030, if HALT is still asserted, the address, function code, size, and read/write signals are again driven to their previous states. The processor does not service interrupt requests while it is halted, but it may assert the IPEND signal as appropriate. 7.5.4 Double Bus Fault When a bus error or an address error occurs during the exception processing sequence for a previous bus error, a previous address error, or a reset exception, the bus or address error causes a double bus fault. For example, the processor attempts to stack several words containing information about the state of the machine while processing a bus error exception. If a bus error exception occurs during the stacking operation, the second error is considered a double bus fault. Only an external reset operation can restart a halted processor. However, bus arbitration can still occur (refer to 7.7 Bus Arbitration). The MC68030 indicates that a double bus fault condition has occurred by continuously asserting the STATUS signal until the processor is reset. The processor asserts STATUS for one, two, or three clock periods to signal other microsequencer status indications. Refer to Section 12 Applications Information for a description of the interpretation of the STATUS signal. A second bus error or address error that occurs after exception processing has completed (during the execution of the exception handler routine or later) does not cause a double bus fault. A bus cycle that is retried does not constitute a bus error or contribute to a double bus fault. The processor continues to retry the same bus cycle as long as the external hardware requests it. 7-96 MC68030 USER'S MANUAL MOTOROLA Bus Operation 7.6 BUS SYNCHRONIZATION The MC68030 overlaps instruction execution; that is, during bus activity for one instruction, instructions that do not use the external bus can be executed. Due to the independent operation of the on-chip caches relative to the operation of the bus controller, many subsequent instructions can be executed, resulting in seemingly nonsequential instruction execution. When this is not desired and the system depends on sequential execution following bus activity, the NOP instruction can be used. The NOP instruction forces instruction and bus synchronization in that it freezes instruction execution until all pending bus cycles have completed. An example of the use of the NOP instruction for this purpose is the case of a write operation of control information to an external register, where the external hardware attempts to control program execution based on the data that is written with the conditional assertion of BERR. If the data cache is enabled and the write cycle results in a hit in the data cache, the cache is updated. That data, in turn, may be used in a subsequent instruction before the external write cycle completes. Since the MC68030 cannot process the bus error until the end of the bus cycle, the external hardware has not successfully interrupted program execution. To prevent a subsequent instruction from executing until the external cycle completes, a NOP instruction can be inserted after the instruction causing the write. In this case, bus error exception processing proceeds immediately after the write before subsequent instructions are executed. This is an irregular situation, and the use of the NOP instruction for this purpose is not required by most systems. Note that even in a system with error detection/correction circuitry, the NOP is not required for this synchronization. Since the MMU always checks the validity of write cycles before they proceed to the data cache and are executed externally, the MC68030 is guaranteed to write correct data to the cache. Thus, there is no danger in subsequent instructions using erroneous data from the cache before an external bus error signals an error. A bus synchronization example is given in Figure 7-58. 7-97 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 Sw EXTERNAL WRITE WRITE TO D. CACHE MOVE. L D0, (A0) D. CACHE READ MOVE . L (A0), D1 NOP PREVENTS EXECUTION OF SUBSEQUENT INSTRUCTIONS UNTIL MOVE. L D0, (A0) WRITE CYCLE COMPLETES Figure 7-58. Bus Synchronization Example 7.7 BUS ARBITRATION The bus design of the MC68030 provides for a single bus master at any one time: either the processor or an external device. One or more of the external devices on the bus can have the capability of becoming bus master. Bus arbitration is the protocol by which an external device becomes bus master; the bus controller in the MC68030 manages the bus arbitration signals so that the processor has the lowest priority. External devices that need to obtain the bus must assert the bus arbitration signals in the sequences described in the following paragraphs. Systems having several devices that can become bus master require external circuitry to assign priorities to the device so that, when two or more external devices attempt to become bus master at the same time, the one having the highest priority becomes bus master first. The sequence of the protocol is: 1. An external device asserts the bus request signal. 2. The processor asserts the bus grant signal to indicate that the bus will become available at the end of the current bus cycle. 3. The external device asserts the bus grant acknowledge signal to indicate that it has assumed bus mastership. BR may be issued any time during a bus cycle or between cycles. BG is asserted in response to BR; it is usually asserted as soon as BR has been synchronized and recognized, except when the MC68030 has made an internal decision to execute a bus cycle. Then, the assertion of BG is deferred until the bus cycle has begun. Additionally, BG is not asserted until the end of a read-modify-write operation (when RMC is negated) in response to a BR signal. When the requesting device receives BG and more than one external device can be bus master, the requesting device should begin whatever arbitration is required. The external device asserts BGACK when it assumes bus mastership and 7-98 MC68030 USER'S MANUAL MOTOROLA Bus Operation maintains BGACK during the entire bus cycle (or cycles) for which it is bus master. The following conditions must be met for an external device to assume mastership of the bus through the normal bus arbitration procedure: * It must have received BG through the arbitration process. * AS must be negated, indicating that no bus cycle is in progress, and the external device must ensure that all appropriate processor signals have been placed in the high-impedance state (by observing specification #7 in MC68030EC/D, MC68030 Electrical Specifications). * The termination signal (DSACKx or STERM) for the most recent cycle must have become inactive, indicating that external devices are off the bus (optional, refer to 7.7.3 Bus Grant Acknowledge). * BGACK must be inactive, indicating that no other bus master has claimed ownership of the bus. Figure 7-59 is a flowchart showing the detail involved in bus arbitration for a single device. Figure 7-60 is a timing diagram for the same operation. This technique allows processing of bus requests during data transfer cycles. The timing diagram shows that BR is negated at the time that BGACK is asserted. This type of operation applies to a system consisting of the processor and one device capable of bus mastership. In a system having a number of devices capable of bus mastership, the bus request line from each device can be wire-ORed to the processor. In such a system, more than one bus request can be asserted simultaneously. The timing diagram in Figure 7-60 shows that BG is negated a few clock cycles after the transition of the BGACK signal. However, if bus requests are still pending after the negation of BG, the processor asserts another BG within a few clock cycles after it was negated. This additional assertion of BG allows external arbitration circuitry to select the next bus master before the current bus master has finished with the bus. The following paragraphs provide additional information about the three steps in the arbitration process. Bus arbitration requests are recognized during normal processing, RESET assertion, HALT assertion, and even when the processor has halted due to a double bus fault. 7-99 MC68030 USER'S MANUAL MOTOROLA Bus Operation CONTROLLER REQUESTING DEVICE REQUEST THE BUS 1) ASSERT BUS REQUEST (BR) GRANT BUS ARBITRATION 1) ASSERT BUS GRANT (BG) ACKNOWLEDGE BUS MASTERSHIP 1) EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER 2) NEXT BUS MASTER WAITS FOR CURRENT CYCLE TO COMPLETE 3) NEXT BUS MASTER ASSERTS BUS GRANT ACKNOWLEDGE (BGACK) TO BECOME NEW MASTER 4) BUS MASTER NEGATES BR TERMINATE ARBITRATION 1) NEGATE BG AND WAIT FOR BGACK TO BE NEGATED OPERATE AS BUS MASTER 1) PERFORM DATA TRANSFERS (READ AND WRITE CYCLES) REARBITRATE OR RESUME CONTROLLER OPERATION RELEASE BUS MASTERSHIP 1) NEGATE BGACK Figure 7-59. Bus Arbitration Flowchart for Single Request 7.7.1 Bus Request External devices capable of becoming bus masters request the bus by asserting BR. This can be a wire-ORed signal (although it need not be constructed from open-collector devices) that indicates to the processor that some external device requires control of the bus. The processor is effectively at a lower bus priority level than the external device and relinquishes the bus after it has completed the current bus cycle (if one has started). If no acknowledge is received while the BR is active, the processor remains bus master once BR is negated. This prevents unnecessary interference with ordinary processing if the arbitration circuitry inadvertently responds to noise or if an external device determines that it no longer requires use of the bus before it has been granted mastership. 7-100 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S2 S4 S0 S2 CLK A31-A0 FC2-FC0 SIZ1-SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D0 BR BG BGACK CONTROLLER DMA DEVICE CONTROLLER Figure 7-60. Bus Arbitration Operation Timing 7.7.2 Bus Grant The processor asserts BG as soon as possible after receipt of BR. This is immediately following internal synchronization except during a read-modify-write cycle or following an internal decision to execute a bus cycle. During a read-modify-write cycle, the processor does not assert BG until the entire operation has completed. RMC is asserted to indicate 7-101 MC68030 USER'S MANUAL MOTOROLA Bus Operation that the bus is locked. In the case an internal decision to execute another bus cycle, BG is deferred until the bus cycle has begun. BG may be routed through a daisy-chained network or through a specific priority-encoded network. The processor allows any type of external arbitration that follows the protocol. 7.7.3 Bus Grant Acknowledge Upon receiving BG, the requesting device waits until AS, DSACKx (or synchronous termination, STERM), and BGACK are negated before asserting its own BGACK. The negation of the AS indicates that the previous master releases the bus after specification #7 (refer to MC68030EC/D, MC68030 Electrical Specifications). The negation of DSACKx or STERM indicates that the previous slave has completed its cycle with the previous master. Note that in some applications, DSACKx might not be used in this way. General-purpose devices are then connected to be dependent only on AS. When BGACK is asserted, the device is the bus master until it negates BGACK. BGACK should not be negated until all bus cycles required by the alternate bus master are completed. Bus mastership terminates at the negation of BGACK. The BR from the granted device should be negated after BGACK is asserted. If a BR is still pending after the assertion of BGACK, another BG is asserted within a few clocks of the negation of BG, as described in the 7.7.4 Bus Arbitration Control. Note that the processor does not perform any external bus cycles before it reasserts BG in this case. 7.7.4 Bus Arbitration Control The bus arbitration control unit in the MC68030 is implemented with a finite state machine. As discussed previously, all asynchronous inputs to the MC68030 are internally synchronized in a maximum of two cycles of the processor clock. As shown in Figure 7-61, input signals labeled R and A are internally synchronized versions of the BR and BGACK signals, respectively. The BG output is labeled G, and the internal high-impedance control signal is labeled T. If T is true, the address, data, and control buses are placed in the high-impedance state after the next rising edge following the negation of AS and RMC. All signals are shown in positive logic (active high), regardless of their true active voltage level. 7-102 MC68030 USER'S MANUAL MOTOROLA Bus Operation RA XA RA GT STATE 0 RA GT RA GT STATE 4 STATE 1 XX XX RX GT RA STATE 3 XA GT GT RX STATE 2 RA RA STATE 5 GT XX STATE 6 RA R - BUS REQUEST A - BUS GRANT ACKNOWLEDGE G - BUS GRANT T - THREE-STATE CONTROL TO BUS CONTROL LOGIC X - DON'T CARE NOTE: The BG output will not be asserted while RMC is asserted. Figure 7-61. Bus Arbitration State Diagram State changes occur on the next rising edge of the clock after the internal signal is valid. The BG signal transitions on the falling edge of the clock after a state is reached during which G changes. The bus control signals (controlled by T) are driven by the processor, immediately following a state change, when bus mastership is returned to the MC68030. State 0, at the top center of the diagram, in which G and T are both negated, is the state of the bus arbiter while the processor is bus master. Request R and acknowledge A keep the arbiter in state 0 as long as they are both negated. When a request R is received, both grant G and signal T are asserted (in state 1 at the top left). The next clock causes a change to state 2, at the lower left, in which G and T are held. The bus arbiter remains in that state until acknowledge A is asserted or request R is negated. Once either occurs, the arbiter changes to the center state, state 3, and negates grant G. The next clock takes the arbiter to state 4, at the upper right, in which grant G remains negated and signal T remains asserted. With acknowledge A asserted, the arbiter remains in state 4 until A is negated or request R is 7-103 MC68030 USER'S MANUAL MOTOROLA Bus Operation again asserted. When A is negated, the arbiter returns to the original state, state 0, and negates signal T. This sequence of states follows the normal sequence of signals for relinquishing the bus to an external bus master. Other states apply to other possible sequences of combinations of R and A. As shown by the path from state 0 to state 4, BGACK alone can be used to place the processor's external bus buffers in the high-impedance state, providing single-wire arbitration capability. The read-modify-write sequence is normally indivisible to support semaphore operations and multiprocessor synchronization. During this indivisible sequence, the MC68030 asserts the RMC signal and causes the bus arbitration state machine to ignore bus requests (assertions of BR) that occur after the first read cycle of the read-modify-write sequence by not issuing bus grants (asserting BG). In some cases, however, it may be necessary to force the MC68030 to release the bus during an read-modify-write sequence. One way for an alternate bus master to force the MC68030 to release the bus applies only to the first read cycle of an read-modify-write sequence. The MC68030 allows normal bus arbitration during this read cycle; a normal relinquish and retry operation (asserting BERR, HALT, and BR at the same time) is used. Note that this method applies only to the first read cycle of the read-modify-write sequence, but this method preserves the integrity of the read-modify-write sequence without imposing any constraint on the alternate bus master. A second method is single-wire arbitration, the timing of which is shown in Figure 7-62. An alternate master forces the MC68030 to release the bus by asserting BGACK and waits for AS to negate before taking the bus. It applies to all bus cycles of a read-modify-write sequence, but can cause system integrity problems if used improperly. The alternate bus master must guarantee the integrity of the read-modify-write sequence by not altering the contents of memory locations accessed by the read-modify-write sequence. Note that for the method to operate properly, AS must be observed to be negated (high) on two consecutive clock edges before the alternate bus master takes the bus. Waiting for this condition ensures that any current or pending bus activity has completed or has been preempted. 7-104 MC68030 USER'S MANUAL MOTOROLA Bus Operation SEE NOTE DO NOT TAKE BUS TAKE BUS CLK 9 12 16 12 AS 47A 47A BGACK 7 ADDRESS NOTE: The alternate bus master must sample AS high on two consecutive rising edges of the clock (after BGACK is recognized low) before taking the bus. Figure 7-62. Single-Wire Bus Arbitration Timing Diagram A timing diagram of the bus arbitration sequence during a processor bus cycle is shown in Figure 7-60. The bus arbitration sequence while the bus is inactive (i.e., executing internal operations such as a multiply instruction) is shown in Figure 7-63. 7.8 RESET OPERATION RESET is a bidirectional signal with which an external device resets the system or the processor resets external devices. When power is applied to the system, external circuitry should assert RESET for a minimum of 520 clocks after VCC is within tolerance. Figure 7-64 is a timing diagram of the powerup reset operation, showing the relationships between RESET, VCC, and bus signals. The clock signal is required to be stable by the time VCC reaches the minimum operating specification. During the reset period, the entire bus threestates (except for non-three-statable signals, which are driven to their inactive state). Once RESET negates, all control signals are driven to their inactive state, the data bus is in read mode, and the address bus is driven. After this, the first bus cycle for reset exception processing begins. 7-105 MC68030 USER'S MANUAL MOTOROLA Bus Operation S4 S0 CLK A31-A0 FC2-FC0 SIZ1-SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D0 BR BG BGACK CONTROLLER BUS INACTIVE (ARBITRATION PERMITTED WHILE THE CONTROLLER IS INACTIVE OR HALTED) ALTERNATE MASTER CONTROLLER Figure 7-63. Bus Arbitration Operation (Bus Inactive) The external RESET signal resets the processor and the entire system. Except for the initial reset, RESET should be asserted for at least 520 clock periods to ensure that the processor resets. Asserting RESET for 10 clock periods is sufficient for resetting the processor logic; the additional clock periods prevent a reset instruction from overlapping the external RESET signal. 7-106 MC68030 USER'S MANUAL MOTOROLA Bus Operation CLK +5 VOLTS VCC t = >520 CLOCKS 1<4 CLOCKS RESET 4 CLOCKS BUS CYCLES ENTIRE ALL CONTROL SIGNALS BUS HIGH INACTIVE. DATA BUS IN IMPEDANCE READ MODE. ADDRESS ISP BUS DRIVEN READ STARTS BUS STATE UNKNOWN Figure 7-64. Initial Reset Operation Timing Resetting the processor causes any bus cycle in progress to terminate as if DSACKx, BERR, or STERM had been asserted. In addition, the processor initializes registers appropriately for a reset exception. Exception processing for a reset operation is described in 8.1.1 Reset Exception. When a reset instruction is executed, the processor drives the RESET signal for 512 clock cycles. In this case, the processor resets the external devices of the system, and the internal registers of the processor are unaffected. The external devices connected to the RESET signal are reset at the completion of the reset instruction. An external RESET signal that is asserted to the processor during execution of a reset instruction must extend beyond the reset period of the instruction by at least eight clock cycles to reset the processor. Figure 765 shows the timing information for the reset instruction. 7-107 MC68030 USER'S MANUAL MOTOROLA Bus Operation S0 S2 S4 S0 S2 CLK A31-A0 FC2-FC0 SIZ1-SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D0 HALT RESET READ RESET INTERNAL 512 CLOCKS RESUME NORMAL OPERATION Figure 7-65. Processor-Generated Reset Operation 7-108 MC68030 USER'S MANUAL MOTOROLA