FW802C-DB - Agere Systems, Inc. - Datasheet.Directory

Data Sheet, Rev. 1

October 2002

FW802C Low-Power PHY

IEEE

1394

A-2000

Two-Cable Transceiver/Arbiter Device



Distinguishing Features

■Compliant with

IEEE

St andard

1394

a-2000, IEE E

Standard for a High Performance Serial Bus

Ame ndm en t 1.

■Low-power consumption during powerdown or

microlow-power sleep mode.

■Supports extended BIAS_HANDSHAKE time for

enhanced interoperabi lity with ca mcorders.

■While unpowered and connected to the bus, the

device will not drive TPBIAS on a connected port

even if receiving incoming b i as voltage on th at port.

■Does not require external filter capacitors for PLL.

■Does not require a separate 5 V supply for 5 V link

controller interope rability.

■Interoperable across

1394

 cable with

1394

physi-

cal layers (PHY) using 5 V supplies.

■Interoperable with

1394

link-layer controllers using

5 V supplies.

■

1394

a-2000 compliant common-mode noise filter

on incoming TPBIAS.

■Powerdown features to conserve energy in battery-

powered applications include:

— Device powerdown pin.

— Link interface disable using LPS.

— Inactive ports powerdown.

— Automatic microlow-power sleep mode during

suspend.

■Interface to link-layer controller supports Annex J

electrical isolation as well as bus-keeper isolation.

Features

■Provides two compliant cable ports at 100 Mbits/s,

200 Mbits/s, and 400 Mbits/s.

■Supp or t s OHC I re quirements .

■Supports arbitrated short bus reset to improve

utilization of the bus.

■Suppor ts ack-accel erated ar bitrat io n and fly- by con-

catenation.

■Supports connection debounce.

■Supports multispeed packet concatenation.

■Supports PHY pinging and remote PHY access

packets.

■Supports full suspend/resume.

■Supports PHY-link interface initialization and reset.

■Supports

1394

a-2000 register set.

■Supports LPS/link-on as a part of PHY-link inter-

face.

■Supports provisions of

IEEE

1394

-1995

Standard

for a High Performance Serial Bus

■Fully interoperable with

FireWire

® implementation

IEEE

1394

-1995.

■Reports cable power fail interrupt when voltage at

CPS pin falls below 7.5 V.

■Separate cable bias and driver termination voltage

supply for each port.

■Meets Intel®

Mobile Power Guideline 2000

Other Features

■48-pin TQFP package.

■Sing le 3.3 V supply operation.

■Data interface to link-layer contro ller provided

through 2/4/8 parallel lines at 50 Mbits/s.

■25 MHz crystal oscillator and PLL provide transmit/

receive data at 100 Mbits/s, 200 Mbits/s, and

400 Mbits/s , and link-l ayer contro ller clock at

50 MHz.

■Node power-class information signaling for system

power management.

■Multip le separat e package si gna l s pr ovide d for ana-

log and digital supplies and grounds.

22 Agere Systems Inc.

Data Sheet, Rev. 1

October 2002

Two-Cable Transceiver/Arbit er Devi ce

FW802C Low-Power PHY

IEEE

1394A-2000

Table of Contents

Contents Page

Distinguishing Features ............................................................................................................................................1

Features ...................................................................................................................................................................1

Other Features .........................................................................................................................................................1

Description ...... ............. ............ ............. ............. ............. ............. ............. ...... ............. ....... ............. ............. ............ 3

Signal Information .....................................................................................................................................................6

Application Information ...........................................................................................................................................10

1394

Application Support Contact Information .......................................................................................................11

Crystal Selection Considerations ............................................................................................................................11

Load Capacitance ............................................................................................................................................12

Board Layout ....................................................................................................................................................12

Absolute Maximum Ratings ....................................................................................................................................12

Electrical Characteristics ........................................................................................................................................13

Timing Characteristics ............................................................................................................................................16

Timing Waveforms ..................................................................................................................................................17

Internal Register Configuration ...............................................................................................................................18

Outline Diagrams ....................................................................................................................................................23

48-Pin TQFP .. ....... ...... ...... ....... ...... ....... ...... ....... ...... .................... ...... ...... .................... ...... ....... ...... ....... ..........23

Ordering Information ...............................................................................................................................................23

List of Figures

Figures Page

Figure 1. Block Diagram ........................................................................................................................................5

Figure 2. Pin Assignments .....................................................................................................................................6

Figure 3. Typical External Component Connections ...........................................................................................10

Figure 4. Typical Port Termination Network ........................................................................................................11

Figure 5. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms ..........................................................17

Figure 6. Dn, CTLn Output Delay Relative to SYSCLK Waveforms ....................................................................17

List of Tables

Tables Page

Table 1. Signal Descriptions...................................................................................................................................7

Table 2. Absolute Maximum Ratings....................................................................................................................12

Table 3. Analog Characteristics............................................................................................................................13

Table 4. Driver Characteristics.............................................................................................................................14

Table 5. Device Characteristics............................................................................................................................15

Table 6. Switching Characteristics .......................................................................................................................16

Table 7. Clock Characteristics .............................................................................................................................16

Table 8. PHY Register Map for the Cable Environment ......................................................................................18

Table 9. PHY Register Fields for the Cable Environment ....................................................................................18

Table 10. PHY Register Page 0: Port Status Page .............................................................................................20

Table 11. PHY Register Port Status Page Fields ................................................................................................21

Table 12. PHY Register Page 1: Vendor Identification Page ..............................................................................22

Table 13. PHY Register Vendor Identification Page Fields .................................................................................22

Data Sheet, Rev. 1 FW802C Low-Power PHY

IEEE

1394A-2000

August 2002 Two-Cable Transceiver/Arbiter Device

Agere Systems Inc. 3

Description

The Agere Systems Inc. FW802C device provides the

analog physical layer functions needed to implement a

two-port node in a cable-based

IEEE

1394

-1995 and

IEEE

1394

a-2000 network.

Each cable port incorporates two differential line trans-

ceivers. The transceivers include cir cuitry to monitor

the line conditions as needed for determining connec-

tion status, for initialization and arbitration, and for

packet reception and transmission. The PHY is

designed to interface with a link-layer controller (LLC).

The PHY requires either an external 24.576 MHz

crystal or crystal oscillator. The internal oscillator

drives an internal phase-locked loop (PLL), which

generates the required 400 MHz reference signal. The

400 MHz reference signal is internally divided to

provide the 49.152 MHz, 98.304 MHz, and

196.608 MHz clock signals that control transmission of

the outbound encoded strobe and data information.

The 49.152 MHz clock signal is also supplied to the

associated LLC for synchronization of the two chips

and is used for resynchronization of the received data.

The powerdown function, when enabled by the PD

signal high, stops operation of the PLL and disables all

circuitry except the cable-not-active signal circuitry.

The PHY supports an isolation barrier between itself

and its LLC. When /ISO is tied high, the link interface

outputs behave normally. When /ISO is tied low,

internal differentiating logic is enabled, and the outputs

become short pulses, which can be coupled through a

capacitor or transformer as described in the

IEEE

1394

-1995 Annex J. To operate with bus-keeper

isolation, the /ISO pin of the FW802C must be tied

high.

Data bits to be transmitted through the cable ports are

received from the LLC on two, four, or eight data lines

(D[0:7]), and are latched internally in the PHY in

synchronization with the 49.152 MHz system clock.

These bits are combined serially, encoded, and

transmitted at 98.304 Mbits/s, 196.608 Mbits/s, or

393.216 Mbits/s as the outbound data-strobe

information stream. During transmission, the encoded

data information is transmitted differentially on the TPA

and TPB cable pair(s).

During packet reception, the TPA and TPB

transmitters of the receiving cable port are disabled,

and the receivers for that port are enabled. The

encoded data information is received on the TPA and

TPB cable pair. The received data-strobe information

is decoded to recover the receive clock signal and the

serial data bits. The serial data bits are split into two,

four, or eight parallel streams, resynchronized to the

local system clock, and sent to the associated LLC.

The received data is also transmitted (repeated) out of

the other active (connected) cable ports.

Both the TPA and TPB cable interfaces incorporate

differential comparators to monitor the line states

during initialization and arbitration. The outputs of

these comparators are used by the internal logic to

determine the arbitration status. The TPA channel

monitors the incoming cable common-mode voltage.

The value of this common-mode voltage is used during

arbitration to set the speed of the next packet

transmission. In addition, the TPB channel monitors

the incoming cable common-mode voltage for the

presence of the remotely supplied twisted-pair bias

voltage. This monitor is called bias-detect.

The TPBIAS circuit monitors the value of incoming

TPA pair common-mode voltage when local TPBIAS is

inactive. Because this circuit has an internal current

source and the connected node has a current sink, the

monitored value indicates the cable connection status.

This monitor is called connect-detect.

Both the TPB bias-detect monitor and TPBIAS

connect-detect monitor are used in suspend/resume

signaling and cable connection detection.

The PHY provides a 1.86 V nominal bias voltage for

driver load termination. This bias voltage, when seen

through a cable by a remote receiver, indicates the

presence of an active connection. The value of this

bias voltage has been chosen to allow interoperability

between transceiver chips operating from 5 V or 3 V

nominal supplies. This bias voltage source should be

stabilized by using a n external filter capacitor of

approx im atel y 0.33 µF.

The transmitter circuitry, the receiver circuitry, and the

twisted-pair bias voltage circuity are all disabled with a

powerdown condition. The powerdown condition

occurs when the PD input is high. The port transmitter

circuitry, the receiver circuitry, and the TPBIAS output

are also disabled when the port is disabled,

suspended, or disconnected.

The line drivers in the PHY operate in a high-

impedance current mode and are designed to work

with external 112 Ω line-termination resistor networks.

One network is provided at each end of each twisted-

pair cable. Each network is composed of a pair of

series-connected 56 Ω resistors. The midpoint of the

pair of resistors that is directly connected to the

twisted-pair A (TPA) signals is connected to the PBIAS

voltage signal. The midpoint of the pair of

FW802C Low-Power PHY

IEEE

1394A-2000 Data Sheet, Rev. 1

Two-Cable Transceiver/Arbiter Device August 2002

4Agere Systems Inc.

Description (continued)

resistors that is directly connected to the twisted-pair B

(TPB) signals is coupled to ground through a parallel

RC network with recommended resistor and capacitor

values of 5 kΩ and 220 pF, respectively.

The value of the external resistors are specified to

meet the standard specifications when connected in

parallel with the internal receiver circuits.

The driver output current, along with other internal

operating currents, is set by an external resistor. This

resistor is connected between the R0 and R1 signals

and has a value of 2.49 kΩ ± 1%.

The FW802C supports suspend/resume as defined in

the

IEEE

1394

a-2000 specification. The suspend

mechanism allows an FW802C port to be put into a

suspended state. In this state, a port is unable to

transmit or receive data packets; however, it remains

capable of detecting connection status changes and

detecting incoming TPBias. When all ports of the

FW802C are suspended, all circuits except the bias

voltage reference generator and the bias detection

circuits are powered down, resulting in significant

power savings. The use of suspend/resume is

recommended.

The signal, C/LKON, as an input, indicates whether a

node is a contender for bus manager. When the

C/LKON signal is asserted, it means the node is a

contender for bus manager. When the signal is not

asserted, it means that the node is not a contender.

The C bit corresponds to bit 20 in the self-ID packet

(see Table 4-29 of the

IEEE

1394

-1995 standard for

additional details).

The power class bits of the self-ID packet do not have

a default value. These bits can be initialized and read/

written through the LLC using Figure 6-1 (PHY

IEEE 1394

a-2000 stan dard. S ee

Table 8 for the address space of the Pwr_class

A powerdown signal (PD) is provided to allow a

powerdown mode where most of the PHY circuits are

powered down to conserve energy in battery-powered

applications. The internal logic in FW802C is reset as

long as the powerdown signal is asserted. A cable

status signal, CNA, provides a high output when none

of the twis ted-pair cable ports are rece iving incoming

bias voltage. This output is not debounced. The CNA

output can be used to determine when to power the

PHY down or up. In the powerdown mode, all circuitry

is disabled except the CNA circuitry. It should be noted

that when the device is powered down, it does not act

in a repeater mode.

When the power supply of the PHY is removed while

the twisted-pair cables are connected, the PHY

transmitter and receiver circuitry has been designed to

present a high impedance to the cable in order to not

load the TPBIAS signal voltage on the other end of the

cable.

For reliable operation, the TPBn signals must be

terminated using the normal termination network

regardless of whether a cable is connected to a port or

not connected to a port. For those applications, when

FW802C is used with one of the ports not brought out

to a connector, those unused ports may be left

unconnected without normal termination. When a port

does not have a cable connected, internal connect-

detect circuitry will keep the port in a disconnected

state.

Note: All gap counts on all nodes of a

1394

bus must

be identical. This may be accomplished by using

PHY configuration packets (see Section 4.3.4.3

IEEE

1394

-1995 standard) or by using two

bus resets, which resets the gap counts to the

maximum level (3Fh).

The link power status (LPS) signal works with the

C/LKON signal to manage the LLC power usage of the

node. The LPS signal indicates that the LLC of the

node is powered up or powered down. If LPS is inac-

tive for more than 1.2 µs and less than 25 µs, PHY/l ink

interface is reset. If LPS is inactive for greater than

25 µs, the PHY will disable the PHY/link interface to

save power. FW802C continues its repeater function.

If the PHY then receives a link-on packet, the C/LKON

signal is activated to output a 6.114 MHz signal, which

can be used by the LLC to power itself up. Once the

LLC is powered up, the LPS signal communicates this

to the PHY and the PHY/link interface is enabled.

C/LKON signal is turned off when LPS is active or

when a bus reset occurs, provided the interrupt that

caused C/LKON is not present.

When the PHY/link interface is in the d isabled state,

the FW802C will automatically enter a low-power

mode, if all ports are inactive (disconnected, disabled,

or suspended). In this low-power mode, the FW802C

disables its PLL and also disables parts of reference

circuitry depending on the state of the ports (some ref-

erence circuitry must remain active in order to detect

incoming TP bias). The lowest power consumption (the

microlow-power sleep mode) is attained when all ports

are either disconnected or disabled with the ports inter-

rupt enable bit cleared. The FW802C will exit the low-

power mode when the LPS input is asserted high or

when a port event occurs that requires the FW802C

Data Sheet, Rev. 1 FW802C Low-Power PHY

IEEE

1394A-2000

August 2002 Two-Cable Transceiver/Arbiter Device

Agere Systems Inc. 5

Description (continued)

to become active in order to respond to the event or to

notify the LLC of the event (e.g., incoming bias or dis-

connection is detected on a suspended port, a new

connection is detected on a nondisabled port, etc.).

The SYSCLK output will become active (and the PHY/

link interface will be initialized and become operative)

within 3 ms after LPS is asserted high, when the

FW802C is in the low-power mode.

Two of the signals are used to set up various test

conditions used in manufacturing. These signals (SE

and SM) should be connected to VSS for normal

operation.

5-5459.f (F)

Figure 1. Block Diagram

LINK

INTERFACE

I/O

RECE IV ED

DATA

DECODER/

ARBITRATION

AND

CONTROL

RETIMER

STATE

MACHINE

LOGIC

BIAS

VOLTAGE

AND

CURRENT

GENERATOR

CABLE PORT 1

OSCILLATOR,

PLL SY STEM,

AND

CLOCK

GENERATOR

TRANSMIT

DATA

ENCODER

CABLE PORT 0

TPA0+

TPA0–

TPB0+

TPB0–

TPBIAS0

TPBIAS1

TPA1+

TPA1–

TPB1+

TPB1–

CPS

LPS

/ISO

CNA

SYSCLK

LREQ

CTL0

CTL1

C/LKON

/RESET CRYSTAL

66 Agere Systems Inc.

Data Sheet, Rev. 1

October 2002

Two-Cable Transceiver/Arbit er Devi ce

FW802C Low-Power PHY

IEEE

1394A-2000

Signal Information

Note: Active-low signals are indicated by “/” at the beginning of signal names, within this document.

5-6236.b (F)

Figure 2. Pin Assignments

7AGERE FW802C

VSS

VDD

CTL1

CTL0

TPB0–

TPB0+

TPA0–

TPA0+

TPBIAS0

TPB1–

TPB1+

TPA1–

TPA1+

TPBIAS1

VSSA

VDDA

VDD

VSS

PLLVDD

/RESET

SYSCLK

VSS

LREQ

PLLVSS

CNA

LPS

VSS

VDD

C/LKON

/ISO

CPS

VDDA

VSSA

PIN #1 IDENTIFIER

Agere Systems Inc. 7

Data Sheet, Rev. 1

October 2002 Two-Cable Transceiver/Arbiter Device

FW802C Low-Power PHY

IEEE

1394A-2000

Signal Information (continued)

Table 1. Signal Descriptions

Pin Signal*Type Name/Description

17 C/LKON I/O Bus Manager Capable Input and Link-On Output. On hardware reset,

this pin is used to set the default value of the contender status indicated

during self-ID. The bit value programming is done by tying the signal

through a 10 kΩ resistor to VDD (high, bus manager capable) or to GND

(low, not bus manager capable). Using either the pull-up or pull-down

resistor allows the link-on output to override the input value when neces-

sary.

After hardware reset, this pin is set as an output. If the LPS is inactive,

C/LKON indicates one of the following events by asserting a 6.114 MHz

signal.

1. FW802C receives a link-on packet addressed to this node.

2. Port_event register bit is 1.

3. Any of the Timeout, Pwr_Fail, or Loop register bits are 1 and the

Resume_int register bit is also 1. Once activated, the C/LKON output

will continue active until the LPS becomes active. The PHY also deas-

serts the C/LKON output when a bus reset occurs, if the C/LKON is

active due solely to the reception of a link-on packet.

Note: If an interrupt condition exists that would otherwise cause the

C/LKON output to be activated if the LPS were inactive, the

C/LKON output will be activated when the LPS subsequently

becomes inactive.

13 CNA O Cable-Not-Active Output. CNA is asserted high when none of the PHY

ports are receiving an incoming bias voltage. This circuit remains active

during the powerdown mode.

20 CPS I Cable Power Status. CPS is normally connected to the cable power

through a 400 kΩ resistor. This circuit drives an internal comparator that

detects the presence of cable power . This information is maintained in one

internal register and is available to the LLC by way of a register read (see

Table 8, Register 0).

1 CTL0 I/O Control I/O. The CTLn signals are bidirectional communications control

signals between the PHY and the LLC. These signals control the passage

of information between the two devices. Bus-keeper circuitry is built into

these terminal s.

2CTL1

3, 4, 6,

7, 8, 9,

10, 11

D[0:7] I/O Data I/O. The Dn signals are bidirectional and pass data between the

PHY and the LLC. Bus-keeper circuitry is built into these terminals.

19 /ISO I Link Interface Isolation Disable Input (Active-Low). /ISO controls the

operation of an internal pulse differentiating function used on the

PHY-LLC interface signals, CTLn and Dn, when they operate as outputs.

When /ISO is asserted low, the isolation barrier is implemented between

PHY and its LLC (as described in Annex J of

IEEE

1394

-1995).

/ISO is normally tied high to disable isolation differentiation. Bus-keepers

are enabled when /ISO is high (inactive) on CTL, D, and LREQ. When

/ISO is low (active), the bus-keepers are disabled. Please refer to Agere’s

application note AP98-074CMPR for more information on isolation.

* Active-low signals are indicated by “/” at the beginning of signal names, within this document.

88 Agere Systems Inc.

Data Sheet, Rev. 1

October 2002

Two-Cable Transceiver/Arbit er Devi ce

FW802C Low-Power PHY

IEEE

1394A-2000

Signal Information (continued)

Table 1. Signal Descriptions (continued)

Pin Signal*Type Name/Description

14 LPS I Link Power Status. LPS is connected to either the VDD supplying the

LLC or to a pulsed output that is active when the LLC is powered for the

purpose of monitoring the LLC power status. If LPS is inactive for more

than 1.2 µs and less than 25 µs, interface is reset. If LPS is inactive for

greater than 25 µs, the PHY will disable the PHY/Link interface to save

power. FW802C continues its repeater function.

48 LREQ I Link Request. LREQ is an output from the LLC that requests the PHY to

perform some service. Bus-keeper circuitry is built into this terminal.

18 PD I Powerdown. When asserted high, PD turns off all internal circuitry except

the bias-detect circuits that drive the CNA signal. Internal FW802C logic is

kept in the reset state as long as PD is asserted. PD terminal is provided

for backward compatibility. It is recommended that the FW802C be

allowed to manage its own power consumption using suspend/resume in

conjunction with LPS. C/LKON features are defined in

1394

a-2000.

41 PLLVDD —Power for PLL Circuit. PLLVDD supplies power to the PLL circuitry

port ion of the device.

42 PLLVSS —Ground for PLL Circuit. PLLVSS is tied to a low-impedance ground

plane.

37 R0 I Current Setting Resistor. An internal reference voltage is applied to a

resistor connected between R0 and R1 to set the operating current and

the cable driver output current. A low temperature-coefficient resistor

(TCR) with a value of 2.49 kΩ ± 1% should be used to meet the

IEEE

1394

-1995 standard requirements for output voltage limits.

38 R1

45 /RESET I Reset (Active-Low). When /RESET is asserted low (active), the FW802C

is reset. An internal pull-up resistor, which is connected to VDD, is

provided, so only an external delay capacitor is required. This input is a

standard logic buffer and can also be driven by an open-drain logic output

buffer.

21 SE I Test Mode Control. SE is used during the manufacturing test and should

be tied to VSS.

22 SM I Test Mode Control. SM is used during the manufacturing test and should

be tied to VSS.

46 SYSCLK O System Clock. SYSCLK provides a 49.152 MHz clock signal, which is

synchronized with the data transfers to the LLC.

28 TPA0+ Analog I/O Portn, Port Cable Pa ir A. TPAn is the port A connection to the twisted-

pair cable. Board traces from each pair of positive and negative differen-

tial signal pins should be kept matched and as short as possible to the

external load resistors and to the cable connector.

34 TPA1+

27 TPA0−Analog I/O Portn, Port Cable Pa ir A. TPAn is the port A connection to the twisted-

pair cable. Board traces from each pair of positive and negative differen-

tial signal pins should be kept matched and as short as possible to the

external load resistors and to the cable connector.

33 TPA1−

26 TPB0+ A nalog I/O Portn, Port C able Pair B. TPBn is the port B connection to the twisted-

pair cable. Board traces from each pair of positive and negative differen-

tial signal pins should be kept matched and as short as possible to the

external load resistors and to the cable connector.

32 TPB1+

* Active-low signals are indicated by “/” at the beginning of signal names, within this document.

Agere Systems Inc. 9

Data Sheet, Rev. 1

October 2002 Two-Cable Transceiver/Arbiter Device

FW802C Low-Power PHY

IEEE

1394A-2000

25 TPB0−Analog I/O Portn, Port Cable Pair B. TPBn is the port B connection to the twisted-

pair cable. Board traces from each pair of positive and negative differen-

tial signal pins should be kept matched and as short as possible to the

external load resistors and to the cable connector.

31 TPB1−

29 TPBIAS0 Analog I/O Portn, Twisted-Pair Bias. TPBIAS provides the 1.86 V nominal bias

voltage needed for proper operation of the twisted-pair cable drivers and

receivers and for sending a valid cable connection signal to the remote

nodes.

35 TPBIAS1

5, 16, 39 VDD —Digital Power. VDD supplies power to the digital portion of the device.

23, 30 VDDA —Analog Circuit Power. VDDA supplies power to the analog portion of the

device.

12, 15, 40,

47 VSS —Digital Ground. All VSS signals should be tied to the low-impedance

ground plane.

24, 36 VSSA —Analog Circuit Ground. All VSSA signals should be tied together to a low-

impedance ground plane.

43 XI — Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel resonant

fundamental mode crystal. Although, when a 24.576 MHz clock source is

used, it can be connected to XI with XO left unconnected. The optimum

values for the external shunt capacitors are dependent on the specifica-

tions of the crystal used. For more details, see Crystal Selection Consider-

ations in the Application Information section.

44 XO

Signal Information (continued)

Table 1. Signal Descriptions (continued)

Pin Signal*Type Name/Description

* Active-low signals are indicated by “/” at the beginning of signal names, within this document.

1010 Agere Systems Inc.

Data Sheet, Rev. 1

October 2002

Two-Cable Transceiver/Arbit er Devi ce

FW802C Low-Power PHY

IEEE

1394A-2000

Application Information

5-6767 (F)

* See Figure 4 for typical port termination network.

Figure 3. Typical External Component Connections

7AGERE FW802C

VSS

VDD

CTL1

CTL0

TPB0–

TPB0+

TPA0–

TPA0+

TPBIAS0

TPB1–

TPB1+

TPA1–

TPA1+

TPBIAS1

VSSA

VDDA

VDD

VSS

PLLVDD

/RESET

SYSCLK

VSS

LREQ

PLLVSS

CNA

LPS

VSS

VDD

C/LKON

/ISO

CPS

VDDA

VSSA

PIN #1 IDENTIFIER

24.576 MHz

0.1 µF2.49 kΩ

510 kΩ

PORT 1*

PORT 0*

CABLE

POWER

400 kΩ

Data Sheet, Rev. 1 FW802C Low-Power PHY

IEEE

1394A-2000

August 2002 Two-Cable Transceiver/Arbiter Device

Agere Systems Inc. 11

Application Information (continued)

5-6930 (F)

Figure 4. Typical Port Termination Network

1394

Application Support Contact Information

E-mail: support1394@agere.com

Crystal Selection Considerations

The FW802C is designed to use an external 24.576 MHz crystal connected between the XI and XO terminals to

provide the reference for an internal oscillator circuit.

IEEE

1394

a-2000 standard requires that FW802C have less

than ±100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. To achieve this,

it is recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used.

The total frequency variation must be kept below ±100 ppm from nominal with some allowance for error introduced

by board and device variations. Trade offs between frequency tolerance and stability may be made as long as the

total frequency variation is less than ±100 ppm.

TPBIAS1

TPA1+

TPA1–

TPB1+

TPB1–

TPBIAS0

TPA0+

TPA0–

TPB0+

TPB0–

TPBIAS1

56 Ω 56 Ω

56 Ω56 Ω

5 kΩ

220 pF

0.33 µF

IEEE

1394

-1995 STANDARD

CONNECTOR

USE SAME PORT TERM INATION NETW ORK AS ILLUSTRATED BELOW.

VGVP

CABLE

POWER

1212 Agere Systems Inc.

Data Sheet, Rev. 1

October 2002

Two-Cable Transceiver/Arbit er Devi ce

FW802C Low-Power PHY

IEEE

1394A-2000

Crystal Selection Considerations (continued)

Load Capacitance

The frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant

mode crystal circuits. Total load capacitance (CL) is a function of not only the discrete load capacitors, but also

capacitances from the FW802C board traces and capacitances of the other FW802C connected components.

The values for load capacitors (CA and CB) should be calculated using this formula:

CA = CB = (CL – Cstray) × 2

Where:

CL = load capacitance specified by the crystal manufacturer

Cstray = capacitance of the board and the FW802C, typically 2—3 pF

Board Layout

The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency and minimizing

noise introduced into the FW802C PLL. The crystal and two load capacitors should be considered as a unit during

layout. They should be placed as close as possible to one another, while minimizing the loop area created by the

combination of the three components. Minimizing the loop area minimizes the effect of the resonant current that

flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possi-

ble to the PHY XI and XO terminals to minimize trace lengths. Vias should not be used to route the XI and XO sig-

nals.

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

Table 2. Absolute Maximum Ratings

* Except for 5 V tolerant I/O (CTL0, CTL1, D0—D7, and LREQ) where VI max = 5.5 V.

Parameter Symbol Min Max Unit

Supply Voltage Range VDD 3.0 3.6 V

Input Voltage Range* VI−0.5 VDD + 0.5 V

Output Voltage Range at Any Output VO−0.5 VDD + 0.5 V

Operating Free Air Temperature TA070

°C

Storage Temperature Range Tstg –65 150 °C

Agere Systems Inc. 13

Data Sheet, Rev. 1

October 2002 Two-Cable Transceiver/Arbiter Device

FW802C Low-Power PHY

IEEE

1394A-2000

Electrical Characteristics

Table 3. Analog Characteristics

Parameter Test Conditions Symbol Min Typ Max Unit

Supply Voltage Source power node VDD—SP 3.0 3.3 3.6 V

Differential Input Voltage Cable inputs, 100 Mbits/s operation VID—100 142 — 260 mV

Cable inputs, 200 Mbits/s operation VID—200 132 — 260 mV

Cable inputs, 400 Mbits/s operation VID—400 100 — 260 mV

Cable inputs, during arbitration VID—ARB 168 — 265 mV

Common-mode Voltage

Source Power Mode TPB cable inputs,

speed signaling off VCM 1.165 — 2.515 V

TPB cable inputs,

S100 speed signaling on VCM—SP—100 1.165 —2.515 V

TPB cable inputs,

S200 speed signaling on VCM—SP—200 0.935 —2.515 V

TPB cable inputs,

S400 speed signaling on VCM—SP—400 0.532 —2.515 V

Common-mode Voltage

Nonsource Power Mode*

* For a node that does not source power (see Section 4.2.2.2 in

IEEE

1394

-1995 Standard).

TPB cable inputs,

speed signa li ng off VCM 1.165 — 2.015 V

TPB cable inputs,

S100 speed signaling on VCM—NSP—100 1.165 —2.015 V

TPB cable inputs,

S200 speed signaling on VCM—NSP—200 0.935 —2.015 V

TPB cable inputs,

S400 speed signaling on VCM—NSP—400 0.532 —2.015 V

Receive Input Jitter TPA, TPB cable inputs,

100 Mbits/s operation ———1.08ns

TPA, TPB cable inputs,

200 Mbits/s operation ———0.5ns

TPA, TPB cable inputs,

400 Mbits/s operation ———0.315ns

Receive Input Skew Between TPA and TPB cable inputs,

100 Mbits/s operation ———0.8ns

Between TPA and TPB cable inputs,

200 Mbits/s operation ———0.55ns

Between TPA and TPB cable inputs,

400 Mbits/s operation ———0.5ns

Positive Arbitration

Comparator Input

Threshold Voltage

—V

TH+89—168mV

Negative Arbitration

Comparator Input

Threshold Voltage

—V

TH−–168 — –89 mV

Speed Signal Input

Threshold Voltage 200 Mbits/s VTH—S200 45 — 139 mV

400 Mbits/s VTH—S400 266 — 445 mV

Output Current TPBIAS outputs IO–5 — 2.5 mA

TPBIAS Output Voltage At rated I/O current VO1.665 — 2.015 V

Current Source for

Connect Detect Circuit —I

CD ——76µA

1414 Agere Systems Inc.

Data Sheet, Rev. 1

October 2002

Two-Cable Transceiver/Arbit er Devi ce

FW802C Low-Power PHY

IEEE

1394A-2000

Electrical Characteristics (continued)

Table 4. Driver Characteristics

Parameter Test Conditions Symbol Min Typ Max Unit

Differential Output Voltage 56 Ω load VOD 172 —265mV

Off-state Common-mode Voltage Drivers disabled VOFF ——20mV

Driver Differential Current,

TPA+, TPA−, TPB+, TPB−Driver enabled,

speed signaling off*

* Limits are defined as the algebraic sum of TPA+ and TPA− driver currents. Limits also apply to T PB+ and TPB− as the algebraic sum of dri ver

currents.

† Limits are defined as the absolute limit of each of TPB+ and TPB− driver currents.

IDIFF −1.05 —1.05mA

Common-mode Speed Signaling

Current, TPB+, TPB−200 Mbits/s speed

signaling enabled†ISP −2.53 —−4.84 mA

400 Mbits/s speed

signaling enabled†ISP −8.1 —−12.4 mA

Agere Systems Inc. 15

Data Sheet, Rev. 1

October 2002 Two-Cable Transceiver/Arbiter Device

FW802C Low-Power PHY

IEEE

1394A-2000

Electrical Characteristics (continued)

Table 5. Device Characteristics

* Device is capable of both differentiated and undifferentiated operation.

Parameter Test Conditions Symbol Min Typ Max Unit

Supply Current:

One Port Active

All Ports Active

Microlow-Power Sleep Mode

PD = 1

VDD = 3.3 V IDD

IDD

—

µA

High-level Output Voltage IOH max, VDD = min VOH VDD – 0.4 — — V

Low-level Output Voltage IOL min, VDD = max VOL ——0.4V

High-level Input Voltage CMOS inputs VIH 0.7VDD —— V

Low-level Input Voltage CMOS inputs VIL — — 0.2VDD V

Pull-up Current,

/RESET Input VI = 0 V II11 — 32 µA

Powerup Reset Time,

/RESET Input VI = 0 V — 2 — — ms

Rising Input Threshold Voltage

/RESET Input —VI

RST 1.1 — 1.4 V

Output Current SYSCLK IOL/IOH

@ TTL –16 — 16 mA

Control, data IOL/IOH

@ CMOS –12 — 12 mA

CNA IOL/IOH –16 — 16 mA

C/LKON IOL/IOH –2 — 2 mA

Input Current,

LREQ, LPS, PD, SE, SM,

PC[0:2] Inputs

VI = VDD or 0 V II——°

±1µA

Off-state Output Current,

CTL[0:1], D[0:7], C/LKON I/Os VO = VDD or 0 V IOZ ——°

±5µA

Power S tatus Input Threshold

Voltage, CPS Input 400 kΩ resistor VTH 7.5 — 8.5 V

Rising Input Threshold Voltage*,

LREQ, CTLn, Dn —V

IT+VDD/2 + 0.3 — VDD/2 + 0.8 V

Falling Input Threshold Voltage*,

LREQ, CTLn, Dn —V

IT−VDD/2 – 0.8 — VDD/2 – 0.3 V

Bus Holding Current,

LREQ, CTLn, Dn VI = 1/2(VDD) — 250 — 550 µA

Rising Input Threshold Voltage

LPS —V

LIH — — 0.24VDD + 1 V

Falling Input Threshold Voltage

LPS —V

LIL 0.24VDD + 0.2 — — V

1616 Agere Systems Inc.

Data Sheet, Rev. 1

October 2002

Two-Cable Transceiver/Arbit er Devi ce

FW802C Low-Power PHY

IEEE

1394A-2000

Timing Characteristics

Table 6. S witching Characteristics

Table 7. Clock Characteristics

Symbol Parameter Measured Test Conditions Min Typ Max Unit

— Jitter, Transmit TPA, TPB — — — 0.15 ns

— Transmit Skew Between

TPA and TPB ———

±0.1 ns

trRise Time, Transmit (TPA/TPB) 10% to 90% RI = 56 Ω,

CI = 10 pF ——1.2ns

tfFall Time, Transmit (TPA/TPB) 90% to 10% RI = 56 Ω,

CI = 10 pF ——1.2ns

tsu Setup Time,

Dn, CTLn, LREQ↑↓ to SYSCLK↑50% to 50% See Figure 5. 6 — — ns

thHold Ti me ,

Dn, CTLn, LREQ↑↓ from SYSCLK↑50% to 50% See Figure 5. 0 — — ns

tdDelay Time,

SYSCLK↑ to Dn, CTLn↑↓ 50% to 50% See Figure 6. 1 — 6 ns

Parameter Symbol Min Typ Max Unit

External Clock Source Frequency f 24.5735 24.5760 24.5785 MHz

Agere Systems Inc. 17

Data Sheet, Rev. 1

October 2002 Two-Cable Transceiver/Arbiter Device

FW802C Low-Power PHY

IEEE

1394A-2000

Timing Waveforms

5-6017.a (F)

Figure 5. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms

5-6018.a (F)

Figure 6. Dn, CTLn Output Delay Relative to SYSCLK Waveforms

SYSCLK

Dn, CTLn, LREQ

tsu th

SYSCLK

Dn, CTLn

1818 Agere Systems Inc.

Data Sheet, Rev. 1

October 2002

Two-Cable Transceiver/Arbit er Devi ce

FW802C Low-Power PHY

IEEE

1394A-2000

Internal Register Configuration

The PHY register map is shown below in Table 8.

Table 8. PHY Register Map for the Cable Environment

The meaning of the register fields within the PHY register map are defined by Table 9 below. Power reset values

not specified are resolved by the operation of the PHY state machines subsequent to a power reset.

Table 9. PHY Register Fields for the Cable Environment

Address Contents

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

00002Physical_ID R PS

00012RHB IBR Gap_count

00102Extended (7) XXXXX Total_ports

00112Max_speed XXXXX Delay

01002LCtrl Contender Jitter Pwr_class

01012Resume_int ISBR Loop Pwr_fail Timeout Port_event Enab_accel Enab_multi

01102XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX

01112Page_select XXXXX Port_select

10002Regi ste r 0 Page_select

11112Register 7 Page_select

REQUIRED XXXXX RESERVED

Field Size Type Power Reset

Value Description

Physical_ID 6 r 000000 The address of this node determined during self-identification. A

value of 63 indicates a malconfigured bus; the link will not transmit

any packets.

R 1 r 0 When set to one, indicates that this node is the root.

PS 1 r — Cable power active.

RHB 1 rw 0 Root hold-off bit. When set to one, the force_root variable is TRUE,

which instructs the PHY to attempt to become the root during the

next tree identify process.

IBR 1 rw 0 Initiate bus reset. When set to one, instructs the PHY to set ibr

TRUE and reset_time to RESET_TIME. These values, in turn,

cause the PHY to initiate a bus reset without arbitration; the reset

signal is asserted for 166 µs. This bit is self-clearing.

Gap_count 6 rw 3F16 Used to configure the arbitration timer setting in order to optimize

gap times according to the topology of the bus. See Section 4.3.6

IEEE

Standard

1394

-1995 for the encoding of this field.

Extended 3 r 7 This field has a constant value of seven, which indicates the

extended PHY register map.

Agere Systems Inc. 19

Data Sheet, Rev. 1

October 2002 Two-Cable Transceiver/Arbiter Device

FW802C Low-Power PHY

IEEE

1394A-2000

Internal Register Configuration (continued)

Table 9. PHY Register Fields for the Cable Environment (continued)

Field Size Type Power Reset Value Description

Total_ports 4 r 2 The number of ports implemented by this PHY. This count

reflects the number.

Max_speed 3 r 0102Indicates the speed(s) this PHY supports:

0002 = 98.304 Mbits/s

0012 = 98.304 and 196.608 Mbits/s

0102 = 98.304, 196.608, and 393.216 Mbits/s

0112 = 98.304, 196.608, 393.216, and 786.43 Mbits/s

1002 = 98.304, 196.608, 393.216, 786.432, and

1,572.864 Mbits/s

1012 = 98.304, 196.608, 393.216, 786.432, 1,572.864, and

3,145.728 Mbits/s

All other values are reserved for future definition.

Delay 4 r 0000 W orst-case repeater delay, expressed as 144 + (delay * 20) ns.

LCtrl 1 rw 1 Link Active. Cleared or set by software to control the value of

the L bit transmitted in the node’s self-ID packet 0, which will be

the logical AND of this bit and LPS active.

Contender 1 rw See description. Cleared or set by software to control the value of the C bit

transmitted in the self-ID packet. Powerup reset value is set by

C/LKON pin.

Jitter 3 r 000 The difference between the fastest and slowest repeater data

delay, expressed as (jitter + 1) * 20 ns.

Pwr_class 3 rw See description. Power Class. Controls the value of the pwr field transmitted in

the self-ID packet. See Section 4.3.4.1 of

IEEE

Standard

1394

1995 for the encoding of this field.

Resume_int 1 rw 0 Resume Interrupt Enable. When set to one, the PHY will set

Port_event to one if resume operations commence for any port.

ISBR 1 rw 0 Initiate Short (Arbitrated) Bus Reset. A write of one to this bit

instructs the PHY to set ISBR true and reset_time to

SHORT_RESET_TIME. These values, in turn, cause the PHY

to arbitrate and issue a short bus reset. This bit is self-clearing.

Loop 1 rw 0 Loop Detect. A write of one to this bit clears it to zero.

Pwr_fail 1 rw 1 Cable Powe r Failure Detect . Set to one when the PS bit

changes from one to zero. A write of one to this bit clears it to

zero.

Timeout 1 rw 0 Arbitration State Machine Time-out. A write of one to this bit

clears it to zero (see MAX_ARB_STATE_TIME).

Port_event 1 rw 0 Port Event Detect. The PHY sets this bit to one if any of con-

nected, bias, disabled, or fault change for a port whose

Int_enable bit is one. The PHY also sets this bit to one if

resume operations commence for any port and Resume_int is

one. A write of one to this bit clears it to zero.

2020 Agere Systems Inc.

Data Sheet, Rev. 1

October 2002

Two-Cable Transceiver/Arbit er Devi ce

FW802C Low-Power PHY

IEEE

1394A-2000

Internal Register Configuration (continued)

Table 9. PHY Register Fields for the Cable Environment (continued)

The port status page is used to access configuration and status information for each of the PHY’s ports. The port is

selected by writing zero to Page_select and the desired port number to Port_select in the PHY register at address

01112. The format of the port status page is illustrated by Table 10 below; reserved fields are shown shaded. The

meanings of the register fields with the port status page are defined by Table 11.

Table 10. PHY Register Page 0: Port Status Page

Field Size Type Power Reset

Value Description

Enab_accel 1 rw 0 Enable Arbitration Acceleration. When set to one, the PHY will

use the enhancements specified in clause 8.11 of

1394

a-2000

sp ecification. PHY behavior is unspecified if the value of

Enab_accel is changed while a bus request is pending.

Enab_multi 1 rw 0 Enable Multispeed Packet Concatenation. When set to one, the

link will signal the speed of all packets to the PHY.

Page_select 3 rw 000 Selects which of eight possible PHY register pages are accessible

through the window at PHY register addresses 10002 through

11112, inc l usiv e.

Port_select 4 rw 000 If the page selected by Page_select presents per-port information,

this field selects which port’s registers are accessible through the

window at PHY register addresses 10002 through 111 12, inclusive.

Ports are numbered monotonically starting at zero, p0.

Address Contents

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

10002AStat BStat Child Connected Bias Disabled

10012Negotiated_speed Int_enable Fault XXXXX XXXXX XXXXX

10102XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX

10112XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX

11002XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX

11012XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX

11102XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX

11112XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX

REQUIRED XXXXX RESERVED

Agere Systems Inc. 21

Data Sheet, Rev. 1

October 2002 Two-Cable Transceiver/Arbiter Device

FW802C Low-Power PHY

IEEE

1394A-2000

Internal Register Configuration (continued)

The meaning of the register fields with the port status page are defined by Table 11 below.

Table 11. PHY Register Port Status Page Fields

Field Size Type Power Reset

Value Description

AStat 2 r — TPA line state for the port:

002 = invalid

012 = 1

102 = 0

112 = Z

BStat 2 r — TPB line state for the port (same encoding as AStat).

Child 1 r 0 If equal to one, the port is a child; otherwise, a parent. The

meaning of this bit is undefined from the time a bus reset is

detected until the PHY transitions to state T1: Child Hand-

shake during the tree identify process (see Section 4.4.2.2 in

IEEE

Standard

1394

-1995).

Connected 1 r 0 If equal to one, the port is connected.

Bias 1 r 0 If equal to one, incoming TPBIAS is detected.

Disabled 1 rw 0 If equal to one, the port is disabled.

Negotiated_speed 3 r 000 Indicates the maximum speed negotiated between this PHY

port and its immediately connected port; the encoding is the

same as for the PHY register Max_speed field.

Int_enable 1 rw 0 Enable port event interrupts. When set to one, the PHY will

set Port_event to one if any of connected, bias, disabled, or

fault (for this port) change state.

Fault 1 rw 0 Set to one if an error is detected during a suspend or resume

operation. A write of one to this bit clears it to zero.

2222 Agere Systems Inc.

Data Sheet, Rev. 1

October 2002

Two-Cable Transceiver/Arbit er Devi ce

FW802C Low-Power PHY

IEEE

1394A-2000

Internal Register Configuration (continued)

The vendor identification page is used to identify the PHY’s vendor and compliance level. The page is selected by

writing one to Page_select in the PHY register at address 01112. The format of the vendor identification page is

shown in Table 12; reserved fields are shown shaded.

Table 12. PHY Register Page 1: Vendor Identification Page

The meaning of the register fields within the vendor identification page are defined by Table 13.

Table 13. PHY Register Vendor Identification Page Fields

The vendor-dependent page provides access to information used in manufacturing test of the FW802C.

Address Contents

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

10002Compliance_level

10012XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX

10102

10112Vendor_ID

11002

11012

11102Product_ID

11112

REQUIRED XXXXX RESERVED

Field Size Type Description

Compliance_level 8 r Standard to which the PHY implementation complies:

0 = not specified

1 =

IEEE

1394

a-2000

Agere’s FW802C compliance level is 1.

All other values reserved for future standardization.

Vendor_ID 24 r The company ID or organizationally unique identifier (OUI) of the manufacturer

of the PHY. Agere’s vendor ID is 00601D16. This number is obtained from the

IEEE

registration authority committee (RAC). The most significant byte of

Vendor_ID appears at PHY register location 10102 and the least significant at

11002.

Product_ID 24 r The meaning of this number is determined by the company or organization that

has been granted Vendor_ID. Agere’s FW802C product ID is 08020116. The

most significant byte of Product_ID appears at PHY register location 11012 and

the least significant at 11112.

Agere Systems Inc. 23

Data Sheet, Rev. 1

October 2002 Two-Cable Transceiver/Arbiter Device

FW802C Low-Power PHY

IEEE

1394A-2000

Outline Diagrams

48-Pin TQFP

Dimensions are in millimeters

5-3080 (F)

Ordering Information

Device Code Package Comcode

FW802C-DB 48-Pin TQFP 700032322

PIN #1

IDENTIFIER ZONE

7.00 ± 0.20

48 37

9.00

± 0.20

7.00

± 0.20

1.60 MAX

SEATING PLANE

DETAIL A

0.08

1.40 ± 0.05

0.50 TYP 0.05/0.15

DETAIL B

0.19/0.27

0.08 M

0.106/0.200

DETAIL A

0.45/0.75

GAGE PLANE

SEATING PLANE

1.00 REF

0.25

9.00 ± 0.20

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere,

Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.

October 2002

DS02-362CMPR-1

For additional informatio n, co nta ct you r Agere Systems Account Manager or the following:

INTERNET: http://www.agere.com

E-MAIL: docmaster@agere.com

N. AMERICA: Agere Systems Inc., Lehigh Valley Cen t ral Ca mpus, Room 10A-301C, 1110 America n Parkway NE, Allentown , PA 18109-91 38

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610- 712- 4106)

ASIA: Agere Systems H ong Kong Ltd., Suites 3201 & 3210 -12, 32 /F, Tow er 2 , The Ga teway, Harbour City, Kowl oo n

Tel. (852) 3129-2000, FAX (852) 3129-2020

CHINA: (86) 21-5047-1212 ( Sh anghai), (86) 755-25881122 (Shenzhen)

JAPAN: (81) 3-5421-1600 (To kyo), KOREA: (82) 2- 767-1 850 (Se oul), SINGAPORE: (65) 6778 - 8833, TAIWAN: (886) 2-2725-5858 (Taipei)

EUROPE: Tel. (44)1344 296 400

IEEE

is a registered trademark and

1394

is a trademark of The Institute of Electrical and Electronics Engineers, Inc.

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logo is a trademark of Apple Computer, Inc.

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is a registered trademark of Intel Corporation.