The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
MOS INTEGRATED CIRCUIT
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
V850ES/HE3, V850ES/HF3, V850ES/HG3, V850ES/HJ3
32-BIT SINGLE-CHIP MICROCONTROLLERS
PRELIMINARY PRODUCT INFORMATION
Document No. U18744EJ1V0PM00 (1st edition)
Date Published August 2007 N
Printed in Japan 2007
DESCRIPTION
The
μ
PD70F3747 (V850ES/HE3),
μ
PD70F3750 (V850ES/HF3),
μ
PD70F3752 (V850ES/HG3), and
μ
PD70F3755,
70F3757 (V850ES/HJ3) are products of the V850 32-bit single-chip microcontrollers, and include peripheral functions
such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, a D/A converter, and a DMA controller.
In addition to their high real-time responsiveness and one-clock-pitch execution of instructions, the V850ES/HE3,
V850ES/HF3, V850ES/HG3, and V850ES/HJ3 include instructions suited to digital servo control applications such as
multiplication instructions executed via a hardware multiplier, saturation instructions, and bit manipulation instructions.
As a real-time control system, this device provides high-level cost performance ideal for industrial equipment, air-
conditioning-/housing-related equipment and measurement instrument applications.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850ES/HE3, V850ES/HF3, V850ES/HG3, V850ES/HJ3 Hardware User’s Manual: To be prepared
V850ES Architecture User’s Manual: U15943E
FEATURES
{ Number of instructions: 83
{ Minimum instruction execution time:
31.25 ns (@ 32 MHz operation with main clock (fXX))
{ Clock
• Main clock oscillation: fX = 4 to 16 MHz
• Subclock oscillation: fXT = 32.768 MHz
• High-speed internal oscillation: fRH = 8 MHz (TYP.)
• Low-speed internal oscillation: fRL = 240 kHz (TYP.)
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set:
Signed multiplication, saturation operations, 32-bit shift
instructions, bit manipulation instructions, load/store
instructions
{ Memory space:
64 MB linear address space
{ External bus interface:
Multiplexed bus mode (V850ES/HJ3 only)
{ Internal memory
Flash memory: 128 to 512 KB
RAM: 8 to 32 KB
{ I/O lines Total: 51/67/84/128
{ Interrupts and exceptions
Non-maskable interrupts: 2 sources
Maskable interrupts: 50 to 78 sources
{ Timer/counters
16-bit timer/event counter AA (TAA): 5 channels
16-bit timer/event counter AB (TAB): 1 to 3 channels
16-bit interval timer M (TMM): 1 channel
{ Motor control function: 1 channel
{ Watchdog timer: 1 channel
{ Watch timer: 1 channel
{ A/D converter: 10-bit resolution × 10 to 24 channels
{ Serial interface
• Asynchronous serial interface (UARTD): 2 to 6 channels
• Clocked serial interface (CSIB): 2, 3 channels
• I2C bus interface: 1 channel
{ DMA controller: 4 channels
{ Power save function:
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
{ On-chip debug function
{ Package: 64- to 144-pin LQFP
{ Operating supply voltage: 3.5 to 5.5 V
Preliminary Product Information U18744EJ1V0PM
2
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
Function list
Generic Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3
Product Name
μ
PD70F3747
μ
PD70F3750
μ
PD70F3752
μ
PD70F3755
μ
PD70F3757
Flash memory 128 KB 256 KB 256 KB 256 KB 512 KB Internal
memory RAM 8 KB 16 KB 16 KB 16 KB 32 KB
Logical space 64 MB Memory
space External memory area
− 15 MB
External bus interface − Address/data buses: 16
Chip select signals: 4
Multiplexed bus mode supported
General-purpose register 32 bits × 32 registers
Minimum instruction
execution time
31.25 ns (fXX = 32 MHz)
Main clock oscillation
fX = 4 to 16 MHz
Subclock oscillation fXT = 32.768 kHz
SSCG Frequency modulation rate specification ±5% (TYP.)
PLL multiplication Multiplication by 8
High-speed internal
oscillation
fRH = 8 MHz (TYP.)
Clocks
Low-speed internal
oscillation
fRL = 240 kHz (TYP.)
I/O ports I/O: 51 I/O: 67 I/O: 84 I/O: 128
16-bit TAA 5 channels 5 channels 5 channels 5 channels
16-bit TAB 1 channel 1 channel 2 channels 3 channels
16-bit TMM 1 channel 1 channel 1 channel 1 channel
Motor control 1 channel 1 channel 1 channel 1 channel
WDT 1 channel 1 channel 1 channel 1 channel
Timer
Watch timer 1 channel 1 channel 1 channel 1 channel
10-bit A/D converter 10 channels 12 channels 16 channels 24 channels
CSIB 2 channels 2 channels 2 channels 3 channels
UARTD 2 channels 2 channels 3 channels 3 channels 6 channels
Serial
interface
I2C 1 channel 1 channel 1 channel 1 channel
DMA controller 4 channels
(transfer target: on-chip peripheral I/O, internal RAM)
4 channels
(transfer target: on-chip peripheral
I/O, internal RAM, external memory)
External 9 (9)Note 9 (9)Note 12 (12)Note 16 (16)Note Interrupt
source Internal 43 43 51 58 64
Power-save function HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE modes
Reset factor RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), power-on-clear (POC), low-
voltage detector (LVI)
On-chip debugging MINICUBE®, MINICUBE2 supported
Operating supply voltage 3.3 to 5.5 V
Package 64-pin LQFP
(10 × 10 mm)
80-pin LQFP
(12 × 12 mm)
100-pin LQFP
(14 × 14 mm)
144-pin LQFP
(20 × 20 mm)
Note The figure in parentheses indicates the number of external interrupts that can release the STOP mode.
Preliminary Product Information U18744EJ1V0PM 3
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
APPLICATIONS
Industrial equipment, air-conditioning-/housing-related equipment, measurement equipment, and consumer
electronics
ORDERING INFORMATION
• V850ES/HE3
Part Number Package On-Chip Flash Memory
μ
PD70F3747GB-GAH-AX 64-pin plastic LQFP (fine pitch) (10 × 10) 128 KB
• V850ES/HF3
Part Number Package On-Chip Flash Memory
μ
PD70F3750GK-GAK-AX 80-pin plastic LQFP (fine pitch) (12 × 12) 256 KB
• V850ES/HG3
Part Number Package On-Chip Flash Memory
μ
PD70F3752GC-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14) 256 KB
• V850ES/HJ3
Part Number Package On-Chip Flash Memory
μ
PD70F3755GJ-GAE-AX
μ
PD70F3757GJ-GAE-AX
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
256 KB
512 KB
Remark The V850ES/Hx3 microcontrollers are lead-free products.
Preliminary Product Information U18744EJ1V0PM
4
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
PIN CONFIGURATION
• V850ES/HE3
64-pin plastic LQFP (fine pitch) (10 × 10)
μ
PD70F3747GB-GAH-AX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AV
REF0
AV
SS
FLMD0
Note 1
V
DD
REGC
Note 2
V
SS
X1
X2
RESET
XT1
XT2
P00/TIAA31/TOAA31
P01/TIAA30/TOAA30
P02/NMI/TIAA40/TOAA40
P03/INTP0/ADTRG/TIAA41/TOAA41
P04/INTP1 32
P05/INTP2/DRST
P06/INTP3
P40/SIB0/KR0
P41/SOB0/KR1
P42/SCKB0/KR2
P30/TXDD0
P31/RXDD0/INTP7
P32/ASCKD0/TOAA01/TIAA00/TOAA00
P33/TIAA01/TOAA01
P34/TIAA10/TOAA10
P35/TIAA11/TOAA11
P50/KR0/TIAB01/TOAB01/TOAB0T1
P51/KR1/TIAB02/TOAB02/TOAB0B1
P52/KR2/TIAB03/TOAB03/TOAB0T2/DDI
P53/KR3/TIAB00/TOAB00/TOAB0B2/DDO
EV
SS
PDL1
PDL0
PCM1/CLKOUT
PCM0
P915/INTP6/SCL00
P914/INTP5/SDA00
P913/INTP4/PCL
P99/SCKB1/TIAB00/TOAB00
P98/SOB1/TIAB03/TOAB03
P97/SIB1/TIAA20/TOAA20
P96/TIAA21/TOAA21
P91/KR7/RXDD1
P90/KR6/TXDD1
P55/KR5/TOAB0B3/DMS
P54/KR4/TOAB0T3/DCK
EV
DD
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
P78/ANI8
P79/ANI9
PDL7
PDL6
PDL5/FLMD1
PDL4
PDL3
PDL2
Notes 1. Connect to VSS in normal mode.
2. Connect the REGC pin to VSS via a 4.7
μ
F (recommended value) capacitor.
Preliminary Product Information U18744EJ1V0PM 5
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
• V850ES/HF3
80-pin plastic LQFP (fine pitch) (12 × 12)
μ
PD70F3750GK-GAK-AX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AV
REF0
AVSS
P00/TIAA31/TOAA31
P01/TIAA30/TOAA30
P02/NMI/TIAA40/TOAA40
P03/INTP0/ADTRG/TIAA41/TOAA41
P04/INTP1
FLMD0Note 1
VDD
REGCNote 2
VSS
X1
X2
RESET
XT1
XT2
P05/INTP2/DRST
P06/INTP3
P40/SIB0/KR0
P41/SOB0/KR1 36
P42/SCKB0/KR2
P30/TXDD0
P31/RXDD0/INTP7
P32/ASCKD0/TOAA01/TIAA00/TOAA00
P33/TIAA01/TOAA01
P34/TIAA10/TOAA10
P35/TIAA11/TOAA11
P38
P39
EVSS
EVDD
P50/KR0/TIAB01/TOAB01/TOAB0T1
P51/KR1/TIAB02/TOAB02/TOAB0B1
P52/KR2/TIAB03/TOAB03/TOAB0T2/DDI
P53/KR3/TIAB00/TOAB00/TOAB0B2/DDO
P54/KR4/TOAB0T3/DCK
P55/KR5/TOAB0B3/DMS
P90/KR6/TXDD1
P91/KR7/RXDD1
P96/TIAA21/TOAA21
PDL3
PDL2
PDL1
PDL0
PCT6
PCT4
PCT1
PCT0
PCM3
PCM2
PCM1/CLKOUT
PCM0
PCS1
PCS0
P915/INTP6/SCL00
P914/INTP5/SDA00
P913/INTP4/PCL
P99/SCKB1/TIAB00/TOAB00
P98/SOB1/TIAB03/TOAB03
P97/SIB1/TIAA20/TOAA20
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
P78/ANI8
P79/ANI9
P710/ANI10
P711/ANI11
PDL11
PDL10
PDL9
PDL8
PDL7
PDL6
PDL5/FLMD1
PDL4
38 3937 40
64 6263 61
Notes 1. Connect to VSS in normal mode.
2. Connect the REGC pin to VSS via a 4.7
μ
F (recommended value) capacitor.
Preliminary Product Information U18744EJ1V0PM
6
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
• V850ES/HG3
100-pin plastic LQFP (fine pitch) (14 × 14)
μ
PD70F3752GC-UEU-AX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AV
REF0
AV
SS
P10/INTP9
P11/INTP10
EV
DD
P00/TIAA31/TOAA31
P01/TIAA30/TOAA30
FLMD0
Note 1
V
DD
REGC
Note 2
V
SS
X1
X2
RESET
XT1
XT2
P02/NMI/TIAA40/TOAA40
P03/INTP0/ADTRG/TIAA41/TOAA41
P04/INTP1
P05/INTP2/DRST
P06/INTP3
P40/SIB0/KR0
P41/SOB0/KR1
P42/SCKB0/KR2
P30/TXDD0 41
P31/RXDD0/INTP7
P32/ASCKD0/TOAA01/TIAA00/TOAA00
P33/TIAA01/TOAA01
P34/TIAA10/TOAA10
P35/TIAA11/TOAA11
P36
P37
EV
SS
EV
DD
P38/TXDD2
P39/RXDD2/INTP8
P50/KR0/TIAB01/TOAB01/TOAB0T1
P51/KR1/TIAB02/TOAB02/TOAB0B1
P52/KR2/TIAB03/TOAB03/TOAB0T2/DDI
P53/KR3/TIAB00/TOAB00/TOAB0B2/DDO
P54/KR4/TOAB0T3/DCK
P55/KR5/TOAB0B3/DMS
P90/KR6/TXDD1
P91/KR7/RXDD1
P92/TIAB11/TOAB11
P93/TIAB12/TOAB12
P94/TIAB13/TOAB13
P95/TIAB10/TOAB10
P96/TIAA21/TOAA21
P97/SIB1/TIAA20/TOAA20
PDL4
PDL3
PDL2
PDL1
PDL0
BV
DD
BV
SS
PCT6
PCT4
PCT1
PCT0
PCM3
PCM2
PCM1/CLKOUT
PCM0
PCS1
PCS0
P915/INTP6/SCL00
P914/INTP5/SDA00
P913/INTP4/PCL
P912
P911
P910
P99/SCKB1/TIAB00/TOAB00
P98/SOB1/TIAB03/TOAB03
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
P78/ANI8
P79/ANI9
P710/ANI10
P711/ANI11
P712/ANI12
P713/ANI13
P714/ANI14
P715/ANI15
PDL13
PDL12
PDL11
PDL10
PDL9
PDL8
PDL7
PDL6
PDL5/FLMD1
43 4442 45
84 8283 81
4946 4847 50
7780 7879 76
Notes 1. Connect to VSS in normal mode.
2. Connect the REGC pin to VSS via a 4.7
μ
F (recommended value) capacitor.
Preliminary Product Information U18744EJ1V0PM 7
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
• V850ES/HJ3
144-pin plastic LQFP (fine pitch) (20 × 20)
μ
PD70F3755GJ-GAE-AX
μ
PD70F3757GJ-GAE-AX
AVREF0
AVSS
P10/INTP9
P11/INTP10
EVDD
P00/TIAA31/TOAA31
P01/TIAA30/TOAA30
FLMD0Note 1
VDD
REGCNote 2
VSS
X1
X2
RESET
XT1
XT2
P02/NMI/TIAA40/TOAA40
P03/INTP0/ADTRG/TIAA41/TOAA41
P04/INTP1
P05/INTP2/DRST
P06/INTP3
P40/SIB0/KR0/RXDD3/INTP14
P41/SOB0/KR1/TXDD3
P42/SCKB0/KR2
P30/TXDD0
P31/RXDD0/INTP7
P32/ASCKD0/TOAA01/TIAA00/TOAA00
P33/TIAA01/TOAA01
P34/TIAA10/TOAA10
P35/TIAA11/TOAA11
P36
P37
EVSS
EVDD
P38/TXDD2
P39/RXDD2/INTP8
PDL3/AD3
PDL2/AD2
PDL1/AD1
PDL0/AD0
BVDD/VDD
BVSS/VSS
PCT7
PCT6/ASTB
PCT5
PCT4/RD
PCT3
PCT2
PCT1/WR1
PCT0/WR0
PCS7
PCS6
PCS5
PCS4
PCM5
PCM4
PCM3/HLDRQ
PCM2/HLDAK
PCM1/CLKOUT
PCM0/WAIT
PCS3/CS3
PCS2/CS2
PCS1/CS1
PCS0/CS0
PCD3
PCD2
PCD1
PCD0
P915/INTP6/SCL00/TXDD4Note 3
P914/INTP5/SDA00/RXDD4Note 3
P913/INTP4/PCL/RXDD5Note 3
P912/SCKB2/TXDD5Note 3
P50/KR0/TIAB01/TOAB01/TOAB0T1
P51/KR1/TIAB02/TOAB02/TOAB0B1
P52/KR2/TIAB03/TOAB03/TOAB0T2/DDI
P53/KR3/TIAB00/TOAB00/TOAB0B2/DDO
P54/KR4/TOAB0T3/DCK
P55/KR5/TOAB0B3/DMS
P60/INTP11
P61/INTP12
P62/INTP13
P63
P64
P65
P66
P67
P68
P69
P610/TIAB20/TOAB20
P611/TIAB21/TOAB21
P612/TIAB22/TOAB22
P613/TIAB23/TOAB23
P614
P615
P80/RXDD3Note 3/INTP14
P81/TXDD3Note 3
P90/KR6/TXDD1
P91/KR7/RXDD1
P92/TIAB11/TOAB11
P93/TIAB12/TOAB12
P94/TIAB13/TOAB13
P95/TIAB10/TOAB10
P96/TIAA21/TOAA21
P97/SIB1/TIAA20/TOAA20
P98/SOB1/TIAB03/TOAB03
P99/SCKB1/TIAB00/TOAB00
P910/SIB2
P911/SOB2
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
P78/ANI8
P79/ANI9
P710/ANI10
P711/ANI11
P712/ANI12
P713/ANI13
P714/ANI14
P715/ANI15
P120/ANI16
P121/ANI17
P122/ANI18
P123/ANI19
P124/ANI20
P125/ANI21
P126/ANI22
P127/ANI23
PDL15/AD15
PDL14/AD14
PDL13/AD13
PDL12/AD12
PDL11/AD11
PDL10/AD10
PDL9/AD9
PDL8/AD8
PDL7/AD7
PDL6/AD6
PDL5/AD5/FLMD1
PDL4/AD4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
Notes 1. Connect to VSS in normal mode.
2. Connect the REGC pin to VSS via a 4.7
μ
F (recommended value) capacitor.
3.
μ
PD70F3757 only
Preliminary Product Information U18744EJ1V0PM
8
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
PIN IDENTIFICATION
AD0 to AD15:
ADTRG:
ANI0 to ANI23:
ASTB:
AVREF0:
AVSS:
BVDD:
BVSS:
CLKOUT:
CS0 to CS3:
DCK:
DDI:
DDO:
DMS:
DRST:
EVDD:
EVSS:
FLMD0, FLMD1:
HLDAK:
HLDRQ:
INTP0 to INTP15:
KR0 to KR7:
NMI:
P00 to P06:
P10, P11:
P30 to P39:
P40 to P42:
P50 to P55:
P60 to P615:
P70 to P715:
P80, P81:
P90 to P915:
P120 to P127:
PCD0 to PCD3:
PCL:
PCM0 to PCM5:
PCS0 to PCS7:
PCT0 to PCT7:
PDH0 to PDH7:
PDL0 to PDL15:
RD
Address/data bus
AD trigger input
Analog input
Address strobe
Analog VDD
Analog VSS
Power supply for bus interface
Ground for bus interface
Clock output
Chip select
Debug clock
Debug data input
Debug data output
Debug mode select
Debug reset
Power supply for external pin
Ground for external pin
Flash programming mode
Hold acknowledge
Hold request
External interrupt input
Key return
Non-maskable interrupt request
Port 0
Port 1
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port 12
Port CD
Programmable clock output
Port CM
Port CS
Port CT
Port DH
Port DL
Read
REGC:
RESET:
RXDD0 to RXDD5:
SCKB0 to SCKB2:
SCL00:
SDA00:
SIB0 to SIB2:
SOB0 to SOB2:
TIAA00, TIAA01,
TIAA10, TIAA11,
TIAA20, TIAA21,
TIAA30, TIAA31,
TIAA40, TIAA41,
TIAB00, TIAB01,
TIAB02, TIAB03,
TIAB10, TIAB11,
TIAB12, TIAB13,
TIAB20, TIAB21,
TIAB22, TIAB23:
TOAA00, TOAA01,
TOAA10, TOAA11,
TOAA20, TOAA21,
TOAA30, TOAA31,
TOAA40, TOAA41,
TOAB00, TOAB01,
TOAB02, TOAB03,
TOAB10, TOAB11,
TOAB12, TOAB13,
TOAB20, TOAB21,
TOAB22, TOAB23
TOAB0B1, TOAB0B2,
TOAB0B3, TOAB0T1,
TOAB0T2, TOAB0T3:
TXDD0 to TXDD5:
VDD:
VSS:
WAIT:
WR0:
WR1:
X1, X2:
XT1, XT2:
Regulator control
Reset
Receive data
Serial clock
Serial clock
Serial data
Serial input
Serial output
Timer input
Timer output
Transmit data
Power supply
Ground
Wait
Write strobe low level data
Write strobe high level data
Crystal for main clock
Crystal for subclock
Preliminary Product Information U18744EJ1V0PM 9
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
INTERNAL BLOCK DIAGRAM
• V850ES/HE3 (
μ
PD70F3747)
NMI
INTP0 to INTP7 INTC
TOAB00 to TOAB03
TIAB00 to TIAB03 16-bit timer/
counter AB:
1 ch
TOAA00 to TOAA40,
TOAA01 to TOAA41
TIAA00 to TIAA40,
TIAA01 to TIAA41 16-bit timer/
counter AA:
5 ch
RAM
Flash memory
PC
General-purpose
registers 32 bits × 32
Multiplier
16 × 16 → 32
ALU
System
registers
32-bit barrel
shifter
CPU
FLMD0
FLMD1
CG
Regulator
PLL
LVI
Ports
PDL0 to PDL07
PCM0, PCM1
P90, P91, P96 to P99, P913 to P915
P70 to P709
P50 to P55
P40 to P42
P30 to P35
P00 to P06
ANI0 to ANI9
AV
SS
AV
REF0
ADTRG
PCL
CLKOUT
XT1
XT2
X1
X2
RESET
V
DD
V
SS
REGC
EV
DD
EV
SS
BCU
16-bit interval
timer M:
1 ch
DCU
DRST
DMS
DDI
DCK
DDO
A/D
converter
POC
SOB0, SOB1
SIB0, SIB1
TOAB0T1 to TOAB0T3
TOAB0B1 to TOAB0B3
CSIB: 2 ch
SCKB0, SCKB1
RXDD0, RXDD1
TXDD0, TXDD1
UARTD:
2 ch
ASCKD0
SDA00
SCL00 I
2
C0
Watchdog
timer 2
Watch timer
KR0 to KR7 Key return
function
DMAC
CLM
High-speed internal oscillator
(8 MHz)
Low-speed internal oscillator
(240 kHz)
8 KB
128 KB
Instruction
queue
Motor control
(TAB0, TAA4)
Preliminary Product Information U18744EJ1V0PM
10
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
• V850ES/HF3 (
μ
PD70F3750)
NMI
TOAB00 to TOAB03
TIAB00 to TIAB03
INTP0 to INTP7 INTC
TOAA00 to TOAA40,
TOAA01 to TOAA41
TIAA00 to TIAA40,
TIAA01 to TIAA41
SOB0, SOB1
SIB0, SIB1
CSIB: 2 ch
256 KB
16 KB
RAM
PC
ALU
CPU
FLMD0
FLMD1
CG
PLL
LVI
PDL0 to PDL11
PCT0, PCT1, PCT4, PCT6
PCS0, PCS1
PCM0 to PCM3
P90, P91, P96 to P99, P913 to P915
P70 to P711
P50 to P55
P40 to P42
P30 to P35, P38, P39
P00 to P06
ANI0 to ANI11
AVSS
AVREF0
ADTRG
PCL
CLKOUT
XT1
XT2
X1
X2
RESET
VDD
VSS
REGC
EVDD
EVSS
BCU
DCU
DRST
DMS
DDI
DCK
DDO
POC
SCKB0, SCKB1
RXDD0, RXDD1
TXDD0, TXDD1
UARTD:
2 ch
ASCKD0
KR0 to KR7
DMAC
SDA00
SCL00 I2C0
CLM
TOAB0T1 to TOAB0T3
TOAB0B1 to TOAB0B3
Instruction
queue
32-bit barrel
shifter
System
registers
Flash memory
A/D
converter
Ports
16-bit timer/
counter AB:
1 ch
16-bit timer/
counter AA:
5 ch
16-bit interval
timer M:
1 ch
Motor control
(TAB0, TAA4)
Watchdog
timer 2
Watch timer
Key return
function
Regulator
General-purpose
registers 32 bits × 32
Multiplier
16 × 16 → 32
High-speed internal oscillator
(8 MHz)
Low-speed internal oscillator
(240 kHz)
Preliminary Product Information U18744EJ1V0PM 11
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
• V850ES/HG3 (
μ
PD70F3752)
NMI
INTP0 to INTP10 INTC
TOAB00, TOAB10
TOAB01, TOAB11
TOAB02, TOAB12
TOAB03, TOAB13
TIAB00, TIAB10
TIAB01, TIAB11
TIAB02, TIAB12
TIAB03, TIAB13
TOAA00 to TOAA40,
TOAA01 to TOAA41
TIAA00 to TIAA40,
TIAA01 to TIAA41
DMAC
RAM
PC
ALU
CPU
FLMD0
FLMD1
CG
PLL
LVI
CLM
PDL0 to PDL13
PCT0, PCT1, PCT4, PCT6
PCS0, PCS1
PCM0 to PCM3
P90 to P915
P70 to P715
P50 to P55
P40 to P42
P30 to P39
P10, P11
P00 to P06
ANI0 to ANI15
AV
SS
AV
REF0
ADTRG
PCL
CLKOUT
XT1
XT2
X1
X2
RESET
V
DD
V
SS
REGC
BV
DD
BV
SS
EV
DD
EV
SS
Instruction
queue
BCU
DCU
DRST
DMS
DDI
DCK
DDO
POC
SOB0, SOB1
SIB0, SIB1
CSIB: 2 ch
SCKB0, SCKB1
RXDD0 to RXDD2
TXDD0 to TXDD2
UARTD:
3 ch
ASCKD0
KR0 to KR7
SDA00
SCL00 I
2
C0
256 KB
16 KB
TOAB0T1 to TOAB0T3
TOAB0B1 to TOAB0B3
32-bit barrel
shifter
System
registers
Flash memory
A/D
converter
Ports
16-bit timer/
counter AB:
2 ch
16-bit timer/
counter AA:
5 ch
16-bit interval
timer M:
1 ch
Motor control
(TAB0, TAA4)
Watchdog
timer 2
Watch timer
Key return
function
Regulator
General-purpose
registers 32 bits × 32
Multiplier
16 × 16 → 32
High-speed internal oscillator
(8 MHz)
Low-speed internal oscillator
(240 kHz)
Preliminary Product Information U18744EJ1V0PM
12
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
• V850ES/HJ3 (
μ
PD70F3755, 70F3757)
NMI
INTP0 to INTP14 INTC
TOAB00 to TOAB20
TOAB01 to TOAB21
TOAB02 to TOAB22
TOAB03 to TOAB23
TIAB00 to TIAB20
TIAB01 to TIAB21
TIAB02 to TIAB22
TIAB03 to TIAB23
TOAA00 to TOAA40,
TOAA01 to TOAA41
TIAA00 to TIAA40,
TIAA01 to TIAA41
DMAC
Note 1
Note 2
RAM
PC
ALU
CPU
HLDRQ
HLDAK
ASTB
RD
WAIT
WR0, WR1
AD0 to AD15
FLMD0
FLMD1
CG
PLL
LVI
CLM
CS0 to CS3
PDL0 to PDL15
PCT0 to PCT7
PCS0 to PCS7
PCM0 to PCM5
PCD0 to PCD3
P120 to P127
P90 to P915
P80, P81
P70 to P715
P60 to P615
P50 to P55
P40 to P42
P30 to P39
P10, P11
P00 to P06
ANI0 to ANI23
AVSS
AVREF0
ADTRG
CLKOUT
XT1
XT2
X1
X2
RESET
VDD
VSS
REGC
BVDD
BVSS
EVDD
EVSS
BCU
DCU
DRST
DMS
DDI
DCK
DDO
POC
SOB0 to SOB2
SIB0 to SIB2
CSIB:
3 ch
SCKB0 to SCKB2
RXDD0 to RXDD5Note 3
TXDD0 to TXDD5Note 3
UARTD:
6 chNote 3
ASCKD0
KR0 to KR7
SDA00
SCL00 I2C0
Motor control
(TAB0, TAA4)
TOAB0T1 to TOAB0T3
TOAB0B1 to TOAB0B3
Instruction
queue
32-bit barrel
shifter
System
registers
Flash memory
A/D
converter
Ports
16-bit timer/
counter AB:
3 ch
16-bit timer/
counter AA:
5 ch
16-bit interval
timer M:
1 ch
Watchdog
timer 2
Watch timer
Key return
function
Regulator
General-purpose
registers 32 bits × 32
Multiplier
16 × 16 → 32
High-speed internal oscillator
(8 MHz)
Low-speed internal oscillator
(240 kHz)
Notes 1.
μ
PD70F3755: 256 KB
μ
PD70F3757: 512 KB
2.
μ
PD70F3755: 16 KB
μ
PD70F3757: 32 KB
3. 6 channels are provided in the
μ
PD70F3757, and 3 channels are provided in the
μ
PD70F3755.
Preliminary Product Information U18744EJ1V0PM 13
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
CONTENTS
1. PIN FUNCTIONS................................................................................................................................15
1.1 Port Pins......................................................................................................................................15
1.2 Non-Port Pins .............................................................................................................................20
1.3 Pin I/O Circuits and Recommended Connection of Unused Pins.........................................26
2. CPU FUNCTIONS ..............................................................................................................................32
3. MEMORY MAP...................................................................................................................................33
4. PORTS.................................................................................................................................................35
5. EXTERNAL BUS INTERFACE FUNCTION (V850ES/HJ3 ONLY)...............................................37
6. CLOCK GENERATION FUNCTION .................................................................................................39
7. 16-BIT TIMER/EVENT COUNTER AA (TAA) ................................................................................41
8. 16-BIT TIMER/EVENT COUNTER AB (TAB) ................................................................................43
9. 16-BIT INTERVAL TIMER M (TMM)...............................................................................................45
10. MOTOR CONTROL FUNCTION.......................................................................................................46
11. WATCH TIMER ..................................................................................................................................48
12. WATCHDOG TIMER 2 FUNCTIONS...............................................................................................50
13. A/D CONVERTER ..............................................................................................................................51
14. ASYNCHRONOUS SERIAL INTERFACE D (UARTD)..................................................................53
15. 3-WIRE VARIABLE-LENGTH SERIAL INTERFACE B (CSIB)....................................................55
16. I2C BUS...............................................................................................................................................57
17. DMA CONTROLLER..........................................................................................................................59
18. INTERRUPT/EXCEPTION PROCESSING FUNCTION ...................................................................61
19. KEY INTERRUPT FUNCTION ..........................................................................................................65
20. STANDBY FUNCTION.......................................................................................................................66
21. RESET FUNCTIONS..........................................................................................................................67
22. CLOCK MONITOR, POWER-ON-CLEAR CIRCUIT, LOW-VOLTAGE DETECTOR....................68
Preliminary Product Information U18744EJ1V0PM
14
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
23. REGULATOR FUNCTION..................................................................................................................69
24. FLASH MEMORY ...............................................................................................................................71
25. ON-CHIP DEBUG FUNCTION ..........................................................................................................72
26. PACKAGE DRAWINGS .....................................................................................................................73
APPENDIX A. DEVELOPMENT TOOLS................................................................................................77
APPENDIX B. COMPARISON BETWEEN V850ES/Hx3 AND V850ES/Hx2.....................................78
Preliminary Product Information U18744EJ1V0PM 15
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
1. PIN FUNCTIONS
1.1 Port Pins
(1/5)
Pin Name I/O Function Alternate Function HE3 HF3 HG3 HJ3
P00 TIAA31/TOAA31 √ √ √ √
P01 TIAA30/TOAA30 √ √ √ √
P02 NMI/TIAA40/TOAA40 √ √ √ √
P03 INTP0/ADTRG/TIAA41/
TOAA41
√ √ √ √
P04 INTP1 √ √ √ √
P05 INTP2/DRST √ √ √ √
P06
I/O Port 0
7-bit I/O port
Input/output can be specified in 1-bit units.
On-chip pull-up resistor can be connected in 1-bit
units.
INTP3 √ √ √ √
P10 INTP9 − − √ √
P11
I/O Port 1
2-bit I/O port
Input/output can be specified in 1-bit units.
On-chip pull-up resistor can be connected in 1-bit
units.
INTP10 − − √ √
P30 TXDD0 √ √ √ √
P31 RXDD0/INTP7 √ √ √ √
P32 ASCKD0/TOAA01/
TIAA00/TOAA00
√ √ √ √
P33 TIAA01/TOAA01 √ √ √ √
P34 TIAA10/TOAA10 √ √ √ √
P35 TIAA11/TOAA11 √ √ √ √
P36 − − − √ √
P37 − − − √ √
TXDD2 − − √ √
P38
− − √ − −
RXDD2/INTP8 − − √ √
P39
I/O Port 3
6-bit I/O port (V850ES/HE3)
8-bit I/O port (V850ES/HF3)
10-bit I/O port (V850ES/HG3, V850ES/HJ3)
Input/output can be specified in 1-bit units.
On-chip pull-up resistor can be connected in 1-bit
units.
− − √ − −
SIB0/KR0/RXDD3/INTP14 − − − √
P40
SIB0/KR0 √ √ √ −
SOB0/KR1/TXDD3 − − − √
P41
SOB0/KR1 √ √ √ −
P42
I/O Port 4
3-bit I/O port
Input/output can be specified in 1-bit units.
On-chip pull-up resistor can be connected in 1-bit
units.
SCKB0/KR2 √ √ √ √
P50 KR0/TIAB01/TOAB01
/TOAB0T1
√ √ √ √
P51 KR1/TIAB02/TOAB02
/TOAB0B1
√ √ √ √
P52 KR2/TIAB03/TOAB03
/TOAB0T2/DDI
√ √ √ √
P53 KR3/TIAB00/TOAB00
/TOAB0B2/DDO
√ √ √ √
P54 KR4/TOAB0T3/DCK √ √ √ √
P55
I/O Port 5
6-bit I/O port
Input/output can be specified in 1-bit units.
On-chip pull-up resistor can be connected in 1-bit
units.
KR5/TOAB0B3/DMS √ √ √ √
Remark HE3: V850ES/HE3, HF3: V850ES/HF3, HG3: V850ES/HG3, HJ3: V850ES/HJ3
Preliminary Product Information U18744EJ1V0PM
16
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
(2/5)
Pin Name I/O Function Alternate Function HE3 HF3 HG3 HJ3
P60 NTP11 − − − √
P61 NTP12 − − − √
P62 INTP13 − − − √
P63 − − − − √
P64 − − − − √
P65 − − − − √
P66 − − − − √
P67 − − − − √
P68 − − − − √
P69 − − − − √
P610 TIAB20/TOAB20
− − − √
P611 TIAB21/TOAB21
− − − √
P612 TIAB22/TOAB22
− − − √
P613 TIAB23/TOAB23
− − − √
P614 − − − − √
P615
I/O Port 6
16-bit I/O port
Input/output can be specified in 1-bit units.
On-chip pull-up resistor can be connected in 1-bit
units.
− − − − √
P70 ANI0 √ √ √ √
P71 ANI1 √ √ √ √
P72 ANI2 √ √ √ √
P73 ANI3 √ √ √ √
P74 ANI4 √ √ √ √
P75 ANI5 √ √ √ √
P76 ANI6 √ √ √ √
P77 ANI7 √ √ √ √
P78 ANI8 √ √ √ √
P79 ANI9 √ √ √ √
P710 ANI10
− √ √ √
P711 ANI11
− √ √ √
P712 ANI12
− − √ √
P713 ANI13
− − √ √
P714 ANI14
− − √ √
P715
I/O Port 7
10-bit I/O port (V850ES/HE3)
12-bit I/O port (V850ES/HF3)
16-bit I/O port (V850ES/HG3, V850ES/HJ3)
Input/output can be specified in 1-bit units.
ANI15 − − √ √
P80 RXDD3/INTP14 − − − √
P81
I/O Port 8
2-bit I/O port
Input/output can be specified in 1-bit units.
On-chip pull-up resistor can be connected in 1-bit
units.
TXDD3 − − − √
Remark HE3: V850ES/HE3, HF3: V850ES/HF3, HG3: V850ES/HG3, HJ3: V850ES/HJ3
Preliminary Product Information U18744EJ1V0PM 17
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
(3/5)
Pin Name I/O Function Alternate Function HE3 HF3 HG3 HJ3
P90 KR6/TXDD1 √ √ √ √
P91 KR7/RXDD1 √ √ √ √
P92 TIAB11/TOAB11 − − √ √
P93 TIAB12/TOAB12 − − √ √
P94 TIAB13/TOAB13 − − √ √
P95 TIAB10/TOAB10 − − √ √
P96 TIAA21/TOAA21 √ √ √ √
P97 SIB1/TIAA20/TOAA20 √ √ √ √
P98 SOB1/TIAB03/TOAB03 √ √ √ √
P99
SCKB1/TIAB00/TOAB00
√ √ √ √
SIB2 − − − √
P910
− − − √ −
SOB2 − − − √
P911
− − − √ −
SCKB2/TXDD5 − − − √
P912
− − − √ −
INTP4/PCL/RXDD5 − − − √
P913
INTP4/PCL √ √ √ −
INTP5/SDA00/RXDD4 − − − √
P914
INTP5/SDA00 √ √ √ −
INTP6/SCL00/TXDD4 − − − √
P915
I/O Port 9
9-bit I/O port (V850ES/HE3, V850ES/HF3)
16-bit I/O port (V850ES/HG3, V850ES/HJ3)
Input/output can be specified in 1-bit units.
On-chip pull-up resistor can be connected in 1-bit
units.
INTP6/SCL00 √ √ √ −
P120 ANI16
− − − √
P121 ANI17
− − − √
P122 ANI18
− − − √
P123 ANI19
− − − √
P124 ANI20
− − − √
P125 ANI21
− − − √
P126 ANI22
− − − √
P127
I/O Port 12
8-bit I/O port
Input/output can be specified in 1-bit units.
ANI23 − − − √
PCD0 − − − − √
PCD1 − − − − √
PCD2 − − − − √
PCD3
I/O Port CD
4-bit I/O port
Input/output can be specified in 1-bit units.
− − − − √
WAIT √ √ √ √
PCM0
− √ √ √ −
PCM1 CLKOUT √ √ √ √
HLDAK − − − √
PCM2
− − √ √ −
HLDRQ − − − √
PCM3
− − √ √ −
PCM4 − − − − √
PCM5
I/O Port CM
2-bit I/O port (V850ES/HE3)
4-bit I/O port (V850ES/HF3, V850ES/HG3)
6-bit I/O port (V850ES/HJ3)
Input/output can be specified in 1-bit units.
− − − − √
Remark HE3: V850ES/HE3, HF3: V850ES/HF3, HG3: V850ES/HG3, HJ3: V850ES/HJ3
Preliminary Product Information U18744EJ1V0PM
18
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
(4/5)
Pin Name I/O Function Alternate Function HE3 HF3 HG3 HJ3
CS0 − − − √
PCS0
− − √ √ −
CS1 − − − √
PCS1
− − √ √ −
PCS2 CS2 − − − √
PCS3 CS3 − − − √
PCS4 − − − − √
PCS5 − − − − √
PCS6 − − − − √
PCS7
I/O Port CS
2-bit I/O port (V850ES/HF3, V850ES/HG3)
8-bit I/O port (V850ES/HJ3)
Input/output can be specified in 1-bit units.
− − − − √
WR0 − − − √
PCT0
− − √ √ −
WR1 − − − √
PCT1
− − √ √ −
PCT2 − − − − √
PCT3 − − − − √
RD − − − √
PCT4
− − √ √ −
PCT5 − − − − √
ASTB − − − √
PCT6
− − √ √ −
PCT7
I/O Port CT
4-bit I/O port (V850ES/HF3, V850ES/HG3)
8-bit I/O port (V850ES/HJ3)
Input/output can be specified in 1-bit units.
− − − − √
AD0 − − − √
PDL0
− √ √ √ −
AD1 − − − √
PDL1
− √ √ √ −
AD2 − − − √
PDL2
− √ √ √ −
AD3 − − − √
PDL3
− √ √ √ −
AD4 − − − √
PDL4
− √ √ √ −
AD5/FLMD1 − − − √
PDL5
FLMD1 √ √ √ −
AD6 − − − √
PDL6
− √ √ √ −
AD7 − − − √
PDL7
− √ √ √ −
AD8 − − − √
PDL8
− − √ √ −
AD9 − − − √
PDL9
I/O Port DL
8-bit I/O port (V850ES/HE3)
12-bit I/O port (V850ES/HF3)
14-bit I/O port (V850ES/HG3)
16-bit I/O port (V850ES/HJ3)
Input/output can be specified in 1-bit units.
− − √ √ −
Remark HE3: V850ES/HE3, HF3: V850ES/HF3, HG3: V850ES/HG3, HJ3: V850ES/HJ3
Preliminary Product Information U18744EJ1V0PM 19
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
(5/5)
Pin Name I/O Function Alternate Function HE3 HF3 HG3 HJ3
AD10 − − − √
PDL10
− − √ √ −
AD11 − − − √
PDL11
− − √ √ −
AD12 − − − √
PDL12
− − − √ −
AD13 − − − √
PDL13
− − − √ −
PDL14 AD14 − − − √
PDL15
I/O Port DL
8-bit I/O port (V850ES/HE3)
12-bit I/O port (V850ES/HF3)
14-bit I/O port (V850ES/HG3)
16-bit I/O port (V850ES/HJ3)
Input/output can be specified in 1-bit units.
AD15 − − − √
Remark HE3: V850ES/HE3, HF3: V850ES/HF3, HG3: V850ES/HG3, HJ3: V850ES/HJ3
Preliminary Product Information U18744EJ1V0PM
20
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
1.2 Non-Port Pins
(1/6)
Pin Name I/O Function Alternate Function HE3 HF3 HG3 HJ3
AD0 PDL0 − − − √
AD1 PDL1 − − − √
AD2 PDL2 − − − √
AD3 PDL3 − − − √
AD4 PDL4 − − − √
AD5 PDL5/FLMD1 − − − √
AD6 PDL6 − − − √
AD7 PDL7 − − − √
AD8 PDL8 − − − √
AD9 PDL9 − − − √
AD10 PDL10 − − − √
AD11 PDL11 − − − √
AD12 PDL12 − − − √
AD13 PDL13 − − − √
AD14 PDL14 − − − √
AD15
I/O Address/data bus for external memory
PDL15 − − − √
ADTRG Input External trigger input for A/D converter P03/INTP0/TIAA41/TOAA41 √ √ √ √
ANI0 P70 √ √ √ √
ANI1 P71 √ √ √ √
ANI2 P72 √ √ √ √
ANI3 P73 √ √ √ √
ANI4 P74 √ √ √ √
ANI5 P75 √ √ √ √
ANI6 P76 √ √ √ √
ANI7 P77 √ √ √ √
ANI8 P78 √ √ √ √
ANI9 P79 √ √ √ √
ANI10 P710
− √ √ √
ANI11 P711
− √ √ √
ANI12 P712
− − √ √
ANI13 P713
− − √ √
ANI14 P714
− − √ √
ANI15 P715
− − √ √
ANI16 P120
− − − √
ANI17 P121
− − − √
ANI18 P122
− − − √
ANI19 P123
− − − √
ANI20 P124
− − − √
ANI21 P125
− − − √
ANI22 P126
− − − √
ANI23
Input Analog voltage input for A/D converter
P127 − − − √
Remark HE3: V850ES/HE3, HF3: V850ES/HF3, HG3: V850ES/HG3, HJ3: V850ES/HJ3
Preliminary Product Information U18744EJ1V0PM 21
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
(2/6)
Pin Name I/O Function Alternate Function HE3 HF3 HG3 HJ3
ASCKD0 Input Serial clock input (UARTD0)
P32/TOAA01/TIAA00/TOAA00
√ √ √ √
ASTB Output Address strobe signal for external memory PCT6 − − − √
AVREF0 − Reference voltage for A/D converter − √ √ √ √
AVSS − Ground potential for A/D converter − √ √ √ √
BVDD − Positive power supply for external I/O (alphabetical
ports and their alternate functions)
− − − √ √
BVSS − Ground potential for external I/O (alphabetical ports
and their alternate functions)
− − − √ √
CLKOUT Output Internal system clock output PCM1 √ √ √ √
CS0 PCS0 − − − √
CS1 PCS1 − − − √
CS2 PCS2 − − − √
CS3
Output Chip select output
PCS3 − − − √
DCK Input Clock input for on-chip debugging P54/KR4 √ √ √ √
DDI Input Data input for on-chip debugging P52/KR2/TIAB03/TOAB03
/TOAB0T2
√ √ √ √
DDO Output Data output for on-chip debugging P53/KR3/TIAB00/TOAB00
/TOAB0B2
√ √ √ √
DMS Input Mode select signal input for on-chip debugging P55/KR5/TOAB0B3 √ √ √ √
DRST Input Reset signal input for on-chip debugging P05/INTP2 √ √ √ √
EVDD − Positive power supply for external I/O (ports
(numerical ports only in V850ES/HG3, V850ES/HJ3)
and their alternate functions)
− √ √ √ √
EVSS − Ground potential for external I/O (ports (numerical
ports only in V850ES/HG3, V850ES/HJ3) and their
alternate functions)
− √ √ √ √
FLMD0 − √ √ √ √
PDL5/AD5 − − − √
FLMD1
− Flash programming mode setting pins
PDL5 √ √ √ −
HLDAK Output Bus hold acknowledge output PCM2 − − − √
HLDRQ Input Bus hold request input PCM3 − − − √
INTP0
P03/ADTRG/TIAA41/TOAA41
√ √ √ √
INTP1 P04
√ √ √ √
INTP2 P05/DRST
√ √ √ √
INTP3 P06
√ √ √ √
P913/PCL/RXDD5 − − − √
INTP4
P913/PCL √ √ √ −
P914/SDA00/RXDD4 − − − √
INTP5
P914/SDA00 √ √ √ −
P915/SCL00/TXDD4 − − − √
INTP6
P915/SCL00 √ √ √ −
INTP7 P31/RXDD0
√ √ √ √
INTP8 P39/RXDD2
− − √ √
INTP9 P10
− − √ √
INTP10
Input Maskable interrupt input
P11 − − √ √
Remark HE3: V850ES/HE3, HF3: V850ES/HF3, HG3: V850ES/HG3, HJ3: V850ES/HJ3
Preliminary Product Information U18744EJ1V0PM
22
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
(3/6)
Pin Name I/O Function Alternate Function HE3 HF3 HG3 HJ3
INTP11 P60
− − − √
INTP12 P61
− − − √
INTP13 P62/SOB3
− − − √
P40/SIB0/KR0/RXDD3 − − − √
INTP14
Input Maskable interrupt input
P80/RXDD3 − − − √
P40/SIB0/RXDD3/INTP14 − − − √
P40/SIB0
√ √ √ −
KR0
P50/TIAB01/TOAB01
/TOAB0T1
√ √ √ √
P41/SOB0/TXDD3 − − − √
P41/SOB0 √ √ √ −
KR1
P51/TIAB02/TOAB02
/TOAB0B1
√ √ √ √
P42/SCKB0 √ √ √ √
KR2
P52/TIAB03/TOAB03
/TOAB0T2/DDI
√ √ √ √
KR3 P53/TIAB00/TOAB00
/TOAB0B2/DDO
√ √ √ √
KR4 P54/TOAB0T3/DCK √ √ √ √
KR5 P55/TOAB0B3/DMS √ √ √ √
KR6 P90/TXDD1 √ √ √ √
KR7
Input Key interrupt input
P91/RXDD1 √ √ √ √
NMI Input Non-maskable interrupt input P02/TIAA40/TOAA40
√ √ √ √
P913/INTP4/RXDD5 − − − √
PCL Output PCL clock output
P913/INTP4 √ √ √ −
RD Output Read strobe signal output for external memory PCT4 − − − √
REGC − Connecting capacitor for regulator output stabilization − √ √ √ √
RESET Input External reset input − √ √ √ √
RXDD0 Serial receive data input (UARTD0) P31/INTP7 √ √ √ √
RXDD1 Serial receive data input (UARTD1) P91/KR7 √ √ √ √
RXDD2 Serial receive data input (UARTD2) P39/INTP8 − − √ √
P40/SIB0/KR0/INTP14 − − − √
RXDD3 Serial receive data input (UARTD3)
P80/INTP14 − − − √
RXDD4 Serial receive data input (UARTD4) P914/INTP5/SDA00 − − − √
RXDD5
Input
Serial receive data input (UARTD5) P913/INTP4/PCL − − − √
SCKB0 Serial clock I/O (CSIB0) P42/KR2 √ √ √ √
SCKB1 Serial clock I/O (CSIB1) P99/TIAB00/TOAB00 √ √ √ √
SCKB2
I/O
Serial clock I/O (CSIB2) P912/TXDD5 − − − √
P915/INTP6/TXDD4 − − − √
SCL00 I/O Serial clock I/O (I2C00)
P915/INTP6 √ √ √ −
P914/INTP5/RXDD4 − − − √
SDA00 I/O Serial transmit/receive data I/O (I2C00)
P914/INTP5 √ √ √ −
Remark HE3: V850ES/HE3, HF3: V850ES/HF3, HG3: V850ES/HG3, HJ3: V850ES/HJ3
Preliminary Product Information U18744EJ1V0PM 23
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
(4/6)
Pin Name I/O Function Alternate Function HE3 HF3 HG3 HJ3
P40/KR0/RXDD3/INTP14 − − − √
SIB0 Serial receive data input (CSIB0)
P40/KR0 √ √ √ −
SIB1 Serial receive data input (CSIB1) P97/TIAA20/TOAA20 √ √ √ √
SIB2
Input
Serial receive data input (CSIB2) P910 − − − √
P41/KR1/TXDD3 − − − √
SOB0 Serial transmit data output (CSIB0)
P41/KR1 √ √ √ −
SOB1 Serial transmit data output (CSIB1) P98/TIAB03/TOAB03 √ √ √ √
SOB2
Output
Serial transmit data output (CSIB2) P911 − − − √
TIAA00 Capture trigger input/external event input/external
clock input (TAA0)
P32/ASCKD0/TOAA01/
TOAA00
√ √ √ √
TIAA01 Capture trigger input (TAA0) P33/TOAA01 √ √ √ √
TIAA10 Capture trigger input/external event input/external
clock input (TAA1)
P34/TOAA10 √ √ √ √
TIAA11 Capture trigger input (TAA1) P35/TOAA11 √ √ √ √
TIAA20 Capture trigger input/external event input/external
clock input (TAA2)
P97/SIB1/TOAA20 √ √ √ √
TIAA21 Capture trigger input (TAA2) P96/TOAA21 √ √ √ √
TIAA30 Capture trigger input/external event input/external
clock input (TAA3)
P01/TOAA30 √ √ √ √
TIAA31 Capture trigger input (TAA3) P00/TOAA31 √ √ √ √
TIAA40 Capture trigger input/external event input/external
clock input (TAA4)
P02/NMI/TOAA40 √ √ √ √
TIAA41
Input
Capture trigger input (TAA4)
P03/INTP0/ADTRG/TOAA41
√ √ √ √
P53/KR3/TOAB00
/TOAB0B2/DDO
√ √ √ √
TIAB00 Capture trigger input/external event input/external
trigger input (TAB0)
P99/SCKB1/TOAB00 √ √ √ √
TIAB01 P50/KR0/TOAB01
/TOAB0T1
√ √ √ √
TIAB02 P51/KR1/TOAB02
/TOAB0B1
√ √ √ √
P52/KR2/TOAB03
/TOAB0T2/DDI
√ √ √ √
TIAB03
Capture trigger input (TAB0)
P98/SOB1/TOAB03 √ √ √ √
TIAB10 Capture trigger input/external event input/external
trigger input (TAB1)
P95/TOAB10 − − √ √
TIAB11 P92/TOAB11
− − √ √
TIAB12 P93/TOAB12
− − √ √
TIAB13
Capture trigger input (TAB1)
P94/TOAB13 − − √ √
TIAB20 Capture trigger input/external event input/external
trigger input (TAB2)
P610/TOAB20 − − − √
TIAB21 P611/TOAB21
− − − √
TIAB22 P612/TOAB22
− − − √
TIAB23
Input
Capture trigger input (TAB2)
P613/TOAB23 − − − √
Remark HE3: V850ES/HE3, HF3: V850ES/HF3, HG3: V850ES/HG3, HJ3: V850ES/HJ3
Preliminary Product Information U18744EJ1V0PM
24
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
(5/6)
Pin Name I/O Function Alternate Function HE3 HF3 HG3 HJ3
TOAA00 P32/ASCKD0/TOAA01
/TIAA00
√ √ √ √
P32/ASCKD0/TIAA00
/TOAA00
√ √ √ √
TOAA01
Timer output (TAA0)
P33/TIAA01 √ √ √ √
TOAA10 P34/TIAA10
√ √ √ √
TOAA11
Timer output (TAA1)
P35/TIAA11 √ √ √ √
TOAA20 P97/SIB1/TIAA20
√ √ √ √
TOAA21
Output
Timer output (TAA2)
P96/TIAA21 √ √ √ √
TOAA30 P01/TIAA30
√ √ √ √
TOAA31
Timer output (TAA3)
P00/TIAA31 √ √ √ √
TOAA40 P02/NMI/TIAA40
√ √ √ √
TOAA41
Output
Timer output (TAA4)
P03/INTP0/ADTRG/TIAA41 √ √ √ √
P53/KR3/TIAB00
/TOAB0B2/DDO
√ √ √ √
TOAB00
P99/SCKB1/TIAB00 √ √ √ √
TOAB01 P50/KR0/TIAB01/TOAB0T1
√ √ √ √
TOAB02 P51/KR1/TIAB02/TOAB0B1
√ √ √ √
P52/KR2/TIAB03/TOAB0T2
/DDI
√ √ √ √
TOAB03
Timer output (TAB0)
P98/SOB1/TIAB03 √ √ √ √
TOAB10 P95/TIAB10
− − √ √
TOAB11 P92/TIAB11
− − √ √
TOAB12 P93/TIAB12
− − √ √
TOAB13
Timer output (TAB1)
P94/TIAB13 − − √ √
TOAB20 P610/TIAB20
− − − √
TOAB21 P611/TIAB21
− − − √
TOAB22 P612/TIAB22
− − − √
TOAB23
Output
Timer output (TAB2)
P613/TIAB23 − − − √
TOAB0B1 P51/KR1/TIAB02/TOAB02
√ √ √ √
TOAB0B2 P53/KR3/TIAB00/DDO
√ √ √ √
TOAB0B3
Motor control output
P55/KR5/DMS √ √ √ √
TOAB0T1 P50/KR0/TIAB01/TOAB01
√ √ √ √
TOAB0T2 P52/KR2/TIAB03/TOAB03
√ √ √ √
TOAB0T3
Output
Motor control inverted input
P54/KR4/DCK √ √ √ √
TXDD0 Serial transmit data output (UARTD0) P30 √ √ √ √
TXDD1 Serial transmit data output (UARTD1) P90/KR6 √ √ √ √
TXDD2 Serial transmit data output (UARTD2) P38 − − √ √
P41/SOB0/KR1 − − − √
TXDD3 Serial transmit data output (UARTD3)
P81 − − − √
TXDD4 Serial transmit data output (UARTD4) P915/INTP6/SCL00 − − − √
TXDD5
Output
Serial transmit data output (UARTD5) P912/SCKB2 − − − √
Remark HE3: V850ES/HE3, HF3: V850ES/HF3, HG3: V850ES/HG3, HJ3: V850ES/HJ3
Preliminary Product Information U18744EJ1V0PM 25
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
(6/6)
Pin Name I/O Function Alternate Function HE3 HF3 HG3 HJ3
VDD − Positive power supply for internal circuit − √ √ √ √
VSS − Ground potential for internal circuit − √ √ √ √
WAIT Input External wait input PCM0 − − − √
WR0
Write strobe for external memory (lower 8 bits)
PCT0 − − − √
WR1
Output
Write strobe for external memory (higher 8 bits)
PCT1 − − − √
X1 Input − √ √ √ √
X2 −
Connecting resonator for main clock
− √ √ √ √
XT1 Input − √ √ √ √
XT2 −
Connecting resonator for subclock
− √ √ √ √
Remark HE3: V850ES/HE3, HF3: V850ES/HF3, HG3: V850ES/HG3, HJ3: V850ES/HJ3
Preliminary Product Information U18744EJ1V0PM
26
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
1.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 1-1. For the
schematic circuit diagram of each type, refer to Figure 1-1.
Table 1-1. Types of Pin I/O Circuits (1/4)
Pin Name Alternate Function I/O Circuit
Type
Recommended Connection of Unused Pins HE3 HF3 HG3 HJ3
P00 TIAA31/TOAA31 √ √ √ √
P01 TIAA30/TOAA30 √ √ √ √
P02 NMI/TIAA40/TOAA40 √ √ √ √
P03 INTP0/ADTRG/TIAA41/
TOAA41
√ √ √ √
P04 INTP1
5-W Input: Independently connect to EVDD or
EVSS via a resistor.
Output: Leave open.
√ √ √ √
P05 INTP2/DRST 5-AF Input: Independently connect to EVSS via a
resistor.
Output: Leave open.
√ √ √ √
P06 INTP3 √ √ √ √
P10 INTP9 − − √ √
P11 INTP10 − − √ √
P30 TXDD0 √ √ √ √
P31 RXDD0/INTP7 √ √ √ √
P32 ASCKD0/TOAA01/
TIAA00/TOAA00
√ √ √ √
P33 TIAA01/TOAA01 √ √ √ √
P34 TIAA10/TOAA10 √ √ √ √
P35 TIAA11/TOAA11 √ √ √ √
P36, P37 − − − √ √
TXDD2 − − √ √
P38
− − √ − −
RXDD2/INTP8 − − √ √
P39
− − √ − −
SIB0/KR0/RXDD3/INTP14 − − − √
P40
SIB0/KR0 √ √ √ −
SOB0/KR1/TXDD3 − − − √
P41
SOB0/KR1 √ √ √ −
P42 SCKB0/KR2 √ √ √ √
P50 KR0/TIAB01/TOAB01
/TOAB0T1
√ √ √ √
P51 KR1/TIAB02/TOAB02
/TOAB0B1
√ √ √ √
P52 KR2/TIAB03/TOAB03/
TOAB0T2/DDI
√ √ √ √
P53 KR3/TIAB00/TOAB00/
TOAB0B2/DDO
√ √ √ √
P54 KR4/TOAB0T3/DCK √ √ √ √
P55 KR5/TOAB0B3/DMS
5-W Input: Independently connect to EVDD or
EVSS via a resistor.
Output: Leave open.
√ √ √ √
Remark HE3: V850ES/HE3, HF3: V850ES/HF3, HG3: V850ES/HG3, HJ3: V850ES/HJ3
Preliminary Product Information U18744EJ1V0PM 27
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
Table 1-1. Types of Pin I/O Circuits (2/4)
Pin Name Alternate Function I/O Circuit
Type
Recommended Connection of Unused Pins HE3 HF3 HG3 HJ3
P60 to P62 NTP11 to INTP13 − − − √
P63 to P69 − − − − √
P610 to P613 TIAB20/TOAB20 to
TIAB23/TOAB23
− − − √
P614, P615 −
5-W Input: Independently connect to EVDD or
EVSS via a resistor.
Output: Leave open.
− − − √
P70 to P79 ANI0 to ANI9 √ √ √ √
P710, P711 ANI10, ANI11 − √ √ √
P712 to P715 ANI12 to ANI15
11-G Input: Independently connect to AVREF0 or
AVSS via a resistor.
Output: Leave open. − − √ √
P80 RXDD3/INTP14 − − − √
P81 TXDD3 − − − √
P90 KR6/TXDD1 √ √ √ √
P91 KR7/RXDD1 √ √ √ √
P92 to P94 TIAB11/TOAB11 to
TIAB13/TOAB13
− − √ √
P95 TIAB10/TOAB10 − − √ √
P96 TIAA21/TOAA21 √ √ √ √
P97 SIB1/TIAA20/TOAA20 √ √ √ √
P98 SOB1/TIAB03/TOAB03 √ √ √ √
P99 SCKB1/TIAB00/TOAB00 √ √ √ √
SIB2 − − − √
P910
− − − √ −
SOB2 − − − √
P911
− − − √ −
SCKB2/TXDD5 − − − √
P912
− − − √ −
INTP4/PCL/RXDD5 − − − √
P913
INTP4/PCL √ √ √ −
INTP5/SDA00/RXDD4 − − − √
P914
INTP5/SDA00 √ √ √ −
INTP6/SCL00/TXDD4 − − − √
P915
INTP6/SCL00
5-W Input: Independently connect to EVDD or
EVSS via a resistor.
Output: Leave open.
√ √ √ −
P120 to P127 ANI16 to ANI23 11-G Input: Independently connect to AVREF0 or
AVSS via a resistor.
Output: Leave open.
− − − √
PCD0 to PCD3 − 5 Input: Independently connect to BVDD or
BVSS via a resistor.
Output: Leave open.
− − − √
Remark HE3: V850ES/HE3, HF3: V850ES/HF3, HG3: V850ES/HG3, HJ3: V850ES/HJ3
Preliminary Product Information U18744EJ1V0PM
28
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
Table 1-1. Types of Pin I/O Circuits (3/4)
Pin Name Alternate Function I/O Circuit
Type
Recommended Connection of Unused Pins HE3 HF3 HG3 HJ3
WAIT − − − √
PCM0
− √ √ √ −
PCM1 CLKOUT √ √ √ √
HLDAK − − − √
PCM2
− − √ √ −
HLDRQ − − − √
PCM3
− − √ √ −
PCM4 − − − − √
PCM5 −
Input: Independently connect to BVDD or
BVSS via a resistor (connect the
V850ES/HE3 and V850ES/HF3 to
EVDD or EVSS).
Output: Leave open.
− − − √
CS0, CS1 − − − √
PCS0, PCS1
− − √ √ −
PCS2, PCS3 CS2, CS3 − − − √
PCS4 to PCS7 − − − − √
WR0 − − − √
PCT0
− − √ √ −
WR1 − − − √
PCT1
− − √ √ −
PCT2, PCT3 − − − − √
RD − − − √
PCT4
− − √ √ −
PCT5 − − − − √
ASTB − − − √
PCT6
− − √ √ −
PCT7 −
5
Input: Independently connect to BVDD or
BVSS via a resistor (connect the
V850ES/HF3 to EVDD or EVSS).
Output: Leave open.
− − − √
AD0 to AD4 − − − √
PDL0 to PDL4
− √ √ √ −
AD5/FLMD1 − − − √
PDL5
FLMD1 √ √ √ −
AD6, AD7 − − − √
PDL6, PDL7
− √ √ √ −
AD8 to AD11 − − − √
PDL8 to PDL11
− − √ √ −
AD12, AD13 − − − √
PDL12, PDL13
− − − √ −
PDL14, PDL15 AD14, AD15
5-K Input: Independently connect to BVDD or
BVSS via a resistor (connect the
V850ES/HE3 and V850ES/HF3 to
EVDD or EVSS).
Output: Leave open.
− − − √
AVREF0 − − Directly connect to VDD. √ √ √ √
AVSS − − − √ √ √ √
BVDD − − − − − √ √
BVSS − − − − − √ √
EVDD − − − √ √ √ √
EVSS − − − √ √ √ √
Remark HE3: V850ES/HE3, HF3: V850ES/HF3, HG3: V850ES/HG3, HJ3: V850ES/HJ3
Preliminary Product Information U18744EJ1V0PM 29
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
Table 1-1. Types of Pin I/O Circuits (4/4)
Pin Name Alternate Function I/O Circuit
Type
Recommended Connection of Unused Pins HE3 HF3 HG3 HJ3
FLMD0 − − Connect to VSS in other than flash mode. √ √ √ √
REGC − − Connect to regulator output stabilization
capacitor.
√ √ √ √
RESET − 2 − √ √ √ √
VDD − − − √ √ √ √
VSS − − − √ √ √ √
X1 − − − √ √ √ √
X2 − − − √ √ √ √
XT1 − Connect to VSS via a resistor. √ √ √ √
XT2 −
16
Leave open. √ √ √ √
Remark HE3: V850ES/HE3, HF3: V850ES/HF3, HG3: V850ES/HG3, HJ3: V850ES/HJ3
Preliminary Product Information U18744EJ1V0PM
30
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
Figure 1-1. Pin I/O Circuits (1/2)
Type 2
Type 5
Schmitt-triggered input with hysteresis characteristics
IN
Data
Output
disable
P-ch
IN/OUT
V
DD
N-ch
Input
enable
Type 5-K
Type 5-W
Data
Output
disable
P-ch
IN/OUT
V
DD
N-ch
Input
enable
P-ch
V
DD
Pull-up
enable
Pull-up
enable
Data
Output
disable
Input
enable
V
DD
P-ch
V
DD
P-ch
IN/OUT
N
-ch
Preliminary Product Information U18744EJ1V0PM 31
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
Figure 1-1. Pin I/O Circuits (2/2)
Type 16
P-ch
Feedback cut-off
XT1 XT2
Type 5-AF
Type 11-G
Data
Output
disable
AVREF0
P-ch
IN/OUT
N-ch
P-ch
N-ch
V
REF
(threshold voltage)
Comparator
Input enable
+
_
AVSS
AVSS
Pull-up
enable
Pull-down
enable
Data
Output
disable
Input enable
VDD
P-ch
VDD
P-ch
IN/OUT
N
-ch
N
-ch
Preliminary Product Information U18744EJ1V0PM
32
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
2. CPU FUNCTIONS
The CPU of the V850ES/Hx3 is based on RISC architecture and executes most instructions in a 1-clock cycle by
using a 5-stage pipeline.
The features of the CPU are as follows.
{ Minimum instruction execution time: 31.25 ns (@ 32 MHz operation with main system clock (fXX))
{ Memory space Program space: 64 MB linear
Data space: 4 GB linear
{ General-purpose registers: 32 bits × 32 registers
{ Internal 32-bit architecture
{ 5-stage pipeline control
{ Multiplication/division instructions
{ Saturation operation instructions
{ 1-clock 32-bit shift instruction
{ Load/store instructions with long/short format
{ Internal memory
Table 2-1. ROM/RAM
Generic Name Products Flash Memory Size RAM Size
V850ES/HE3
μ
PD70F3747 128 KB 8 KB
V850ES/HF3
μ
PD70F3750 256 KB 16 KB
V850ES/HG3
μ
PD70F3752 256 KB 16 KB
μ
PD70F3755 256 KB 16 KB V850ES/HJ3
μ
PD70F3757 512 KB 32 KB
{ Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1
Preliminary Product Information U18744EJ1V0PM 33
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
3. MEMORY MAP
The memory maps of the V850ES/Hx3 are shown below.
{ Address Space
Program space
Peripheral I/O area
Internal RAM area
Use prohibited area
External memory areaNote
Internal ROM area
(external memory area)
Data space
Image 63
Image 1
Image 0
Peripheral I/O area
Internal RAM area
Use prohibited area
External memory areaNote
Internal ROM area
(external memory area)
16 MB
64 MB
4 GB
64 MB
•
•
•
Note The external memory area is available only in the V850ES/HJ3, and is a use-prohibited area in other
products.
Preliminary Product Information U18744EJ1V0PM
34
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
{ Data Memory Map
(64 KB)
Use prohibited
Use prohibited
External memory areaNote 2
(8 MB)
Internal ROM areaNote 4
(128/256/512 KB)
External memory areaNote 2
(1 MB)
Internal RAM areaNote 1
(8/16/32 KB)
On-chip peripheral I/O area
(4 KB)
Use prohibited
External memory areaNote 2
(4 MB)
External memory area
Note 2
(2 MB)
(2 MB) CS0Note 3
CS1Note 3
CS2Note 3
CS3Note 3
3FF0000H
3FFFFFFH
3FEBFFFH
1000000H
0FFFFFFH
0800000H
07FFFFFH
0400000H
3FFFFFFH
0200000H
01FFFFFH
0000000H
3FFFFFFH
3FFF000H
3FFEFFFH
3FF0000H
01FFFFFH
0100000H
00FFFFFH
0000000H
Notes 1. RAM size is different for each product (see Table 2-1).
2. The external memory area is available only in the V850ES/HJ3, and is a use-prohibited area in
other products.
3. CS0 to CS3 are available only in the V850ES/HJ3, and are use-prohibited areas in other products.
4. ROM (flash memory) size is different for each product (see Table 2-1).
Preliminary Product Information U18744EJ1V0PM 35
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
4. PORTS
The number of I/O ports of the V850ES/Hx3 is shown below.
Product Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3
Number of ports 51 67 84 128
The following figure shows the basic configurations of ports.
(1/2)
(a) V850ES/HE3
P00
P06
Port 0
PCM0
PCM1 Port CM
P96
P99 Port 9
P913
P915
P90
P91
PDL0
PDL7
Port DL
P40
P42
Port 4
P50
P55
Port 5
P70
P79
Port 7
P30
P35
Port 3
(b) V850ES/HF3
P00
P06
Port 0
PCM0
PCM3
Port CM
PCS0
PCS1 Port CS
P96
P99 Port 9
P913
P915
P90
P91
PCT0
PCT1 Port CT
PCT4
PCT6
PDL0
PDL11
Port DL
P40
P42
Port 4
P50
P55
Port 5
P70
P711
Port 7
P30
P35
Port 3
P38
P39
Preliminary Product Information U18744EJ1V0PM
36
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
(2/2)
(c) V850ES/HG3
P00
P06
Port 0
P120
P127
Port 12
PCM0
PCM3
Port CM
PCT0
PCT1
PCT4
PCT6
Port CT
P90
P915
Port 9
PDL0
PDL13
Port DL
P30
P39
Port 3
Port 1
P40
P42
Port 4
P50
P55
Port 5
P70
P715
P10
P11
Port CS
PCS0
PSC1
Port 7
(d) V850ES/HJ3
P00
P06
Port 0
PCD0
PCD3
Port CD
P120
P127
Port 12
PCM0
PCM5
Port CM
PCS0
PCS7
PCT0
PCT7
Port CS
Port CT
P90
P915
Port 9
PDH0
PDH7
Port DH
PDL0
PDL15
Port DL
P30
P39
Port 3
Port 1
P40
P42
Port 4
P50
P55
Port 5
P60
P615
P70
P715
P80
P81
Port 6
P10
P11
Port 7
Port 8
Preliminary Product Information U18744EJ1V0PM 37
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
5. EXTERNAL BUS INTERFACE FUNCTION (V850ES/HJ3 ONLY)
The V850ES/HJ3 incorporate an external bus interface function that can be used to connect memories, such as
ROM or RAM, and peripheral I/O externally.
The external bus interface function has the following features.
{ Multiplexed bus output
{ 8-bit/16-bit data bus sizing function
{ Chip select function for four spaces
{ Wait function
• Programmable wait function
• External wait function
{ Idle state function
{ Bus hold function
The following pins are used for the external bus interface.
Table 5-1. List of Bus Control Pins
Bus Control Pin Alternate Function I/O Function
AD0 to AD15 PDL0 to PDL15 I/O Address/data bus
WAIT PCM0 Input External wait control
CLKOUT PCM1 Output Internal system clock
CS0 to CS3 PCS0 to PCS3 Output Chip select
WR0, WR1 PCT0, PCT1 Output Write strobe signal
RD PCT4 Output Read strobe signal
ASTB PCT6 Output Address strobe signal
HLDRQ PCM3 Input
HLDAK PCM2 Output
Bus hold control
Preliminary Product Information U18744EJ1V0PM
38
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
Figure 5-1. Timing Example in Multiplexed Bus Mode (Read → Write)
T1 T2 T3
CLKOUT (output)
AD0 to AD15 (I/O) DataAddress
ASTB (output)
RD (output)
WAIT (input)
WR0, WR1 (output)
T1 T2 T3
Data
Address
Remark The broken lines indicate high-impedance state.
Preliminary Product Information U18744EJ1V0PM 39
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
6. CLOCK GENERATION FUNCTION
The clock generation function has the following features.
{ Main clock oscillator
• PLL mode (×8): fX = 4 to 16 MHz (fXX = 12 to 32 MHz)
• Clock through mode: fX = 4 to 16 MHz (fXX = 4 to 16 MHz)
{ Subclock oscillator
• fXT = 32.768 kHz
{ Low-speed internal oscillator (fRL = 240 kHz)
• Default clock of watchdog timer
• Sampling clock for clock monitor function of the main clock oscillator
• Can be used as the internal system clock after the main clock is stopped
{ High-speed internal oscillator (fRH = 8 MHz)
• Can be used as the internal system clock
{ Internal system clock generation
• 7 levels (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
{ Peripheral clock generation
{ Clock output function
Preliminary Product Information U18744EJ1V0PM
40
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
The following figure shows the configuration of the clock generation function.
SELCNT0.ISEL07
PCC.CK[2:0]
f
xx
f
RL
f
RH
f
RH
Prescaler 3
PCC.CK3
IDLE
control Prescaler 2
WT, TMM0, TAA1,
TAA3, TAA5
WT, CSIB0
CLKOUT
(Internal system clock output)
Main clock
oscillator
PLL circuit
SSCG circuit
PLLCTL.SELPLL
XT1
Subclock
oscillator
Prescaler 1
Internal system clock
Peripheral clock
WDT2
PCC.FRC
PCC.MFRC
Main clock
oscillator
stop control
STOP mode
1/8
TMM0
Low-speed
internal
oscillator
1/128
PCL
Selector
1/8
UARTDn, TAAn
RCM.RSTOP
RCM.HRSTOP
PCC.MCK
PCLM.PCK[1:0]
PRSM0, PRSCM0 registers
WDT2, TMM0
MCM.MCM0
1
0
1
0
0
1
XT2
f
XT
f
X
f
X
f
PLSS
f
PLL
X1
X2
HALT
control
HALT mode
CPU clock
Detected illegal stop of main clock oscillator
when STOP mode is released.
f
PCL
f
XX
f
XX
/512
f
RH
/8
f
X
/128
f
BRG
f
XX
- f
XX
/1024
f
CPU
f
CLK
f
RL
/8
f
XT
f
XX
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
f
XX
/32
f
XT
f
RL
IDLE
control
1
0
IDLE1, IDLE2 mode
High-speed
internal
oscillator
High-speed
internal
oscillator
oscillation
control
Selector
Selector
Oscillation
illegal stop
detection
Remark fX: Main clock oscillation frequency
f
RH: High-speed internal oscillation frequency
f
RL: Low-speed internal oscillation frequency
f
XX: Main clock frequency
f
XT: Subclock frequency
f
CPU: CPU clock frequency
f
CLK: Internal system clock frequency
f
BRG: Watch timer clock frequency/baud rate count frequency
f
PCL: Programmable frequency
Preliminary Product Information U18744EJ1V0PM 41
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
7. 16-BIT TIMER/EVENT COUNTER AA (TAA)
The number of TAAs in the V850ES/Hx3 is shown below.
Product Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3
Number of channels 5 channels
(TAA0 to TAA4)
5 channels
(TAA0 to TAA4)
5 channels
(TAA0 to TAA4)
5 channels
(TAA0 to TAA4)
The timer/counter function has the following features.
• 16 bit timer/counter (TAAn)
• Clock selection: 8 ways
• Capture/trigger input pins: 2
• External event count input pin: 1
• External trigger input pin: 1
• Timer/counter: 1
• Capture/compare registers: 2
(32-bit capture function available by using a cascade connection with timer AA.)
• Capture/compare match interrupt request signals: 2
• Timer output pins: 2
The TAAn function has the following features.
• Interval timer
• External event counter
• External trigger pulse output
• One-shot pulse output
• PWM output
• Free-running timer
• Pulse width measurement
• Timer tuning function
Preliminary Product Information U18744EJ1V0PM
42
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
The following figure shows the configuration of TAA.
Internal bus
Internal bus
TAAnCNT
16-bit counter
TAAnCCR0
CCR0
buffer
register
TAAnCCR1
CCR1
buffer
register
Clear
INTTAAnOV
TOAAn0
TOAAn1
INTTAAnCC0
INTTAAnCC1
f
XX
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
f
XX
/32
f
XX
/64
f
XX
/128
TIAAn0
TIAAn1
Selector
Selector
Output
controller
Edge detector
Remark fXX = Main clock frequency
n = 0 to 4
Preliminary Product Information U18744EJ1V0PM 43
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
8. 16-BIT TIMER/EVENT COUNTER AB (TAB)
The number of TABs in the V850ES/Hx3 is shown below.
Product Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3
Number of channels 1 channel (TAB0) 1 channel (TAB0) 2 channels
(TAB0, TAB1)
3 channels
(TAB0 to TAB2)
The TAB function has the following features.
• 16-bit timer/counter (TABn)
• Clock selection: 8 ways
• Capture/trigger input pins: 4
• External event count input pin: 1
• External trigger input pin: 1
• Timer/counter: 1
• Capture/compare registers: 4
• Capture/compare match interrupt request signals: 4
• Timer output pins: 4
The TABn function has the following features.
• Interval timer
• External event counter
• External trigger pulse output
• One-shot pulse output
• PWM output
• Free-running timer
• Pulse width measurement
• Triangular wave PWM output
• Timer tuning function
Preliminary Product Information U18744EJ1V0PM
44
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
The following figure shows the configuration of TAB.
TAB0CNT
TABnCCR0
CCR0
buffer
register
TAB0CCR1
CCR1
buffer
register
TAB0CCR2
TOAB00
INTTAB0OV
CCR2
buffer
register
TAB0CCR3
CCR3
buffer
register
TOAB01
TOAB02
TOAB03
INTTAB0CC0
INTTAB0CC1
INTTAB0CC2
INTTAB0CC3
f
XX
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
f
XX
/32
f
XX
/64
f
XX
/128
TIABn0
TIABn1
TIABn2
TIABn3
Internal bus
Internal bus
16-bit counter
Clear
Selector
Selector
Output controller
Edge detector
Remark fXX: Main clock frequency
n = 0 (V850ES/HE3, V850ES/HF3)
n = 0, 1 (V850ES/HG3)
n = 0 to 2 (V850ES/HJ3)
Preliminary Product Information U18744EJ1V0PM 45
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
9. 16-BIT INTERVAL TIMER M (TMM)
The number of TMMs in the V850ES/Hx3 is shown below.
Product Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3
Number of channels 1 channel (TMM0) 1 channel (TMM0) 1 channel (TMM0) 1 channel (TMM0)
The TMM function has the following features.
• Interval function
• Clock selection: 8 ways
• 16 bit counter × 1 (Not available to counter lead in timer count operation)
• Compare register × 1 (Not available to write compare register in timer count operation)
• Compare match interrupt × 1
The following figure shows the configuration of TMM.
TM0CTL0
f
XX
f
XX
/2
f
XX
/4
f
XX
/64
f
XX
/512
INTWT
f
RL
/8
f
XT
Controller
Clear
INTTM0EQ0
TM0CMP0
TM0CE
TM0CKS2 TM0CKS1TM0CKS0
Internal bus
16-bit counter
Selector
Match
Remark f
XX: Main clock frequency
f
XT: Subclock frequency
f
RL: Low-speed internal oscillation frequency
INTWT: Watch timer interrupt request signal
Preliminary Product Information U18744EJ1V0PM
46
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
10. MOTOR CONTROL FUNCTION
The number of motor control functions of the V850ES/Hx3 is shown below.
Product Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3
Number of channels 1 channel 1 channel 1 channel 1 channel
Timer AB0 (TAB) and the TMQ0 option (TMQOPA0) can be used as an inverter function that controls a motor.
It performs a tuning operation with timer AA4 (TAA4) and A/D conversion of the A/D converter can be started when
the value of TMQ0 matches the value of TAA4. The following operations can be performed as motor control functions.
• 6-phase PWM output function with 16-bit resolution (with dead-timer, for upper and lower arms)
• Timer tuning operation function (tunable with TAA4)
• Cycle setting function (cycle can be changed during operation of crest or valley interrupt)
• Compare register rewriting: Anytime rewrite, batch rewrite, or intermittent rewrite
(selectable during TAB0 operation)
• Interrupt and transfer culling functions
• Dead-time setting function
• A/D trigger timing function of the A/D converter (four types of timing can be generated)
• 0% output and 100% output available
• 0% output and 100% output selectable by crest interrupt and valley interrupt
• Forced output stop function
• At valid edge detection by external pin input (INTP1, INTP3)
Preliminary Product Information U18744EJ1V0PM 47
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
The following figure shows the configuration of motor control function.
Carrier
3-phase PWM
generation
TAB0
3-phase PWM
generation with
dead time from
3-phase PWM
Culling control
A/D trigger selection
TAB option
A/D trigger timing
generation in
tuning operation
with TMQ0
TAA4
• PWM generation
TAA3
• Interrupt control
INTC
High-impedance
output
controller
TOAB0T1
TOAB0B1
TOAB0T2
TOAB0B2
TOAB0T3
TOAB0B3
TOAA31
TOAB00
INTP1
Valley interrupt
(INTTAB0OV)
Crest interrupt
(INTTAB0CC0)
Edge detection
Edge detection
Noise elimination
INTP3
Noise elimination
A/D trigger of A/D converter
•
•
•
•
•
•
Preliminary Product Information U18744EJ1V0PM
48
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
11. WATCH TIMER
The number of watch timer in the V850ES/Hx3 is shown below.
Product Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3
Number of channels 1 channel 1 channel 1 channel 1 channel
The watch timer has the following functions.
• Watch timer: An interrupt request signal (INTWT) is generated at intervals of 0.5 or 0.25 seconds by using
the main clock or subclock.
• Interval timer: An interrupt request signal (INTWTI) is generated at set intervals.
The watch timer and interval timer functions can be used at the same time.
Preliminary Product Information U18744EJ1V0PM 49
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
The following figure shows the configuration of watch timer.
Internal bus
Watch timer operation mode register
(WTM)
f
BRG
f
W
/2
4
f
W
/2
5
f
W
/2
6
f
W
/2
7
f
W
/2
8
fW/210 fW/211
f
W
/2
9
f
XT
11-bit prescaler
Clear
Clear
INTWT
CSIB
INTWTI
WTM0WTM1WTM2WTM3WTM4WTM5WTM6WTM7
5-bit counter
f
W
3
f
X
f
X
/8
f
X
/4
f
X
/2
f
X
BGCS00BGCS01BGCE0
3-bit
prescaler
8-bit counter
Clear
Match
f
BGCS
PRSM0 register
PRSCM0 register
2
Internal bus
Clock
control
1/2
Selector
Selector
SelectorSelector
Selector
Remark fX: Main clock oscillation frequency
fBGCS: Watch timer source clock frequency
fBRG: Watch timer count clock frequency
fXT: Subclock frequency
fW: Watch timer clock frequency
INTWT: Watch timer interrupt request signal
INTWTI: Interval timer interrupt request signal
Preliminary Product Information U18744EJ1V0PM
50
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
12. WATCHDOG TIMER 2 FUNCTIONS
The number of watchdog timers in the V850ES/Hx3 is shown below.
Product Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3
Number of channels 1 channel 1 channel 1 channel 1 channel
The watchdog timer has the following functions.
• Reset mode: Reset operation upon overflow of watchdog timer (generates the
WDTRES signal)
• Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer (generates the
INTWDT signal)
The following figure shows the configuration of the watchdog timer functions.
fX/27Clock
input
controller
Output
controller WDT2RES
(internal reset signal)
WDCS22
Internal bus
INTWDT2
WDCS21 WDCS20
fRL/23
WDCS23WDCS24
0WDM21 WDM20
Selector
16-bit
counter
fX/216 to fX/223,
fRL/212 to fRL/219
Watchdog timer enable
register (WDTE) Watchdog timer mode
register 2 (WDTM2)
33
2Clear
Remark fXX: Main clock frequency
fRL: Low-speed internal oscillation clock frequency
INTWDT2: Non-maskable interrupt request signal from watchdog timer 2
WDTRES2: Watchdog timer 2 reset signal
Preliminary Product Information U18744EJ1V0PM 51
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
13. A/D CONVERTER
The number of A/D converter in the V850ES/Hx3 is shown below.
Product Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3
Number of mounted 1 channel 1 channel 1 channel 1 channel
Number of ANI channels 10 channels 12 channels 16 channels 24 channels
The A/D converter has the following features.
{ 10-bit resolution
{ 10/12/16/24 channels
{ Successive approximation method
{ Operating voltage: AVREF0 = 4.0 to 5.5 V
{ Analog input voltage: 0 V to AVREF0
{ The following functions are provided as operation modes.
• Continuous select mode
• Continuous scan mode
• One-shot select mode
• One-shot scan mode
{ The following functions are provided as trigger modes.
• Software trigger mode
• External trigger mode (external, 1)
• Timer trigger mode
{ Power-fail monitor function (conversion result compare function)
Preliminary Product Information U18744EJ1V0PM
52
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
The following figure shows the configuration of the A/D converter.
ANI0
:
:
:
:
ANI1
ANI2
ANIm
ADA0M2
ADA0M1ADA0M0 ADA0S
ADA0PFT
Controller
Voltage
comparator
ADA0PFM
ADA0CR0
ADA0CR1
.
.
.
ADA0CR2
ADA0CR14
ADA0CR15
Internal bus
AV
REF0
ADA0CE bit
AV
SS
INTAD
Edge
detection
ADTRG
Controller
Sample & hold circuit
ADA0ETS0 bit
INTTP2CC0
INTTP2CC1
ADA0ETS1 bit
ADA0CE bit
ADA0TMD1 bit
ADA0TMD0 bit
ADA0PFE bit
ADA0PFC bit
SAR
Voltage comparator
&
Compare voltage
generation DAC
Selector
Selector
Remark m = 9 (V850ES/HE3)
m = 11 (V850ES/HF3)
m = 15 (V850ES/HG3)
m = 23 (V850ES/HJ3)
Preliminary Product Information U18744EJ1V0PM 53
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
14. ASYNCHRONOUS SERIAL INTERFACE D (UARTD)
The number of UARTDs in the V850ES/Hx3 is shown below.
V850ES/HJ3 Product Name V850ES/HE3 V850ES/HF3 V850ES/HG3
μ
PD70F3755
μ
PD70F3757
Number of channels 2 channels 2 channels 3 channels 3 channels 6 channels
{ Transfer rate: 300 bps to 1.5 Mbps (using internal system clock of 32 MHz and dedicated baud rate generator)
{ Full-duplex communication: On-chip UARTDn receive data register (UDnRX)
On-chip UARTDn transmit data register (UDnTX)
{ 2-pin configuration: TXDDn: Transmit data output pin
RXDDn: Receive data input pin
{ Reception error detect function
• Parity error
• Framing error
• Overrun error
• LIN communication data consistency error detect function
• SBF reception success detect function
{ Interrupt sources: 3 types
• Reception completion interrupt (INTUDnR): This interrupt occurs upon transfer of receive data from the
receive shift register to receive data register after serial transfer
completion, in the reception enabled status.
• Transmission enable interrupt (INTUDnT): This interrupt occurs upon transfer of transmit data from the
transmit data register to the transmit shift register in the
transmission enabled status.
• Status interrupt (INTUDnS): This interrupt occurs upon detection of a reception error, a LIN
communication data consistency error, or SBF reception
success.
{ Character length: 7, 8 bits
{ Parity function: Odd, even, 0, none
{ Transmission stop bit: 1, 2 bits
{ On-chip dedicated baud rate generator
{ MSB-/LSB-first transfer selectable
{ Transmit/receive data inverted input/output possible
{ SBF (Sync Break Field) transmission/reception in the LIN (Local Interconnect Network) communication format
possible
• 13 to 20 bits are selectable for SBF transmission
• Recognition of 11 bits or more possible for SBF reception in LIN format
• SBF reception flag provided
• Function to check consistency of transmit data (the function to compare transmit data and receive data, and
detect mismatch) is available
Remark n = 0, 1 (V850ES/HE3, V850ES/HF3)
n = 0 to 2 (V850ES/HG3,
μ
PD70F3755)
n = 0 to 5 (
μ
PD70F3757)
Preliminary Product Information U18744EJ1V0PM
54
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
The following figure shows the configuration of UARTD.
Internal bus
UDnOPT0UDnCTL0 UDnSTR
UDnCTL1
UDnCTL2
Receive
shift register
UDnRX
Filter
Selector
UDnTX
Transmission
controller
Reception
controller
Baud rate
generator
INTUDnR
INTUDnS
INTUDnT
TXDDn
RXDDn
f
XX
to f
XX
/1,024
ASCKD0
Note
Reception unit Transmission
unit
Transmit
shift register
Baud rate
generator
Selector
UDnOPT1
Internal bus
Transmit/
receive data
comparison
Clock selector
Note UARTD0 only
Preliminary Product Information U18744EJ1V0PM 55
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
15. 3-WIRE VARIABLE-LENGTH SERIAL INTERFACE B (CSIB)
The number of CSIB in the V850ES/Hx3 is shown below.
Product Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3
Number of channels 2 channels 2 channels 2 channels 3 channels
{ Transfer rate: 8 Mbps max. (fXX = 32 MHz, using internal clock)
{ Master mode and slave mode selectable
{ 8-bit to 16-bit transfer, 3-wire serial interface
{ Interrupt request signals (INTCBnT, INTCBnR) × 2
{ Serial clock and data phase switchable
{ Transfer data length selectable in 1-bit units between 8 and 16 bits
{ Transfer data MSB-first/LSB-first switchable
{ 3-wire transfer SOBn: Serial data output
SIBn: Serial data input
SCKBn: Serial clock I/O
Transmission mode, reception mode, and transmission/reception mode specifiable
Remark n = 0 to 2 (V850ES/HE3, V850ES/HF3, V850ES/HG3)
n = 0 to 3 (V850ES/HJ3)
Preliminary Product Information U18744EJ1V0PM
56
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
The following figure shows the configuration of CSIB.
Internal bus
CBnCTL2CBnCTL0
CBnSTR
Controller
INTCBnR
SOBn
INTCBnT
CBnTX
SO latch
Shift register
CBnRX
CBnCTL1
Phase control
SIBn
Note
f
CCLK
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
f
XX
/32
f
XX
/64
SCKBn
Selector
Phase
control
Note n = 0 (fBRG)
n = 1 (TOAA01)
n = 2, 3 (fXX/128)
Remark n = 0 to 2 (V850ES/HE3, V850ES/HF3, V850ES/HG3)
n = 0 to 3 (V850ES/HJ3)
Preliminary Product Information U18744EJ1V0PM 57
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
16. I2C BUS
The number of I2C of the V850ES/Hx3 is shown below.
Product Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3
Number of channels 1 channel 1 channel 1 channel 1 channel
{ Transfer rate: Standard mode (100 kbps max.)/high-speed mode (400 kbps max.)
{ Conforms to I2C bus format (multimaster supported)
{ 2-wire SCL00: Serial clock pin
SDA00: Serial data bus pin
Preliminary Product Information U18744EJ1V0PM
58
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
The following figure shows the configuration of I2C.
Internal bus
IIC status register 0 (IICS0)
IIC control register 0
(IICC0)
Slave address
register 0 (SVA0)
Noise
eliminator
Noise
eliminator
Bus status
detector
Match
signal
IIC shift
register 0 (IIC0)
SO latch
IICE0
DQ
Set
Clear
CL01,
CL00
TRC0
DFC0
DFC0
SDA00
SCL00
N-ch open-drain
output
N-ch open-drain
output
Data
retention time
correction
circuit
Start
condition
generator
Stop
condition
generator
ACK
generator Wakeup controller
ACK detector
Output control
Stop condition
detector
Serial clock counter
Interrupt request
signal generator
Serial clock
controller
Serial clock
wait controller
Prescaler
INTIIC0
IIC shift register 0
(IIC0)
IICC0.STT0, SPT0
IICS0.MSTS0, EXC0, COI0
IICS0.MSTS0,
EXC0, COI0
LREL0
WREL0
SPIE0
WTIM0
ACKE0
STT0 SPT0
MSTS0
ALD0 EXC0 COI0 TRC0
ACKD0
STD0 SPD0
Start condition
detector
Internal bus
CLD0 DAD0 SMC0 DFC0 CL01 CL00 CLX0
IIC clock select
register 0 (IICCL0)
STCF0
IICBSY0 STCEN0 IICRSV0
IIC flag register 0
(IICF0)
IIC function expansion
register 0 (IICX0)
fxx
IIC division clock select
register 0 (OCKS0)
fxx to fxx/5
Prescaler
OCKSTH0OCKSEN0 OCKS01 OCKS00
Preliminary Product Information U18744EJ1V0PM 59
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
17. DMA CONTROLLER
The number of DMA controller of the V850ES/Hx3 is shown below.
Product Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3
Number of channels 4 channels 4 channels 4 channels 4 channels
{ 4 independent DMA channels
{ Transfer unit: 8/16 bits
{ Maximum transfer count: 65,536 (216)
{ Transfer type: Two-cycle transfer
{ Transfer mode: Single transfer mode
{ Transfer requests
• Request by interrupts from on-chip peripheral I/O (serial interface, timer/counter, A/D converter) or interrupts
from external input pin
• Requests by software trigger
{Transfer targets
• Internal RAM ⇔ Peripheral I/O
• Peripheral I/O ⇔ Peripheral I/O
• Internal RAM ⇔ External memoryNote
• External memory ⇔ Peripheral I/ONote
• External memory ⇔ External memoryNote
Note V850ES/HJ3 only
Preliminary Product Information U18744EJ1V0PM
60
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
The following figure shows the configuration of DMA controller.
CPU
Internal RAM On-chip
peripheral I/O
On-chip peripheral I/O bus
Internal bus
Data
control
Address
control
Count
control
Channel
control
DMAC
Bus interface
External bus
External
RAM
Note
External
ROM
Note
External
I/O
Note
DMA source address
register n (DSAnH/DSAnL)
DMA transfer count
register n (DBCn)
DMA channel control
register n (DCHCn)
DMA destination address
register n (DDAnH/DDAnL)
DMA addressing control
register n (DADCn)
DMA trigger factor
register n (DTFRn)
Note V850ES/HJ3 only
Remark n = 0 to 3
Preliminary Product Information U18744EJ1V0PM 61
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
18. INTERRUPT/EXCEPTION PROCESSING FUNCTION
The features of interrupt/exception processing function is shown below.
{ Interrupts
Internal External
Non maskable Maskable Total Non maskable Maskable Total
V850ES/HE3
μ
PD70F3747 1 42 43 1 8 9
V850ES/HF3
μ
PD70F3750 1 42 43 1 8 9
V850ES/HG3
μ
PD70F3752 1 50 51 1 11 12
μ
PD70F3755 1 57 58 1 15 16 V850ES/HJ3
μ
PD70F3757 1 63 64 1 15 16
• 8 levels of programmable priorities
• Masks interrupt requests according to priority
• Masks can be specified for each maskable interrupt request.
• Noise elimination, edge detection, and valid edge specification for external interrupt request signals.
{ Exceptions
• Software exceptions: 32 sources
• Exception trap: 2 sources (illegal opcode exception, debug trap)
Interrupt/exception sources are listed in Table 18-1.
Preliminary Product Information U18744EJ1V0PM
62
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
Table 18-1. Interrupt Source List (1/3)
Interrupt/Exception Source Type
Name Interrupt
Control
Register
Generating Source Generating
Unit
Default
Priority
V850ES/
HE3
V850ES/
HF3
V850ES/
HG3
V850ES/
HJ3
Reset RESET − RESET input from internal source Reset − √ √ √ √
NMI − NMI pin valid edge input Pin − √ √ √ √ Non-
maskable INTWDT2 − WDT2 overflow WDT2 − √ √ √ √
TRAP0n
(n = 0 to FH)
− TRAP instruction − − √ √ √ √ Software
exception
TRAP1n
(n = 0 to FH)
− TRAP instruction − − √ √ √ √
Exception
trap
ILGOP/
DBG0
− Illegal instruction code/DBTRAP instruction − − √ √ √ √
INTLVIL LVILIC Detection of low voltage (voltage under
reference level)
LVI 0 √ √ √ √
INTLVIH LVIHIC Detection of low voltage (voltage over
reference level)
LVI 1 √ √ √ √
INTP0 PIC0 External interrupt 0 (INTP0) Pin 2 √ √ √ √
INTP1 PIC1 External interrupt 1 (INTP1) Pin 3 √ √ √ √
INTP2 PIC2 External interrupt 2 (INTP2) Pin 4 √ √ √ √
INTP3 PIC3 External interrupt 3 (INTP3) Pin 5 √ √ √ √
INTP4 PIC4 External interrupt 4 (INTP4) Pin 6 √ √ √ √
INTP5 PIC5 External interrupt 5 (INTP5) Pin 7 √ √ √ √
INTP6 PIC6 External interrupt 6 (INTP6) Pin 8 √ √ √ √
INTP7 PIC7 External interrupt 7 (INTP7) Pin 9 √ √ √ √
INTTAB0OV TAB0OVIC TAB0 overflow TAB0 10 √ √ √ √
INTTAB0CC0 TAB0CCIC0 TAB0 capture 0/compare 0 match TAB0 11 √ √ √ √
INTTAB0CC1 TAB0CCIC1 TAB0 capture 1/compare 1 match TAB0 12 √ √ √ √
INTTAB0CC2 TAB0CCIC2 TAB0 capture 2/compare 2 match TAB0 13 √ √ √ √
INTTAB0CC3 TAB0CCIC3 TAB0 capture 3/compare 3 match TAB0 14 √ √ √ √
INTTAA0OV TAA0OVIC TAA0 overflow TAA0 15 √ √ √ √
INTTAA0CC0 TAA0CCIC0 TAA0 capture 0/compare 0 match TAA0 16 √ √ √ √
INTTAA0CC1 TAA0CCIC1 TAA0 capture 1/compare 1 match TAA0 17 √ √ √ √
INTTAA1OV TAA1OVIC TAA1 overflow TAA1 18 √ √ √ √
INTTAA1CC0 TAA1CCIC0 TAA1 capture 0/compare 0 match TAA1 19 √ √ √ √
INTTAA1CC1 TAA1CCIC1 TAA1 capture 1/compare 1 match TAA1 20 √ √ √ √
INTTAA2OV TAA2OVIC TAA2 overflow TAA2 21 √ √ √ √
INTTAA2CC0 TAA2CCIC0 TAA2 capture 0/compare 0 match TAA2 22 √ √ √ √
INTTAA2CC1 TAA2CCIC1 TAA2 capture 1/compare 1 match TAA2 23 √ √ √ √
INTTAA3OV TAA3OVIC TAA3 overflow TAA3 24 √ √ √ √
INTTAA3CC0 TAA3CCIC0 TAA3 capture 0/compare 0 match TAA3 25 √ √ √ √
INTTAA3CC1 TAA3CCIC1 TAA3 capture 1/compare 1 match TAA3 26 √ √ √ √
INTTAA4OV TAA4OVIC TAA4 overflow TAA4 27 √ √ √ √
INTTAA4CC0 TAA4CCIC0 TAA4 capture 0/compare 0 match TAA4 28 √ √ √ √
INTTAA4CC1 TAA4CCIC1 TAA4 capture 1/compare 1 match TAA4 29 √ √ √ √
INTTM0EQ0 TM0EQIC0 TMM0 compare match TMM0 30 √ √ √ √
INTCB0R CB0RIC CSIB0 reception completion/reception error CSIB0 31 √ √ √ √
Maskable
INTCB0T CB0TIC CSIB0 continuous transfer write enable CSIB0 32 √ √ √ √
Preliminary Product Information U18744EJ1V0PM 63
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
Table 18-1. Interrupt Source List (2/3)
Interrupt/Exception Source Type
Name Interrupt
Control
Register
Generating Source Generating
Unit
Default
Priority
V850ES/
HE3
V850ES/
HF3
V850ES/
HG3
V850ES/
HJ3
INTCB1R CB1RIC CSIB1 reception completion/error CSIB1 33 √ √ √ √
INTCB1T CB1TIC CSIB1 continuous transfer write enable CSIB1 34 √ √ √ √
INTUD0S UD0SIC UARTD0 status interrupt UARTD0 35 √ √ √ √
INTUD0R UD0RIC UARTD0 reception completion UARTD0 36 √ √ √ √
INTUD0T UD0TIC UARTD0 continuous transfer enable UARTD0 37 √ √ √ √
INTUD1S UD1SIC UARTD1 status interrupt UARTD1 38 √ √ √ √
INTUD1R UD1RIC UARTD1 reception completion UARTD1 39 √ √ √ √
INTUD1T UD1TIC UARTD1 continuous transfer enable UARTD1 40 √ √ √ √
INTIIC0 IIC0IC IIC0 reception completion IIC0 √ √ √ √
INTUD4S UD4SIC UARTD4 status interrupt UARTD4
41
√Note
INTAD ADIC A/D converter completion AD 42 √ √ √ √
INTDMA0 DMAIC0 DMA0 transfer completion DMA 43 √ √ √ √
INTDMA1 DMAIC1 DMA1 transfer completion DMA 44 √ √ √ √
INTDMA2 DMAIC2 DMA2 transfer completion DMA 45 √ √ √ √
INTDMA3 DMAIC3 DMA3 transfer completion DMA 46 √ √ √ √
INTKR KRIC Key return interrupt KR 47 √ √ √ √
INTWTI WTIIC Interval of watch timer WT 48 √ √ √ √
INTWT WTIC Reference time of watch timer WT 49 √ √ √ √
INTP8 PIC8 External interrupt 8 (INTP8) Pin 50 √ √
INTP9 PIC9 External interrupt 9 (INTP9) Pin 51 √ √
INTP10 PIC10 External interrupt 10 (INTP10) Pin 52 √ √
INTTAB1OV TAB1OVIC TAB1 overflow TAB1 53 √ √
INTTAB1CC0 TAB1CCIC0 TAB1 capture 0/compare 0 match TAB1 54 √ √
INTTAB1CC1 TAB1CCIC1 TAB1 capture 1/compare 1 match TAB1 55 √ √
INTTAB1CC2 TAB1CCIC2 TAB1 capture 2/compare 2 match TAB1 56 √ √
INTTAB1CC3 TAB1CCIC3 TAB1 capture 2/compare 3 match TAB1 57 √ √
INTUD2S UD2SIC UARTD2 status interrupt UARTD2 58 √ √
INTUD2R UD2RIC UARTD2 reception completion UARTD2 59 √ √
INTUD2T UD2TIC UARTD2 continuous transfer enable UARTD2 60 √ √
INTP11 PIC11 External interrupt 11 (INTP11) Pin 61 √
INTP12 PIC12 External interrupt 12 (INTP12) Pin 62 √
INTP13 PIC13 External interrupt 13 (INTP13) Pin 63 √
INTP14 PIC14 External interrupt 14 (INTP14) Pin 64 √
INTUD3S UD3SIC UARTD3 status interrupt UARTD3 65
√Note
INTUD3R UD3RIC UARTD3 reception completion UARTD3 66 √Note
INTUD3T UD3TIC UARTD3 continuous transfer enable UARTD3 67 √Note
INTUD4R UD4RIC UARTD4 reception completion UARTD4 68 √Note
INTUD4T UD4TIC UARTD4 continuous transfer enable UARTD4 69 √Note
INTTAB2OV TAB2OVIC TAB2 overflow TAB2 70 √
Maskable
INTTAB2CC00 TAB2CCIC0 TAB2 capture 0/compare 0 match TAB2 71 √
Note
μ
PD70F3757 only
Preliminary Product Information U18744EJ1V0PM
64
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
Table 18-1. Interrupt Source List (3/3)
Interrupt/Exception Source Type
Name Interrupt
Control
Register
Generating Source Generating
Unit
Default
Priority
V850ES/
HE3
V850ES/
HF3
V850ES/
HG3
V850ES/
HJ3
INTTAB2CC01 TAB2CCIC1 TAB2 capture 1/compare 1 match TAB2 72 √
INTTAB2CC02 TAB2CCIC2 TAB2 capture 2/compare 2 match TAB2 73 √
INTTAB2CC03 TAB2CCIC3 TAB2 capture 3/compare 3 match TAB2 74 √
INTUD5S UD5SIC UARTD5 status interrupt UARTD5 75 √Note
INTCB2R CB2RIC CSIB2 reception completion/error CSIB2 √
INTUD5R UD5RIC UARTD5 reception completion UARTD5
76
√Note
INTCB2T CB2TIC CSIB2 continuous transfer write enable CSIB2 √
Maskable
INTUD5T UD5TIC UARTD5 continuous transfer enable UARTD5
77
√Note
Note
μ
PD70F3757 only
Preliminary Product Information U18744EJ1V0PM 65
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
19. KEY INTERRUPT FUNCTION
The number of key interrupt of the V850ES/Hx3 is shown below.
Product Name V850ES/HE3 V850ES/HF3 V850ES/HG3 V850ES/HJ3
Number of channels 1 channel 1 channel 1 channel 1 channel
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0
to KR7).
The following figure shows the configuration of key interrupt.
INTKR
Key return mode register (KRM)
KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0
KR7
KR6
KR5
KR4
KR3
KR2
KR1
KR0
Preliminary Product Information U18744EJ1V0PM
66
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
20. STANDBY FUNCTION
The power consumption of the system can be effectively reduced by using the standby modes in combination and
selecting the appropriate mode for the application. The available standby modes are listed in Table 20-1.
Table 20-1. Standby Modes
Mode Function Overview
HALT mode Mode to stop only the operating clock of the CPU
IDLE1 mode Mode to stop all the operations of the internal circuit except the oscillator, PLL operationNote,
and flash memory
IDLE2 mode Mode to stop all the operations of the internal circuit except the oscillator
STOP mode Mode to stop all the operations of the internal circuit except the subclock oscillator
Subclock operation mode Mode to operate internal system clock by subclock
Sub-IDLE mode Mode to stop all the operations of the internal circuit except the oscillator in subclock
operation mode
Note PLL retains the previous operation status.
The following figure shows the status transitions of the standby function.
Reset
Subclock operation mode
(fx operates, PLL operates)
Subclock operation mode
(fx stops, PLL stops)
Sub-IDLE mode
(fx operates, PLL operates)
Sub-IDLE mode
(fx stops, PLL stops)
STOP mode
(fx stops, PLL stops)
IDLE2 mode
(fx operates, PLL stops)
IDLE1 mode
(fx operates, PLL operates)
IDLE1 mode
(fx operates, PLL stops)
HALT mode
(fx operates, PLL stops)
HALT mode
(fx operates, PLL operates)
Normal operation mode
Oscillation
stabilization wait
Clock through mode
(PLL operates)
Clock through mode
(PLL stops)
PLL mode
(PLL operates)
Internal oscillation
clock operation
WDT overflow
Oscillation
stabilization wait
PLL lockup
time wait
Oscillation
stabilization wait
Oscillation
stabilization wait
Preliminary Product Information U18744EJ1V0PM 67
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
21. RESET FUNCTIONS
The following reset functions are available.
(1) Five types of reset sources
• External reset input via the RESET pin
• Reset via the watchdog timer 2 (WDT2) overflow (WDT2RES)
• System reset by comparing the supply voltage and detection voltage by using the low-voltage detector (LVI)
• System reset by the clock monitor (CLM) upon detection of oscillation stop
• System reset by comparing the supply voltage and detection voltage by using the power-on-clear (POC)
circuit
After a reset is released, the source of the reset can be confirmed with the reset source flag register (RESF).
(2) Emergency operation mode
If the WDT2 overflows during the main clock oscillation stabilization time inserted after reset, a main clock
oscillation anomaly is judged and the CPU starts operating on the internal oscillation clock.
The outline of the reset functions is shown below.
CLMRF LVIRF
WDT2RF
Reset source flag
register (RESF)
Internal bus
WDT2 reset signal
CLM reset signal
POC reset signal
RESET
LVI reset signal
Reset signal
Reset signal
Reset signal to
LVIM/LVIS register
Clear
SetSet
Clear Clear
Set
Preliminary Product Information U18744EJ1V0PM
68
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
22. CLOCK MONITOR, POWER-ON-CLEAR CIRCUIT, LOW-VOLTAGE DETECTOR
(1) Clock monitor
The clock monitor samples the main clock by using the low-speed internal oscillation clock (fRL) and generates
a reset request signal when oscillation of the main clock is stopped.
(2) Power-on-clear circuit
Functions of the power-on-clear (POC) circuit are shown below.
• Generates a reset signal upon power application.
• Compares the supply voltage (VDD) and detection voltage (VPOC0), and generates a reset signal when VDD <
VPOC0 (detection voltage (VPOC0): 3.5 V ±0.2 V).
(3) Low-voltage detector
The low-voltage detector (LVI) has the following functions.
• Compares the supply voltage (VDD) and detection voltage (VLVI) and generates an interrupt request signal or
internal reset signal when VDD < VLVI.
• The level of the supply voltage to be detected can be changed by software (in two steps).
• An interrupt request signal or internal reset signal can be selected.
• Can operate in STOP mode.
• Operation can be stopped by software.
Preliminary Product Information U18744EJ1V0PM 69
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
23. REGULATOR FUNCTION
The V850ES/Hx3 includes a regulator to reduce power consumption and noise.
This regulator supplies a stepped-down VDD power supply voltage to the oscillator block and internal logic circuits
except the A/D converter and output buffers). The regulator output voltage is set to 2.5 V (TYP.).
The outline of the regulator functions is shown below.
(1/2)
(a) V850ES/HE3, V850ES/HF3
EV
DD
I/O buffer
Regulator
Sub-oscillator
A/D converter
EV
DD
AV
REF0
FLMD0
V
DD
EV
DD
REGC
Main
oscillator
Internal digital circuits
2.5 V (TYP.)
Flash
memory
Bidirectional level shifter
(b) V850ES/HG3
EV
DD
I/O buffer
BV
DD
I/O buffer
Regulator
Sub-oscillator
A/D converter
BV
DD
AV
REF0
FLMD0
V
DD
EV
DD
REGC
Internal digital circuits
2.5 V (TYP.)
Main
oscillator
Flash
memory
Bidirectional level shifter
Preliminary Product Information U18744EJ1V0PM
70
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
(2/2)
(c) V850ES/HJ3
EVDD I/O buffer
Bidirectional level shifter
BVDD I/O buffer
Regulator
Sub-oscillator
A/D converter
BVDD/VDD
AVREF0
FLMD0
VDD
EVDD
REGC
Flash
memory
Internal digital circuits
2.5 V (TYP.)
Regulator
Main
oscillator
Preliminary Product Information U18744EJ1V0PM 71
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
24. FLASH MEMORY
Flash memory versions offer the following advantages for development environments and mass production
applications.
{ For altering software after the V850ES/Hx3 is soldered onto the target system.
{ For data adjustment when starting mass production.
{ For differentiating software according to the specification in small scale production of various models.
{ For facilitating inventory management.
{ For updating software after shipment.
The flash memory in the V850ES/Hx3 has the following features.
{ 4-byte/1-clock access (when instruction is fetched)
{ Capacity: 128/256/512 KB
{ Rewrite voltage: Erase/write with a single power supply
{ Rewriting method
• Rewriting by communication with dedicated flash programmer via serial interface (on-board/off-board
programming)
• Rewriting flash memory by user program (self programming)
{ Flash memory write prohibit function supported (security function)
{ Safe rewriting of entire flash memory area by self programming using boot swap function
{ Interrupts can be acknowledged during self programming.
Preliminary Product Information U18744EJ1V0PM
72
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
25. ON-CHIP DEBUG FUNCTION
Debugging can be implemented with the V850ES/Hx3 mounted on the target system.
The NEC Electronics on-chip debug emulators MINICUBE and MINICUBE2 are planned to support the
V850ES/Hx3.
{ MINICUBE
An on-chip debug function is implemented by using the DCU (debug control unit) in the V850ES/Hx3, using the
DRST, DCK, DMS, DDI, and DDO pins as the debug interface pins.
{ MINICUBE2
An on-chip debug function is implemented by using the user resources (on-chip flash memory, internal RAM,
etc.) instead of the DCU, and using the SIB0, SOB0, and SCKB0 pins or the RXDD0 and TXDD0 pins as the
interface pins.
Preliminary Product Information U18744EJ1V0PM 73
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
26. PACKAGE DRAWINGS
• V850ES/HE3
S
y
e
Sxb
M
θ
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
A3
S
0.125 +0.075
−0.025
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
10.00±0.20
10.00±0.20
12.00±0.20
12.00±0.20
1.60 MAX.
0.10±0.05
1.40±0.05
0.25
c
θ
e
x
y
ZD
ZE
0.50
0.08
0.08
1.25
1.25
L
Lp
L1
0.50
0.60±0.15
1.00±0.20
P64GB-50-GAH
3°+5°
−3°
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
detail of lead end
0.20
b
16
32
1
64 17
33
49
48
64-PIN PLASTIC LQFP(FINE PITCH)(10x10)
+0.07
−0.03
Preliminary Product Information U18744EJ1V0PM
74
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
• V850ES/HF3
S
y
e
Sxb M
θ
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
A3
S
0.125 +0.075
−0.025
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
12.00±0.20
12.00±0.20
14.00±0.20
14.00±0.20
1.60 MAX.
0.10±0.05
1.40±0.05
0.25
c
θ
e
x
y
ZD
ZE
0.50
0.08
0.08
1.25
1.25
L
Lp
L1
0.50
0.60±0.15
1.00±0.20
P80GK-50-GAK
3°+5°
−3°
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
detail of lead end
0.20
b
20
40
1
80 21
41
61
60
80-PIN PLASTIC LQFP (FINE PITCH) (12x12)
+0.07
−0.03
Preliminary Product Information U18744EJ1V0PM 75
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
• V850ES/HG3
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
S
y
e
Sxb
M
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
A3
S
0.125
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
14.00±0.20
14.00±0.20
16.00±0.20
16.00±0.20
1.60 MAX.
0.10±0.05
1.40±
+
+
+
0.05
0.25
c
e
x
θ
θ
y
ZD
ZE
0.50
0.08
0.08
1.00
1.00
L
Lp
L1
0.50
0.60±0.15
1.00±0.20
P100GC-50-UEU-1
NEC Electronics Corporation 2007
3°3°
5°
detail of lead end
0.20 0.07
0.075
0.025
0.03
b
25
50
1
100 26
51
75
76
Preliminary Product Information U18744EJ1V0PM
76
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
• V850ES/HJ3
144-PIN PLASTIC LQFP (FINE PITCH) (20x20)
S
y
e
Sxb M
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
A3
S
0.125
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
20.00±0.20
20.00±0.20
22.00±0.20
22.00±0.20
1.60 MAX.
0.10±0.05
1.40±0.05
0.25
c
e
x
y
ZD
ZE
0.50
0.08
0.08
1.25
1.25
L
Lp
L1
0.50
0.60±0.15
1.00±0.20
P144GJ-50-GAE-1
3°
detail of lead end
0.20
b
36
72
1
144 37
73
108
109
+0.07
0.03
+0.075
0.025
+3°
5°
θ
θ
NEC Electronics Corporation 2007
Preliminary Product Information U18744EJ1V0PM 77
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
APPENDIX A. DEVELOPMENT TOOLS
(1) Hardware
Product Name Description
Full-function in-circuit emulator (IECUBE®) QB-V850ESFX3Note In-circuit emulator for V850ES/Hx3, V850ES/Fx3
On-chip debug emulator (MINICUBE) QB-V850MININote Emulator for on-chip debugging
On-chip emulator with programming function
(MINICUBE2)
QB-MINI2Note Emulator for on-chip debugging. Also used as a
programmer.
Flash programmer (Flash Pro IV) PG-FP4Note Flash programmer for writing programs to products with
a single-power supply flash memory
Flash programmer (Flash Pro V) PG-FP5Note Flash programmer for writing programs to products with
a single-power supply flash memory
Note Under development
(2) Software
Product Name Description
Compiler CA850Note C compiler conforming to ANSI-C standards
Debugger ID850QBNote Used in combination with in-circuit emulator
Real-time OS RX850Note, RX850 ProNote Real-time OS conforming to
μ
ITRON specifications
Project Manager PM+Note Integrated development environment platform
Device file DF703757Note Definition file for V850ES/Hx3
Note Under development
Preliminary Product Information U18744EJ1V0PM
78
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
APPENDIX B. COMPARISON BETWEEN V850ES/Hx3 AND V850ES/Hx2
Table B-1. Major Differences Between V850ES/Hx3 and V850ES/Hx2
Major Difference V850ES/Hx3 V850ES/Hx2
Minimum instruction execution time 31.25 ns (32 MHz operation) 50 ns (20 MHz operation)
SSCG Available None
High-speed internal oscillator Available (fRH = 8 MHz (TYP.)) None
Low-speed internal oscillator Available (fRL = 240 kHz (TYP.)) Available (fRL = 200 kHz (TYP.))
TAA (high-performance type of TMP) TMP 16-bit timer
TAB (high-performance type of TMQ) TMQ
Motor control function Available None
Asynchronous serial interface UARTD (high-performance type of UARTD) UARTA
I2C bus Available None
Preliminary Product Information U18744EJ1V0PM 79
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
Preliminary Product Information U18744EJ1V0PM
80
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
NEC Electronics Corporation
1753, Shimonumabe, Nakahara-ku,
Kawasaki, Kanagawa 211-8668,
Japan
Tel: 044-435-5111
http://www.necel.com/
[America]
NEC Electronics America, Inc.
2880 Scott Blvd.
Santa Clara, CA 95050-2554, U.S.A.
Tel: 408-588-6000
800-366-9782
http://www.am.necel.com/
[Asia & Oceania]
NEC Electronics (China) Co., Ltd
7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian
District, Beijing 100083, P.R.China
Tel: 010-8235-1155
http://www.cn.necel.com/
Shanghai Branch
Room 2509-2510, Bank of China Tower,
200 Yincheng Road Central,
Pudong New Area, Shanghai, P.R.China P.C:200120
Tel:021-5888-5400
http://www.cn.necel.com/
Shenzhen Branch
Unit 01, 39/F, Excellence Times Square Building,
No. 4068 Yi Tian Road, Futian District, Shenzhen,
P.R.China P.C:518048
Tel:0755-8282-9800
http://www.cn.necel.com/
NEC Electronics Hong Kong Ltd.
Unit 1601-1613, 16/F., Tower 2, Grand Century Place,
193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: 2886-9318
http://www.hk.necel.com/
NEC Electronics Taiwan Ltd.
7F, No. 363 Fu Shing North Road
Taipei, Taiwan, R. O. C.
Tel: 02-8175-9600
http://www.tw.necel.com/
NEC Electronics Singapore Pte. Ltd.
238A Thomson Road,
#12-08 Novena Square,
Singapore 307684
Tel: 6253-8311
http://www.sg.necel.com/
NEC Electronics Korea Ltd.
11F., Samik Lavied’or Bldg., 720-2,
Yeoksam-Dong, Kangnam-Ku,
Seoul, 135-080, Korea
Tel: 02-558-3737
http://www.kr.necel.com/
For further information,
please contact:
G0706
[Europe]
NEC Electronics (Europe) GmbH
Arcadiastrasse 10
40472 Düsseldorf, Germany
Tel: 0211-65030
http://www.eu.necel.com/
Hanover Office
Podbielskistrasse 166 B
30177 Hannover
Tel: 0 511 33 40 2-0
Munich Office
Werner-Eckert-Strasse 9
81829 München
Tel: 0 89 92 10 03-0
Stuttgart Office
Industriestrasse 3
70565 Stuttgart
Tel: 0 711 99 01 0-0
United Kingdom Branch
Cygnus House, Sunrise Parkway
Linford Wood, Milton Keynes
MK14 6NP, U.K.
Tel: 01908-691-133
Succursale Française
9, rue Paul Dautier, B.P. 52
78142 Velizy-Villacoublay Cédex
France
Tel: 01-3067-5800
Sucursal en España
Juan Esplandiu, 15
28007 Madrid, Spain
Tel: 091-504-2787
Tyskland Filial
Täby Centrum
Entrance S (7th floor)
18322 Täby, Sweden
Tel: 08 638 72 00
Filiale Italiana
Via Fabio Filzi, 25/A
20124 Milano, Italy
Tel: 02-667541
Branch The Netherlands
Steijgerweg 6
5616 HS Eindhoven
The Netherlands
Tel: 040 265 40 10
μ
PD70F3747, 70F3750, 70F3752, 70F3755, 70F3757
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany.
MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or a trademark in
the United States of America.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the
United States and Japan.
TRON is an abbreviation of The Real-Time Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative purposes
in semiconductor product operation and application examples. The incorporation of these circuits, software and
information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC
Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of
these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products,
customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and
anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special", and "Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated
"quality assurance program" for a specific application. The recommended applications of an NEC Electronics
product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC
Electronics products before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M5 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio and
visual equipment, home electronic appliances, machine tools, personal electronic equipment and
industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life
support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
