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FAN4149 Ground Fault Interrupter Features Description Meets 2015 UL943 Self-Test Requirements (in combination with FAN41501) Precision Sense Amplifier and Bandgap Reference The FAN4149 is a low-power controller for detecting hazardous current paths to ground and ground-toneutral faults. The FAN4149 application circuit opens the load contacts before a harmful shock occurs. Low-VOS Offset for Direct DC Coupling of Sense Coil Built-in Noise Filter High-Current SCR Gate Driver Adjustable Sensitivity 500 A Quiescent Current Minimum External Components Ideal for 120 V or 220 V Systems Space-Saving, SOT23, 6-Pin Package Applications GFCI Output Receptacle GFCI Circuit Breakers Portable GFCI Cords Residual-Current Devices (RCD) The FAN4149, in combination with the FAN41501 automonitoring digital controller, meets the 2015 UL943 selftest requirements for permanently connected GFCI products. The FAN4149 detects and protects against a hot-wire-to-ground fault and a neutral-to-line/load short. The FAN41501 periodically monitors the FAN4149 and critical GFI components to comply with the 2015 UL943 requirements. The minimum number of components and the small 6-pin package allow for a dense, flexible, application solution. The FAN4149 contains a precision bandgap 14 V shunt regulator, precision low-VOS sense amplifier, time-delay noise filter, window-detection comparators, and an SCR driver. The shunt regulator operates with a low quiescent current, which allows for a high value, lowwattage series supply resistor. The internal temperature compensated shunt regulator, sense amplifier, and bias circuitry provide for precision ground-fault detection. This enables the use of larger component variations so that binning or trimming external components is not required. The typical 50 V VOS sense amplifier offset allows for direct DC coupling of the sense coil. This eliminates the large AC-coupling capacitor. The internal delay filter rejects high-frequency noise spikes common with inductive loads. This decreases false nuisance tripping. The SCR driver provides increased current and temperature compensation to allow for a wider selection of external SCRs. The minimum number of external components and the 6-pin SOT23 package allow a low-cost, compact design and layout. Ordering Information Part Number Operating Temperature Range Package Packing Method FAN4149M6X -35C to +85C 6-Lead, SOT23, JEDEC M0-178, 1.6 mm Tape and Reel (c) 2014 Fairchild Semiconductor Corporation FAN4149 * Rev. 1.0.0 www.fairchildsemi.com FAN4149 -- Ground Fault Interrupter July 2014 AMPOUT VS C1 VFB VREF I1 SCR A1 Delay SCR Driver T1 Q1 R1 VTH C2 VS VREF VTH Figure 1. GND Rectifier and Bias VREF VS Block Diagram Typical Application RTEST1 TEST D1 Neutral Coil 1:200 D3 Sense Coil 1:1000 D4 D5 Line Hot R3 Solenoid D2 Load Hot Load Neutral Line Neutral MOV C2 C3 RIN RTEST2 D6 Q1 R1 VS AmpOut SCR Test VFB GND C5 VREF R2 Figure 2. Typical Application VDD FAN41501 GND C4 FAN4149 SCR C1 R4 RSET Fault Test Q2 EOL Alarm Phase (1,2) Table 1. Typical Values R1: 75 k RIN: 470 RTEST1: 15 k RTEST2: 10 k RSET: 750 k (3) R2: 75 k R3: 1 M R4: 909 k C1: 22 nF C2: 10 nF C3: 5.6 nF C4: 220 nF C5: 1 F XMFR: Magnetic Metals 5029/F3006 Notes: 1. Contact Fairchild for self-test requirement details. 2. Portions of this schematic are subject to U.S. patents 8,085,516 and 8,760,824. 3. Value depends on sense-coil characteristics and application. (c) 2014 Fairchild Semiconductor Corporation FAN4149 * Rev. 1.0.0 www.fairchildsemi.com 2 FAN4149 -- Ground Fault Interrupter Block Diagram FAN4149 -- Ground Fault Interrupter Pin Configuration PIN 1 6 Amp Out 2 5 VFB 3 4 VREF SCR 1 GND VS Figure 3. Pin Configuration Pin Definitions Pin # Name 1 SCR Gate drive for external SCR 2 GND Supply input for FAN4149 circuitry 3 VS Supply input for FAN4149 circuitry 4 VREF 5 VFB 6 Description Non-inverting input for current sense amplifier Inverting input for current sense amplifier Amp Out An external resistor connected to VFB sets the IFAULT sensitivity threshold (c) 2014 Fairchild Semiconductor Corporation FAN4149 * Rev. 1.0.0 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Condition ICC Supply Current Continuous Current, VS to GND VCC Supply Voltage Continuous Voltage to GND, All Pins TSTG Storage Temperature Range ESD Electrostatic Discharge Capability Min. Max. Unit 15 mA -0.8 16.0 V -65 +150 C Human Body Model, ANSI/ESDA/JEDEC JS-001-2012 2.5 Charged Device Model, JESD22-C101 1.0 kV DC Electrical Characteristics Unless otherwise specified, TA=25C, Ishunt=1 mA, and referencing Figure 2. Symbol VREG Parameter Conditions Power Supply Shunt Regulator Voltage VS to GND Min. Typ. Max. Unit 13.7 14.0 14.3 V IQ Quiescent Current Line to GND=10 V 425 500 575 A VREF Reference Voltage VREF to GND 6.85 7.00 7.15 V VTH Trip Threshold Amp Out to VREF 4.35 4.50 4.65 V Gain=1000 -175 50 175 V Gain=1000 -100 100 V Design Value -50 50 nA VOS IOS G Amplifier Offset Amplifier Offset Drift (4) Amplifier Input Offset(5) (5) Amplifier DC Gain Design Value (5) fGBW Amplifier Gain Bandwidth VSW+ Amplifier Positive Voltage Swing VSW- Design Value 100 dB 3 MHz 5.5 V Amplifier Negative Voltage Swing VREF to Amp Out, IFAULT=-10 A 5.5 V ISINK Amplifier Current Sink Amp Out=VREF + 3 V VFB=VREF + 100 mV 400 A ISRL Amplifier Current Source Amp Out=VREF - 3 V,VFB=VREF -100 mV 400 Delay Filter Delay from C1 Trip to SCR L->H 0.65 SCR Output Resistance SCR to GND=250 mV, Amp Out=VREF SCR Output Voltage SCR to GND, Amp Out=VREF SCR Output Voltage SCR to GND, AMP Out=VREF +4 V 3.0 SCR Output Current SCR to GND=1 V Amp Out=VREF + 4 V, ISHUNT=2 mA 650 td ROUT VOUT IOUT Amp Out to VREF, IFAULT=10 A 0 A 1.00 1.35 ms 0.5 1.0 k 1 10 mV V 725 A Notes: 4. Maximum VOS offset temperature cycling drift from initial value (JEDEC JESD22-A104). 5. Guaranteed by design, not tested in production. (c) 2014 Fairchild Semiconductor Corporation FAN4149 * Rev. 1.0.0 www.fairchildsemi.com 4 FAN4149 -- Ground Fault Interrupter Absolute Maximum Ratings Refer to Figure 2. T = 1 ms (timer delay) P = Period of the AC Line (1/60 Hz) P = Period of the AC Line (1/60 Hz) N= Ratio of secondary-to-primary turns (1000:1) RSET = 750 k (standard 1% value) The FAN4149 is a GFCI controller for AC ground-fault circuit interrupters. The low-VOS offset for the sense amplifier allows for direct DC coupling of the sense coil when the FAN4149 is biased with a full-wave diode bridge. This allows for the FAN4149 to be used with the FAN41501 digital auto-monitoring controller to provide for a low-BOM-cost, complete, GFI solution with self testing for the critical GFCI components. In practice, the transformer is non-ideal, so RSET may need to be adjusted by up to 30% to obtain the desired IFAULT trip threshold. The internal shunt regulator rectifier circuit is supplied from the full-wave rectifier bridge and 75 k series resistor. A typical 220 nF VS bypass capacitor is used to filter the VAC ripple voltage. The internal 14 V shunt regulator uses a precision temperature-compensated bandgap reference. The combination of precision reference circuitry and precision sense amplifier provides for an accurate ground-fault tolerance. This allows for selection of external components with wider and lower-cost parameter variations. Due to the low quiescent current, a high-value external series resistor (R1) can be used to reduce the maximum power wattage required for this resistor. The 14 V shunt regulator generates the VREF reference voltage for the sense amplifier's (A1) non-inverting input (AC ground reference). It also supplies the bias for the delay timer (t1), comparators (C1 & C2), and the SCR driver. Calculation of VOS Trip Threshold Error Since the sense coil is directly connected to the feedback of the sense amplifier, the VOS offset introduces an IFAULT threshold error. This error can be calculated as follows: %Error =100 x (VOS x RSET) / (RIN + RLDC) / VTH where: The secondary winding of the sense transformer is connected to pin 4 (VREF) and to a resistor, RIN, which is directly DC connected to the inverting input of the sense amplifier at pin 5 (VFB). The feedback resistor (RSET) converts the sense transformer's secondary current to a voltage at pin 6 (Amp Out). This voltage is compared to the internal window comparator (C1 & C2). When the Amp Out voltage exceeds the VTH threshold voltage, the window comparator triggers the internal delay timer. The output of the window comparator must stay HIGH for the duration of the t1 timer. If the window comparator's output goes LOW, the internal delay timer starts a reset cycle. If the window comparator's output is still HIGH at the end of the t1 pulse, the SCR driver enables current source I1 and disables Q1. Current source I1 then enables the external SCR; which energizes the solenoid, opens the contact switches to the load, and removes the hazardous ground fault. The window comparator allows for detection of a positive or negative IFAULT signal, independent from the phase of the line voltage. RSET = (VTH x N) / (1.22 x IFAULT x COS( x t/P)) (2) RSET RIN RLDC VTH = = = = 175 V (worst case) 50 V (typical) 750 k 470 (typical value) 75 (sense coil secondary DC resistance) 4.5 V 5.4% (worst case) 1.5% (typical) Grounded Neutral Detection If the neutral load terminal side is incorrectly connected to the earth ground, the sense coil does not correctly detect the hazardous ground fault current from "load hot" to earth ground due to the partial IFAULT current flowing from the grounded neutral fault (load neutral) to earth ground. To detect a grounded neutral fault, a grounded neutral coil is required. When a low resistive path occurs from the line neutral and load neutral terminals, the sense and neutral coils are mutually coupled. The mutual coupling produces a positive feedback path around the sense amplifier, which causes the sense amplifier to oscillate. When the peak oscillation voltage exceeds the SCR trigger threshold, the internal delay timer is enabled. Since the amplifier's output signal is crossing the window comparator's trip threshold typically at 6 kHz, the delay timer alternates between detection of a fault/no-fault. The ratio of the fault/no-fault detection time interval determines if the SCR driver is enabled. where: VTH = 4.5 V IFAULT = 5 mARMS (UL943) (c) 2014 Fairchild Semiconductor Corporation FAN4149 * Rev. 1.0.0 = The VOS 100 V maximum drift specification is based on temperature cycling per JEDEC JESD22-A104, Condition B, 850 temperature cycles at -55C to +125C. The Amp Out signal must exceed the window comparator's VTH threshold voltage for longer than the delay timer and calculated by: (1) VOS %Error= Calculation of RSET Resistor VTH = IFAULT x 1.22 x RSET x COS(2 x (t/2P)) / N (3) The sensitivity of the grounded neutral detection can be changed by the neutral coil turns and the value of C2 and C3. www.fairchildsemi.com 5 FAN4149 -- Ground Fault Interrupter Functional Description Starting in June of 2015, UL943 requires all permanently connected GFCI products to perform a self-test function. By adding Fairchild's FAN41501 product to the FAN4149 application (see Figure 2), a fully compliant 2015 UL943 self-test function can be achieved with two, small, independent, 6-pin, 1.6 mmwide devices and a minimum number of external components. The 2015 UL code requires that, at power up, the GFCI self test the critical GFCI components -- (c) 2014 Fairchild Semiconductor Corporation FAN4149 * Rev. 1.0.0 www.fairchildsemi.com 6 FAN4149 -- Ground Fault Interrupter FAN4149, SCR, sense coil, and solenoid -- within five seconds and thereafter within every three hours. The self-test cycle cannot open the load contacts. If a component failure is detected, the load power must be denied. Refer to the FAN41501 datasheet for more details about the UL943 self-test features. GFCI Self Test Requirement FAN4149 -- Ground Fault Interrupter Typical Performance Characteristics Unless otherwise specified, TA=25C and according to Figure 2 with SCR disconnected. Ch1: VS (Pin 3), 10 V/Div Ch1: VS (Pin 3), 10 V/Div Ch2: AmpOut (Pin 6), 5 V/Div Ch2: AmpOut (Pin 6), 2 V/Div Ch3: VREF (Pin 4), 5 V/Div Ch3: SCR (Pin 1), 1 V/Div Ch4: SCR (Pin 1), 500 mV/Div Ch4: IFAULT, 10 mA/Div Figure 4. Typical Waveforms, No Ground Fault Figure 5. Typical Waveforms, 4 mA Ground Fault Ch1: VS (Pin 3), 10 V/Div Ch1: VS (Pin 3), 10 V/Div Ch2: AmpOut (Pin 6), 5 V/Div Ch2: AmpOut (Pin 6), 5 V/Div Ch3: SCR (Pin 1), 1 V/Div Ch3: SCR (Pin 1), 1 V/Div Ch4: IFAULT, 10 mA/Div Figure 6. Typical Waveforms, 5 mA Ground Fault Figure 7. Typical Waveforms for Grounded Neutral Detection Continued on the following page... (c) 2014 Fairchild Semiconductor Corporation FAN4149 * Rev. 1.0.0 www.fairchildsemi.com 7 FAN4149 -- Ground Fault Interrupter Typical Performance Characteristics (Continued) Unless otherwise specified, TA=25C and according to Figure 1 with SCR disconnected. Ch2: AmpOut (Pin 6), 2 V/Div Figure 8. Typical Waveform for Grounded Neutral Detection (c) 2014 Fairchild Semiconductor Corporation FAN4149 * Rev. 1.0.0 www.fairchildsemi.com 8 Figure 9. Shunt Regulator Voltage vs. Temperature Figure 10. Quiescent Current vs. Temperature Figure 11. Reference Voltage vs. Temperature Figure 12. VH Threshold Voltage vs. Temperature Figure 13. VL Threshold Voltage vs. Temperature Figure 14. Typical VOS vs. Temperature Figure 15. IOUT SCR Out vs. Temperature (c) 2014 Fairchild Semiconductor Corporation FAN4149 * Rev. 1.0.0 www.fairchildsemi.com 9 FAN4149 -- Ground Fault Interrupter Typical Temperature Characteristics REVISIONS LTR A C 2 D 0.15 C A-B DESCRIPTION E.C.N. RELEASE TO DOCUMENT CONTROL 2X DATE 11/4/2006 5 JULY 07 DWG UPDATED TO CONFORM TO MO178 BY/APP'D H.ALLEN L.HUEBENER SYMM C L 2.9 (0.95) 1.9 (0.95) D A (1.00MIN) 1.4 C D 1.6 2.8 (2.60) (0.70MIN) 0.15 C D 2X 0.15 C PIN 1 INDEX AREA 2X 3 TIPS 0.95 B (1.90) 2X 0.3-0.5 0.20 C A-B D LAND PATTERN RECOMMENDATION SEE DETAIL A 1.45 MAX 1.30 0.90 0.08 0.22 C 0.15 0.05 6X 0.10 C R0.10MIN GAGE PLANE R0.10MIN 0.25 8 0 0.60 0.30 SEATING PLANE 0.60 REF DETAIL A NOTES: A. THIS PACKAGE CONFORMS TO JEDEC MO-178, VARIATION AB. B. ALL DIMENSIONS ARE IN MILLIMETERS. C. DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. D. DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. E. DIMENSIONS AND TOLERANCING AS PER ASME Y14.5M-1994 F. DRAWING FILE NAME: MA06EREV2 SCALE: 2:1 APPROVALS DATE L.HUEBENER 5 JULY 07 H.ALLEN 17 JULY 07 6LD,SOT23,JEDEC MO-178 VARIATION AB, 1.6MM WIDE 1:1 FORMERLY: / NA N/A MKT-MA06E SHEET : 2 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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