CY2545IT - Cypress Semiconductor - Datasheet.Directory

CY2545

CY2547

Quad PLL Programmable Spread Spectrum

Clock Generator with Serial I2C Interface

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 001-13196 Rev. *A Revised October 05, 2007

Features

■Four fully integrated phase locked loops (PLLs)

■Input frequency range

❐External crystal: 8 to 48 MHz

❐External reference: 8 to 166 MHz clock

■Wide operating output frequency range

❐3 to 166 MHz

■Serial programmable over 2-wire I2C interface

■Programmable spread spectrum with center and down

spread option and Lexmark and Linear modulation profiles

■VDD supply voltage options:

❐2.5V, 3.0V, and 3.3V for CY2545

❐1.8V for CY2547

■Selectable output clock voltages independent of VDD supply:

❐2.5V, 3.0V, and 3.3V for CY2545

❐1.8V for CY2547

■Power down, output enable, or frequency select features

■Low jitter, high accuracy outputs

■Ability to synthesize nonstandard frequencies with

Fractional-N capability

■Up to eight clock outputs with programmable drive strength

■Glitch-free outputs while frequency switch ing

■24-pin QFN package

■Commercial and industrial temp erature ranges

Benefits

■Multiple high performance PLLs allow synthesis of unrelated

frequencies

■Nonvolatile programming for personalization of PLL

frequencies, spread spectrum characteristics, drive strength,

crystal load capacitance, and output frequencies

■Application specific programmable EMI reduction using

Spread Spectrum for clocks

■Programmable PLLs for system frequency margin tests

■Meets critical timing requirement s in complex system

designs

■Suitability for PC, consumer , portable, and networking appli-

cations

■Capable of Zero PPM frequency synthesis error

■Uninterrupted system operation during clock frequency

switch

■Application compatibility in standard and low power systems

Logic Block Diagram

OSC

MUX

and

Control

Logic

I2C

PLL1

PLL2

PLL3

(SS)

PLL4

(SS)

Output

Dividers

and

Drive

Strength

Control

CLK1

CLK

CLK3

CLK

Crossbar

Switch

CLKIN/RST

SSON

XOUT

XIN/

EXCLKIN

PD#/OE

SCL

SDA

Bank

[+] Feedback

CY2545

CY2547

Document #: 001-13196 Rev. *A Page 2 of 15

Pinouts

Figure 1. Pin Diagram - CY2545 24 LD QFN

CLKIN/RST

CLK1

PD#OE

CY2545

24 23 22 21 20 19

78910 11 12

GND

VDD_CLK_B1

DNU

CLK2

SDA

SCL

LK3/FS

CLK4

GND

CLK5

VDD_CLK_B

CLK6/SSON

VDD_CLK_B

CLK7

GND

CLK8

VDD

XOUT

XIN/

EXCLKIN

GND

24LD QFN

Table 1. Pin Definition - CY2545 24 LD QFN (VDD = 2.5V, 3.0V or 3.3V Supply)

Pin Number Name IO Description

1 GND Power Power supply ground

2 CLK1 Output Programmable clock output. Output voltage depends on Bank1 voltage

3 VDD_CLK_B1 Power Power supply for Bank1 (CLK1, CLK2) output: 2.5V/3.0V/3.3 V

4 PD#/OE Input Multifunction programmable pin: Output enable or Power down mode

5 DNU DNU Do not use this pin

6 CLK2 Output Programmable clock output. Output voltage depends on Bank1 voltage

7 GND Power Power supply ground

8 SCL Input Serial data clock

9 SDA Input/Output Serial data input/output

10 CLK3/FS Output/Input Multifunction programmable pin: Programmable clock output or frequency

select input pin. Output voltage of CLK3 depends on Bank2 voltage

11 CLK4 Output Programmable clock output. Output voltage depends on Bank2 voltage

12 GND Power Power supply ground

13 CLK5 Output Programmable clock output. Output voltage depends on Ba nk2 voltage

14 VDD_CLK_B2 Power Power supply for Bank2 (CLK3, CLK4, CLK5) output: 2.5V/3.0V/3.3V

15 CLK6/SSON Output/Input Multifunction programmable pin: Programmable clock output or spread

spectrum ON/OFF control input pin. Output voltage of CLK6 depends on

Bank3 voltage

16 VDD_CLK_B3 Power Power supply for Bank3 (CLK6, CLK7, CLK8) output: 2.5V/3.0V/3.3V

17 CLK7 Output Programmable clock output. Output voltage depends on Ba nk3 voltage

18 GND Power Power supply ground

19 GND Power Power supply ground

20 CLK8 Output Programmable clock output. Output voltage depends on Ba nk3 voltage

21 CLKIN/RST Input/Input Multifunction programmable pin. High true reset input or 2.5V/3.0V/3.3V

external reference clock input. The signal level of CLKIN input must track

VDD power supply on pin 22.

[+] Feedback

CY2545

CY2547

Document #: 001-13196 Rev. *A Page 3 of 15

Figure 2. Pin Diagram - CY2547 24 LD QFN

22 VDD Power Power supply for core and inputs: 2.5V/3.0V/3.3V

23 XOUT Output Crystal output

24 XIN/EXCLKIN Input Crystal input or 1.8V external clock input

Table 1. Pin Definition - CY2545 24 LD QFN (VDD = 2.5V, 3.0V or 3.3V Supply) (continued)

Pin Number Name IO Description

CLKIN/RST

CLK1

PD#OE

CY2547

24 23 22 21 20 19

7 8 9 10 11 12

GND

VDD_CLK_B1

VDD

CLK2

SDA

SCL

CLK4

GND

CLK5

VDD_CLK_B

CLK6/SSON

VDD_CLK_B

CLK7

GND

CLK8

VDD

XOUT

XIN/

EXCLKIN

GND

24LD QFN

CLK3/FS

Table 2. Pin Definition - CY2547 24 LD QFN (VDD = 1.8V Supply)

Pin Number Name IO Description

1 GND Power Power supp ly ground

2 CLK1 Output Programmable clock output. Output voltage depends on Bank1 voltage

3 VDD_CLK_B1 Power Power supply for Bank1 (CLK1, CLK2) output: 1.8V

4 PD#/OE Input Multifunction programmable pin: Output enable or Power down mode

5 VDD Power Power supp ly for core and inputs: 1.8V

6 CLK2 Output Programmable output clock. Output voltage depends on Bank1 voltage

7 GND Power Power supp ly ground

8 SCL Input Serial data clock

9 SDA Input/Output Serial da ta input

10 CLK3/FS Output/Input Multifunction programmable pin: Programmable clock output or frequency

select input pin. Output voltage of CLK3 depends on VDD_CLK_B2 voltage

11 CLK4 Output Programmable output clock. Output voltage depends on Bank2 voltage

12 GND Power Power supply ground

13 CLK5 Output Programmable clock output. Output voltage depends on Bank2 voltage

14 VDD_CLK_B2 Power Power supply for Bank2 (CLK3, CLK4, CLK5) output: 1.8V

15 CLK6/SSON Output/Input Multifunction programmable pin: Programmable clock out pu t or spre ad

spectrum ON/OFF control input pin. Output voltage of CLK6 depends on

VDD_CLK_B3 voltage

16 VDD_CLK_B3 Power Power supply for Bank3 (CLK6, CLK7, CLK8) output: 1.8V

17 CLK7 Output Programmable clock output. Output voltage depends on Bank3 voltage

18 GND Power Power supply ground

[+] Feedback

CY2545

CY2547

Document #: 001-13196 Rev. *A Page 4 of 15

General Description

Four Configurable PLLs

The CY2545 and CY2547 have four I2C programmable PLLs

available to generate output fre quencies ranging from 3 to 166

MHz. The advantage of having four PLLs is that a single device

generates up to four independent frequencies from a single

crystal. Two sets of frequencies for each PLL can be

programmed. This enables in system frequency switching using

multifunction frequency select pin, FS.

I2C Programming

The CY2545 and CY2547 have a serial I2C interface that

programs the configuration memory array to synthesize output

frequencies by programmable output divider, spread character-

istics, drive strength, and crystal load capacitance. I2C can also

be used for in system control of these programmable features.

Input Reference Clocks

The input to the CY2545 and CY2547 is either a crystal or a clock

signal. The input frequency range for crystals is 8 MHz to 48

MHz. There is provision for two reference clock inputs, CLKIN

and EXCLKIN with frequency range of 8 MHz to 166 MHz. For

both devices, when CLKIN signal at pin 21 is used as a reference

input, a valid signal at EXCLKIN (as specified in the AC and DC

Electrical S pecification table), must be present for the devices to

operate properly.

Multiple Power Supplies

The CY2545 and CY2547 are designed to operate at internal

core supply voltage of 1.8V. In the case of the high voltage part

(CY2545), an internal regulator is used to generate 1.8V from the

2.5V/3.0V/3.3V VDD supply voltage at pin 22. For the low voltage

part (CY2547), this internal regulator is bypassed and 1.8V at

VDD pin 22 is directl y used.

Output Bank Settings

These devices have eight clock outputs grouped in three output

driver banks. The Bank 1, Bank 2, and Bank 3 correspond to

(CLK1, CLK2), (CLK3, CLK4, CLK5), and (CLK6, CLK7, CLK8),

respectively . Separate power supplies are used for each of these

banks and they can be any of 2.5V , 3.0V, or 3.3V for CY2545 and

1.8V for CY2547 giving user multiple choice of output clock

voltage levels.

Output Source Selection

These devices have eight clock outputs (CLK1 - 8). There are six

available clock sources for these outputs. These clock sources

are: XIN/EXCLKIN, CLKIN, PLL1, PLL2, PLL3, or PLL4. Output

clock source selection is done using four out of six crossbar

switch. Thus, any one of these six available clock sources can

be arbitrarily selected for the clock outputs. This gives user a

flexibility to have up to four independent clock outputs.

Spread Spectrum Control

Two of the four PLLs (PLL3 and PLL4) have spread spectrum

capability for EMI reduction in the system. The device uses a

Cypress proprietary PLL and Spread Spectrum Clock (SSC)

technology to synthesize and modulate the frequency of the PLL.

The spread spectrum feature can be turned on or off using a

multifunction control pin (CLK7/ SSON). It can be progr ammed to

either center spread range from ±0.125% to ±2.50% or down

spread range from –0.25% to –5.0% with Lexmark or Linear

profile.

Frequency Select

The device can store two different PLL frequency configurations,

output source selection and output divider values for all eight

outputs in its nonvolatile memory location. There is a multi-

function programmable pin, CLK3/FS which, if programmed as

frequency select input, can be used to select between these two

arbitrarily programmed settings.

Glitch-Free Frequen cy Switch

When the frequency select pin (FS) is used to switch frequency,

the outputs are glitch-free provided frequency is switched using

output dividers. This feature enables uninterrupted system

operation while clock frequency is switch ed.

Device Reset Function

There is a multifunction CLKIN/RST (pin 21) that can be

programmed to use for the device reset function. There a re two

different programmable modes of operation for this device reset

function. Fi rst one (call ed POR l ike reset), when used brings the

device in the default register settings loosing all configuration

changes made through the I2C interface. The second (called

Clean Start), keeps the I2C programmed values while giving all

outputs a simultaneous clean start from its low pull down state.

19 GND Power Power supply ground

20 CLK8 Output Programmable clock output. Output voltage depends on Bank3 voltage

21 CLKIN/RST Input/Input Multifunction programmable pin: High true reset input or 1.8V external low

voltage reference clock input

22 VDD Power Power supply for core and inputs: 1.8V

23 XOUT Output Crystal output

24 XIN/EXCLKIN Input Crystal input or 1.8V external clock input

Table 2. Pin Definition - CY2547 24 LD QFN (VDD = 1.8V Supply) (continued)

Pin Number Name IO Description

[+] Feedback

CY2545

CY2547

Document #: 001-13196 Rev. *A Page 5 of 15

PD#/OE Mode

PD#/OE (Pin 4) is programmable to operate as either power

down (PD#) or output enable (OE) mode. PD# is a low true input.

If activated it shuts off the entire chip, resulting in minimum

device power consumption. Setting this signal high brings the

device into operational mode with default register settings.

When this pin is programmed as output enable (OE), clock

outputs are enabled or disabled using OE pin. Individual clock

outputs can be programmed to be sensitive to this OE pin.

Keep Alive Mode

By activating the device in the keep alive mode, power down

mode is changed to power savin g mode. This disabl es all PLLs

and outputs, but preserves the contents of the volatile registers.

Thus, any configuration changes made through the I2C interface

are preserved. By deactivating the keep alive mode, I2C memory

is not preserved during pow er down, but power consumption is

reduced relative to the keep alive mode .

Output Drive Strength

The DC drive strength of the individual clock output can be

programmed for different values. Table 3 shows the typical rise

and fall times for different drive strength settings.

Generic Configuration and Custom Frequency

There is a generic set of output frequencies available from the

factory that can be used for the device evaluation purposes. The

device, CY2545/CY2547 can be custom programmed to any

desired frequencies and listed features. For customer specific

programming and I2C programmable memory bitmap definitions,

please contact your local Cypress Field Application Engineer

(FAE) or sales representative.

Table 3. Output Drive Strength

Output Drive Strength Rise/Fall Time (ns)

(Typical Value)

Low 6.8

Mid Low 3.4

Mid High 2.0

High 1.0

[+] Feedback

CY2545

CY2547

Document #: 001-13196 Rev. *A Page 6 of 15

Serial I2C Programming Interface Protocol

and Timing

To enhance the flexibility and function of the clock synthesizer , a

two signal serial interface is provided. Through the Serial Data

Interface, various device functions, such as individual clock

output buffers, are individually enabled or disabled. The registers

associated with the Serial Data Interface initialize to their default

setting upon power up and therefore, use of this interface is

optional. Clock device register changes are normally made at

system initialization, if any are required.

The CY2545 and CY2547 use a 2-wire serial interface SDA and

SCL that operates up to 400 kbits/s in read or write mode. The

SDA and SCL timing and data transfer sequence is shown in

Figure 3. The basic write serial format is:

Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock

Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit

Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in

MA+2; ACK; etc. until STOP Bit. The basic serial format is illus-

trated in Figure 4.

Device Address

The device serial interface address is 69H. The device address

is combined with a read/write bit as the LSB and is sent after

each start bit.

Data Valid

Data is valid when the clock is HIGH, and is only transitioned

when the clock is LOW, as illustrated in Figure 5.

Data Frame

A start and stop sequence indicates every new data frame, as

illustrated in Figure 6.

S tart Sequence - The start frame is indicated by SDA going LOW

when SCL is HIGH. Every time a start signal is supplied, the next

8-bit data must be the device address (seven bits) and a R/W bit,

followed by register address (eight bits) and register data (eight

bits).

S top Sequence - The stop frame is indicated by SDA going HIGH

when SCL is HIGH. A stop frame frees the bus to go to another

part on the same bus or to another random register address.

Acknowledge Pulse

During write mode the CY2545/CY2547 responds with an

acknowledge pulse after every eigh t bits. Do this by pulling the

SDA line LOW during the N*9th clock cycle as illustrated in

Figure 7 (N = the number of bytes transmitted). During read

mode, the master generates the acknowledge pulse after

reading the data packet.

Write Operations

Writing Individual Bytes

A valid write operation must have a full 8-bit register address

after the device address word from the master , which is followed

by an acknowledge bit from th e slave (ack = 0/LOW). The next

eight bits must contain the data word intended for storage. After

the data word is received, the slave responds with another

acknowledge bit (ack = 0/LOW), and the master must end the

write sequence with a STOP condition.

Writing Multiple Bytes

To write multiple bytes at a time, the master does not end the

write sequence with a STOP condition; instead, the master

sends multiple contiguous bytes of data to be stored. After each

byte, the slave respon ds with an acknowledge bit, the same as

after the first byte, and accepts data until the STOP condition

responds to the acknowledge bit. When receiving multiple bytes,

the CY2545 and CY2547 internally increment the register

address.

Read Operations

Read operations are initiated the same way as write operation s

except that the R/W bit of the slave address is set to ‘1’ (HIGH).

There are three basic read operations: current address read,

random read, and sequenti al read.

Current Address Read

The CY2545 and CY2547 have an onboard address counter that

retains 1 more than the a ddress of the last word access. If the

last word written or read was word ‘n’, then a current address

read operation returns the value stored i n location ‘n+1’. When

the CY2545/CY2547 receive the slave address with the R/W bit

set to a ‘1’, the CY2545/CY2547 issue an acknowledge and

transmit the 8-bit word. The master device does not

acknowledge the transfer, but generates a STOP condition,

which causes the CY2545/CY2547 to stop transmission.

Random Read

Through random read operations, the master may access any

memory location. To perform this type of read operation, first the

word address must be set. This is done by sending the address

to the CY2545/CY2547 as part of a write operation. After sending

the word address, the master generates a START condition

following the acknowledge. This terminates the write operation

before any data is stored in the address, but not before the

internal address pointer is set. Next, the master reissues the

control byte with the R/W byte set to ‘1’. The CY2545/CY2547

then issue an acknowledge and transmit the 8-bit word. The

master device does not acknowledge the transfer , but generates

a STOP condition, which causes the CY2545/CY2547 to stop

transmission.

Sequential Read

Sequential read operatio ns follo w the same process a s rand om

reads except that the master issues an acknowledge instea d of

a STOP condition after transmitting the first 8-bit data word. This

action increments the internal address pointer, and subsequently

output of the next 8-bit data word. By continuing to issue

acknowledges instead of STOP conditions, the master serially

reads the entire contents of the slave device memory. When the

internal address pointer points to the FFH register , af ter the next

increment, the pointer points to the 00H register.

[+] Feedback

CY2545

CY2547

Document #: 001-13196 Rev. *A Page 7 of 15

Figure 3. Data Transfer Sequence on the S erial Bus

Figure 4. Data Frame Architecture

Figure 5. Data Valid and Data Transition Periods

SCL

START

Condition

SDA

STOP

Data may Address or

Acknowledge

Valid be changed Condition

SDA Write

Start Signal

Device

Address

7-bit

R/W = 0

1 Bit

8-bit

Address

Slave

1 Bit

ACK Slave

1 Bit

ACK

8-bit

Data

Stop Signal

Multiple

Contiguous

Registers

Slave

1 Bit

ACK

8-bit

Data

(XXH) (XXH) (XXH+1)

Slave

1 Bit

ACK

8-bit

Data

(XXH+2)

Slave

1 Bit

ACK

8-bit

Data

(FFH)

Slave

1 Bit

ACK

8-bit

Data

(00H)

Slave

1 Bit

ACK Slave

1 Bit

ACK

SDA Read

Start Signal

Device

Address

7-bit

R/W = 1

1 Bit

8-bit

Data

Slave

1 Bit

ACK Slave

1 Bit

ACK

Stop Signal

SDA Read

Start Signal

Device

Address

7-bit

R/W = 0

1 Bit

8-bit

Address

Slave

1 Bit

ACK Slave

1 Bit

ACK

7-bit

Device

Stop Signal

Multiple

Contiguous

Registers

Master

1 Bit

ACK

8-bit

Data

Master

1 Bit

ACK

(XXH) (XXH)

Master

1 Bit

ACK

8-bit

Data

(XXH+1)

Master

1 Bit

ACK

8-bit

Data

(FFH)

Master

1 Bit

ACK

8-bit

Data

(00H)

Master

1 Bit

ACK Master

1 Bit

ACK

Current

Address

Read

Address

+R/W=1

Repeated

Start bit

SDA

SCL

Data Va lid Transition

to next Bit

CLK

LOW

CLK

HIGH

VIH

VIL

[+] Feedback

CY2545

CY2547

Document #: 001-13196 Rev. *A Page 8 of 15

Serial I2C Programming Interface Timing

Figure 6. .Start and S t o p Fra me

Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data)

SDA

SCL

START Transition

to next Bit STOP

SDA

SCL

DA6 DA5 DA0 R/W ACK RA7 RA6 RA1 RA0 ACK STOP

START ACK D7 D6 D1 D0

+++

Serial I2C Programming Interface Timing Specifications

Parameter Description Min Max Unit

fSCL Frequency of SCL – 400 kHz

Start Mode Time from SDA LOW to SCL LOW 0.6 – μs

CLKLOW SCL LOW Period 1.3 – μs

CLKHIGH SCL HIGH Period 0.6 – μs

tSU Data Transition to SCL HIGH 250 – ns

tDH Data Hold (SCL LOW to data transition) 0 – ns

Rise Time of SCL and SDA – 300 ns

Fall Time of SCL and SDA – 300 ns

Stop Mode Time from SCL HIGH to SDA HIGH 0.6 – µs

Stop Mode to Start Mode 1.3 – µs

[+] Feedback

CY2545

CY2547

Document #: 001-13196 Rev. *A Page 9 of 15

Absolute Maximum Conditions

Parameter Description Condition Min Max Unit

VDD Supply voltage for CY2545 –0.5 4.5 V

VDD Supply Voltage for CY2547 –0.5 2.6 V

VDD_CLK_BX Output Bank supply voltage –0.5 4.5 V

VIN Input voltage for CY2545 Relative to VSS –0.5 VDD+0.5 V

VIN Input voltage for CY2547 Relative to VSS –0.5 2.2 V

TSTemperature and storage Nonfunctional –65 +150 °C

ESDHBM ESD protection (Human Body Model) JEDEC EIA/JESD22-A114-E 2000 Volts

UL-94 Flammability rating V-0 @1/8 in. 10 ppm

MSL Moisture sensitivity level 3

Recommended Operating Conditions

Parameter Description Min Typ Max Unit

VDD VDD Operating voltage for CY2545 2.25 –3.60 V

VDD VDD Operating voltage for CY2547 1.65 1.8 1.95 V

VDD_CLK_BX Output driver voltage for Bank 1, 2 and 3 1.43 –3.60 V

TAC Commercial ambient temperature 0–+70°C

TAI Industrial ambient temperature –40 -- +85 °C

CLOAD Maximum load capacitance ––15pF

tPU Power up time for all VDD to reach minimum specified voltage (power

ramps must be monotonic) 0.05 – 500 ms

[+] Feedback

CY2545

CY2547

Document #: 001-13196 Rev. *A Page 10 of 15

DC Electrical Specifications

Parameter Description Conditions Min Typ Max Unit

VOL Output low voltage IOL = 2 mA, drive streng th = [00 ] – – 0.4 V

IOL = 3 mA, drive strength = [01 ]

IOL = 7 mA, drive strength = [10 ]

IOL = 12 mA, drive strength = [11]

VOH Output high voltage IOH = –2 mA, drive strength = [00] VDD_CLK_BX

– 0.4 ––V

IOH = –3 mA, drive strength = [01]

IOH = –7 mA, drive strength = [10]

IOH = –12 mA, drive strength = [11]

VOLSD Output low voltage, SDA IOL = 4 mA – – 0.4 V

VIL1 Input low voltage of PD#/OE,

RST, FS, and SSON – – 0.2*VDD V

VIL2 Input low voltage of CLKIN for

CY2545 – – 0.1*VDD V

VIL3 Input low voltage of EXCLKIN for

CY2545 – – 0.18 V

VIL4 Input low voltage of CLKIN,

EXCLKIN for CY2547 – – 0.1*VDD V

VIH1 Input high voltage of PD#/OE,

RST, FS, and SSON 0.8*VDD ––V

VIH2 Input high voltage of CLKIN for

CY2545 0.9*VDD ––V

VIH3 Input high voltage of EXCLKIN

for CY2545 1.62 – 2.2 V

VIH4 Input high voltage of CLKIN,

EXCLKIN for CY2547 0.9*VDD ––V

IILPD Input low current of RST and

PD#/OE VIL = 0V – – 10 µA

IIHPD Input high current of RST and

PD#/OE VIH = VDD – – 10 µA

IILSR Input low current of SSON and

FS VIL = 0V (Internal pull dn = 160k typ) – – 10 µA

IIHSR Input high current of SSON and

FS VIH = VDD (Int erna l pul l dn = 160 k typ) 14 – 36 µA

RDN Pull down resistor of

(CLK1-CLK8) when off,

CLK6/SSON and CLK3/FS

100 160 250 kΩ

IDD[1,2] Supply current for CY2547 PD# = High, No load – 20 – mA

Supply current for CY2545 PD# = High, No load – 22 – mA

IDDS[1] Standby current PD# = Low, No load, with I2C circuit not

in Keep Alive Mode –3–µA

IPD[1] Power down current PD# = Low , No load, with I2C circuit in

Keep Alive Mode ––1mA

CIN[1] Input capacitance SSON, RST, PD#/OE or FS inputs – 7 pF

[+] Feedback

CY2545

CY2547

Document #: 001-13196 Rev. *A Page 11 of 15

AC Electrical Specifications

Parameter Description Conditions Min Typ Max Unit

FIN (crystal) Crystal frequency, XIN 8–48 MHz

FIN (clock) Input clock frequency Clock inputs CLKIN or EXCLKIN 8–166 MHz

FCLK Output clock frequency 3–166 MHz

DC1 Output duty cycle, all clocks

except Ref Out Duty cycle is defined in Figure 9; t1/t2, measured 50%

of VDD 45 50 55 %

DC2 Ref out clock duty cycle Ref In Min 45%, Max 55% 40 – 60 %

TRF1[1] Output rise/fall time Measured from 20% to 80% of VDD_CLK_BX, as shown

in Figure 10, CLOAD = 15 pF, Drive strength [00] –6.8–ns

TRF2[1] Output rise/fall time Measured from 20% to 80% of VDD_CLK_BX, as shown

in Figure 10, CLOAD = 15 pF, Drive strength [01] –3.4–ns

TRF3[1] Output rise/fall time Measured from 20% to 80% of VDD_CLK_BX, as shown

in Figure 10, CLOAD = 15 pF, Drive strength [10] –2.0–ns

TRF4[1] Output rise/fall time Measured from 20% to 80% of VDD_CLK_BX, as shown

in Figure 10, CLOAD = 15 pF, Drive strength [11] –1.0–ns

TCCJ[1,2] Cycle-to-cycle jitter max (Pk-Pk) Configuration dependent. See Table 4 – 150 – ps

TLOCK[1] PLL Lock time Measured from 90% of the applied power supply level – 1 3 ms

Table 4. Configuration Example for C-C Jitter

Ref. Freq.

(MHz)

CLK1 Output CLK2 Output CLK3 Output CLK4 Output CLK5 Output

Freq.

(MHz) C-C Jitter

Typ (ps) Freq.

(MHz) C-C Jitter

Typ (ps) Freq.

(MHz) C-C Jitter

Typ (ps) Freq.

(MHz) C-C Jitter

Typ (ps) Freq.

(MHz) C-C Jitter

Typ (ps)

14.3181 8.0 134 166 103 48 92 74.25 81 Not Used

19.2 74.25 99 166 94 8 91 27 110 48 75

27 48 67 27 109 166 103 74.25 97 Not Used

48 48 93 27 123 166 137 166 138 8 103

Recommended Crystal Specification for SMD Package

Parameter Description Ra nge 1 Range 2 Range 3 Unit

Fmin Minimum frequency 8 14 28 MHz

Fmax Maximum frequency 14 28 48 MHz

R1 Motional resistance (ESR) 135 50 30 Ω

C0 Shunt capacitance 4 4 2 pF

CL Parallel load capacitance 18 14 12 pF

DL(max) Maximum crystal drive level 300 300 300 µW

Recommended Crystal Specification for Thru-Hole Package

Parameter Description Range 1 Range 2 Range 3 Unit

Fmin Minimum frequency 8 14 24 MHz

Fmax Maximum frequency 14 24 32 MHz

R1 Motional resistance (ESR) 90 50 30 Ω

C0 Shunt capacitance 7 7 7 pF

CL Parallel load capacitance 18 12 12 pF

DL(max) Maximum crystal drive level 1000 1000 1000 µW

Notes

1. Guaranteed by design but not 100% tested.

2. Configuration dependent.

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CY2547

Document #: 001-13196 Rev. *A Page 12 of 15

Test and Measurement Setup

Figure 8. Test and Measurement Setup

Voltage and Timing Definitions

Figure 9. Duty Cycle Definition

Figure 10. Rise Time = TRF, Fall Time = TRF

0.1 μF

VDD Outputs

CLOAD

GND

DUT

Clock

Output

DD_CLK_B

50% of V

DD_CLK_B

Clock

Output

TRF

V DD_CLK_BX

80% of V

DD_CLK_BX

20% of V

DD_CLK_BX

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CY2547

Document #: 001-13196 Rev. *A Page 13 of 15

Ordering Information

Part Number[1] Type VDD(V) Production Flow

Pb-free

CY2545Cxxx 24-pin QFN Supply voltage: 2.5V, 3.0V or 3.3V Commercial, 0°C to 70°C

CY2545CxxxT 24-pin QFN Tape & Reel Supply voltage: 2.5V, 3.0V or 3.3V Commercial, 0°C to 70 °C

CY2547Cxxx 24-pin QFN Supply voltage: 1.8V Commercial, 0°C to 70°C

CY2547CxxxT 24-pin QFN Tape & Reel Supply voltage: 1.8V Commercial, 0°C to 70°C

CY2545Ixxx 24-pin QFN Supply voltage: 2.5V, 3.0V or 3.3V Industrial, –40°C to 85°C

CY2545IxxxT 24-pin QFN Tape & Reel Supply voltage: 2.5V, 3.0V or 3.3V Industrial, –40°C to 85°C

CY2547Ixxx 24-pin QFN Supply voltage: 1.8V Industrial, –40°C to 85°C

CY2547IxxxT 24-pin QFN Tape & Reel Supply voltage: 1.8V Industrial, –40°C to 85°C

Note

1. xxx indicates Factory Programmable and are factory programmed configuratio ns. For more de t ails, con t act your loca l Cypre ss FAE or Cypress Sales Representative.

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CY2547

Document #: 001-13196 Rev. *A Page 14 of 15

Package Drawing and Dimensions

Figure 11. 24-LD QFN 4x4 mm (Subcon Punch Type Pkg with 2.49x2.49 EPAD) LF24A/LY24A

5. PACKAGE CODE

LY24A

LF24A

PART # DESCRIPTION

LEAD FREE

STANDARD

2. REFERENCE JEDEC#: MO-220

4. ALL DIMENSIONS ARE IN MM [MIN/MAX]

1. HATCH IS SOLDERABLE EXPOSED METAL.

3. PACKAGE WEIGHT: 0.042g

NOTES:

SOLDERABLE

EXPOSED

PAD

1.00 MAX.

SEATING

PLANE

0.23±0.05

0.50

0.05

0°-12°

0.30-0.50

2.45

0.05 MAX.

0.80 MAX.

0.20 REF.

PIN1 ID

0.45

0.20 R.

SIDE VIEW

3.90

4.10

3.70

3.80

4.10

3.70

3.80

3.90

0.42±0.18

2.55

2.45

(4X)

TOP VIEW BOTTOM VIEW

2.49

?0.50

51-85203-*A

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Document #: 001-13196 Rev. *A Revised October 05, 2007 Page 15 of 15

Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these compon ents in an I2C system, p rovided

that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders.

CY2545

CY2547

circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress p roducts are not warranted nor int ended to be used for med ical,

life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cy press do es not auth orize its produc ts for use as crit ical

components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (Unit ed States and fore ign),

United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, crea te der ivative works of ,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee prod uct to be used only in conjunction with a Cyp ress

integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials describ ed herein. Cyp ress does not

assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re

a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document History Page

Document Title: CY2545 CY2547 Quad PLL Programmable Spread Spectrum Clock Generator with Serial I2C Interface

Document Number: 001-13196

REV. ECN NO. Issue

Date Orig. of

Change Description of Cha ng e

** 870780 See ECN RGL/AESA New Data Sheet

*A 1504843 See ECN RGL/AESA Changed I2 C Tsu specification from 100ns to 250 ns

Changed ESD spec from MIL-STD to JEDEC

Combined VDD operating condition spec for CY2545 to a single VDD spec

Changed name from VDD_CORE to VDD

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