LTC3307A 5V, 3A Synchronous Step-Down Silent Switcher in 2mm x 2mm LQFN FEATURES DESCRIPTION High Efficiency: 8m NMOS, 31m PMOS nn Programmable Frequency to 3MHz nn Tiny Inductor and Capacitors nn Peak Current Mode Control nn 22ns Minimum On-Time nn Wide Bandwidth, Fast Transient Response nn Silent SwitcherTM Architecture nn Ultralow EMI Emissions nn Low Ripple Burst Mode(R) Operation with I of 40A Q nn Safely Tolerates Inductor Saturation in Overload nn V Range: 2.25V to 5.5V IN nn V OUT Range: 0.5V to VIN nn V OUT Accuracy: 1% Over Temperature Range nn Precision 400mV Enable Threshold nn Shutdown Current: 1A nn Power Good, Internal Compensation and Soft Start nn Thermally Enhanced 2mm x 2mm LQFN Package nn AEC-Q100 Qualified for Automotive Applications The LTC(R)3307A is a very small, high efficiency, low noise, monolithic synchronous 3A step-down DC/DC converter operating from a 2.25V to 5.5V input supply. Using constant frequency, peak current mode control at switching frequencies up to 3MHz and minimum on-time as low as 22ns, this regulator achieves fast transient response with small external components. Silent Switcher architecture minimizes EMI emissions. APPLICATIONS All registered trademarks and trademarks are the property of their respective owners. nn The LTC3307A operates in forced continuous or pulse skip mode for low noise, or low-ripple Burst Mode operation for high efficiency at light loads, ideal for batterypowered systems. The IC regulates output voltages as low as 500mV. Other features include output overvoltage protection, short-circuit protection, thermal shutdown, clock synchronization, and up to 100% duty cycle operation for low dropout. The device is available in a low profile 12-lead 2mm x 2mm x0.74mm LQFN package with exposed pad for low thermal resistance. Optical Networking, Servers, Telecom Automotive, Industrial, Communications nn Distributed DC Power Systems (POL) nn FPGA, ASIC, P Core Supplies nn nn TYPICAL APPLICATION Efficiency and Power Loss Efficiency and PowerOperation Loss in Burst Mode in Burst Mode Operation High Efficiency, 2MHz, 1.2V 3A Step-Down Converter VIN = 2.25V TO 5.5V 10 100 90 1F 0201 1F 0201 VIN VIN SW SW 10pF LTC3307A 140k FB VIN 100k 15F x2 PGND PGOOD 3307A TA01a 0.1 60 50 40 30 10 AGND 1 70 20 10nF MODE/SYNC RT EFFICIENCY 80 VOUT 1.2V 3A 0 0.001 0.01 POWER LOSS VIN = 3.3V VOUT = 1.2V fSW = 2 MHz 0.001 Murata DFE201210S-R47M 0.01 0.1 LOAD CURRENT (A) 1 POWER LOSS (W) EN 4.7F 470nH EFFICIENCY (%) 4.7F 3 0.0001 3307A TA01b fOSC = 2MHz Rev. A Document Feedback For more information www.analog.com 1 LTC3307A ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) EN 2 VIN 3 PGND 4 PGOOD 1 12 11 13 PGND 5 6 SW AGND FB TOP VIEW SW VIN ............................................................... -0.3V to 6V EN......................... -0.3V to Lesser of (VIN + 0.3V) or 6V FB......................... -0.3V to Lesser of (VIN + 0.3V) or 6V MODE/SYNC......... -0.3V to Lesser of (VIN + 0.3V) or 6V RT......................... -0.3V to Lesser of (VIN + 0.3V) or 6V AGND to PGND........................................ -0.3V to +0.3V PGOOD.......................................................... -0.3V to 6V IPGOOD.......................................................................5mA Operating Junction Temperature Range (Note 2): LTC3307AE........................................ -40C to +125C LTC3307AI..........................................-40C to +125C LTC3307AJ.........................................-40C to +150C LTC3307AH.........................................-40C to +150C LTC3307AMP......................................-55C to +150C Storage Temperature Range.................. -65C to +150C Maximum Reflow (Package Body) Temperature.... 260C 10 RT 9 MODE/SYNC 8 VIN 7 PGND LQFN PACKAGE 12-LEAD (2mm x 2mm x 0.74mm) TJMAX = 150C, JA = 51C/W, JB = 12C/W, JCBOTTOM = 8.6C/W, JCTOP = 73C/W, JT = 0.6C/W AND VALUES DETERMINED PER JESD51-7 ON A JEDEC 2S2P PCB, EXPOSED PAD (PIN 13) IS PGND, MUST BE SOLDERED TO PCB ORDER INFORMATION TAPE AND REEL TAPE AND REEL MINI PACKAGE TYPE PART MARKING* TEMPERATURE RANGE -40C to 125C LTC3307AEV#TRPBF LTC3307AEV#TRMPBF LHFR LTC3307AIV#TRPBF LTC3307AIV#TRMPBF LHFR LTC3307AJV#TRPBF LTC3307AJV#TRMPBF LHFR LTC3307AHV#TRPBF LTC3307AHV#TRMPBF LHFR LTC3307AMPV#TRPBF LTC3307AMPV#TRMPBF LHFR -55C to 150C LTC3307AEV#WTRPBF LTC3307AEV#WTRMPBF LHFR -40C to 125C LTC3307AIV#WTRPBF LTC3307AIV#WTRMPBF LHFR LTC3307AJV#WTRPBF LTC3307AJV#WTRMPBF LHFR LTC3307AHV#WTRPBF LTC3307AHV#WTRMPBF LHFR LQFN (Laminate Package with QFN Footprint) -40C to 125C -40C to 150C -40C to 150C AUTOMOTIVE PRODUCTS** LQFN (Laminate Package with QFN Footprint) -40C to 125C -40C to 150C -40C to 150C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for thesemodels. Rev. A 2 For more information www.analog.com LTC3307A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range (Note 2), otherwise specifications are at TA = 25C; VIN=3.3V, VEN=VIN, MODE/SYNC=Float, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Input Supply Operating Supply Voltage (VIN) VIN Undervoltage Lockout VIN Undervoltage Lockout Hysteresis VIN Rising VIN Quiescent Current in Shutdown VEN = 0.1V VIN Quiescent Current (Note 3) Burst Mode Operation, Sleeping All Modes, Not Sleeping Enable Threshold Enable Threshold Hysteresis VEN Rising EN Pin Leakage VEN =0.5V l 2.25 l 2.0 l 0.375 5.5 V 2.1 150 2.2 V mV 1 2 A 40 1.2 60 2 A mA 0.4 50 0.425 V mV 20 nA 0.5 0.505 V 0.015 0.05 %/V 20 nA 42 ns Voltage Regulation Regulated Feedback Voltage (VFB) Feedback Voltage Line Regulation l 0.495 VIN = 2.25V to 5.5V FB Pin Input Current VFB = 0.5V Minimum On Time (tON,min) VIN = 5.5V Maximum Duty Cycle 22 l l 100 % Top Switch ON-Resistance 31 m Bottom Switch ON-Resistance 8 m Top Switch Current Limit (IPEAKMAX) VOUT/VIN 0.2 4.5 Bottom Switch Current Limit (IVALLEYMAX) 4.8 5.1 3.9 Bottom Switch Reverse Current Limit (IREVMAX) Forced Continuous Mode SW Leakage Current VEN = 0.1V -0.75 -1.5 A A -2.25 100 A nA Power Good and Soft-Start PGOOD Rising Threshold PGOOD Hysteresis As a Percentage of the Regulated VOUT l l 97 0.7 98 1.2 99 1.7 % % Overvoltage Rising Threshold Overvoltage Hysteresis As a Percentage of the Regulated VOUT l l 107 1 110 2.2 114 3.5 % % PGOOD Delay 120 PGOOD Pull Down Resistance VPGOOD = 0.1V PGOOD Leakage Current VPGOOD = 5.5V Soft-Start Duration VOUT rising from 0V to PGOOD Threshold 10 s 20 20 nA l 0.25 1 3 ms l 1.9 2 2.1 MHz l 1.9 2 2.1 MHz l 1 3 MHz l 40 Level High Level Low l l 1.2 For Programming Pulse Skip Mode For Programming Forced Continuous Mode For Programming Burst Mode Operation l l l Oscillator and MODE/SYNC Default Oscillator Frequency Oscillator Frequency with RT = 34.8k Frequency Range RT Programming and Synchronization Minimum SYNC High or Low Pulse Width SYNC Pulse Voltage Levels MODE/SYNC No Clock Detect Time MODE/SYNC Pin Threshold ns 0.4 10 1.0 VIN - 0.1 Float V V s 0.1 VIN - 1.0 V V V Rev. A For more information www.analog.com 3 LTC3307A ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3307A is tested under pulsed load conditions such that TJTA. The LTC3307AE is guaranteed to meet specifications from 0C to 85C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. The LTC3307AI is guaranteed over the -40C to 125C operating junction temperature range. The LTC3307AJ and LTC3307AH are guaranteed over the -40C to 150C operating junction temperature range. The LTC3307AMP is guaranteed over the -55C to 150C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures above 125C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance, and other environmental factors. The junction temperature (TJ in C) is calculated from ambient temperature (TA in C) and power dissipation (PD in Watts) according to the formula: TJ = TA + (PD * JA), where JA (in C/W) is the package thermal impedance. See High Temperature Considerations section for more details. The LTC3307A includes overtemperature protection that protects the device during momentary overload conditions. Junction temperatures will exceed 150C when overtemperature protection is engaged. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: Supply current specification does not include switching currents. Actual supply currents will be higher. Rev. A 4 For more information www.analog.com LTC3307A TYPICAL PERFORMANCE CHARACTERISTICS Feedback Voltage VIN=3.3V, TA = 25C, unless otherwise noted. Minimum On-Time 505 Minimum On-Time 60 60 50 50 502 501 500 499 498 497 MINIMUM ON-TIME (ns) 503 MINIMUM ON-TIME (ns) 40 30 20 150C 25C -50C 10 496 495 -50 -25 0 0 25 50 75 100 125 150 TEMPERATURE (C) 2 2.5 3 3.5 4 4.5 INPUT VOLTAGE (V) 3307A G01 40 PMOS NMOS RDS(ON) (m) RDS(ON) (m) 28 24 20 16 12 VIN = 3.3V 2.16 25 PMOS NMOS 20 2.12 2.08 2.04 2.00 1.96 1.92 1.88 1.84 5 -50 -25 5.5 0 1.80 25 50 75 100 125 150 TEMPERATURE (C) 3307A G04 3.2 2.20 2.16 3.0 2.16 2.8 2.12 1.92 2.4 2.2 2.0 1.8 1.6 1.4 1.88 VIN = 5.5V VIN = 3.3V VIN = 2.25V 1.84 1.80 -50 -25 FREQUENCY (MHz) FREQUENCY (MHz) 1.96 0 25 50 75 100 125 150 TEMPERATURE (C) 3307A G07 3 3.5 4 4.5 INPUT VOLTAGE (V) 5.5 RT Switching Frequency RT = 34.8 k 2.08 2.04 2.00 1.96 1.92 1.88 1.2 VIN = 5.5V VIN = 3.3V VIN = 2.25V 1.84 1.0 0.8 5 2.12 2.6 2.00 2.5 3307A G06 Switching Frequency Default Switching Frequency 2.04 2 3307A G05 2.20 2.08 25 50 75 100 125 150 TEMPERATURE (C) 3307A G03 10 8 5 0 Default Switching Frequency 15 3 3.5 4 4.5 INPUT VOLTAGE (V) VIN = 5.5V VIN = 3.3V VIN = 2.25V 2.20 30 32 DEFAULT FREQUENCY (MHz) 0 -50 -25 5.5 35 36 2.5 20 Switch On Resistance 40 2 30 3307A G02 Switch On Resistance 44 4 5 40 10 DEFAULT FREQUENCY (MHz) FEEDBACK VOLTAGE (mV) 504 20 25 30 35 40 45 50 55 60 65 70 75 RT (k) 3307A G08 1.80 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 3307A G09 Rev. A For more information www.analog.com 5 LTC3307A TYPICAL PERFORMANCE CHARACTERISTICS PMOS Current Limit Switch Current Limits 5.5 DUTY CYCLE = 20% DUTY CYCLE = 20% 5.0 4.5 4.0 3.5 3.0 0 4.5 4.0 3.5 25C -60C 150C 3.0 NMOS IVALLEYMAX PMOS IPEAKMAX 2.5 -50 -25 PMOS CURRENT (A) 5.0 PMOS CURRENT (A) SWITCH CURRENT (A) PMOS Current Limit 5.5 5.5 5.0 2.5 25 50 75 100 125 150 TEMPERATURE (C) 2 2.5 3 3.5 4 4.5 INPUT VOLTAGE (V) 3307A G10 2.5 VIN=3.3V, TA = 25C, unless otherwise noted. 5 2.5 5.5 VIN = 2.5V VIN = 3.3V VIN = 5V 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 3307A G12 VIN Quiescent Current, Burst Mode Operation, Sleeping VIN Shutdown Current VIN Quiescent Current All Modes, Not Sleeping 70 1.30 1.25 1.5 1.0 VIN CURRENT (mA) 60 VIN CURRENT (A) VIN CURRENT (A) 3.5 3.0 65 55 50 45 1.20 1.15 1.10 40 0.5 VIN = 5.5V VIN = 3.3V VIN = 2.25V 35 0 -50 -25 0 30 -50 -25 25 50 75 100 125 150 TEMPERATURE (C) 0 25 50 75 100 125 150 TEMPERATURE (C) 3307A G13 0 -50 -25 2.4 EN RISING 400 PMOS NMOS 0 390 380 370 360 EN FALLING 350 25 50 75 100 125 150 TEMPERATURE (C) 3307A G16 25 50 75 100 125 150 TEMPERATURE (C) 340 -50 -25 0 VIN UVLO Threshold 2.3 VIN UVLO (V) EN THRESHOLD (mV) 4 2 0 3307A G15 EN Threshold VIN = 5.5V 1 1.00 -50 -25 410 3 VIN = 5.5V VIN = 3.3V VIN = 2.25V 1.05 3307A G14 Switch Leakage SWITCH LEAKAGE CURRENT (A) 4.0 3307A G11 2.0 5 4.5 RISING FALLING 2.2 2.1 2.0 1.9 25 50 75 100 125 150 TEMPERATURE (C) 3307A G17 1.8 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 3307A G18 Rev. A 6 For more information www.analog.com LTC3307A TYPICAL PERFORMANCE CHARACTERISTICS VOUT Load Regulation in = 1.2V Application VOUT=1.2V 1.212 108 106 UV, UV, OV, OV, 104 102 100 VOUT RISING VOUT FALLING VOUT RISING VOUT FALLING 1.212 1.210 1.210 1.208 1.208 1.206 1.206 1.204 1.204 1.202 1.202 1.200 1.198 1.196 98 1.188 25 50 75 100 125 150 TEMPERATURE (C) 0 0.5 1 1.192 1.5 2 2.5 100 95 90 85 85 75 70 VOUT = 0.5V VOUT = 0.75V VOUT = 1V VOUT = 1.2V VOUT = 1.8V 55 50 0.001 93 0.01 0.1 ILOAD (A) 1 VOUT = 0.5V VOUT = 0.75V VOUT = 1V VOUT = 1.2V VOUT = 1.8V 65 50 0.001 3 0.01 3307A G22 95 Murata DFE201612E SERIES EFFICIENCY (%) 90 330nH 470nH 680nH 1.4 1.8 2.2 2.6 SWITCHING FREQUENCY (MHz) 3.0 3307A G25 0.1 ILOAD (A) 1 75 70 50 0.001 3 100 90 70 87 85 83 81 3 3.5 4 VIN (V) 0.1 ILOAD (A) 5 5.5 3307A G26 3 3307A G24 fSW = 2MHz, Murata DFE201612E-R47M 60 50 40 30 BURST FC PULSE SKIP 10 4.5 1 Efficiencyvs vsLoad, Load,3.3V 3.3Vto1.2V, Efficiency to 1.2V, ffSW = 2MHz SW=2MHz 20 0.01A (BURSTING) 3A (CONTINUOUS) 2.5 0.01 3307A G23 80 2 VOUT = 1V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V 65 89 75 5.5 80 91 77 5 fSW = 2MHz Murata DFE201210S-R47M 55 fSW = 2MHz Murata DFE201612E-R47M 79 3 3.5 4 4.5 INPUT VOLTAGE (V) 60 Efficiency = 1.2V Efficiencyvs vsVVININ,,VVOUT OUT=1.2V, Burst Mode Operation fSW=2MHz, BurstMode Operation 93 91 1 70 55 92 88 75 60 Efficiency Efficiencyvs vsFsw fSW, 3.3Vin to 1.2Vout, 1.5A 3.3VINto1.2V ILOAD==1.5A OUT,Iload 89 80 EFFICIENCY (%) 65 EFFICIENCY (%) 90 85 80 2.5 Efficiency,VVININ==5.0V Efficiency, 5V BurstMode ModeOperation Operation Burst fSW = 2MHz Murata DFE201210S-R47M 95 EFFICIENCY (%) EFFICIENCY (%) 100 2 3307A G21 90 60 EFFICIENCY (%) 1.188 Efficiency,VVIN Efficiency, = 3.3V IN=3.3V Burst Mode Mode Operation Operation Burst fSW = 2MHz Murata DFE201210S-R47M 95 3 3307 G20 3307A G19 100 ILOAD = 0A ILOAD = 3A 1.190 ILOAD (A) Efficiency,VVIN Efficiency, = 2.5V IN=2.5V Burst Mode Mode Operation Operation Burst 1.198 1.194 VIN = 2.25V VIN = 3.3V VIN = 5.5V 1.190 0 1.200 1.196 1.194 1.192 96 -50 -25 VOUTLine LineRegulation Regulationinin Vout VOUT==1.2V Application Vout 1.2V Application VOUT (V) 110 VOUT (V) PERCENTAGE OF THE REGULATED VOUT (%) UV, OV PGOOD Thresholds 112 VIN=3.3V, TA = 25C, unless otherwise noted. 0 0.001 0.01 0.1 ILOAD (A) 1 3 3307A G27 Rev. A For more information www.analog.com 7 LTC3307A TYPICAL PERFORMANCE CHARACTERISTICS Start-Up Waveforms Start-Up Forced Continuous Continuous Mode Mode Forced VIN=3.3V, TA = 25C, unless otherwise noted. Start-Up Start-Up Waveforms Burst Mode Operation Start-Up Waveforms Start-Up Waveforms Pulse Skip Mode EN 2V/DIV EN 2V/DIV EN 2V/DIV VOUT 500mV/DIV IL 500mA/DIV VOUT 500mV/DIV VOUT 500mV/DIV IL 250mA/DIV IL 250mA/DIV PGOOD 2V/DIV PGOOD 2V/DIV PGOOD 2V/DIV 200s/DIV 3307A G28 200s/DIV 3307A G29 3.3VIN to 1.2V OUT, 2MHz TYPICAL APPLICATION RLOAD = 120 3.3VIN to 1.2V OUT, 2MHz TYPICAL APPLICATION RLOAD = 120 Switching Waveforms, Forced Continuous Mode Switching Waveforms, Waveforms, Switching Pulse Skip Skip Mode Mode Pulse IL 500mA/DIV IL 500mA/DIV VOUT 10mV/DIV VOUT 10mV/DIV 3307A G31 3.3VIN to 1.2V OUT, 2MHz TYPICAL APPLICATION RLOAD = 120 SW 2V/DIV IL 200mA/DIV VOUT 5mV/DIV 3307A G33 3307A G32 200ns/DIV 3.3VIN to 1.2V OUT, 2MHz TYPICAL APPLICATION ILOAD = 500mA 4s/DIV 5.0VIN to 1.2V OUT, 2MHz APPLICATION ILOAD = 2mA Load Transient Response, Forced Continuous Mode 800ns/DIV 3.3VIN to 1.2V OUT, 2MHz TYPICAL APPLICATION ILOAD = 50mA Load Transient Response, Pulse Skip Mode Load Transient Response, Burst Mode Operation ILOAD 2A/DIV ILOAD 2A/DIV ILOAD 2A/DIV IL 2A/DIV IL 2A/DIV IL 2A/DIV VOUT 50mV/DIV VOUT 50mV/DIV VOUT 50mV/DIV 10s/DIV 3307A G34 3.3VIN to 1.2V OUT, 2MHz TYPICAL APPLICATION COUT = 30F, L = 470nH LOAD STEP: 50mA TO 2.25A (10A/uS) 3307A G30 Switching Waveforms, Burst Mode Operation SW 5V/DIV SW 2V/DIV 200s/DIV 10s/DIV 3307A G35 3.3VIN to 1.2V OUT, 2MHz TYPICAL APPLICATION COUT = 30F, L = 470nH LOAD STEP: 50mA TO 2.25A (10A/uS) 10s/DIV 3307A G36 3.3VIN to 1.2V OUT, 2MHz TYPICAL APPLICATION COUT = 30F, L = 470nH LOAD STEP: 50mA TO 2.25A (10A/uS) Rev. A 8 For more information www.analog.com LTC3307A PIN FUNCTIONS AGND (Pin 1): The AGND pin is the output voltage remote ground sense. Connect the AGND pin directly to the negative terminal of the output capacitor at the load. The AGND pin is also the ground reference for the internal analog circuitry. Place a small analog bypass 0201 or 0402 ceramic capacitor as close as possible to the VIN (Pin 3) and AGND pins. Connect RT and FB returns to AGND as well. EN (Pin 2): The EN pin has a precision IC enable threshold with hysteresis. An external resistor divider, from VIN or from another supply, can be used to program the threshold below which the LTC3307A will shut down. If the precision threshold is not required, tie EN directly to VIN. When the EN pin is low the LTC3307A enters a low current shutdown mode where all internal circuitry is disabled. Do not float this pin. VIN (Pins 3, 8): The VIN pins supply current to internal circuitry and topside power switch. Connect both VIN pins together with short wide traces and bypass to PGND and AGND with low ESR capacitors located as close as possible to the pins. PGND (Pins 4, 7, Exposed Pad Pin 13): The PGND pins are the return path of the internal bottom side power switch. Connect the negative terminal of the input capacitors as close to the PGND pins as possible. For low parasitic inductance and good thermal performance, connect Pin 4 and Pin 7 to a large continuous ground plane on the printed circuit board directly under the LTC3307A. The PGND exposed pad is the main electrical and thermal highway and should be connected to large PCB ground plane(s) with many vias. SW (Pins 5, 6): The SW pins are the switching outputs of the internal power switches. Connect these pins together and to the inductor with a short, wide trace. MODE/SYNC (Pin 9): The MODE/SYNC pin is a mode selection and external clock synchronization input. Ground this pin to enable Pulse Skip mode at light loads. For higher efficiency at light loads, tie this pin to VIN to enable the low-ripple Burst Mode operation. For faster transient response, lower noise and full frequency operation over a wide load range, float this pin to enable forced continuous mode. Drive MODE/SYNC with an external clock to synchronize the switcher to the applied frequency. While synchronizing, the part operates in the forced continuous mode. The slope compensation is automatically adapted to the external clock frequency. In the absence of an external clock the switching frequency is determined by theRTpin. RT (Pin 10): The RT pin sets the switching frequency with an external resistor to AGND. If this pin is tied to VIN, the buck will switch at the default oscillator frequency. If the external clock is driving the MODE/SYNC pin, the RT pin is ignored. PGOOD (Pin 11): The PGOOD pin is the open drain output of an internal power good comparator. When the regulated output voltage falls below the PGOOD threshold or rises above the overvoltage threshold, this pin is pulled low. When VIN is above VIN UVLO and the part is in shutdown, this pin is also pulled low. FB (Pin 12): Program the output voltage and close the control loop by connecting this pin to the middle node of a resistor divider between the VOUT and AGND. The LTC3307A regulates FB to 500mV (typical). A phase lead capacitor connected between FB and VOUT may be used to optimize transient response. Rev. A For more information www.analog.com 9 LTC3307A BLOCK DIAGRAM VIN R1 R2 (OPT) 2 EN 0.4V + - MODE DETECT 9 10 0.55V 0.5V 0.49V INTERNAL REFERENCE BURST FORCED CONTINUOUS PULSE SKIP MODE/SYNC RT VIN SWITCH LOGIC AND ANTI-SHOOT THROUGH S Q OSCILLATOR RT R + - L SW 5, 6 VOUT COUT 4, 7, AND 13 (EXPOSED PAD) BURST DETECT FB GM VC CPAR CIN PGND SLOPE COMP 1 AGND VIN 3, 8 0.5V 0.49V RC CC 0.55V + - + - PGOOD RA CFF 12 11 RB FAULT ISS SS FAULT CSS 3307A BD Rev. A 10 For more information www.analog.com LTC3307A OPERATION Voltage Regulation Mode Selection The LTC3307A is a 5V, 3A monolithic, constant frequency, peak current mode control, step-down DC/DC converter. The synchronous buck switching regulators are internally compensated and require only external feedback resistors to set the output voltage. An internal oscillator, with the frequency set using a resistor on the RT pin or synchronized to an external clock, turns on the internal top power switch at the beginning of each clock cycle. Current in the inductor ramps up until the top switch current comparator trips and turns off the top power switch. The peak inductor current at which the top switch turns off is controlled by an internal VC voltage. The error amplifier regulates VC by comparing the voltage on the FB pin with an internal 500mV reference. An increase in the load current causes a reduction in the feedback voltage relative to the reference, causing the error amplifier to raise the VC voltage until the average inductor current matches the new load current. When the top power switch turns off, the synchronous power switch turns on and ramps down the inductor current for the remainder of the clock cycle or, if in pulse skip or Burst mode, until the inductor current falls to zero. If an overload condition results in excessive current flowing through the bottom switch, the next clock cycle will be skipped until switch current returns to a safe level. The LTC3307A operates in three different modes set by the MODE/SYNC pin: pulse skip mode (when the MODE/ SYNC pin is set low), forced continuous mode (when the MODE/SYNC pin is floating) and Burst Mode operation (when the MODE/SYNC pin is set high). The enable pin has a precision 400mV threshold to provide event-based power-up sequencing by connecting the EN pin to the output of another buck through a resistor divider. If the EN pin is low, the device is shut down and in a low quiescent current state. When the EN pin is above its threshold, the switching regulator will be enabled. The LTC3307A has forward and reverse inductor current limiting, short-circuit protection, output over-voltage protection, and soft-start to limit inrush current during startup or recovery from a short-circuit. In pulse skip mode, the oscillator operates continuously and positive SW transitions are aligned to the clock. Negative inductor current is disallowed and, during light loads, switch pulses are skipped to regulate the output voltage. In forced continuous mode, the oscillator operates continuously. The top switch turns on every cycle and regulation is maintained by allowing the inductor current to reverse at light load. This mode allows the buck to run at a fixed frequency with minimal output ripple. In forced continuous mode, if the inductor current reaches IREVMAX (into the SW pin), the bottom switch will turn off for the remainder of the cycle to limit the current. In Burst Mode operation at light loads, the output capacitor is charged to a voltage slightly higher than its regulation point. The regulator then goes into a sleep state, during which time the output capacitor provides the load current. In sleep, most of the regulator's circuitry is powered down, helping conserve input power. When the output voltage drops below its programmed value, the circuitry is powered on and another burst cycle begins. The sleep time decreases as load current increases. In Burst Mode operation, the regulator will burst at light loads whereas at higher loads it will operate in constant frequency PWM mode. Rev. A For more information www.analog.com 11 LTC3307A OPERATION Synchronizing the Oscillator to an External Clock Output Overvoltage Protection The LTC3307A's internal oscillator can be synchronized through an internal PLL circuit to an external frequency by applying a square wave clock signal to the MODE/ SYNC pin. During an output overvoltage event, when the FB pin voltage is greater than 110% of nominal, the LTC3307A top power switch will be turned off. If the output remains out of regulation for more than 120s, the PGOOD pin will be pulled low. During synchronization, the top power switch turn-on is locked to the rising edge of the external frequency source. While synchronizing, the switcher operates in forced continuous mode. The slope compensation is automatically adapted to the external clock frequency. The synchronization frequency range is 1MHz to 3MHz. After detecting an external clock on the first rising edge of the MODE/SYNC pin, the internal PLL gradually adjusts its operating frequency to match the frequency and phase of the signal on the MODE/SYNC pin. When the external clock is removed, the LTC3307A will detect the absence of the external clock within approximately 10s. During this time, the PLL will continue to provide clock cycles. Once the external clock removal has been detected, the oscillator will gradually adjust its operating frequency to the one programmed by the RT pin. Output Power Good When the LTC3307A's output voltage is within the -2%/+10% window of the nominal regulation voltage the output is considered good and the open-drain PGOOD pin goes high impedance and is typically pulled high with an external resistor. Otherwise, the internal pull-down device will pull the PGOOD pin low. The PGOOD pin is also pulled low during the following fault conditions: EN pin is low, VIN is too low or thermal shutdown. To filter noise and short duration output voltage transients, the lower threshold has a hysteresis of 1.2%, the upper threshold has a hysteresis of 2%, and both have a built-in time delay to report PGOOD, typically 120s. An output overvoltage event should not happen under normal operating conditions. Overtemperature Protection To prevent thermal damage to the LTC3307A and its surrounding components, the device incorporates an overtemperature (OT) function. When the die temperature reaches 165C (typical, not tested) the switcher is shut down and remains in shutdown until the die temperature falls to 160C (typical, not tested). Output Voltage Soft-Start Soft starting the output prevents current surge on the input supply and/or output voltage overshoot. During the soft-start, the output voltage will proportionally track the internal node voltage ramp. An active pull-down circuit discharges that internal node in the case of fault conditions. The ramp will restart when the fault is cleared. Fault conditions that initiate the soft-start ramp are the EN pin transitioning low, VIN voltage falling too low, or thermal shutdown. Dropout Operation As the input supply voltage approaches the output voltage, the duty cycle increases toward 100%. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle, eventually reaching 100% duty cycle. The output voltage will then be determined by the input voltage minus the DC voltage drop across the internal P-channel MOSFET and the inductor. Rev. A 12 For more information www.analog.com LTC3307A Low Supply Operation The LTC3307A is designed to operate down to an input supply voltage of 2.25V. One important consideration at low input supply voltages is that the RDS(ON) of the internal power switches increases. Calculate the worst case LTC3307A power dissipation and die junction temperature at the lowest input voltages. Output Short-Circuit Protection and Recovery The peak inductor current level, at which the current comparator shuts off the top power switch, is controlled by the internal VC voltage. When the output current increases, the error amplifier raises VC until the average inductor current matches the load current. The LTC3307A clamps the maximum VC voltage, thereby limiting the peak inductor current. When the output is shorted to ground, the inductor current decays very slowly when the bottom power switch is on because the voltage across the inductor is low. To keep the inductor current in control, a secondary limit is imposed on the valley of the inductor current. If the inductor current measured through the bottom power switch remains greater than IVALLEYMAX at the end of the cycle, the top power switch will be held off. Subsequent switching cycles will be skipped until the inductor current falls below IVALLEYMAX. Recovery from an output short circuit may involve a softstart cycle if VFB falls more than approximately 100mV below regulation. During such a recovery, VFB will quickly charge up by that ~100mV and then follow the soft-start ramp until regulation is reached. APPLICATIONS INFORMATION Refer to the Block Diagram for reference. Output Voltage and Feedback Network The output voltage is programmed by a resistor divider between the output and the FB pin. Choose the resistor values according to: V R A = RB OUT - 1 (1) 500mV as shown in Figure1: Reference designators refer to the Block Diagram. Typical values for RB range from 40k to 400k. 0.1% resistors are recommended to maintain output voltage accuracy. The buck regulator transient response may improve with an optional phase lead capacitor CFF that helps cancel the pole created by the feedback resistors and the input capacitance of the FB pin. Experimentation with capacitor values between 2pF and 22pF may improve transient response. The values used in the typical application circuits are a good starting point. Operating Frequency Selection and Trade-Offs VOUT BUCK SWITCHING FB REGULATOR RA RB CFF + (OPTIONAL) 3307A F01 Figure1. Feedback Resistor Network COUT Selection of the operating frequency is a trade-off between efficiency, component size, transient response and input voltage range. The advantage of high frequency operation is that smaller inductor and capacitor values may be used. Higher switching frequencies allow for higher control loop bandwidth and, therefore, faster transient response. The Rev. A For more information www.analog.com 13 LTC3307A APPLICATIONS INFORMATION disadvantages of higher switching frequencies are lower efficiency, because of increased switching losses, and a smaller input voltage range, because of minimum switch on-time limitations. Table1. RT Value vs Switching Frequency fSW (MHz) RT (k) 1.0 71.5 1.2 59.0 1.4 49.9 1.6 43.2 1.8 38.3 2.0 34.8 2.2 30.9 2.4 28.7 2.6 26.1 2.8 24.3 3.0 22.6 The minimum on-time of the buck regulator imposes a minimum operating duty cycle. The highest switching frequency (fSW(MAX)) for a given application can be calculated as follows: fSW (MAX ) = VOUT tON(MIN) * VIN(MAX ) (2) where VIN(MAX) is the maximum input voltage, VOUT is the output voltage and tON(MIN) is the minimum top switch on-time. This equation shows that a slower switching frequency is necessary to accommodate a high VIN(MAX)/VOUT ratio. The LTC3307A is capable of a maximum duty cycle of 100%, therefore, the VIN-to-VOUT dropout is limited by the RDS(ON) of the top switch, the inductor DCR and the load current. Inductor Selection and Maximum Output Current Setting the Switching Frequency The LTC3307A uses a constant frequency peak current mode control architecture. There are three methods to set the switching frequency. The first method, connecting the RT pin to VIN, sets the switching frequency to the internal default with a nominal value of 2MHz. The second method is with a resistor (RT) tied from the RT pin to ground. The frequency can be programmed from 1MHz to 3MHz. Table1 and the Equation 3 show the necessary RT value for a desired switching frequency: RT = 73.4 fsw The third method to set the switching frequency is by synchronizing the internal PLL circuit to an external square wave clock applied to the MODE/SYNC pin. The synchronization frequency range is 1MHz to 3MHz. The square wave amplitude should have valleys that are below 0.4V and peaks above 1.2V. High and low pulse widths should both be at least 40ns. - 1.9 (3) where RT is in k and fSW is the desired switching frequency in MHz, ranging from 1MHz to 3MHz. Considerations in choosing an inductor are inductance, RMS current rating, saturation current rating, DCR and core loss. Select the inductor value based on the following equation: L L VOUT VOUT for * 1- 0.5 (4) 0.9A * fSW VIN(MAX ) VIN(MAX ) VOUT 0.25 * VIN(MAX ) 0.9A * fSW for VOUT VIN(MAX ) > 0.5 (5) where fSW is the switching frequency, VIN(MAX) is the maximum input voltage. To avoid overheating of the inductor choose an inductor with an RMS current rating that is greater than the maximum expected output load of the application. Overload and short-circuit conditions need to be taken into consideration. Rev. A 14 For more information www.analog.com LTC3307A APPLICATIONS INFORMATION In addition, ensure that the saturation current rating (typically labeled ISAT) of the inductor is higher than the maximum expected load current plus half the inductor ripplecurrent: 1 ISAT > ILOAD(MAX ) + IL (6) 2 where ILOAD(MAX) is the maximum output load current for a given application and IL is the inductor ripple current calculated as: IL = A more conservative choice would be to use an inductor with an ISAT rating higher than the maximum current limit of the LTC3307A. To keep the efficiency high, choose an inductor with the lowest series resistance (DCR). The core material should be intended for high frequency applications. Table 2 shows recommended inductors from several manufacturers. V * 1- OUT (7) L * fSW VIN VOUT Table 2. Recommended Inductors with Typical Specifications MANUFACTURER INDUCTOR FAMILY INDUCTANCE (nH) ITEMP (A)* ISAT (A) DCR (m) W x L x H (mm) Murata DFE18SAN-E0 240 3.2 4.2 36 1.6 x 0.8 x 0.8 Murata DFE18SAN-G0 240 3.5 4.9 30 1.6 x 0.8 x 1.0 Murata DFE201210S 110, 470 6.3, 4.0 11, 5.3 8, 27 2.0 x 1.2 x 1.0 Murata DFE201610E 240 to 680 5.5 to 3.7 7.0 to 4.8 16 to 36 2.0 x 1.6 x 1.0 Murata DFE201612E 240 to 680 6.0 to 4.1 7.8 to 4.8 13 to 27 2.0 x 1.6 x 1.2 Murata DFE252010F 330 to 680 5.6 to 4.1 7.6 to 5.5 16 to 31 2.5 x 2.0 x 1.0 Murata DFE252012F 330 to 680 6.0 to 4.6 8.5 to 6.0 14 to 25 2.5 x 2.0 x 1.2 Vishay IHHP-0806AB-01 220 to 470 5.3 to 4.2 5.8 to 4.4 13 to 29 2.0 x 1.6 x 1.2 Vishay IHHP-1008AB-01 220 to 680 7.4 to 3.8 7.1 to 4.1 8.4 to 28 2.5 x 2.0 x 1.2 XFRMS XFHCL43LT 220 to 470 8.0 to 4.5 7.0 to 3.8 13 to 25 (max) 2.5 x 2.0 x 1.2 NIC NPIM26LP 240 to 680 6.5 to 4.2 7.5 to 5.1 15 to 36 2.0 x 1.6 x 1.0 NIC NPIM20LP 240 to 680 6.0 to 4.4 9.5 to 5.5 18 to 32 2.5 x 2.0 x 1.0 Sumida 201610CDMCC/DS 240, 470 5.2, 3.8 6.5, 4.2 19, 34 2.2 x 1.8 x 1.0 Sumida 252010CDMCC/DS 330 to 1000 5.2 to 3.2 6.8 to 3.8 16 to 46 2.7 x 2.2 x 1.0 Wurth Electronik WE-PMMI-0805LP 110 3 6 24 2.0 x 1.2 x 0.6 Wurth Electronik WE-PMMI-0806 240 to 470 3.5 to 3.0 4.0 to 3.4 15 to 20 2.0 x 1.6 x 0.6 Wurth Electronik WE-PMCI-0806 240, 470 3.6, 2.9 5.4, 4.2 19, 34 2.0 x 1.6 x 1.0 Wurth Electronik WE-PMCI-1008 470 3.3 5 25 2.5 x 2.0 x 1.0 Wurth Electronik WE-LQS-2512 160 3.7 6.4 16 2.5 x 2.0 x 1.2 *Strongly depends on the PCB thermal properties Rev. A For more information www.analog.com 15 LTC3307A APPLICATIONS INFORMATION Input Capacitors Bypass the input of the LTC3307A with at least two ceramic capacitors close to the part, one on each side from VIN to PGND, for best performance. These capacitors should be 0603 or 0805 in size. Smaller, optional 0201 capacitors can also be placed as close as possible to the LTC3307A directly on the traces leading from VIN (Pin3) and PGND (Pin4) and on the traces leading from VIN (Pin8) and PGND (Pin7) for better performance with minimal (if at all) increase in application footprint. See the layout section for more detail. X7R or X5R capacitors are recommended for best performance across temperature and input voltage variations (see Table3). Note that larger input capacitance is required when a lower switching frequency is used. If the input power source has high impedance, or there is significant inductance due to long wires or cables, additional bulk capacitance may be necessary. This can be provided with an electrolytic capacitor. A ceramic input capacitor combined with trace or cable inductance forms a high quality (under damped) tank circuit. If the LTC3307A circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the LTC3307A's voltage rating. This situation is easily avoided (see Application Note AN88). Table3. Ceramic Capacitor Manufacturers VENDOR URL AVX www.avxcorp.com Murata www.murata.com TDK www.tdk.com Taiyo Yuden www.t-yuden.com Samsung www.samsungsem.com Wurth Elektronik www.we-online.com Output Capacitor, Output Ripple and Transient Response The output capacitor has two essential functions. Along with the inductor, it filters the square wave generated by the LTC3307A at the SW pin to produce the DC output. In this role, it determines the output ripple; thus, low impedance at the switching frequency is important. The second function is to store energy in order to satisfy transient loads and stabilize the LTC3307A's control loop. The LTC3307A is internally compensated and has been designed to operate at a high bandwidth for fast transient response capability. The selection of COUT affects the bandwidth of the system, but the transient response is also affected by VOUT, VIN, fSW and other factors. A good place to start is with the output capacitance value of approximately: I COUT = 20 * MAX fSW 0.5 VOUT (8) where COUT is the recommended output capacitor value in F, fSW is the switching frequency in MHz, IMAX =3A is the rated output current in Amps, and VOUT is in Volts. A lower value output capacitor saves space and cost but transient performance will suffer and loop stability must be verified. Ceramic capacitors have very low equivalent series resistance (ESR) and provide the best output ripple and transient performance. Use X5R or X7R ceramic capacitors (see Table3). Even better output ripple and transient performance can be achieved by using low-ESL reverse geometry or three-terminal ceramic capacitors. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop increases the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation components and the output capacitor size. Typically, 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. Although affected by VOUT, VIN, fSW, tON(MIN), the equivalent series inductance (ESL) of the output capacitor, and other factors, the output droop, VDROOP, is usually about 3 times the linear drop of the first cycle: VDROOP = 3 * IOUT COUT * fSW (9) where IOUT is the load step. Rev. A 16 For more information www.analog.com LTC3307A APPLICATIONS INFORMATION Transient performance and control loop stability can be improved with a higher COUT and/or the addition of a feedforward capacitor CFF placed between VOUT and FB. Capacitor CFF provides phase lead compensation by creating a high frequency zero which improves the phase margin and the high-frequency response. The values used in the typical application circuits are a good starting point. LTpowerCAD(R) is a useful tool to help optimize CFF and COUT for a desired transient performance. Applying a load transient and monitoring the response of the system or using a network analyzer to measure the actual loop response are two ways to experimentally verify transient performance and control loop stability, and to optimize CFF and COUT. When using the load transient response method to stabilize the control loop apply an output current pulse of 20% to 100% of full load current having a very fast rise time. This will produce a transient on the output voltage. Monitor VOUT for overshoot or ringing that might indicate a stability problem (see Application NoteAN149). The rising threshold of the EN comparator is 400mV, with 50mV of hysteresis. The EN pin can be tied to VIN if the shutdown feature is not used. Adding a resistor divider from VIN to EN programs the LTC3307A to regulate the output only when VIN is above a desired voltage (see Figure2). Typically, this threshold, VIN(EN), is used in situations where the input supply is current limited, or has a relatively high source resistance. A switching regulator draws near constant power from its input source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. The VIN(EN) threshold prevents the regulator from operating at source voltages where problems may occur. This threshold can be adjusted by setting the values R1 and R2 such that they satisfy the followingequation: R1 VIN(EN) = + 1 * 400mV (10) R2 as shown in Figure2: Output Voltage Sensing The LTC3307A's AGND pin is the ground reference for the internal analog circuitry, including the bandgap voltage reference. To achieve good load regulation connect the AGND pin to the negative terminal of the output capacitor (COUT) at the load. Any drop in the high current power ground return path will be compensated. The AGND node carries very little current and, therefore, can be a minimal size trace. Place a small analog bypass 0201 or 0402 ceramic capacitor as close as possible to the LTC3307A directly on the traces leading from VIN (Pin3) and AGND pin. All of the signal components, such as the FB resistor dividers and the RT resistor, should be referenced to the AGND node. See the example PCB Layout for moreinformation. Enable Threshold Programming The LTC3307A has a precision threshold enable pin to enable or disable the switching. When forced low, the device enters a low current shutdown mode. VIN BUCK SWITCHING EN REGULATOR R1 R2 3307A F02 Figure2. EN Divider The LTC3307A will remain off until VIN is above VIN(EN). The buck regulator will remain enabled until VIN falls to 0.875*VIN(EN) and EN is 350mV. Alternatively, a resistor divider from an output of an upstream regulator to the EN pin of the LTC3307A provides event-based power-up sequencing, enabling the LTC3307A when the output of the upstream regulator reaches a predetermined level (e.g. 90% of the regulated output). Replace VIN(EN) in Equation10 with that predeterminedlevel. Rev. A For more information www.analog.com 17 LTC3307A APPLICATIONS INFORMATION Low EMI PCB Layout The LTC3307A is specifically designed to minimize EMI/EMC emissions and also to maximize efficiency and improve transient response when switching at highfrequencies. See Figure3 for a recommended PCB layout. For optimal performance the LTC3307A requires that both input supply VIN pins (Pins 3, 8) each have a local decoupling capacitor with their ground terminals soldered directly to the ground plane on the top layer near PGND pins (Pins 4, 7). These capacitors provide the AC current to the internal power MOSFETs and their drivers. Large, switched currents flow in the VIN and PGND pins and the input capacitors. The loops formed by the input capacitors should be as small as possible by placing the capacitors adjacent to the VIN and PGND pins. Capacitors with small case size such as 0603 are optimal due to lowest parasitic VIN PGND GROUND PLANE ON LAYER 2 COUT1 CIN1 VOUT inductance. Even smaller 0201 capacitors can additionally be placed right next to the respective VIN and PGND pins for better performance with minimal (if at all) increase in application footprint. In addition, place a local, unbroken ground plane under the application circuit on the layer closest to the surface layer. Decoupling AGND is also very important. Place a small analog bypass 0201 or 0402 capacitor as close as possible to the LTC3307A directly on the traces leading from VIN (Pin 3) and AGND (Pin 1). Place the inductor on the same side of the circuit board. The trace connecting SW pins (Pins5,6) to the inductor should be as short as possible to reduce radiated EMI and parasitic coupling. Keep the FB and RT nodes small and far away or shielded from the noisy SW node. VIN CIN1 RT RT 10 7 CIN3 10 L 13 CFF RA 1 RA CBYP 1 COUT1 L VOUT 4 CIN4 RB COUT2 CIN2 AGND VIN COUT3 CIN3 13 CFF 4 7 CIN4 RB PGND GROUND PLANE ON LAYER 2 CBYP COUT4 COUT2 CIN2 AGND PGND VOUT VIN 3307A F03 Figure3a. Recommended PCB Layout for the LTC3307A Small Solution Size PGND 3307A F03b Figure 3b. Recommended PCB Layout for the LTC3307A with capacitors COUT1 and COUT2 rotated by 90, which reduces highfrequency output ripple. Optional 0201 capacitors COUT3 and COUT4 further improve the high-frequency output ripple Rev. A 18 For more information www.analog.com LTC3307A APPLICATIONS INFORMATION High Temperature Considerations Care should be taken in the layout of the PCB to ensure good heat sinking of the LTC3307A. Connect the exposed pad on the bottom of the package (Pin 13) to a large, unbroken ground plane under the application circuit on the layer closest to the surface layer. Place many vias to minimize thermal and electrical impedance. Solder the PGND pins (Pins 4, 7) directly to a ground plane on the top layer. Connect the top layer ground plane to ground plane(s) on lower levels with many thermal vias. These layers will spread heat dissipated by the LTC3307A. Figure4 is a simplified thermal representation of a thermally enhanced LQFN package with exposed pad, with the silicon die and thermal metrics identified. The current source represents power loss PD on the die; node voltages represent temperatures; electrical impedances represent conductive thermal impedances JCBOTTOM, JCTOP, VIA, CB, and convective thermal impedances BA and CA. The junction temperature, TJ, is calculated from the ambient temperature, TA, as: high. Assuming, somewhat arbitrarily but not unreasonably, that VIA ~ (CB + BA)/2, we back calculate (CB + BA)/2 = VIA 60C/W for such a board. The importance of thermal vias becomes clear once we observe that if the test PCB had low-thermal-resistance vias, the JA would have been reduced by up to 10C/W, which is an improvement of up to 20%. Similarly, having more ground planes that are larger, uninterrupted and higher-copper-weight improves CB + BA, which has a dominant effect on JA, given the low value of JCBOTTOM of the package. See the Application Note, "Application Notes for Thermally Enhanced Leaded Plastic Packages", for the proper size and layout of the thermal vias and solder stencils. The maximum load current should be derated as the ambient temperature approaches the maximum junction rating. Power dissipation within the LTC3307A is estimated by calculating the total power loss from an efficiency measurement and subtracting the inductor loss. TA DIE TCTOP TJ = TA + PD * JA(11) where, neglecting the JCTOP + CA path: PD TA CB + BA CB + BA JA JCBOTTOM + + VIA (12) ! 2 2 PACKAGE SUBSTRATE LQFN JCTOP TJ BA TA BA JCBOTTOM CB CB PCB where JCBOTTOM = 8.6C/W. The value of JA = 51C/W reported in the Pin Configuration section corresponds to JEDEC standard 2S2P test PCB, which does not have good thermal vias, i.e., VIA is relatively CA VIA CB CB PCB 3307A F04 BA TA BA TA Figure4. Multi-Layer PCB with Thermal Vias Acts as a Heat Sink Rev. A For more information www.analog.com 19 LTC3307A TYPICAL APPLICATIONS VIN UVLO 3.0V, 1MHz, 1.8V, 3A, Pulse Skip Mode VIN = 3.0V TO 5.5V 4.7F 1F 0201 1F 0201 1.3M EN 200k 15pF VFB LTC3307A VIN 33F x2 10nF AGND RT PGND 261k 100k MODE/SYNC 71.5k VOUT 1.8V 3A SW SW VIN VIN 4.7F 1H 1M PGOOD 3307A TA02 VIN fOSC = 1MHz Small Solution Size, 3MHz, 1.2V, 3A, Forced Continuous Mode VIN = 2.25V TO 5.5V 4.7F 1F 0201 1F 0201 EN VIN VIN 4.7F 330nH 10pF LTC3307A FLOAT VFB MODE/SYNC AGND RT 22.6k PGND VOUT 1.2V 3A SW SW PGOOD VIN 140k 100k 10F x2 10nF 1M VIN 3307A TA03 fOSC = 3MHz Rev. A 20 For more information www.analog.com LTC3307A TYPICAL APPLICATIONS VIN UVLO 3.0V, 2.5V, 3A, Syncing to 1MHz VIN = 3.0V TO 5.5V 4.7F 1F 0201 1F 0201 1.3M EN VIN VIN 200k SW SW 6.8pF LTC3307A VFB VIN VIN 22F x2 10nF AGND RT PGND VOUT 2.5V 3A 402k 100k MODE/SYNC fSYNC = 1MHz 4.7F 1.2H 511k PGOOD 3307A TA04 VOUT High Efficiency, 2MHz, 3A, 5V to 3.3V VIN = 5V 4.7F 1F 0201 1F 0201 680nH EN VIN VIN SW SW 6.8pF LTC3307A MODE/SYNC RT 4.7F FB VIN VOUT 3.3V 3A 562k 100k 10F x2 10nF AGND PGND PGOOD 511k 3307A TA05 VOUT fOSC = 2MHz Rev. A For more information www.analog.com 21 LTC3307A TYPICAL APPLICATIONS High Efficiency, 2MHz, 3A, 5V to 2.5V VIN = 5V 4.7F 1F 0201 1F 0201 EN VIN VIN 680nH MODE/SYNC RT VOUT 2.5V 3A SW SW 6.8pF LTC3307A 4.7F FB VIN 402k 100k 10F x2 10nF AGND PGND PGOOD 511k 3307A TA06 VOUT fOSC = 2MHz High Efficiency, 2MHz, 3A, 3.3V to 1.8V VIN = 3.3V 4.7F 1F 0201 470nH 1F 0201 EN VIN VIN SW SW 15pF LTC3307A MODE/SYNC RT 4.7F FB VIN VOUT 1.8V 3A 261k 100k 15F x2 10nF AGND PGND PGOOD 511k VOUT 3307A TA07 fOSC = 2MHz Rev. A 22 For more information www.analog.com LTC3307A TYPICAL APPLICATIONS High Efficiency, 2MHz, 3A, 3.3V to 1.0V VIN = 3.3V 4.7F 1F 0201 1F 0201 EN VIN VIN SW SW 10pF LTC3307A MODE/SYNC RT 4.7F 330nH FB VIN 200k VOUT 1.0V 3A 15F x2 200k 10nF AGND PGOOD PGND 511k 3307A TA08 VOUT fOSC = 2MHz High Efficiency, 2MHz, 3A, 2.5V to 0.75V VIN = 2.5V 4.7F 1F 0201 330nH 1F 0201 EN VIN VIN SW SW 10pF LTC3307A MODE/SYNC RT 4.7F FB VIN VOUT 0.75V 3A 100k 200k 22F x2 10nF AGND PGND PGOOD 511k VOUT 3307A TA09 fOSC = 2MHz Rev. A For more information www.analog.com 23 For more information www.analog.com 0.70 0.05 aaa Z 2x PACKAGE TOP VIEW D 0.70 SUGGESTED PCB LAYOUT TOP VIEW 2.50 0.05 0.70 0.0000 X aaa Z // bbb Z 0.7500 0.2500 0.0000 0.2500 0.7500 PACKAGE OUTLINE Y E 2x Z H1 MIN 0.65 0.01 0.30 0.22 DETAIL C SUBSTRATE SYMBOL A A1 L b D E D1 E1 e H1 H2 aaa bbb ccc ddd eee fff DETAIL B H2 MOLD CAP NOM 0.74 0.02 0.40 0.25 2.00 2.00 0.70 0.70 0.50 0.24 REF 0.50 REF DIMENSIONS 12b eee M Z X Y fff M Z DETAIL C A1 12x 0.10 0.10 0.10 0.10 0.15 0.08 MAX 0.83 0.03 0.50 0.28 e/2 e L SUBSTRATE THK MOLD CAP HT NOTES DETAIL A DETAIL B A (Reference LTC DWG # 05-08-1530 Rev B) e 7 6 D1 e 0.250 5 DETAIL A PACKAGE BOTTOM VIEW 6 11 b 12 4 1 PIN 1 NOTCH 0.14 x 45 4 SEE NOTES DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE THE EXPOSED HEAT FEATURE MAY HAVE OPTIONAL CORNER RADII 5 6 LQFN 12 0618 REV B METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES 4 3. PRIMARY DATUM -Z- IS SEATING PLANE 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 E1 b 10 ccc M Z X Y PACKAGE DESCRIPTION 2.50 0.05 0.25 0.05 5 0.2500 PIN 1 CORNER 0.2500 ddd Z Z 24 ccc M Z X Y LQFN Package 12-Lead (2mm x 2mm x 0.74mm) LTC3307A Rev. A LTC3307A REVISION HISTORY REV DATE DESCRIPTION A 11/19 Add AEC-Q100 Qualified PAGE NUMBER 1 Add J-grade and #W parts 2 Note 2: Add J-grade 4 Table 2 Added thermal properties note 15 Modified Figure 3 into 3a and 3b Capacitor App circuit changes 18 20-26 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 25 LTC3307A TYPICAL APPLICATION High Efficiency, 2MHz, 0.5V, 3A VIN = 2.25V TO 5.5V 4.7F 1F 0201 EN VIN VIN LTC3307A 1F 0201 220nH SW SW FB MODE/SYNC 33F x2 VIN 4.7F 1M (OPT) VOUT 0.5V 3A 10nF RT AGND PGND PGOOD 511k VOUT 3307A TA08 fOSC = 2MHz RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3308A 5V, 4A Synchronous Step-Down SilentSwitcher in 2mmx2mm LQFN Monolithic Synchronous Step-Down DC/DC Capable of Supplying 4A at Switching Frequencies up to 3MHz. SilentSwitcher Architecture for Ultralow EMI Emissions. 2.25V to 5.5V Input Operating Range. 0.5V to VIN Output Voltage Range with 1% Accuracy. PGOOD Indication, RTProgramming, SYNC Input. 2mm x 2mm LQFN. LTC3309A 5V, 6A Synchronous Step-Down SilentSwitcher in 2mmx2mm LQFN Monolithic Synchronous Step-Down DC/DC Capable of Supplying 6A at Switching Frequencies up to 3MHz. SilentSwitcher Architecture for Ultralow EMI Emissions. 2.25V to 5.5V Input Operating Range. 0.5V to VIN Output Voltage Range with 1% Accuracy. PGOOD Indication, RTProgramming, SYNC Input. 2mm x 2mm LQFN. LTC3315A Dual 5V, 2A Synchronous Step-Down DC/DCs in 2mmx2mm LQFN Dual Monolithic Synchronous Step-Down Voltage Regulators each Capable of Supplying 2A at Switching Frequencies up to 3MHz. 2.25V to 5.5V Input Operating Range. 0.5V to VIN Output Voltage Range with 1% Accuracy. PGOOD Indication, SYNC Input. 2mm x 2mm LQFN. LTC3310S 5V, 10A Synchronous Step-Down SilentSwitcher 2 in 3mmx3mm LQFN Monolithic Synchronous Step-Down DC/DC Capable of Supplying 10A at Switching Frequencies up to 5MHz. Silent Switcher Architecture for Ultralow EMI Emissions. 2.25V to 5.5V Input Operating Range. 0.5V to VIN Output Voltage Range with 1% Accuracy. PGOOD Indication, RT Programming, SYNC Input. Configurable for Paralleling Power Stages. 3mm x 3mm LQFN. LTC3370/ LTC3371 4-Channel 8A Configurable 1A Buck DC/DCs Four Synchronous Buck Regulators with 8 x 1A Power Stages. Can Connect Up to Four Power Stages in Parallel to Make a High Current Output (4A Maximum) with a Single Inductor, 8Output Configurations Possible, Precision PGOOD Indication. LTC3371 Has a Watchdog Timer. LTC3370: 32-Lead 5mm x 5mm QFN. LTC3371: 38-Lead 5mm x 7mm QFN and TSSOP LTC3374A 8-Channel Parallelable 1A Buck DC/DCs Eight 1A Synchronous Buck Regulators. Can Connect Up to Four Power Stages in Parallel to Make a High Current Output (4A Maximum) with a Single Inductor, 15 Output Configurations Possible. Precision Enable inputs and PGOOD_ALL reporting. 38-Lead 5mm x 7mm QFN and TSSOP LTC3375 8-Channel Parallelable 1A Buck DC/DCs Eight 1A Synchronous Buck Regulators. Can Connect Up to Four Power Stages in Parallel to Make a High Current Output (4A Maximum) with a Single Inductor, 15 Output Configurations Possible. Precision Enable Inputs and PGOOD_ALL Reporting. I2C Programming with a Watchdog Timer and Pushbutton. 48-Lead 7mm x 7mm QFN LTC3616 5.5V, 6A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.25 to 5.5V, VOUT(MIN)=0.6V, IQ=75A, ISD<1A, 3mmx5mm QFN-24 Package LTC3412A 3A, 4MHz, Monolithic Synchronous Step-Down Regulator 95% Efficiency, VIN: 2.25 to 5.5V, VOUT(MIN)=0.8V, IQ=64A, ISD<1A, 4mmx4mm QFN-16 Package Rev. A 26 11/19 www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2019