© Semiconductor Components Industries, LLC, 2015
July, 2019 − Rev. 3
1Publication Order Number:
NVMFS5113PL/D
NVMFS5113PL
MOSFET – Power, Single
P-Channel
-60 V, 14 mW, -64 A
Features
•Low RDS(on) to Minimize Conduction Losses
•High Current Capability
•Avalanche Energy Specified
•NVMFS5113PLWF − Wettable Flanks Product
•NVM Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS −60 V
Gate−to−Source Voltage VGS "20 V
Continuous Drain Cur-
rent RqJC (Notes 1, 2, 3)
Steady
State
TC = 25°CID−64 A
TC = 100°C−45
Power Dissipation RqJC
(Notes 1, 2)
TC = 25°CPD150 W
TC = 100°C 75
Continuous Drain Cur-
rent RqJA (Notes 1, 2, 3)
Steady
State
TA = 25°CID−10 A
TA = 100°C−7
Power Dissipation RqJA
(Notes 1, 2)
TA = 25°CPD3.8 W
TA = 100°C 1.9
Pulsed Drain Current TA = 25°C, tp = 10 msIDM −415 A
Operating Junction and Storage Temperature TJ, Tstg −55 to
175
°C
Source Current (Body Diode) IS−150 A
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL(pk) = 46 A, L = 0.3 mH, RG = 25 W)
EAS 315 mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Symbol Value Unit
Junction−to−Case − Steady State (Drain)
(Note 2)
RqJC 1.0 °C/W
Junction−to−Ambient − Steady State (Note 2) RqJA 39 °C/W
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Continuous DC current rating. Maximum current for pulses as long as
1 second is higher but is dependent on pulse duration and duty cycle.
−60 V 14 mW @ −10 V
RDS(on)
−64 A
ID
V(BR)DSS
22 mW @ −4.5 V
www.onsemi.com
P−Channel
D (5, 6)
S (1, 2, 3)
G (4)
DFN5
CASE 488AA
STYLE 1
MARKING
DIAGRAM
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
XXXXXX
AYWZZ
S
S
S
G
D
D
D
D
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
ORDERING INFORMATION
1
NVMFS5113PL
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2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA−60 V
Zero Gate Voltage Drain Current IDSS VGS = 0 V,
VDS = −60 V
TJ = 25°C−1.0 mA
TJ = 125°C−100
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = "20 V "100 nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = −250 mA−1.5 −2.5 V
Drain−to−Source On Resistance RDS(on) VGS = −10 V, ID = −17 A 10.5 14 mW
VGS = −4.5 V, ID = −5 A 16 22
Froward Transconductance gFS VDS = −15 V, ID = −15 A 43 S
CHARGES AND CAPACITANCES
Input Capacitance Ciss VGS = 0 V, f = 1.0 MHz,
VDS = −25 V
4400 pF
Output Capacitance Coss 505
Reverse Transfer Capacitance Crss 319
Total Gate Charge QG(TOT) VDS = −48 V,
ID = −17 A
VGS = −4.5 V 45 nC
VGS = −10 V 83
Threshold Gate Charge QG(TH)
VGS = −10 V, VDS = −48 V,
ID = −17 A
4
Gate−to−Source Charge QGS 13
Gate−to−Drain Charge QGD 27
Plateau Voltage VGP 3.5 V
SWITCHING CHARACTERISTICS (Notes 4)
Turn−On Delay Time td(on)
VGS = −10 V, VDS = −48 V,
ID = −17 A, RG = 2.5 W
15 ns
Rise Time tr37
Turn−Off Delay Time td(off) 54
Fall Time tf77
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V,
IS = −17 A
TJ = 25°C−0.79 −1.0 V
TJ = 125°C−0.65
Reverse Recovery Time tRR
VGS = 0 V, dls/dt = 100 A/ms,
Is = −17 A
41 ns
Charge Time ta22
Discharge Time tb19
Reverse Recovery Charge QRR 50 nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
NVMFS5113PL
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3
TYPICAL CHARACTERISTICS
100
1000
10000
100000
10 20 30 40 50 60
0.60
0.90
1.20
1.50
1.80
2.10
−50 −25 0 25 50 75 100 125 150 175
0.010
0.015
0.020
0.025
0.030
0.035
0.040
0.045
0.050
0 102030405060708090100
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
110.0
120.0
123456
0.0
10.0
20.0
30.0
40.0
50.0
60.0
0.0 1.0 2.0 3.0 4.0 5.0
Figure 1. On−Region Characteristics
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−ID, DRAIN CURRENT (A)
−6 V to −10 V
−4.0 V
VGS = −2.8 V
VDS = −10 V
TJ = 25°C
TJ = −55°C
TJ = 125°C
Figure 2. Transfer Characteristics
−VGS, GATE−TO−SOURCE VOLTAGE (V)
−ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
−VGS, GATE−TO−SOURCE VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID = −17 A
TJ = 25°C
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
−ID, DRAIN CURRENT (A)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VGS = −4.5 V
TJ = 25°C
VGS = −10 V
Figure 5. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
VGS = −10 V
ID = −17 A
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−IDSS, LEAKAGE (nA)
TJ = 125°C
TJ = 150°C
VGS = 0 V
−3.6 V
−3.2 V
TJ = 25°C
0.010
0.012
0.014
0.016
0.018
0.020
4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
1.00
1.30
1.60
1.90
2.00
1.70
1.40
1.10
0.70
0.80
NVMFS5113PL
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4
TYPICAL CHARACTERISTICS
0.01
0.1
1
10
100
1000
0.1 1 10 100
0
10
20
30
40
50
60
70
80
90
100
110
120
0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
0 102030405060708090
Figure 7. Capacitance Variation
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
TJ = 25°C
f = 1 MHz
VGS = 0 V
Ciss
Coss
Crss
Figure 8. Gate−to−Source Voltage vs. Total
Charge
Qg, TOTAL GATE CHARGE (nC)
VGS, GATE−TO−SOURCE VOLTAGE (V)
VDS = −48 A
ID = −17 A
TJ = 25°C
QT
Qgs
Qgd
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
RG, GATE RESISTANCE (W)
t, TIME (ns)
VDD = −48 V
VGS = −10 V
ID = −17 A
td(off)
td(on)
tf
tr
Figure 10. Diode Forward Voltage vs. Current
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
−IS, SOURCE CURRENT (A)
VGS = 0 V
TJ = 25°C
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−ID, DRAIN CURRENT (A)
VGS ≤ −10 V
Single Pulse
TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
100 ms
1 ms
dc
10 ms
10 ms
Figure 12. Avalanche Characteristics
TAV, TIME IN AVALANCHE (s)
IPEAK, DRAIN CURRENT (A)
0
1000
2000
3000
4000
5000
6000
0 102030405060
1.0
10.0
100.0
1000.0
1 10 100
100
1.00E−05 1.00E−02
10
1
1.00E−04 1.00E−03
TJ(initial) = 125°C
TJ(initial) = 25°C
NVMFS5113PL
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5
TYPICAL CHARACTERISTICS
0.01
0.1
1
10
100
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
Figure 13. Thermal Response
PULSE TIME (sec)
RqJA(t) (°C/W) EFFECTIVE TRANSIENT
THERMAL RESISTANCE
0.1
Duty Cycle = 0.5
0.2
0.05
0.02
0.01
Single Pulse
DEVICE ORDERING INFORMATION
Device Marking Package Shipping†
NVMFS5113PLT1G V5113L DFN5
(Pb−Free)
1500 / Tape & Reel
NVMFS5113PLWFT1G 5113LW DFN5
(Pb−Free)
1500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
M3.00 3.40
q0 −−−
_
3.80
12
_
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE N DATE 25 JUN 201
8
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
1234
TOP VIEW
SIDE VIEW
BOTTOM VIEW
D1
E1 q
D
E
2
2
B
A
0.20 C
0.20 C
2 X
2 X
DIM MIN NOM
MILLIMETERS
A0.90 1.00
A1 0.00 −−−
b0.33 0.41
c0.23 0.28
D5.15
D1 4.70 4.90
D2 3.80 4.00
E6.15
E1 5.70 5.90
E2 3.45 3.65
e1.27 BSC
G0.51 0.575
K1.20 1.35
L0.51 0.575
L1 0.125 REF
A
0.10 C
0.10 C
DETAIL A
14
L1
e/2
8X
D2
G
E2
K
b
A0.10 B
C
0.05 cL
DETAIL A
A1
c
4 X
C
SEATING
PLANE
GENERIC
MARKING DIAGRAM*
1
XXXXXX
AYWZZ
1
MAX
1.10
0.05
0.51
0.33
5.10
4.20
6.10
3.85
0.71
1.50
0.71
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
M
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
1.270
2X
0.750
1.000
0.905
4.530
1.530
4.5600.495
3.200
1.330
0.965
2X
2X
4X
4X
PIN 5
(EXPOSED PAD)
STYLE 2:
PIN 1. ANODE
2. ANODE
3. ANODE
4. NO CONNECT
5. CATHODE
5.00 5.30
6.00 6.30
PITCH
DIMENSIONS: MILLIMETERS
1
RECOMMENDED
e
2X
0.475
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some product
s
may not follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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DFN5 5x6, 1.27P (SO−8FL)
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