MSP430F5509IRGCT - Texas Instruments

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

MIXED SIGNAL MICROCONTROLLER

1FEATURES

•Low Supply-Voltage Range, 1.8 V to 3.6 V •16-Bit Timer TA0, Timer_A With Five

Capture/Compare Registers

•Ultra-Low Power Consumption

•16-Bit Timer TA1, Timer_A With Three

–Active Mode (AM) Capture/Compare Registers

All System Clocks Active

•16-Bit Timer TA2, Timer_A With Three

–195 µA/MHz at 8 MHz, 3 V, Flash Capture/Compare Registers

Program Execution (Typical)

•16-Bit Timer TB0, Timer_B With Seven

–115 µA/MHz at 8 MHz, 3 V, RAM Program Capture/Compare Shadow Registers

Execution (Typical)

•Two Universal Serial Communication

–Standby Mode (LPM3) Interfaces

–Real Time Clock With Crystal, –USCI_A0 and USCI_A1 Each Supporting

Watchdog, and Supply Supervisor

Operational, Full RAM Retention, Fast –Enhanced UART Supporting

Wake-Up: Auto-Baudrate Detection

1.9 µA at 2.2 V, 2.1 µA at 3 V (Typical) –IrDA Encoder and Decoder

–Low-Power Oscillator (VLO), –Synchronous SPI

General-Purpose Counter, Watchdog, –USCI_B0 and USCI_B1 Each Supporting

and Supply Supervisor Operational, Full –I2CTM

RAM Retention, Fast Wake-Up: –Synchronous SPI

1.4 µA at 3 V (Typical)

•Full-Speed Universal Serial Bus (USB)

–Off Mode (LPM4)

Full RAM Retention, Supply Supervisor –Integrated USB-PHY

Operational, Fast Wake-Up: –Integrated 3.3-V/1.8-V USB Power System

1.1 µA at 3 V (Typical) –Integrated USB-PLL

–Shutdown Mode (LPM4.5) –Eight Input, Eight Output Endpoints

0.18 µA at 3 V (Typical) •10-Bit Analog-to-Digital (A/D) Converter With

•Wake-Up From Standby in Less Than 5 µsWindow Comparator

•16-Bit RISC Architecture, Extended Memory, •Comparator

Up to 25-MHz System Clock •Hardware Multiplier Supporting 32-Bit

•Flexible Power Management System Operations

–Fully Integrated LDO With Programmable •Serial Onboard Programming, No External

Regulated Core Supply Voltage Programming Voltage Needed

–Supply Voltage Supervision, Monitoring, •Three Channel Internal DMA

and Brownout •Basic Timer With Real Time Clock Feature

•Unified Clock System •Family Members are Summarized in Table 1

–FLL Control Loop for Frequency •For Complete Module Descriptions, See the

Stabilization MSP430x5xx/MSP430x6xx Family User's Guide

–Low-Power Low-Frequency Internal Clock (SLAU208)

Source (VLO)

–Low-Frequency Trimmed Internal Reference

Source (REFO)

–32-kHz Watch Crystals (XT1)

–High-Frequency Crystals up to 32 MHz

(XT2)

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

DESCRIPTION

The Texas Instruments MSP430™family of ultra-low-power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with extensive

low-power modes, is optimized to achieve extended battery life in portable measurement applications. The

device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to

maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to

active mode in less than 5 µs.

The MSP430F5510, MSP430F5509, and MSP430F5508 devices are microcontroller configurations with

integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 10-bit analog-to-digital

converter (ADC), two universal serial communication interfaces (USCI), hardware multiplier, DMA, real-time clock

module with alarm capabilities, and 31 or 47 I/O pins.

The MSP430F5507, MSP430F5506, MSP430F5505, and MSP430F5504 devices are microcontroller

configurations with integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 10-bit

analog-to-digital converter (ADC), two universal serial communication interfaces (USCI), hardware multiplier,

DMA, real-time clock module with alarm capabilities, and 31 I/O pins.

The MSP430F5503, MSP430F5502, and MSP430F5500 include all of these peripherals but have a comparator

instead of the 10-bit ADC.

Typical applications include analog and digital sensor systems, data loggers, etc., that require connectivity to

various USB hosts.

Family members available are summarized in Table 1.

Table 1. Family Members

USCI

PROGRAM SRAM ADC10_A Comp_B PACKAGE

CHANNEL A: CHANNEL B:

DEVICE MEMORY Timer_A(2) Timer_B(3) I/O

(KB)(1) (CH) (CH) TYPE

UART/LIN/ SPI/I2C

(KB) IrDA/SPI

64 RGC,

10 ext / 2 int 8 47 80 ZQE

MSP430F5510 32 4 + 2 5, 3, 3 7 2 2 48 PT,

6 ext / 2 int 4 31 48 RGZ

64 RGC,

10 ext / 2 int 8 47 80 ZQE

MSP430F5509 24 4 + 2 5, 3, 3 7 2 2 48 PT,

6 ext / 2 int 4 31 48 RGZ,

64 RGC,

10 ext / 2 int 8 47 80 ZQE

MSP430F5508 16 4 + 2 5, 3, 3 7 2 2 48 PT,

6 ext / 2 int 4 31 48 RGZ,

MSP430F5507 32 4 + 2 5, 3, 3 7 1 1 6 ext / 2 int - 31 48 RGZ

MSP430F5506 24 4 + 2 5, 3, 3 7 1 1 6 ext / 2 int - 31 48 RGZ

MSP430F5505 16 4 + 2 5, 3, 3 7 1 1 6 ext / 2 int - 31 48 RGZ

48 PT,

MSP430F5504 8 4 + 2 5, 3, 3 7 1 1 6 ext / 2 int - 31 48 RGZ

MSP430F5503 32 4 + 2 5, 3, 3 7 1 1 - 4 31 48 RGZ

MSP430F5502 24 4 + 2 5, 3, 3 7 1 1 - 4 31 48 RGZ

MSP430F5501 16 4 + 2 5, 3, 3 7 1 1 - 4 31 48 RGZ

MSP430F5500 8 4 + 2 5, 3, 3 7 1 1 - 4 31 48 RGZ

(1) The additional 2-KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use.

(2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(3) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Table 2. Ordering Information(1)

PACKAGED DEVICES(2)

TAPLASTIC 64-PIN VQFN PLASTIC 80-BALL BGA PLASTIC 48-PIN VQFN PLASTIC 48-PIN LQFP

(RGC) (ZQE) (RGZ) (PT)

MSP430F5510IRGC MSP430F5510IZQE MSP430F5510IRGZ MSP430F5510IPT

MSP430F5509IRGC MSP430F5509IZQE MSP430F5509IRGZ MSP430F5509IPT

MSP430F5508IRGC MSP430F5508IZQE MSP430F5508IRGZ MSP430F5508IPT

MSP430F5507IRGZ MSP430F5504IPT

MSP430F5506IRGZ

–40°C to 85°C MSP430F5505IRGZ

MSP430F5504IRGZ

MSP430F5503IRGZ

MSP430F5502IRGZ

MSP430F5501IRGZ

MSP430F5500IRGZ

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/package.

Unified

Clock

System

32KB

24KB

16KB

Flash

4KB+2KB

RAM

MCLK

ACLK

SMCLK

I/O Ports

P1/P2

2×8 I/Os

Interrupt

& Wakeup

1×16 I/Os

CPUXV2

and

Working

Registers

EEM

(S:3+1)

XIN XOUT

JTAG/

SBW

Interface

PA PB PC

DMA

3 Channel

XT2IN

XT2OUT

Power

Management

LDO

SVM/SVS

Brownout

SYS

Watchdog

Port Map

Control

(P4)

I/O Ports

P3/P4

1×5 I/Os

1×13 I/Os

×8 I/Os

I/O Ports

P5/P6

1×6 I/Os

1×14 I/Os

×8 I/Os

Full-speed

USB

USB-PHY

USB-LDO

USB-PLL

MPY32

TA0

Timer_A

5 CC

Registers

TA1

Timer_A

3 CC

Registers

TB0

Timer_B

7 CC

Registers

RTC_A CRC16

USCI0,1

Ax: UART,

IrDA, SPI

Bx: SPI, I2C

COMP_B

DVCC DVSS AVCC AVSS

P1.x P2.x P3.x P4.x P5.x P6.x

DP,DM,PUR

RST/NMI

TA2

Timer_A

3 CC

Registers

REF

VCORE

MAB

MDB

ADC10_A

200 KSPS

12 Channels

(10 ext/ 2 int)

Window

Comparator

10 Bit

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Functional Block Diagram –MSP430F5510IRGC, MSP430F5509IRGC, MSP430F5508IRGC,

MSP430F5510IZQE, MSP430F5509IZQE, MSP430F5508IZQE

1P6.0/CB0/A0

2P6.1/CB1/A1

3P6.2/CB2/A2

4P6.3/CB3/A3

5P6.4/CB4/A4

6P6.5/CB5/A5

7P6.6/CB6/A6

8P6.7/CB7/A7

9P5.0/A8/VeREF+

10P5.1/A9/VeREF-

11AVCC1

12P5.4/XIN

13P5.5/XOUT

14AVSS1

15DVCC1

16DVSS1

VCORE

P1.0/TA0CLK/ACLK

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

P1.6/TA1CLK/CBOUT

P1.7/TA1.0

P2.0/TA1.1

P2.1/TA1.2

P2.2/TA2CLK/SMCLK

P2.3/TA2.0

P2.4/TA2.1

P2.5/TA2.2

P2.6/RTCCLK/DMAE0

33 P2.7/UCB0STE/UCA0CLK

34 P3.0/UCB0SIMO/UCB0SDA

35 P3.1/UCB0SOMI/UCB0SCL

36 P3.2/UCB0CLK/UCA0STE

37 P3.3/UCA0TXD/UCA0SIMO

38 P3.4/UCA0RXD/UCA0SOMI

39 DVSS2

40 DVCC2

41 P4.0/PM_UCB1STE/PM_UCA1CLK

42 P4.1/PM_UCB1SIMO/PM_UCB1SDA

43 P4.2/PM_UCB1SOMI/PM_UCB1SCL

44 P4.3/PM_UCB1CLK/PM_UCA1STE

45 P4.4/PM_UCA1TXD/PM_UCA1SIMO

46 P4.5/PM_UCA1RXD/PM_UCA1SOMI

47 P4.6/PM_NONE

48 P4.7/PM_NONE

VSSU

PU.0/DP

PUR

PU.1/DM

VBUS

VUSB

V18

AVSS2

P5.2/XT2IN

P5.3/XT2OUT

TEST/SBWTCK

PJ.0/TDO

PJ.1/TDI/TCLK

PJ.2/TMS

PJ.3/TCK

RST/NMI/SBWTDIO

MSP430F5510IRGC

MSP430F5509IRGC

MSP430F5508IRGC

Note: Power Pad connection to

V recommended

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Pin Designation –MSP430F5510IRGC, MSP430F5509IRGC, MSP430F5508IRGC

A1 A2 A3 A4 A5 A6 A7 A8 A9

B1 B2 B3 B4 B5 B6 B7 B8 B9

C1 C2

D1 D2 D4 D5 D6 D7 D8 D9

E1 E2 E4 E5 E6 E7 E8 E9

F1 F2 F4 F5 F8 F9

G1 G2 G4 G5 G8 G9

J1 J2 J4 J5 J6 J7 J8 J9

H1 H2 H4 H5 H6 H7 H8 H9

ZQEPACKAGE

(TOP VIEW)

C4 C5 C6 C7 C8 C9

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Pin Designation –MSP430F5510IZQE, MSP430F5509IZQE, MSP430F5508IZQE

Unified

Clock

System

32KB

24KB

16KB

Flash

4KB+2KB

RAM

MCLK

ACLK

SMCLK

CPUXV2

and

Working

Registers

EEM

(S:3+1)

XIN XOUT

JTAG/

SBW

Interface

DMA

3 Channel

XT2IN

XT2OUT

Power

Management

LDO

SVM/SVS

Brownout

SYS

Watchdog

Port Map

Control

(P4)

Full-speed

USB

USB-PHY

USB-LDO

USB-PLL

MPY32

TA0

Timer_A

5 CC

Registers

TA1

Timer_A

3 CC

Registers

TB0

Timer_B

7 CC

Registers

RTC_A CRC16

USCI0,1

Ax: UART,

IrDA, SPI

Bx: SPI, I2C

COMP_B

DVCC DVSS AVCC AVSS

DP,DM,PUR

RST/NMI

TA2

Timer_A

3 CC

Registers

REF

VCORE

MAB

MDB

ADC10_A

200 KSPS

8 Channels

(6 ext/ 2 int)

Window

Comparator

10 Bit

I/O Ports

P1/P2

1×8 I/Os

Interrupt

& Wakeup

1×9 I/Os

×1 I/Os

PA PB PC

I/O Ports

1×8 I/Os

×8 I/Os

I/O Ports

P5/P6

1×6 I/Os

1×10 I/Os

×4 I/Os

P1.x P2.x P3.x P4.x P5.x P6.x

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Functional Block Diagram –MSP430F5510IRGZ, MSP430F5509IRGZ, MSP430F5508IRGZ,

MSP430F5510IPT, MSP430F5509IPT, MSP430F5508IPT

1P6.0/CB0/A0

2P6.1/CB1/A1

3P6.2/CB2/A2

4P6.3/CB3/A3

5P5.0/A8/VeREF+

6P5.1/A9/VeREF-

7AVCC1

8P5.4/XIN

9P5.5/XOUT

10AVSS1

11DVCC1

12DVSS1

VCORE

P1.0/TA0CLK/ACLK

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

P1.6/TA1CLK/CBOUT

P1.7/TA1.0

P2.0/TA1.1

PJ.0/TDO

PJ.1/TDI/TCLK

25 PJ.2/TMS

26 PJ.3/TCK

27 DVSS2

28 DVCC2

29 P4.0/PM_UCB1STE/PM_UCA1CLK

30 P4.1/PM_UCB1SIMO/PM_UCB1SDA

31 P4.2/PM_UCB1SOMI/PM_UCB1SCL

32 P4.3/PM_UCB1CLK/PM_UCA1STE

33 P4.4/PM_UCA1TXD/PM_UCA1SIMO

34 P4.5/PM_UCA1RXD/PM_UCA1SOMI

35 P4.6/PM_NONE

36 P4.7/PM_NONE

VSSU

PU.0/DP

PUR

PU.1/DM

VBUS

VUSB

V18

AVSS2

P5.2/XT2IN

P5.3/XT2OUT

TEST/SBWTCK

RST/NMI/SBWTDIO

MSP430F5510IRGZ

MSP430F5509IRGZ

MSP430F5508IRGZ

MSP430F5510IPT

MSP430F5509IPT

MSP430F5508IPT

Note: for RGZ package Power Pad

connection to V recommended

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Pin Designation –MSP430F5510IRGZ, MSP430F5509IRGZ, MSP430F5508IRGZ,

MSP430F5510IPT, MSP430F5509IPT, MSP430F5508IPT

Unified

Clock

System

32KB

24KB

16KB

8KB

Flash

4KB+2KB

RAM

MCLK

ACLK

SMCLK

I/O Ports

P1/P2

1×8 I/Os

Interrupt

& Wakeup

1×9 I/Os

×1 I/Os

CPUXV2

and

Working

Registers

EEM

(S:3+1)

XIN XOUT

JTAG/

SBW

Interface

PA PB PC

DMA

3 Channel

XT2IN

XT2OUT

Power

Management

LDO

SVM/SVS

Brownout

SYS

Watchdog

Port Map

Control

(P4)

I/O Ports

1×8 I/Os

×8 I/Os

I/O Ports

P5/P6

1×6 I/Os

1×10 I/Os

×4 I/Os

Full-speed

USB

USB-PHY

USB-LDO

USB-PLL

MPY32

TA0

Timer_A

5 CC

Registers

TA1

Timer_A

3 CC

Registers

TB0

Timer_B

7 CC

Registers

RTC_A CRC16

USCI0

Ax: UART,

IrDA, SPI

Bx: SPI, I2C

ADC10_A

200 KSPS

8 Channels

(6 int/ 2 ext)

Window

Comparator

10 Bit

DVCC DVSS AVCC AVSS

P1.x P2.x P3.x P4.x P5.x P6.x

DP,DM,PUR

RST/NMI

TA2

Timer_A

3 CC

Registers

REF

VCORE

MAB

MDB

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Functional Block Diagram –MSP430F5507IRGZ, MSP430F5506IRGZ, MSP430F5505IRGZ,

MSP430F5504IRGZ, MSP430F5504IPT

1P6.0/A0

2P6.1/A1

3P6.2/A2

4P6.3/A3

5P5.0/A8/VeREF+

6P5.1/A9/VeREF-

7AVCC1

8P5.4/XIN

9P5.5/XOUT

10AVSS1

11DVCC1

12DVSS1

VCORE

P1.0/TA0CLK/ACLK

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

P1.6/TA1CLK

P1.7/TA1.0

P2.0/TA1.1

PJ.0/TDO

PJ.1/TDI/TCLK

25 PJ.2/TMS

26 PJ.3/TCK

27 DVSS2

28 DVCC2

29 P4.0/PM_UCB1STE/PM_UCA1CLK

30 P4.1/PM_UCB1SIMO/PM_UCB1SDA

31 P4.2/PM_UCB1SOMI/PM_UCB1SCL

32 P4.3/PM_UCB1CLK/PM_UCA1STE

33 P4.4/PM_UCA1TXD/PM_UCA1SIMO

34 P4.5/PM_UCA1RXD/PM_UCA1SOMI

35 P4.6/PM_NONE

36 P4.7/PM_NONE

VSSU

PU.0/DP

PUR

PU.1/DM

VBUS

VUSB

V18

AVSS2

P5.2/XT2IN

P5.3/XT2OUT

TEST/SBWTCK

RST/NMI/SBWTDIO

MSP430F5507IRGZ

MSP430F5506IRGZ

MSP430F5505IRGZ

MSP430F5504IRGZ

MSP430F5504IPT

Note: For RGZ package Power Pad

connection to V recommended

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Pin Designation –MSP430F5507IRGZ, MSP430F5506IRGZ, MSP430F5505IRGZ,

MSP430F5504IRGZ, MSP430F5504IPT

Unified

Clock

System

32KB

24KB

16KB

8KB

Flash

4KB+2KB

RAM

MCLK

ACLK

SMCLK

I/O Ports

P1/P2

1×8 I/Os

Interrupt

& Wakeup

1×9 I/Os

×1 I/Os

CPUXV2

and

Working

Registers

EEM

(S:3+1)

XIN XOUT

JTAG/

SBW

Interface

PA PB PC

DMA

3 Channel

XT2IN

XT2OUT

Power

Management

LDO

SVM/SVS

Brownout

SYS

Watchdog

Port Map

Control

(P4)

I/O Ports

1×8 I/Os

×8 I/Os

I/O Ports

P5/P6

1×6 I/Os

1×10 I/Os

×4 I/Os

Full-speed

USB

USB-PHY

USB-LDO

USB-PLL

MPY32

TA0

Timer_A

5 CC

Registers

TA1

Timer_A

3 CC

Registers

TB0

Timer_B

7 CC

Registers

RTC_A CRC16

USCI0

Ax: UART,

IrDA, SPI

Bx: SPI, I2C

COMP_B

DVCC DVSS AVCC AVSS

P1.x P2.x P3.x P4.x P5.x P6.x

DP,DM,PUR

RST/NMI

TA2

Timer_A

3 CC

Registers

VCORE

MAB

MDB

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Functional Block Diagram –MSP430F5503IRGZ, MSP430F5502IRGZ, MSP430F5501IRGZ,

MSP430F5500IRGZ

1P6.0/CB0

2P6.1/CB1

3P6.2/CB2

4P6.3/CB3

5P5.0

6P5.1

7AVCC1

8P5.4/XIN

9P5.5/XOUT

10AVSS1

11DVCC1

12DVSS1

VCORE

P1.0/TA0CLK/ACLK

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

P1.6/TA1CLK/CBOUT

P1.7/TA1.0

P2.0/TA1.1

PJ.0/TDO

PJ.1/TDI/TCLK

25 PJ.2/TMS

26 PJ.3/TCK

27 DVSS2

28 DVCC2

29 P4.0/PM_UCB1STE/PM_UCA1CLK

30 P4.1/PM_UCB1SIMO/PM_UCB1SDA

31 P4.2/PM_UCB1SOMI/PM_UCB1SCL

32 P4.3/PM_UCB1CLK/PM_UCA1STE

33 P4.4/PM_UCA1TXD/PM_UCA1SIMO

34 P4.5/PM_UCA1RXD/PM_UCA1SOMI

35 P4.6/PM_NONE

36 P4.7/PM_NONE

VSSU

PU.0/DP

PUR

PU.1/DM

VBUS

VUSB

V18

AVSS2

P5.2/XT2IN

P5.3/XT2OUT

TEST/SBWTCK

RST/NMI/SBWTDIO

MSP430F5503IRGZ

MSP430F5502IRGZ

MSP430F5501IRGZ

MSP430F5500IRGZ

Note: Power Pad connection to

V recommended

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Pin Designation –MSP430F5503IRGZ, MSP430F5502IRGZ, MSP430F5501IRGZ,

MSP430F5500IRGZ

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Table 3. TERMINAL FUNCTIONS

TERMINAL

NO. I/O(1) DESCRIPTION

NAME RGZ

RGC ZQE

/PT

General-purpose digital I/O

P6.4/CB4/A4 5 N/A C1 I/O Comparator_B input CB4 (not available on PT and RGZ package devices)

Analog input A4 –ADC (not available on PT and RGZ package devices)

General-purpose digital I/O

P6.5/CB5/A5 6 N/A D2 I/O Comparator_B input CB5 (not available on PT and RGZ package devices)

Analog input A5 –ADC (not available on PT and RGZ package devices)

General-purpose digital I/O

P6.6/CB6/A6 7 N/A D1 I/O Comparator_B input CB6 (not available on PT and RGZ package devices)

Analog input A6 –ADC (not available on PT and RGZ package devices)

General-purpose digital I/O

P6.7/CB7/A7 8 N/A D3 I/O Comparator_B input CB7 (not available on PT and RGZ package devices)

Analog input A7 –ADC (not available on PT and RGZ package devices)

General-purpose digital I/O

Analog input A8 –ADC (not available on '5503, '5502, '5501, '5500 devices)

P5.0/A8/VeREF+ 9 5 E1 I/O Input for an external reference voltage to the ADC (not available on '5503,

'5502, '5501, '5500 devices)

General-purpose digital I/O

Analog input A9 –ADC (not available on '5503, '5502, '5501, '5500 devices)

P5.1/A9/VeREF- 10 6 E2 I/O Negative terminal for an externally provided ADC reference (not available on

'5503, '5502, '5501, '5500 devices)

AVCC1 11 7 F2 Analog power supply

General-purpose digital I/O

P5.4/XIN 12 8 F1 I/O Input terminal for crystal oscillator XT1

General-purpose digital I/O

P5.5/XOUT 13 9 G1 I/O Output terminal of crystal oscillator XT1

AVSS1 14 10 G2 Analog ground supply

DVCC1 15 11 H1 Digital power supply

DVSS1 16 12 J1 Digital ground supply

Regulated core power supply output (internal use only, no external current

VCORE(2) 17 13 J2 loading)

General-purpose digital I/O with port interrupt

P1.0/TA0CLK/ACLK 18 14 H2 I/O TA0 clock signal TA0CLK input ; ACLK output (divided by 1, 2, 4, or 8)

General-purpose digital I/O with port interrupt

P1.1/TA0.0 19 15 H3 I/O TA0 CCR0 capture: CCI0A input, compare: Out0 output

BSL transmit output

General-purpose digital I/O with port interrupt

P1.2/TA0.1 20 16 J3 I/O TA0 CCR1 capture: CCI1A input, compare: Out1 output

BSL receive input

General-purpose digital I/O with port interrupt

P1.3/TA0.2 21 17 G4 I/O TA0 CCR2 capture: CCI2A input, compare: Out2 output

General-purpose digital I/O with port interrupt

P1.4/TA0.3 22 18 H4 I/O TA0 CCR3 capture: CCI3A input compare: Out3 output

General-purpose digital I/O with port interrupt

P1.5/TA0.4 23 19 J4 I/O TA0 CCR4 capture: CCI4A input, compare: Out4 output

General-purpose digital I/O with port interrupt

P1.6/TA1CLK/CBOUT 24 20 G5 I/O TA1 clock signal TA1CLK input

Comparator_B output

General-purpose digital I/O with port interrupt

P1.7/TA1.0 25 21 H5 I/O TA1 CCR0 capture: CCI0A input, compare: Out0 output

General-purpose digital I/O with port interrupt

P2.0/TA1.1 26 22 J5 I/O TA1 CCR1 capture: CCI1A input, compare: Out1 output

(1) I = input, O = output, N/A = not available

(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended

capacitor value, CVCORE.

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Table 3. TERMINAL FUNCTIONS (continued)

TERMINAL

NO. I/O(1) DESCRIPTION

NAME RGZ

RGC ZQE

/PT

General-purpose digital I/O with port interrupt

P2.1/TA1.2 27 N/A G6 I/O TA1 CCR2 capture: CCI2A input, compare: Out2 output

General-purpose digital I/O with port interrupt

P2.2/TA2CLK/SMCLK 28 N/A J6 I/O TA2 clock signal TA2CLK input ; SMCLK output

General-purpose digital I/O with port interrupt

P2.3/TA2.0 29 N/A H6 I/O TA2 CCR0 capture: CCI0A input, compare: Out0 output

General-purpose digital I/O with port interrupt

P2.4/TA2.1 30 N/A J7 I/O TA2 CCR1 capture: CCI1A input, compare: Out1 output

General-purpose digital I/O with port interrupt

P2.5/TA2.2 31 N/A J8 I/O TA2 CCR2 capture: CCI2A input, compare: Out2 output

General-purpose digital I/O with port interrupt

P2.6/RTCCLK/DMAE0 32 N/A J9 I/O RTC clock output for calibration

DMA external trigger input

General-purpose digital I/O

Slave transmit enable –USCI_B0 SPI mode

P2.7/UCB0STE/UCA0CLK 33 N/A H7 I/O Clock signal input –USCI_A0 SPI slave mode

Clock signal output –USCI_A0 SPI master mode

General-purpose digital I/O

P3.0/UCB0SIMO/UCB0SDA 34 N/A H8 I/O Slave in, master out –USCI_B0 SPI mode

I2C data –USCI_B0 I2C mode

General-purpose digital I/O

P3.1/UCB0SOMI/UCB0SCL 35 N/A H9 I/O Slave out, master in –USCI_B0 SPI mode

I2C clock –USCI_B0 I2C mode

General-purpose digital I/O

Clock signal input –USCI_B0 SPI slave mode

P3.2/UCB0CLK/UCA0STE 36 N/A G8 I/O Clock signal output –USCI_B0 SPI master mode

Slave transmit enable –USCI_A0 SPI mode

General-purpose digital I/O

P3.3/UCA0TXD/UCA0SIMO 37 N/A G9 I/O Transmit data –USCI_A0 UART mode

Slave in, master out –USCI_A0 SPI mode

General-purpose digital I/O

P3.4/UCA0RXD/UCA0SOMI 38 N/A G7 I/O Receive data –USCI_A0 UART mode

Slave out, master in –USCI_A0 SPI mode

General-purpose digital I/O with reconfigurable port mapping secondary

function

P4.0/PM_UCB1STE/ 41 29 E8 I/O Default mapping: Slave transmit enable –USCI_B1 SPI mode

PM_UCA1CLK Default mapping: Clock signal input –USCI_A1 SPI slave mode

Default mapping: Clock signal output –USCI_A1 SPI master mode

General-purpose digital I/O with reconfigurable port mapping secondary

P4.1/PM_UCB1SIMO/ function

42 30 E7 I/O

PM_UCB1SDA Default mapping: Slave in, master out –USCI_B1 SPI mode

Default mapping: I2C data –USCI_B1 I2C mode

General-purpose digital I/O with reconfigurable port mapping secondary

P4.2/PM_UCB1SOMI/ function

43 31 D9 I/O

PM_UCB1SCL Default mapping: Slave out, master in –USCI_B1 SPI mode

Default mapping: I2C clock –USCI_B1 I2C mode

General-purpose digital I/O with reconfigurable port mapping secondary

function

P4.3/PM_UCB1CLK/ 44 32 D8 I/O Default mapping: Clock signal input –USCI_B1 SPI slave mode

PM_UCA1STE Default mapping: Clock signal output –USCI_B1 SPI master mode

Default mapping: Slave transmit enable –USCI_A1 SPI mode

DVSS2 39 27 F9 Digital ground supply

DVCC2 40 28 E9 Digital power supply

General-purpose digital I/O with reconfigurable port mapping secondary

P4.4/PM_UCA1TXD/ function

45 33 D7 I/O

PM_UCA1SIMO Default mapping: Transmit data –USCI_A1 UART mode

Default mapping: Slave in, master out –USCI_A1 SPI mode

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Table 3. TERMINAL FUNCTIONS (continued)

TERMINAL

NO. I/O(1) DESCRIPTION

NAME RGZ

RGC ZQE

/PT

General-purpose digital I/O with reconfigurable port mapping secondary

P4.5/PM_UCA1RXD/ function

46 34 C9 I/O

PM_UCA1SOMI Default mapping: Receive data –USCI_A1 UART mode

Default mapping: Slave out, master in –USCI_A1 SPI mode

General-purpose digital I/O with reconfigurable port mapping secondary

P4.6/PM_NONE 47 35 C8 I/O function

Default mapping: no secondary function.

General-purpose digital I/O with reconfigurable port mapping secondary

P4.7/PM_NONE 48 36 C7 I/O function

Default mapping: no secondary function.

B8,

VSSU 49 37 USB PHY ground supply

B9 General-purpose digital I/O - controlled by USB control register

PU.0/DP 50 38 A9 I/O USB data terminal DP

PUR 51 39 B7 I/O USB pullup resistor pin (open drain)

General-purpose digital I/O - controlled by USB control register

PU.1/DM 52 40 A8 I/O USB data terminal DM

VBUS 53 41 A7 USB LDO input (connect to USB power source)

VUSB 54 42 A6 USB LDO output

V18 55 43 B6 USB regulated power (internal use only, no external current loading)

AVSS2 56 44 A5 Analog ground supply

General-purpose digital I/O

P5.2/XT2IN 57 45 B5 I/O Input terminal for crystal oscillator XT2

General-purpose digital I/O

P5.3/XT2OUT 58 46 B4 I/O Output terminal of crystal oscillator XT2

Test mode pin –select digital I/O on JTAG pins

TEST/SBWTCK 59 47 A4 I Spy-bi-wire input clock

General-purpose digital I/O

PJ.0/TDO 60 23 C5 I/O Test data output port

General-purpose digital I/O

PJ.1/TDI/TCLK 61 24 C4 I/O Test data input or test clock input

General-purpose digital I/O

PJ.2/TMS 62 25 A3 I/O Test mode select

General-purpose digital I/O

PJ.3/TCK 63 26 B3 I/O Test clock

Reset input active low

RST/NMI/SBWTDIO 64 48 A2 I/O Non-maskable interrupt input

Spy-bi-wire data input/output

General-purpose digital I/O

P6.0/CB0/A0 1 1 A1 I/O Comparator_B input CB0 (not available on '5507, '5506, '5505, '5504 devices)

Analog input A0 –ADC (not available on '5503, '5502, '5501, '5500 devices)

General-purpose digital I/O

P6.1/CB1/A1 2 2 B2 I/O Comparator_B input CB1 (not available on '5507, '5506, '5505, '5504 devices)

Analog input A1 –ADC (not available on '5503, '5502, '5501, '5500 devices)

General-purpose digital I/O

P6.2/CB2/A2 3 3 B1 I/O Comparator_B input CB2 (not available on '5507, '5506, '5505, '5504 devices)

Analog input A2 –ADC (not available on '5503, '5502, '5501, '5500 devices)

General-purpose digital I/O

P6.3/CB3/A3 4 4 C2 I/O Comparator_B input CB3 (not available on '5507, '5506, '5505, '5504 devices)

Analog input A3 –ADC (not available on '5503, '5502, '5501, '5500 devices)

Reserved N/A N/A (3)

(3) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Table 3. TERMINAL FUNCTIONS (continued)

TERMINAL

NO. I/O(1) DESCRIPTION

NAME RGZ

RGC ZQE

/PT

Exposed QFN package pad. Connection to VSS recommended (not available

QFN Pad Pad Pad N/A on PT package devices)

ProgramCounter PC/R0

StackPointer SP/R1

StatusRegister SR/CG1/R2

ConstantGenerator CG2/R3

General-PurposeRegister R4

General-PurposeRegister R5

General-PurposeRegister R6

General-PurposeRegister R7

General-PurposeRegister R8

General-PurposeRegister R9

General-PurposeRegister R10

General-PurposeRegister R11

General-PurposeRegister R12

General-PurposeRegister R13

General-PurposeRegister R15

General-PurposeRegister R14

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

SHORT-FORM DESCRIPTION

CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,

other than program-flow instructions, are performed as register operations in conjunction with seven addressing

modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register

operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant

generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all

instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes and

additional instructions for the expanded address range. Each instruction can operate on word and byte data.

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Operating Modes

The MSP430 devices have one active mode and six software selectable low-power modes of operation. An

interrupt event can wake up the device from any of the low-power modes, service the request, and restore back

to the low-power mode on return from the interrupt program.

The following seven operating modes can be configured by software:

•Active mode (AM)

–All clocks are active

•Low-power mode 0 (LPM0)

–CPU is disabled

–ACLK and SMCLK remain active, MCLK is disabled

–FLL loop control remains active

•Low-power mode 1 (LPM1)

–CPU is disabled

–FLL loop control is disabled

–ACLK and SMCLK remain active, MCLK is disabled

•Low-power mode 2 (LPM2)

–CPU is disabled

–MCLK and FLL loop control and DCOCLK are disabled

–DCO's dc-generator remains enabled

–ACLK remains active

•Low-power mode 3 (LPM3)

–CPU is disabled

–MCLK, FLL loop control, and DCOCLK are disabled

–DCO's dc generator is disabled

–ACLK remains active

•Low-power mode 4 (LPM4)

–CPU is disabled

–ACLK is disabled

–MCLK, FLL loop control, and DCOCLK are disabled

–DCO's dc generator is disabled

–Crystal oscillator is stopped

–Complete data retention

•Low-power mode 4.5 (LPM4.5)

–Internal regulator disabled

–No data retention

–Wakeup from RST/NMI, P1, and P2.

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 4. Interrupt Sources, Flags, and Vectors

SYSTEM WORD

INTERRUPT SOURCE INTERRUPT FLAG PRIORITY

INTERRUPT ADDRESS

System Reset

Power-Up

External Reset WDTIFG, KEYV (SYSRSTIV)(1) (2) Reset 0FFFEh 63, highest

Watchdog Timeout, Password

Violation

Flash Memory Password Violation

System NMI SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

PMM VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62

Vacant Memory Access JMBOUTIFG (SYSSNIV)(1)

JTAG Mailbox

User NMI

NMI NMIIFG, OFIFG, ACCVIFG, BUSIFG (Non)maskable 0FFFAh 61

Oscillator Fault (SYSUNIV)(1) (2)

Flash Memory Access Violation

Comp_B Comparator B interrupt flags (CBIV)(1) (3) Maskable 0FFF8h 60

TB0 TB0CCR0 CCIFG0 (3) Maskable 0FFF6h 59

TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,

TB0 Maskable 0FFF4h 58

TB0IFG (TB0IV)(1) (3)

Watchdog Timer_A Interval Timer WDTIFG Maskable 0FFF2h 57

Mode

USCI_A0 Receive/Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (3) Maskable 0FFF0h 56

USCI_B0 Receive/Transmit UCB0RXIFG, UCB0TXIFG (UCAB0IV)(1) (3) Maskable 0FFEEh 55

ADC10_A ADC10IFG0(1) (3) (4) Maskable 0FFECh 54

TA0 TA0CCR0 CCIFG0(3) Maskable 0FFEAh 53

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,

TA0 Maskable 0FFE8h 52

TA0IFG (TA0IV)(1) (3)

USB_UBM USB interrupts (USBIV)(1) (3) Maskable 0FFE6h 51

DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1) (3) Maskable 0FFE4h 50

TA1 TA1CCR0 CCIFG0(3) Maskable 0FFE2h 49

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,

TA1 Maskable 0FFE0h 48

TA1IFG (TA1IV)(1) (3)

I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)(1) (3) Maskable 0FFDEh 47

USCI_A1 Receive/Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (3) Maskable 0FFDCh 46

USCI_B1 Receive/Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (3) Maskable 0FFDAh 45

TA2 TA2CCR0 CCIFG0(3) Maskable 0FFD8h 44

TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,

TA2 Maskable 0FFD6h 43

TA2IFG (TA2IV)(1) (3)

I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)(1) (3) Maskable 0FFD4h 42

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RTC_A Maskable 0FFD2h 41

RT0PSIFG, RT1PSIFG (RTCIV)(1) (3)

0FFD0h 40

Reserved Reserved(5) ⋮ ⋮

0FF80h 0, lowest

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(3) Interrupt flags are located in the module.

(4) Only on devices with ADC, otherwise reserved.

(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain

compatibility with other devices, it is recommended to reserve these locations.

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Memory Organization

Table 5. Memory Organization(1)

MSP430F5508 MSP430F5509 MSP430F5510

MSP430F5504 MSP430F5505 MSP430F5506 MSP430F5507

MSP430F5500 MSP430F5501 MSP430F5502 MSP430F5503

Memory (flash) Total Size 8 KB 16 KB 24 KB 32 KB

Main: interrupt vector 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h

Main: code memory 00FFFFh-00E000h 00FFFFh-00C000h 00FFFFh-00A000h 00FFFFh-008000h

Sector 1 2 KB 2 KB 2 KB 2 KB

0033FFh–002C00h 0033FFh–002C00h 0033FFh–002C00h 0033FFh–002C00h

RAM Sector 0 2 KB 2 KB 2 KB 2 KB

002BFFh–002400h 002BFFh–002400h 002BFFh–002400h 002BFFh–002400h

2 KB 2 KB 2 KB 2 KB

USB RAM(2) 0023FFh–001C00h 0023FFh–001C00h 0023FFh–001C00h 0023FFh–001C00h

Info A 128 B 128 B 128 B 128 B

0019FFh–001980h 0019FFh–001980h 0019FFh–001980h 0019FFh–001980h

Info B 128 B 128 B 128 B 128 B

00197Fh–001900h 00197Fh–001900h 00197Fh–001900h 00197Fh–001900h

Information memory

(flash) Info C 128 B 128 B 128 B 128 B

0018FFh–001880h 0018FFh–001880h 0018FFh–001880h 0018FFh–001880h

Info D 128 B 128 B 128 B 128 B

00187Fh–001800h 00187Fh–001800h 00187Fh–001800h 00187Fh–001800h

BSL 3 512 B 512 B 512 B 512 B

0017FFh–001600h 0017FFh–001600h 0017FFh–001600h 0017FFh–001600h

BSL 2 512 B 512 B 512 B 512 B

0015FFh–001400h 0015FFh–001400h 0015FFh–001400h 0015FFh–001400h

Bootstrap loader (BSL)

memory (flash) BSL 1 512 B 512 B 512 B 512 B

0013FFh–001200h 0013FFh–001200h 0013FFh–001200h 0013FFh–001200h

BSL 0 512 B 512 B 512 B 512 B

0011FFh–001000h 0011FFh–001000h 0011FFh–001000h 0011FFh–001000h

Size 4 KB 4 KB 4 KB 4 KB

Peripherals 000FFFh–0h 000FFFh–0h 000FFFh–0h 000FFFh–0h

(1) N/A = Not available

(2) USB RAM can be used as general purpose RAM when not used for USB operation.

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Bootstrap Loader (BSL)

The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the

device memory via the BSL is protected by an user-defined password. For complete description of the features of

the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's Guide

(SLAU319).

USB BSL

All devices come pre-programmed with the USB BSL. Use of the USB BSL requires external access to the six

pins shown in Table 6. In addition to these pins, the application must support external components necessary for

normal USB operation (for example, proper crystal on XT2IN and XT2OUT, proper decoupling, etc.).

Table 6. USB BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION

RST/NMI/SBWTDIO Entry sequence signal

PU.0/DP USB data terminal DP

PU.1/DM USB data terminal DM

PUR USB pullup resistor terminal

VBUS USB bus power supply

VSSU USB ground supply

UART BSL

A UART BSL is also available that can be programmed by the user into the BSL memory by replacing the

pre-programmed, factory supplied, USB BSL. Use of the UART BSL requires external access to the six pins

shown in Table 7.

Table 7. UART BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION

RST/NMI/SBWTDIO Entry sequence signal

TEST/SBWTCK Entry sequence signal

P1.1 Data transmit

P1.2 Data receive

VCC Power supply

VSS Ground supply

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

JTAG Operation

JTAG Standard Interface

The MSP430 family supports the standard JTAG interface, which requires four signals for sending and receiving

data. The JTAG signals are shared with general-purpose I/Os. The TEST/SBWTCK pin is used to enable the

JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430

development tools and device programmers. The JTAG pin requirements are shown in Table 8. For further

details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's

Guide, literature number SLAU278.

Table 8. JTAG Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION

PJ.3/TCK IN JTAG clock input

PJ.2/TMS IN JTAG state control

PJ.1/TDI/TCLK IN JTAG data input/TCLK input

PJ.0/TDO OUT JTAG data output

TEST/SBWTCK IN Enable JTAG pins

RST/NMI/SBWTDIO IN External reset

VCC Power supply

VSS Ground supply

Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface.

Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire

interface pin requirements are shown in Table 9. For further details on interfacing to development tools and

device programmers, see the MSP430 Hardware Tools User's Guide, literature number SLAU278.

Table 9. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION

TEST/SBWTCK IN Spy-Bi-Wire clock input

RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output

VCC Power supply

VSS Ground supply

Flash Memory

The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the

CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the

flash memory include:

•Flash memory has n segments of main memory and four segments of information memory (A to D) of

128 bytes each. Each segment in main memory is 512 bytes in size.

•Segments 0 to n may be erased in one step, or each segment may be individually erased.

•Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also

called information memory.

•Segment A can be locked separately.

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

RAM Memory

The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,

however all data is lost. Features of the RAM memory include:

•RAM memory has n sectors. The size of a sector can be found in the Memory Organization section.

•Each sector 0 to n can be completely disabled, however data retention is lost.

•Each sector 0 to n automatically enters low power retention mode when possible.

•For Devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.

Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x5xx/MSP430x6xx Family User's Guide,

literature number SLAU208.

Digital I/O

There are up to six 8-bit I/O ports implemented: For 64 pin options, P1, P2, P4, P6, and are complete, P5 is

reduced to 6-bit I/O and P3 to 5-bit I/O. For 48 pin options, P6 is reduced to 4-bit I/O, P2 to 1-bit I/O, and P3 is

completely removed. Port PJ contains four individual I/O ports, common to all devices.

•All individual I/O bits are independently programmable.

•Any combination of input, output, and interrupt conditions is possible.

•Pullup or pulldown on all ports is programmable.

•Drive strength on all ports is programmable.

•Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.

•Read/write access to port-control registers is supported by all instructions.

•Ports can be accessed byte-wise (P1 through P6) or word-wise in pairs (PA through PC).

Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4.

Table 10. Port Mapping, Mnemonics, and Functions

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION

0 PM_NONE None DVSS

PM_CBOUT0 - Comparator_B output

1PM_TB0CLK TB0 clock input

PM_ADC10CLK - ADC10CLK

2PM_DMAE0 DMAE0 input

PM_SVMOUT - SVM output

3TB0 high impedance input

PM_TB0OUTH TB0OUTH

4 PM_TB0CCR0A TB0 CCR0 capture input CCI0A TB0 CCR0 compare output Out0

5 PM_TB0CCR1A TB0 CCR1 capture input CCI1A TB0 CCR1 compare output Out1

6 PM_TB0CCR2A TB0 CCR2 capture input CCI2A TB0 CCR2 compare output Out2

7 PM_TB0CCR3A TB0 CCR3 capture input CCI3A TB0 CCR3 compare output Out3

8 PM_TB0CCR4A TB0 CCR4 capture input CCI4A TB0 CCR4 compare output Out4

9 PM_TB0CCR5A TB0 CCR5 capture input CCI5A TB0 CCR5 compare output Out5

10 PM_TB0CCR6A TB0 CCR6 capture input CCI6A TB0 CCR6 compare output Out6

PM_UCA1RXD USCI_A1 UART RXD (Direction controlled by USCI - input)

11 PM_UCA1SOMI USCI_A1 SPI slave out master in (direction controlled by USCI)

PM_UCA1TXD USCI_A1 UART TXD (Direction controlled by USCI - output)

12 PM_UCA1SIMO USCI_A1 SPI slave in master out (direction controlled by USCI)

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Table 10. Port Mapping, Mnemonics, and Functions (continued)

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION

PM_UCA1CLK USCI_A1 clock input/output (direction controlled by USCI)

13 PM_UCB1STE USCI_B1 SPI slave transmit enable (direction controlled by USCI)

PM_UCB1SOMI USCI_B1 SPI slave out master in (direction controlled by USCI)

14 PM_UCB1SCL USCI_B1 I2C clock (open drain and direction controlled by USCI)

PM_UCB1SIMO USCI_B1 SPI slave in master out (direction controlled by USCI)

15 PM_UCB1SDA USCI_B1 I2C data (open drain and direction controlled by USCI)

PM_UCB1CLK USCI_B1 clock input/output (direction controlled by USCI)

16 PM_UCA1STE USCI_A1 SPI slave transmit enable (direction controlled by USCI)

17 PM_CBOUT1 None Comparator_B output

18 PM_MCLK None MCLK

19 PM_RTCCLK None RTCCLK output

PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI - input)

20 PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)

PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI - output)

21 PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)

PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)

22 PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI)

PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)

23 PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)

PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI)

24 PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)

PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI)

25 PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI)

26 - 30 Reserved None DVSS

Disables the output driver as well as the input Schmitt-trigger to prevent

31 (0FFh)(1) PM_ANALOG parasitic cross currents when applying analog signals.

(1) The value of the PMPAP_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are

ignored resulting in a read out value of 31.

Table 11. Default Mapping

PIN PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION

USCI_B1 SPI slave transmit enable (direction controlled by USCI)

P4.0/P4MAP0 PM_UCB1STE/PM_UCA1CLK USCI_A1 clock input/output (direction controlled by USCI)

USCI_B1 SPI slave in master out (direction controlled by USCI)

P4.1/P4MAP1 PM_UCB1SIMO/PM_UCB1SDA USCI_B1 I2C data (open drain and direction controlled by USCI)

USCI_B1 SPI slave out master in (direction controlled by USCI)

P4.2/P4MAP2 PM_UCB1SOMI/PM_UCB1SCL USCI_B1 I2C clock (open drain and direction controlled by USCI)

USCI_A1 SPI slave transmit enable (direction controlled by USCI)

P4.3/P4MAP3 PM_UCB1CLK/PM_UCA1STE USCI_B1 clock input/output (direction controlled by USCI)

USCI_A1 UART TXD (Direction controlled by USCI - output)

P4.4/P4MAP4 PM_UCA1TXD/PM_UCA1SIMO USCI_A1 SPI slave in master out (direction controlled by USCI)

USCI_A1 UART RXD (Direction controlled by USCI - input)

P4.5/P4MAP5 PM_UCA1RXD/PM_UCA1SOMI USCI_A1 SPI slave out master in (direction controlled by USCI)

P4.6/P4MAP6 PM_NONE None DVSS

P4.7/P4MAP7 PM_NONE None DVSS

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Oscillator and System Clock

The clock system in the MSP430F550x family of devices is supported by the Unified Clock System (UCS)

module that includes support for a 32-kHz watch crystal oscillator (XT1 LF mode; XT1 HF mode is not

supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency

oscillator (REFO), an integrated internal digitally-controlled oscillator (DCO), and a high-frequency crystal

oscillator XT2. The UCS module is designed to meet the requirements of both low system cost and low power

consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a

digital modulator, stabilizes the DCO frequency to a programmable multiple of the selected FLL reference

frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 5 µs. The UCS

module provides the following clock signals:

•Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the

internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal

digitally-controlled oscillator DCO.

•Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made

available to ACLK.

•Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by

same sources made available to ACLK.

•ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

Power Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains

programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor

(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is

implemented to provide the proper internal reset signal to the device during power-on and power-off. The

SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply

voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not

automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs operations with

32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication

as well as signed and unsigned multiply and accumulate operations.

Real-Time Clock (RTC_A)

The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated

real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers

that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar

mode integrates an internal calendar which compensates for months with less than 31 days and includes leap

year correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.

Watchdog Timer (WDT_A)

The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be configured as an interval timer and can generate

interrupts at selected time intervals.

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

System Module (SYS)

The SYS module handles many of the system functions within the device. These include power on reset and

power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap

loader entry mechanisms, as well as, configuration management (device descriptors). It also includes a data

exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.

Table 12. System Module Interrupt Vector Registers

INTERRUPT VECTOR REGISTER ADDRESS INTERRUPT EVENT VALUE PRIORITY

SYSRSTIV , System Reset 019Eh No interrupt pending 00h

Brownout (BOR) 02h Highest

RST/NMI (POR) 04h

PMMSWBOR (BOR) 06h

Wakeup from LPMx.5 08h

Security violation (BOR) 0Ah

SVSL (POR) 0Ch

SVSH (POR) 0Eh

SVML_OVP (POR) 10h

SVMH_OVP (POR) 12h

PMMSWPOR (POR) 14h

WDT timeout (PUC) 16h

WDT password violation (PUC) 18h

KEYV flash password violation (PUC) 1Ah

FLL unlock (PUC) 1Ch

Peripheral area fetch (PUC) 1Eh

PMM password violation (PUC) 20h

Reserved 22h to 3Eh Lowest

SYSSNIV , System NMI 019Ch No interrupt pending 00h

SVMLIFG 02h Highest

SVMHIFG 04h

SVSMLDLYIFG 06h

SVSMHDLYIFG 08h

VMAIFG 0Ah

JMBINIFG 0Ch

JMBOUTIFG 0Eh

SVMLVLRIFG 10h

SVMHVLRIFG 12h

Reserved 14h to 1Eh Lowest

SYSUNIV, User NMI 019Ah No interrupt pending 00h

NMIFG 02h Highest

OFIFG 04h

ACCVIFG 06h

Reserved 08h

Reserved 0Ah to 1Eh Lowest

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. For

example, the DMA controller can be used to move data from the ADC10_A conversion register to RAM. Using

the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system

power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or

from a peripheral.

The USB timestamp generator also utilizes the DMA trigger assignments described in Table 13.

Table 13. DMA Trigger Assignments(1)

CHANNEL

TRIGGER 0 1 2

0 DMAREQ DMAREQ DMAREQ

1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG

2 TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG

3 TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG

4 TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG

5 TA2CCR0 CCIFG TA2CCR0 CCIFG TA2CCR0 CCIFG

6 TA2CCR2 CCIFG TA2CCR2 CCIFG TA2CCR2 CCIFG

7 TB0CCR0 CCIFG TB0CCR0 CCIFG TB0CCR0 CCIFG

8 TB0CCR2 CCIFG TB0CCR2 CCIFG TB0CCR2 CCIFG

9 Reserved Reserved Reserved

10 Reserved Reserved Reserved

11 Reserved Reserved Reserved

12 Reserved Reserved Reserved

13 Reserved Reserved Reserved

14 Reserved Reserved Reserved

15 Reserved Reserved Reserved

16 UCA0RXIFG UCA0RXIFG UCA0RXIFG

17 UCA0TXIFG UCA0TXIFG UCA0TXIFG

18 UCB0RXIFG UCB0RXIFG UCB0RXIFG

19 UCB0TXIFG UCB0TXIFG UCB0TXIFG

20 UCA1RXIFG UCA1RXIFG UCA1RXIFG

21 UCA1TXIFG UCA1TXIFG UCA1TXIFG

22 UCB1RXIFG UCB1RXIFG UCB1RXIFG

23 UCB1TXIFG UCB1TXIFG UCB1TXIFG

24 ADC10IFG0(2) ADC10IFG0(2) ADC10IFG0(2)

25 Reserved Reserved Reserved

26 Reserved Reserved Reserved

27 USB FNRXD USB FNRXD USB FNRXD

28 USB ready USB ready USB ready

29 MPY ready MPY ready MPY ready

30 DMA2IFG DMA0IFG DMA1IFG

31 DMAE0 DMAE0 DMAE0

(1) If a reserved trigger source is selected, no Trigger1 is generated.

(2) Only on devices with ADC. Reserved on devices without ADC.

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Universal Serial Communication Interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous

communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as

UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,

A and B.

The USCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, or IrDA.

The USCI_Bn module provides support for SPI (3 pin or 4 pin) or I2C.

The MSP430F55xx series includes two complete USCI modules (n = 0, 1).

TA0

TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple

capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may

be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 14. TA0 Signal Connections

INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER

MODULE

INPUT INPUT OUTPUT OUTPUT

BLOCK

RGC/ZQE RGZ, PT RGC/ZQE RGZ, PT

SIGNAL SIGNAL SIGNAL SIGNAL

18/H2-P1.0 14-P1.0 TA0CLK TACLK

ACLK ACLK

(internal) Timer NA NA

SMCLK SMCLK

(internal)

18/H2-P1.0 14-P1.0 TA0CLK TACLK

19/H3-P1.1 15-P1.1 TA0.0 CCI0A 19/H3-P1.1 15-P1.1

DVSS CCI0B CCR0 TA0 TA0.0

DVSS GND

DVCC VCC

20/J3-P1.2 16-P1.2 TA0.1 CCI1A 20/J3-P1.2 16-P1.2

ADC10 ADC10

CBOUT (internal)(1) (internal)(1)

CCI1B

(internal) ADC10SHSx = ADC10SHSx =

CCR1 TA1 TA0.1 {1} {1}

DVSS GND

DVCC VCC

21/G4-P1.3 17-P1.3 TA0.2 CCI2A 21/G4-P1.3 17-P1.3

ACLK CCI2B

(internal) CCR2 TA2 TA0.2

DVSS GND

DVCC VCC

22/H4-P1.4 18-P1.4 TA0.3 CCI3A 22/H4-P1.4 18-P1.4

DVSS CCI3B CCR3 TA3 TA0.3

DVSS GND

DVCC VCC

23/J4-P1.5 19-P1.5 TA0.4 CCI4A 23/J4-P1.5 19-P1.5

DVSS CCI4B CCR4 TA4 TA0.4

DVSS GND

DVCC VCC

(1) Only on devices with ADC.

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

TA1

TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple

capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may

be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 15. TA1 Signal Connections

INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER

MODULE

INPUT INPUT OUTPUT OUTPUT

BLOCK

RGC/ZQE RGZ, PT RGC/ZQE RGZ, PT

SIGNAL SIGNAL SIGNAL SIGNAL

24/G5-P1.6 20-P1.6 TA1CLK TACLK

ACLK ACLK

(internal) Timer NA NA

SMCLK SMCLK

(internal)

24/G5-P1.6 20-P1.6 TA1CLK TACLK

25/H5-P1.7 21-P1.7 TA1.0 CCI0A 25/H5-P1.7 21-P1.7

DVSS CCI0B CCR0 TA0 TA1.0

DVSS GND

DVCC VCC

26/J5-P2.0 22-P2.0 TA1.1 CCI1A 26/J5-P2.0 22-P2.0

CBOUT CCI1B

(internal) CCR1 TA1 TA1.1

DVSS GND

DVCC VCC

27/G6-P2.1 TA1.2 CCI2A 27/G6-P2.1

ACLK CCI2B

(internal) CCR2 TA2 TA1.2

DVSS GND

DVCC VCC

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

TA2

TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple

capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may

be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 16. TA2 Signal Connections

INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER

MODULE

INPUT INPUT OUTPUT OUTPUT

BLOCK

RGC, ZQE RGZ, PT RGC, ZQE RGZ, PT

SIGNAL SIGNAL SIGNAL SIGNAL

28/J6-P2.2 TA2CLK TACLK

ACLK ACLK

(internal) Timer NA NA

SMCLK SMCLK

(internal)

28/J6-P2.2 TA2CLK TACLK

29/H6-P2.3 TA2.0 CCI0A 29/H6-P2.3

DVSS CCI0B CCR0 TA0 TA2.0

DVSS GND

DVCC VCC

30/J7-P2.4 TA2.1 CCI1A 30/J7-P2.4

CBOUT CCI1B

(internal) CCR1 TA1 TA2.1

DVSS GND

DVCC VCC

31/J8-P2.5 TA2.2 CCI2A 31/J8-P2.5

ACLK CCI2B

(internal) CCR2 TA2 TA2.2

DVSS GND

DVCC VCC

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

TB0

TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple

capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may

be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 17. TB0 Signal Connections

INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER

MODULE

INPUT INPUT OUTPUT OUTPUT

BLOCK

RGC/ZQE(1) RGZ, PT(1) RGC/ZQE(1) RGZ, PT(1)

SIGNAL SIGNAL SIGNAL SIGNAL

TB0CLK TBCLK

ACLK ACLK

(internal) Timer NA NA

SMCLK SMCLK

(internal)

TB0CLK TBCLK ADC10 ADC10

(internal)(2) (internal)(2)

TB0.0 CCI0A ADC10SHSx = ADC10SHSx =

{2} {2}

CCR0 TB0 TB0.0

TB0.0 CCI0B

DVSS GND

DVCC VCC ADC10 (internal) ADC10 (internal)

TB0.1 CCI1A ADC10SHSx = ADC10SHSx =

{3} {3}

CBOUT CCR1 TB1 TB0.1

CCI1B

(internal)

DVSS GND

DVCC VCC

TB0.2 CCI2A

TB0.2 CCI2B CCR2 TB2 TB0.2

DVSS GND

DVCC VCC

TB0.3 CCI3A

TB0.3 CCI3B CCR3 TB3 TB0.3

DVSS GND

DVCC VCC

TB0.4 CCI4A

TB0.4 CCI4B CCR4 TB4 TB0.4

DVSS GND

DVCC VCC

TB0.5 CCI5A

TB0.5 CCI5B CCR5 TB5 TB0.5

DVSS GND

DVCC VCC

TB0.6 CCI6A

ACLK CCI6B

(internal) CCR6 TB6 TB0.6

DVSS GND

DVCC VCC

(1) Timer functions selectable via the port mapping controller.

(2) Only on devices with ADC.

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Comparator_B

The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,

battery voltage supervision, and monitoring of external analog signals.

ADC10_A

The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR

core, sample select control, reference generator, and a conversion result buffer. A window comparator with lower

and upper limits allows CPU-independent result monitoring with three window comparator interrupt flags.

CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data

checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

REF Voltage Reference

The reference module (REF) is responsible for generation of all critical reference voltages that can be used by

the various analog peripherals in the device.

USB Universal Serial Bus

The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module

supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO,

PHY, and PLL. The PLL is highly-flexible and can support a wide range of input clock frequencies. USB RAM,

when not used for USB communication, can be used by the system.

Embedded Emulation Module (EEM) (S Version)

The Embedded Emulation Module (EEM) supports real-time in-system debugging. The S version of the EEM

implemented on all devices has the following features:

•Three hardware triggers/breakpoints on memory access

•One hardware trigger/breakpoint on CPU register write access

•Up to four hardware triggers can be combined to form complex triggers/breakpoints

•One cycle counter

•Clock control on module level

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Peripheral File Map

Table 18. Peripherals

OFFSET ADDRESS

MODULE NAME BASE ADDRESS RANGE

Special Functions (see Table 19) 0100h 000h - 01Fh

PMM (see Table 20) 0120h 000h - 01Fh

Flash Control (see Table 21) 0140h 000h - 00Fh

CRC16 (see Table 22) 0150h 000h - 007h

RAM Control (see Table 23) 0158h 000h - 001h

Watchdog (see Table 24) 015Ch 000h - 001h

UCS (see Table 25) 0160h 000h - 01Fh

SYS (see Table 26) 0180h 000h - 01Fh

Shared Reference (see Table 27) 01B0h 000h - 001h

Port Mapping Control (see Table 28) 01C0h 000h - 002h

Port Mapping Port P4 (see Table 28) 01E0h 000h - 007h

Port P1/P2 (see Table 29) 0200h 000h - 01Fh

Port P3/P4 (see Table 30) 0220h 000h - 00Bh

Port P5/P6 (see Table 31) 0240h 000h - 00Bh

Port PJ (see Table 32) 0320h 000h - 01Fh

TA0 (see Table 33) 0340h 000h - 02Eh

TA1 (see Table 34) 0380h 000h - 02Eh

TB0 (see Table 35) 03C0h 000h - 02Eh

TA2 (see Table 36) 0400h 000h - 02Eh

Real Timer Clock (RTC_A) (see Table 37) 04A0h 000h - 01Bh

32-bit Hardware Multiplier (see Table 38) 04C0h 000h - 02Fh

DMA General Control (see Table 39) 0500h 000h - 00Fh

DMA Channel 0 (see Table 39) 0510h 000h - 00Ah

DMA Channel 1 (see Table 39) 0520h 000h - 00Ah

DMA Channel 2 (see Table 39) 0530h 000h - 00Ah

USCI_A0 (see Table 40) 05C0h 000h - 01Fh

USCI_B0 (see Table 41) 05E0h 000h - 01Fh

USCI_A1 (see Table 42) 0600h 000h - 01Fh

USCI_B1 (see Table 43) 0620h 000h - 01Fh

ADC10_A (see Table 44) 0740h 000h - 01Fh

Comparator_B (see Table 45) 08C0h 000h - 00Fh

USB configuration (see Table 46) 0900h 000h - 014h

USB control (see Table 47) 0920h 000h - 01Fh

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Table 19. Special Function Registers (Base Address: 0100h)

SFR interrupt enable SFRIE1 00h

SFR interrupt flag SFRIFG1 02h

SFR reset pin control SFRRPCR 04h

Table 20. PMM Registers (Base Address: 0120h)

PMM Control 0 PMMCTL0 00h

PMM control 1 PMMCTL1 02h

SVS high side control SVSMHCTL 04h

SVS low side control SVSMLCTL 06h

PMM interrupt flags PMMIFG 0Ch

PMM interrupt enable PMMIE 0Eh

PMM Power mode 5 control PMM5CTL 10h

Table 21. Flash Control Registers (Base Address: 0140h)

Flash control 1 FCTL1 00h

Flash control 3 FCTL3 04h

Flash control 4 FCTL4 06h

Table 22. CRC16 Registers (Base Address: 0150h)

CRC data input CRC16DI 00h

CRC data input reverse byte CRCDIRB 02h

CRC initialization and result CRCINIRES 04h

CRC result reverse byte CRCRESR 06h

Table 23. RAM Control Registers (Base Address: 0158h)

RAM control 0 RCCTL0 00h

Table 24. Watchdog Registers (Base Address: 015Ch)

Watchdog timer control WDTCTL 00h

Table 25. UCS Registers (Base Address: 0160h)

UCS control 0 UCSCTL0 00h

UCS control 1 UCSCTL1 02h

UCS control 2 UCSCTL2 04h

UCS control 3 UCSCTL3 06h

UCS control 4 UCSCTL4 08h

UCS control 5 UCSCTL5 0Ah

UCS control 6 UCSCTL6 0Ch

UCS control 7 UCSCTL7 0Eh

UCS control 8 UCSCTL8 10h

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Table 26. SYS Registers (Base Address: 0180h)

System control SYSCTL 00h

Bootstrap loader configuration area SYSBSLC 02h

JTAG mailbox control SYSJMBC 06h

JTAG mailbox input 0 SYSJMBI0 08h

JTAG mailbox input 1 SYSJMBI1 0Ah

JTAG mailbox output 0 SYSJMBO0 0Ch

JTAG mailbox output 1 SYSJMBO1 0Eh

Bus Error vector generator SYSBERRIV 18h

User NMI vector generator SYSUNIV 1Ah

System NMI vector generator SYSSNIV 1Ch

Reset vector generator SYSRSTIV 1Eh

Table 27. Shared Reference Registers (Base Address: 01B0h)

Shared reference control REFCTL 00h

Table 28. Port Mapping Registers

(Base Address of Port Mapping Control: 01C0h, Port P4: 01E0h)

Port mapping key/ID register PMAPKEYID 00h

Port mapping control register PMAPCTL 02h

Port P4.0 mapping register P4MAP0 00h

Port P4.1 mapping register P4MAP1 01h

Port P4.2 mapping register P4MAP2 02h

Port P4.3 mapping register P4MAP3 03h

Port P4.4 mapping register P4MAP4 04h

Port P4.5 mapping register P4MAP5 05h

Port P4.6 mapping register P4MAP6 06h

Port P4.7 mapping register P4MAP7 07h

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Table 29. Port P1/P2 Registers (Base Address: 0200h)

Port P1 input P1IN 00h

Port P1 output P1OUT 02h

Port P1 direction P1DIR 04h

Port P1 pullup/pulldown enable P1REN 06h

Port P1 drive strength P1DS 08h

Port P1 selection P1SEL 0Ah

Port P1 interrupt vector word P1IV 0Eh

Port P1 interrupt edge select P1IES 18h

Port P1 interrupt enable P1IE 1Ah

Port P1 interrupt flag P1IFG 1Ch

Port P2 input P2IN 01h

Port P2 output P2OUT 03h

Port P2 direction P2DIR 05h

Port P2 pullup/pulldown enable P2REN 07h

Port P2 drive strength P2DS 09h

Port P2 selection P2SEL 0Bh

Port P2 interrupt vector word P2IV 1Eh

Port P2 interrupt edge select P2IES 19h

Port P2 interrupt enable P2IE 1Bh

Port P2 interrupt flag P2IFG 1Dh

Table 30. Port P3/P4 Registers (Base Address: 0220h)

Port P3 input P3IN 00h

Port P3 output P3OUT 02h

Port P3 direction P3DIR 04h

Port P3 pullup/pulldown enable P3REN 06h

Port P3 drive strength P3DS 08h

Port P3 selection P3SEL 0Ah

Port P4 input P4IN 01h

Port P4 output P4OUT 03h

Port P4 direction P4DIR 05h

Port P4 pullup/pulldown enable P4REN 07h

Port P4 drive strength P4DS 09h

Port P4 selection P4SEL 0Bh

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Table 31. Port P5/P6 Registers (Base Address: 0240h)

Port P5 input P5IN 00h

Port P5 output P5OUT 02h

Port P5 direction P5DIR 04h

Port P5 pullup/pulldown enable P5REN 06h

Port P5 drive strength P5DS 08h

Port P5 selection P5SEL 0Ah

Port P6 input P6IN 01h

Port P6 output P6OUT 03h

Port P6 direction P6DIR 05h

Port P6 pullup/pulldown enable P6REN 07h

Port P6 drive strength P6DS 09h

Port P6 selection P6SEL 0Bh

Table 32. Port J Registers (Base Address: 0320h)

Port PJ input PJIN 00h

Port PJ output PJOUT 02h

Port PJ direction PJDIR 04h

Port PJ pullup/pulldown enable PJREN 06h

Port PJ drive strength PJDS 08h

Table 33. TA0 Registers (Base Address: 0340h)

TA0 control TA0CTL 00h

Capture/compare control 0 TA0CCTL0 02h

Capture/compare control 1 TA0CCTL1 04h

Capture/compare control 2 TA0CCTL2 06h

Capture/compare control 3 TA0CCTL3 08h

Capture/compare control 4 TA0CCTL4 0Ah

TA0 counter register TA0R 10h

Capture/compare register 0 TA0CCR0 12h

Capture/compare register 1 TA0CCR1 14h

Capture/compare register 2 TA0CCR2 16h

Capture/compare register 3 TA0CCR3 18h

Capture/compare register 4 TA0CCR4 1Ah

TA0 expansion register 0 TA0EX0 20h

TA0 interrupt vector TA0IV 2Eh

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Table 34. TA1 Registers (Base Address: 0380h)

TA1 control TA1CTL 00h

Capture/compare control 0 TA1CCTL0 02h

Capture/compare control 1 TA1CCTL1 04h

Capture/compare control 2 TA1CCTL2 06h

TA1 counter register TA1R 10h

Capture/compare register 0 TA1CCR0 12h

Capture/compare register 1 TA1CCR1 14h

Capture/compare register 2 TA1CCR2 16h

TA1 expansion register 0 TA1EX0 20h

TA1 interrupt vector TA1IV 2Eh

Table 35. TB0 Registers (Base Address: 03C0h)

TB0 control TB0CTL 00h

Capture/compare control 0 TB0CCTL0 02h

Capture/compare control 1 TB0CCTL1 04h

Capture/compare control 2 TB0CCTL2 06h

Capture/compare control 3 TB0CCTL3 08h

Capture/compare control 4 TB0CCTL4 0Ah

Capture/compare control 5 TB0CCTL5 0Ch

Capture/compare control 6 TB0CCTL6 0Eh

TB0 register TB0R 10h

Capture/compare register 0 TB0CCR0 12h

Capture/compare register 1 TB0CCR1 14h

Capture/compare register 2 TB0CCR2 16h

Capture/compare register 3 TB0CCR3 18h

Capture/compare register 4 TB0CCR4 1Ah

Capture/compare register 5 TB0CCR5 1Ch

Capture/compare register 6 TB0CCR6 1Eh

TB0 expansion register 0 TB0EX0 20h

TB0 interrupt vector TB0IV 2Eh

Table 36. TA2 Registers (Base Address: 0400h)

TA2 control TA2CTL 00h

Capture/compare control 0 TA2CCTL0 02h

Capture/compare control 1 TA2CCTL1 04h

Capture/compare control 2 TA2CCTL2 06h

TA2 counter register TA2R 10h

Capture/compare register 0 TA2CCR0 12h

Capture/compare register 1 TA2CCR1 14h

Capture/compare register 2 TA2CCR2 16h

TA2 expansion register 0 TA2EX0 20h

TA2 interrupt vector TA2IV 2Eh

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Table 37. Real Time Clock Registers (Base Address: 04A0h)

RTC control 0 RTCCTL0 00h

RTC control 1 RTCCTL1 01h

RTC control 2 RTCCTL2 02h

RTC control 3 RTCCTL3 03h

RTC prescaler 0 control RTCPS0CTL 08h

RTC prescaler 1 control RTCPS1CTL 0Ah

RTC prescaler 0 RTCPS0 0Ch

RTC prescaler 1 RTCPS1 0Dh

RTC interrupt vector word RTCIV 0Eh

RTC seconds/counter register 1 RTCSEC/RTCNT1 10h

RTC minutes/counter register 2 RTCMIN/RTCNT2 11h

RTC hours/counter register 3 RTCHOUR/RTCNT3 12h

RTC day of week/counter register 4 RTCDOW/RTCNT4 13h

RTC days RTCDAY 14h

RTC month RTCMON 15h

RTC year low RTCYEARL 16h

RTC year high RTCYEARH 17h

RTC alarm minutes RTCAMIN 18h

RTC alarm hours RTCAHOUR 19h

RTC alarm day of week RTCADOW 1Ah

RTC alarm days RTCADAY 1Bh

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Table 38. 32-bit Hardware Multiplier Registers (Base Address: 04C0h)

16-bit operand 1 –multiply MPY 00h

16-bit operand 1 –signed multiply MPYS 02h

16-bit operand 1 –multiply accumulate MAC 04h

16-bit operand 1 –signed multiply accumulate MACS 06h

16-bit operand 2 OP2 08h

16 ×16 result low word RESLO 0Ah

16 ×16 result high word RESHI 0Ch

16 ×16 sum extension register SUMEXT 0Eh

32-bit operand 1 –multiply low word MPY32L 10h

32-bit operand 1 –multiply high word MPY32H 12h

32-bit operand 1 –signed multiply low word MPYS32L 14h

32-bit operand 1 –signed multiply high word MPYS32H 16h

32-bit operand 1 –multiply accumulate low word MAC32L 18h

32-bit operand 1 –multiply accumulate high word MAC32H 1Ah

32-bit operand 1 –signed multiply accumulate low word MACS32L 1Ch

32-bit operand 1 –signed multiply accumulate high word MACS32H 1Eh

32-bit operand 2 –low word OP2L 20h

32-bit operand 2 –high word OP2H 22h

32 ×32 result 0 –least significant word RES0 24h

32 ×32 result 1 RES1 26h

32 ×32 result 2 RES2 28h

32 ×32 result 3 –most significant word RES3 2Ah

MPY32 control register 0 MPY32CTL0 2Ch

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Table 39. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)

DMA channel 0 control DMA0CTL 00h

DMA channel 0 source address low DMA0SAL 02h

DMA channel 0 source address high DMA0SAH 04h

DMA channel 0 destination address low DMA0DAL 06h

DMA channel 0 destination address high DMA0DAH 08h

DMA channel 0 transfer size DMA0SZ 0Ah

DMA channel 1 control DMA1CTL 00h

DMA channel 1 source address low DMA1SAL 02h

DMA channel 1 source address high DMA1SAH 04h

DMA channel 1 destination address low DMA1DAL 06h

DMA channel 1 destination address high DMA1DAH 08h

DMA channel 1 transfer size DMA1SZ 0Ah

DMA channel 2 control DMA2CTL 00h

DMA channel 2 source address low DMA2SAL 02h

DMA channel 2 source address high DMA2SAH 04h

DMA channel 2 destination address low DMA2DAL 06h

DMA channel 2 destination address high DMA2DAH 08h

DMA channel 2 transfer size DMA2SZ 0Ah

DMA module control 0 DMACTL0 00h

DMA module control 1 DMACTL1 02h

DMA module control 2 DMACTL2 04h

DMA module control 3 DMACTL3 06h

DMA module control 4 DMACTL4 08h

DMA interrupt vector DMAIV 0Ah

Table 40. USCI_A0 Registers (Base Address: 05C0h)

USCI control 0 UCA0CTL1 00h

USCI control 1 UCA0CTL0 01h

USCI baud rate 0 UCA0BR0 06h

USCI baud rate 1 UCA0BR1 07h

USCI modulation control UCA0MCTL 08h

USCI status UCA0STAT 0Ah

USCI receive buffer UCA0RXBUF 0Ch

USCI transmit buffer UCA0TXBUF 0Eh

USCI LIN control UCA0ABCTL 10h

USCI IrDA transmit control UCA0IRTCTL 12h

USCI IrDA receive control UCA0IRRCTL 13h

USCI interrupt enable UCA0IE 1Ch

USCI interrupt flags UCA0IFG 1Dh

USCI interrupt vector word UCA0IV 1Eh

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Table 41. USCI_B0 Registers (Base Address: 05E0h)

USCI synchronous control 1 UCB0CTL1 00h

USCI synchronous control 0 UCB0CTL0 01h

USCI synchronous bit rate 0 UCB0BR0 06h

USCI synchronous bit rate 1 UCB0BR1 07h

USCI synchronous status UCB0STAT 0Ah

USCI synchronous receive buffer UCB0RXBUF 0Ch

USCI synchronous transmit buffer UCB0TXBUF 0Eh

USCI I2C own address UCB0I2COA 10h

USCI I2C slave address UCB0I2CSA 12h

USCI interrupt enable UCB0IE 1Ch

USCI interrupt flags UCB0IFG 1Dh

USCI interrupt vector word UCB0IV 1Eh

Table 42. USCI_A1 Registers (Base Address: 0600h)

USCI control 0 UCA1CTL1 00h

USCI control 1 UCA1CTL0 01h

USCI baud rate 0 UCA1BR0 06h

USCI baud rate 1 UCA1BR1 07h

USCI modulation control UCA1MCTL 08h

USCI status UCA1STAT 0Ah

USCI receive buffer UCA1RXBUF 0Ch

USCI transmit buffer UCA1TXBUF 0Eh

USCI LIN control UCA1ABCTL 10h

USCI IrDA transmit control UCA1IRTCTL 12h

USCI IrDA receive control UCA1IRRCTL 13h

USCI interrupt enable UCA1IE 1Ch

USCI interrupt flags UCA1IFG 1Dh

USCI interrupt vector word UCA1IV 1Eh

Table 43. USCI_B1 Registers (Base Address: 0620h)

USCI synchronous control 0 UCB1CTL1 00h

USCI synchronous control 1 UCB1CTL0 01h

USCI synchronous bit rate 0 UCB1BR0 06h

USCI synchronous bit rate 1 UCB1BR1 07h

USCI synchronous status UCB1STAT 0Ah

USCI synchronous receive buffer UCB1RXBUF 0Ch

USCI synchronous transmit buffer UCB1TXBUF 0Eh

USCI I2C own address UCB1I2COA 10h

USCI I2C slave address UCB1I2CSA 12h

USCI interrupt enable UCB1IE 1Ch

USCI interrupt flags UCB1IFG 1Dh

USCI interrupt vector word UCB1IV 1Eh

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Table 44. ADC10_A Registers (Base Address: 0740h)

ADC10_A Control register 0 ADC10CTL0 00h

ADC10_A Control register 1 ADC10CTL1 02h

ADC10_A Control register 2 ADC10CTL2 04h

ADC10_A Window Comparator Low Threshold ADC10LO 06h

ADC10_A Window Comparator High Threshold ADC10HI 08h

ADC10_A Memory Control Register 0 ADC10MCTL0 0Ah

ADC10_A Conversion Memory Register ADC10MEM0 12h

ADC10_A Interrupt Enable ADC10IE 1Ah

ADC10_A Interrupt Flags ADC10IGH 1Ch

ADC10_A Interrupt Vector Word ADC10IV 1Eh

Table 45. Comparator_B Registers (Base Address: 08C0h)

Comp_B control register 0 CBCTL0 00h

Comp_B control register 1 CBCTL1 02h

Comp_B control register 2 CBCTL2 04h

Comp_B control register 3 CBCTL3 06h

Comp_B interrupt register CBINT 0Ch

Comp_B interrupt vector word CBIV 0Eh

Table 46. USB Configuration Registers (Base Address: 0900h)

USB key/ID USBKEYID 00h

USB module configuration USBCNF 02h

USB PHY control USBPHYCTL 04h

USB power control USBPWRCTL 08h

USB PLL control USBPLLCTL 10h

USB PLL divider USBPLLDIV 12h

USB PLL interrupts USBPLLIR 14h

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Table 47. USB Control Registers (Base Address: 0920h)

Input endpoint#0 configuration IEPCNF_0 00h

Input endpoint #0 byte count IEPCNT_0 01h

Output endpoint#0 configuration OEPCNF_0 02h

Output endpoint #0 byte count OEPCNT_0 03h

Input endpoint interrupt enables IEPIE 0Eh

Output endpoint interrupt enables OEPIE 0Fh

Input endpoint interrupt flags IEPIFG 10h

Output endpoint interrupt flags OEPIFG 11h

USB interrupt vector USBIV 12h

USB maintenance MAINT 16h

Time stamp TSREG 18h

USB frame number USBFN 1Ah

USB control USBCTL 1Ch

USB interrupt enables USBIE 1Dh

USB interrupt flags USBIFG 1Eh

Function address FUNADR 1Fh

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)

Voltage applied at VCC to VSS –0.3 V to 4.1 V

Voltage applied to any pin (excluding VCORE, VBUS, V18)(2) –0.3 V to VCC + 0.3 V

Diode current at any device pin ±2 mA

Storage temperature range, Tstg (3) –55°C to 150°C

Maximum junction temperature, TJ95°C

(1) Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

Thermal Packaging Characteristics(1)

PARAMETER VALUE UNIT

VQFN (RGC) 30

VQFN (RGZ) 28.6

θJA Junction-to-ambient thermal resistance, still air(2) °C/W

LQFP (PT) 62.8

BGA (ZQE) 55.5

VQFN (RGC) 15.6

VQFN (RGZ) 14.4

θJC(TOP) Junction-to-case (top) thermal resistance(3) °C/W

LQFP (PT) 18.2

BGA (ZQE) 21.2

VQFN(RGC) 1.6

VQFN (RGZ) 1.6

θJC(BOTTOM) Junction-to-case (bottom) thermal resistance(4) °C/W

LQFP (PT) N/A

BGA (ZQE) N/A

VQFN (RGC) 8.9

VQFN (RGZ) 5.5

θJB Junction-to-board thermal resistance(5) °C/W

LQFP (PT) 28.3

BGA (ZQE) 19.3

(1) N/A = not applicable

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard

test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Recommended Operating Conditions MIN NOM MAX UNIT

PMMCOREVx = 0 1.8 3.6 V

PMMCOREVx = 0, 1 2.0 3.6 V

Supply voltage during program execution and flash

VCC programming(AVCC = DVCC1/2 = DVCC)(1) PMMCOREVx = 0, 1, 2 2.2 3.6 V

PMMCOREVx = 0, 1, 2, 3 2.4 3.6 V

PMMCOREVx = 0 1.8 3.6 V

PMMCOREVx = 0, 1 2.0 3.6 V

Supply voltage during USB operation, USB PLL disabled

USB_EN = 1, UPLLEN = 0 PMMCOREVx = 0, 1, 2 2.2 3.6 V

VCC,USB PMMCOREVx = 0, 1, 2, 3 2.4 3.6 V

PMMCOREVx = 2 2.2 3.6 V

Supply voltage during USB operation, USB PLL enabled(2)

USB_EN = 1, UPLLEN = 1 PMMCOREVx = 2, 3 2.4 3.6 V

VSS Supply voltage (AVSS = DVSS1/2 = DVSS) 0 V

TAOperating free-air temperature I version –40 85 °C

TJOperating junction temperature I version -40 85 °C

CVCORE Capacitor at VCORE 470 nF

CDVCC/Capacitor ratio of DVCC to VCORE 10

CVCORE PMMCOREVx = 0,

1.8 V ≤VCC ≤3.6 V 0 8.0

(default condition)

PMMCOREVx = 1, 0 12.0

Processor frequency (maximum MCLK frequency)(3) 2.0 V ≤VCC ≤3.6 V

fSYSTEM MHz

(see Figure 1)PMMCOREVx = 2, 0 20.0

2.2 V ≤VCC ≤3.6 V

PMMCOREVx = 3, 0 25.0

2.4 V ≤VCC ≤3.6 V

fSYSTEM_USB Minimum processor frequency for USB operation 1.5 MHz

USB_wait Wait state cycles during USB operation 16 cycles

(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be

tolerated during power up and operation.

(2) USB operation with USB PLL enabled requires PMMCOREVx ≥2 for proper operation.

(3) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

2.01.8

SystemFrequency-MHz

SupplyVoltage-V

ThenumberswithinthefieldsdenotethesupportedPMMCOREVxsettings.

2.2 2.4 3.6

0,1,2,30,1,20,10

1,2,3

1,2

2,3

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Figure 1. Maximum System Frequency

Electrical Characteristics

Active Mode Supply Current Into VCC Excluding External Current

over recommended operating free-air temperature (unless otherwise noted)(1) (2) (3)

FREQUENCY (fDCO = fMCLK = fSMCLK)

EXECUTION

PARAMETER VCC PMMCOREVx 1 MHz 8 MHz 12 MHz 20 MHz 25 MHz UNIT

MEMORY TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX

0 0.25 0.27 1.55 1.68

1 0.28 1.74 2.58 2.78

IAM, Flash Flash 3 V mA

2 0.30 1.91 2.84 4.68 5.06

3 0.32 2.09 3.10 5.13 6.0 6.5

0 0.17 0.19 0.91 1.00

1 0.19 1.03 1.54 1.67

IAM, RAM RAM 3 V mA

2 0.20 1.16 1.73 2.84 3.11

3 0.21 1.24 1.87 3.1 3.9 4.3

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load

capacitance are chosen to closely match the required 12.5 pF.

(3) Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0).

fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.

XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)

-40°C 25°C 60°C 85°C

PARAMETER VCC PMMCOREVx UNIT

TYP MAX TYP MAX TYP MAX TYP MAX

2.2 V 0 73 77 85 80 85 97

ILPM0,1MHz Low-power mode 0(3)(4) µA

3 V 3 79 83 92 88 95 105

2.2 V 0 6.5 6.5 8 7.5 8 11

ILPM2 Low-power mode 2(5)(4) µA

3 V 3 7.0 7.0 9 7.9 8.9 13

0 1.60 1.90 2.6 3.4

2.2 V 1 1.65 2.00 2.7 3.6

2 1.75 2.15 2.9 3.8

Low-power mode 3,

ILPM3,XT1LF 0 1.8 2.1 2.6 2.8 3.6 6.0 µA

crystal mode(6)(4) 1 1.9 2.3 2.9 3.8

3 V 2 2.0 2.4 3.0 4.0

3 2.0 2.5 3.0 3.1 4.0 6.5

0 1.1 1.3 1.8 1.9 2.7 5.0

1 1.1 1.4 2.0 2.8

Low-power mode 3,

ILPM3,VLO 3 V µA

VLO mode(7)(4) 2 1.2 1.5 2.1 2.9

3 1.3 1.5 2.0 2.2 3.0 5.5

0 0.9 1.1 1.5 1.8 2.5 4.8

1 1.1 1.2 2.0 2.6

ILPM4 Low-power mode 4(8)(4) 3 V µA

2 1.2 1.2 2.1 2.7

3 1.3 1.3 1.6 2.2 2.8 5.0

ILPM4.5 Low-power mode 4.5(9) 3 V 0.15 0.18 0.35 0.26 0.45 0.80 µA

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load

capacitance are chosen to closely match the required 12.5 pF.

(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz

USB disabled (VUSBEN = 0, SLDOEN = 0).

(4) Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL, SVML).

High side monitor disabled (SVMH). RAM retention enabled.

(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting

= 1 MHz operation, DCO bias generator enabled.

USB disabled (VUSBEN = 0, SLDOEN = 0)

(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz

USB disabled (VUSBEN = 0, SLDOEN = 0)

(7) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz

USB disabled (VUSBEN = 0, SLDOEN = 0)

(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz

USB disabled (VUSBEN = 0, SLDOEN = 0)

(9) Internal regulator disabled. No data retention.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Schmitt-Trigger Inputs –General Purpose I/O(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

1.8 V 0.80 1.40

VIT+ Positive-going input threshold voltage V

3 V 1.50 2.10

1.8 V 0.45 1.00

VIT–Negative-going input threshold voltage V

3 V 0.75 1.65

1.8 V 0.3 0.85

Vhys Input voltage hysteresis (VIT+ –VIT–) V

3 V 0.4 1.0

For pullup: VIN = VSS

RPull Pullup/pulldown resistor 20 35 50 kΩ

For pulldown: VIN = VCC

CIInput capacitance VIN = VSS or VCC 5 pF

(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).

Inputs –Ports P1 and P2(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN MAX UNIT

Port P1, P2: P1.x to P2.x, External trigger pulse width to

t(int) External interrupt timing(2) 2.2 V/3 V 20 ns

set interrupt flag

(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.

(2) An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set by trigger signals shorter

than t(int).

Leakage Current –General Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN MAX UNIT

Ilkg(Px.x) High-impedance leakage current (1) (2) 1.8 V/3 V ±50 nA

(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

Outputs –General Purpose I/O (Full Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN MAX UNIT

I(OHmax) =–3 mA(1) VCC –0.25 VCC

1.8 V

I(OHmax) =–10 mA(2) VCC –0.60 VCC

VOH High-level output voltage V

I(OHmax) =–5 mA(1) VCC –0.25 VCC

3 V

I(OHmax) =–15 mA(2) VCC –0.60 VCC

I(OLmax) = 3 mA(1) VSS VSS + 0.25

1.8 V

I(OLmax) = 10 mA(2) VSS VSS + 0.60

VOL Low-level output voltage V

I(OLmax) = 5 mA(1) VSS VSS + 0.25

3 V

I(OLmax) = 15 mA(2) VSS VSS + 0.60

(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

specified.

(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage

drop specified.

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Outputs –General Purpose I/O (Reduced Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS VCC MIN MAX UNIT

I(OHmax) =–1 mA(2) VCC –0.25 VCC

1.8 V

I(OHmax) =–3 mA(3) VCC –0.60 VCC

VOH High-level output voltage V

I(OHmax) =–2 mA(2) VCC –0.25 VCC

3 V

I(OHmax) =–6 mA(3) VCC –0.60 VCC

I(OLmax) = 1 mA(2) VSS VSS + 0.25

1.8 V

I(OLmax) = 3 mA(3) VSS VSS + 0.60

VOL Low-level output voltage V

I(OLmax) = 2 mA(2) VSS VSS + 0.25

3 V

I(OLmax) = 6 mA(3) VSS VSS + 0.60

(1) Selecting reduced drive strength may reduce EMI.

(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop

specified.

(3) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage

drop specified.

Output Frequency –General Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

(1)(2)VCC = 1.8 V 16

PMMCOREVx = 0

Port output frequency

fPx.y MHz

(with load) VCC = 3 V 25

PMMCOREVx = 3

VCC = 1.8 V

ACLK 16

PMMCOREVx = 0

SMCLK

fPort_CLK Clock output frequency MHz

MCLK VCC = 3 V 25

CL= 20 pF(2) PMMCOREVx = 3

(1) A resistive divider with 2 ×R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full

drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL= 20 pF is connected to the output to VSS.

(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

0.0 0.5 1.0 1.5 2.0

T = 25°C

T = 85°C

V = 1.8 V

Px.y

V – Low-Level Output Voltage – V

I – Typical Low-Level Output Current – mA

0.0

5.0

10.0

15.0

20.0

25.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

T = 25°C

T = 85°C

V = 3.0 V

Px.y

V – Low-Level Output Voltage – V

I – Typical Low-Level Output Current – mA

-8.0

-7.0

-6.0

-5.0

-4.0

-3.0

-2.0

-1.0

0.0

0.0 0.5 1.0 1.5 2.0

T = 25°C

T = 85°C

V = 1.8 V

Px.y

V – High-Level Output Voltage – V

I – Typical High-Level Output Current – mA

-25.0

-20.0

-15.0

-10.0

-5.0

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

T = 25°C

T = 85°C

V = 3.0 V

Px.y

V – High-Level Output Voltage – V

I – Typical High-Level Output Current – mA

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Typical Characteristics –Outputs, Reduced Drive Strength (PxDS.y = 0)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT

vs vs

LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE

Figure 2. Figure 3.

TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs vs

HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE

Figure 4. Figure 5.

0.0 0.5 1.0 1.5 2.0

T = 25°C

T = 85°C

V = 1.8 V

Px.y

V – Low-Level Output Voltage – V

I – Typical Low-Level Output Current – mA

0.0

5.0

10.0

15.0

20.0

25.0

30.0

35.0

40.0

45.0

50.0

55.0

60.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

T = 25°C

T = 85°C

V = 3.0 V

Px.y

V – Low-Level Output Voltage – V

I – Typical Low-Level Output Current – mA

-60.0

-55.0

-50.0

-45.0

-40.0

-35.0

-30.0

-25.0

-20.0

-15.0

-10.0

-5.0

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

T = 25°C

T = 85°C

V = 3.0 V

Px.y

V – High-Level Output Voltage – V

I – Typical High-Level Output Current – mA

-20

-16

-12

-8

-4

0.0 0.5 1.0 1.5 2.0

T = 25°C

T = 85°C

V = 1.8 V

Px.y

V – High-Level Output Voltage – V

I – Typical High-Level Output Current – mA

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Typical Characteristics –Outputs, Full Drive Strength (PxDS.y = 1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT

vs vs

LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE

Figure 6. Figure 7.

TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs vs

HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE

Figure 8. Figure 9.

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Crystal Oscillator, XT1, Low-Frequency Mode(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fOSC = 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 1, 0.075

TA= 25°C

Differential XT1 oscillator crystal fOSC = 32768 Hz, XTS = 0,

ΔIDVCC.LF current consumption from lowest XT1BYPASS = 0, XT1DRIVEx = 2, 3 V 0.170 µA

drive setting, LF mode TA= 25°C

fOSC = 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3, 0.290

TA= 25°C

XT1 oscillator crystal frequency,

fXT1,LF0 XTS = 0, XT1BYPASS = 0 32768 Hz

LF mode

XT1 oscillator logic-level

fXT1,LF,SW square-wave input frequency, XTS = 0, XT1BYPASS = 1(2) (3) 10 32.768 50 kHz

LF mode XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 0, 210

fXT1,LF = 32768 Hz, CL,eff = 6 pF

Oscillation allowance for

OALF kΩ

LF crystals(4) XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 1, 300

fXT1,LF = 32768 Hz, CL,eff = 12 pF

XTS = 0, XCAPx = 0(6) 2

XTS = 0, XCAPx = 1 5.5

Integrated effective load

CL,eff pF

capacitance, LF mode(5) XTS = 0, XCAPx = 2 8.5

XTS = 0, XCAPx = 3 12.0

XTS = 0, Measured at ACLK,

Duty cycle LF mode 30 70 %

fXT1,LF = 32768 Hz

Oscillator fault frequency,

fFault,LF XTS = 0(8) 10 10000 Hz

LF mode(7)

fOSC = 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 0, 1000

TA= 25°C,

CL,eff = 6 pF

tSTART,LF Startup time, LF mode 3 V ms

fOSC = 32768 Hz, XTS = 0,

XT1BYPASS = 0, XT1DRIVEx = 3, 500

TA= 25°C,

CL,eff = 12 pF

(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

(a) Keep the trace between the device and the crystal as short as possible.

(b) Design a good ground plane around the oscillator pins.

(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in

the Schmitt-trigger Inputs section of this datasheet.

(3) Maximum frequency of operation of the entire device cannot be exceeded.

(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

(a) For XT1DRIVEx = 0, CL,ef f ≤6 pF.

(b) For XT1DRIVEx = 1, 6 pF ≤CL,ef f ≤9 pF.

(d) For XT1DRIVEx = 3, CL,ef f ≥6 pF.

(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(8) Measured with logic-level input frequency but also applies to operation with crystals.

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Crystal Oscillator, XT2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fOSC = 4 MHz, XT2OFF = 0, 200

XT2BYPASS = 0, XT2DRIVEx = 0, TA= 25°C

fOSC = 12 MHz, XT2OFF = 0, 260

XT2BYPASS = 0, XT2DRIVEx = 1, TA= 25°C

XT2 oscillator crystal current

IDVCC.XT2 3 V µA

consumption fOSC = 20 MHz, XT2OFF = 0, 325

XT2BYPASS = 0, XT2DRIVEx = 2, TA= 25°C

fOSC = 32 MHz, XT2OFF = 0, 450

XT2BYPASS = 0, XT2DRIVEx = 3, TA= 25°C

XT2 oscillator crystal

fXT2,HF0 XT2DRIVEx = 0, XT2BYPASS = 0(3) 4 8 MHz

frequency, mode 0

XT2 oscillator crystal

fXT2,HF1 XT2DRIVEx = 1, XT2BYPASS = 0(3) 8 16 MHz

frequency, mode 1

XT2 oscillator crystal

fXT2,HF2 XT2DRIVEx = 2, XT2BYPASS = 0(3) 16 24 MHz

frequency, mode 2

XT2 oscillator crystal

fXT2,HF3 XT2DRIVEx = 3, XT2BYPASS = 0(3) 24 32 MHz

frequency, mode 3

XT2 oscillator logic-level

fXT2,HF,SW square-wave input frequency, XT2BYPASS = 1(4) (3) 0.7 32 MHz

bypass mode XT2DRIVEx = 0, XT2BYPASS = 0, 450

fXT2,HF0 = 6 MHz, CL,eff = 15 pF

XT2DRIVEx = 1, XT2BYPASS = 0, 320

fXT2,HF1 = 12 MHz, CL,eff = 15 pF

Oscillation allowance for

OAHF Ω

HF crystals(5) XT2DRIVEx = 2, XT2BYPASS = 0, 200

fXT2,HF2 = 20 MHz, CL,eff = 15 pF

XT2DRIVEx = 3, XT2BYPASS = 0, 200

fXT2,HF3 = 32 MHz, CL,eff = 15 pF

fOSC = 6 MHz,

XT2BYPASS = 0, XT2DRIVEx = 0, 0.5

TA= 25°C, CL,eff = 15 pF

tSTART,HF Startup time 3 V ms

fOSC = 20 MHz

XT2BYPASS = 0, XT2DRIVEx = 2, 0.3

TA= 25°C, CL,eff = 15 pF

Integrated effective load

CL,eff 1 pF

capacitance, HF mode(6) (1)

Duty cycle Measured at ACLK, fXT2,HF2 = 20 MHz 40 50 60 %

fFault,HF Oscillator fault frequency(7) XT2BYPASS = 1(8) 30 300 kHz

(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(2) To improve EMI on the XT2 oscillator the following guidelines should be observed.

(a) Keep the traces between the device and the crystal as short as possible.

(b) Design a good ground plane around the oscillator pins.

(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.

(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.

(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(3) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device

operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.

(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined

in the Schmitt-trigger Inputs section of this datasheet.

(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(8) Measured with logic-level input frequency but also applies to operation with crystals.

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V 6 9.4 14 kHz

dfVLO/dTVLO frequency temperature drift Measured at ACLK(1) 1.8 V to 3.6 V 0.5 %/°C

dfVLO/dVCC VLO frequency supply voltage drift Measured at ACLK(2) 1.8 V to 3.6 V 4 %/V

Duty cycle Measured at ACLK 1.8 V to 3.6 V 40 50 60 %

(1) Calculated using the box method: (MAX(-40 to 85°C) –MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C–(–40°C))

(2) Calculated using the box method: (MAX(1.8 to 3.6 V) –MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V –1.8 V)

Internal Reference, Low-Frequency Oscillator (REFO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

IREFO REFO oscillator current consumption TA= 25°C 1.8 V to 3.6 V 3 µA

REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V 32768 Hz

fREFO Full temperature range 1.8 V to 3.6 V ±3.5 %

REFO absolute tolerance calibrated TA= 25°C 3 V ±1.5 %

dfREFO/dTREFO frequency temperature drift Measured at ACLK(1) 1.8 V to 3.6 V 0.01 %/°C

dfREFO/dVCC REFO frequency supply voltage drift Measured at ACLK(2) 1.8 V to 3.6 V 1.0 %/V

Duty cycle Measured at ACLK 1.8 V to 3.6 V 40 50 60 %

tSTART REFO startup time 40%/60% duty cycle 1.8 V to 3.6 V 25 µs

(1) Calculated using the box method: (MAX(-40 to 85°C) –MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C–(–40°C))

(2) Calculated using the box method: (MAX(1.8 to 3.6 V) –MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V –1.8 V)

01 2 34567

Typical DCO Frequency, V = 3.0 V, T = 25°C

CC A

DCORSEL

100

0.1

f – MHz

DCO

DCOx = 31

DCOx = 0

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz

fDCO(0,31) DCO frequency (0, 31) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz

fDCO(1,0) DCO frequency (1, 0) DCORSELx = 1, DCOx = 0, MODx = 0 0.15 0.36 MHz

fDCO(1,31) DCO frequency (1, 31) DCORSELx = 1, DCOx = 31, MODx = 0 1.47 3.45 MHz

fDCO(2,0) DCO frequency (2, 0) DCORSELx = 2, DCOx = 0, MODx = 0 0.32 0.75 MHz

fDCO(2,31) DCO frequency (2, 31) DCORSELx = 2, DCOx = 31, MODx = 0 3.17 7.38 MHz

fDCO(3,0) DCO frequency (3, 0) DCORSELx = 3, DCOx = 0, MODx = 0 0.64 1.51 MHz

fDCO(3,31) DCO frequency (3, 31) DCORSELx = 3, DCOx = 31, MODx = 0 6.07 14.0 MHz

fDCO(4,0) DCO frequency (4, 0) DCORSELx = 4, DCOx = 0, MODx = 0 1.3 3.2 MHz

fDCO(4,31) DCO frequency (4, 31) DCORSELx = 4, DCOx = 31, MODx = 0 12.3 28.2 MHz

fDCO(5,0) DCO frequency (5, 0) DCORSELx = 5, DCOx = 0, MODx = 0 2.5 6.0 MHz

fDCO(5,31) DCO frequency (5, 31) DCORSELx = 5, DCOx = 31, MODx = 0 23.7 54.1 MHz

fDCO(6,0) DCO frequency (6, 0) DCORSELx = 6, DCOx = 0, MODx = 0 4.6 10.7 MHz

fDCO(6,31) DCO frequency (6, 31) DCORSELx = 6, DCOx = 31, MODx = 0 39.0 88.0 MHz

fDCO(7,0) DCO frequency (7, 0) DCORSELx = 7, DCOx = 0, MODx = 0 8.5 19.6 MHz

fDCO(7,31) DCO frequency (7, 31) DCORSELx = 7, DCOx = 31, MODx = 0 60 135 MHz

Frequency step between range

SDCORSEL SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) 1.2 2.3 ratio

DCORSEL and DCORSEL + 1

Frequency step between tap

SDCO SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) 1.02 1.12 ratio

DCO and DCO + 1

Duty cycle Measured at SMCLK 40 50 60 %

DCO frequency temperature

dfDCO/dT fDCO = 1 MHz, 0.1 %/°C

drift(1)

dfDCO/dVCC DCO frequency voltage drift(2) fDCO = 1 MHz 1.9 %/V

(1) Calculated using the box method: (MAX(-40 to 85°C) –MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C–(–40°C))

(2) Calculated using the box method: (MAX(1.8 to 3.6 V) –MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V –1.8 V)

Figure 10. Typical DCO frequency

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

PMM, Brown-Out Reset (BOR)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

BORHon voltage,

V(DVCC_BOR_IT–) | dDVCC/dt|<3 V/s 1.45 V

DVCC falling level

BORHoff voltage,

V(DVCC_BOR_IT+) | dDVCC/dt|<3 V/s 0.80 1.30 1.50 V

DVCC rising level

V(DVCC_BOR_hys) BORHhysteresis 60 250 mV

Pulse length required at

tRESET RST/NMI pin to accept a 2 µs

reset

PMM, Core Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Core voltage, active mode,

VCORE3(AM) 2.4 V ≤DVCC ≤3.6 V 1.90 V

PMMCOREV = 3

Core voltage, active mode,

VCORE2(AM) 2.2 V ≤DVCC ≤3.6 V 1.80 V

PMMCOREV = 2

Core voltage, active mode,

VCORE1(AM) 2.0 V ≤DVCC ≤3.6 V 1.60 V

PMMCOREV = 1

Core voltage, active mode,

VCORE0(AM) 1.8 V ≤DVCC ≤3.6 V 1.40 V

PMMCOREV = 0

Core voltage, low-current mode,

VCORE3(LPM) 2.4 V ≤DVCC ≤3.6 V 1.94 V

PMMCOREV = 3

Core voltage, low-current mode,

VCORE2(LPM) 2.2 V ≤DVCC ≤3.6 V 1.84 V

PMMCOREV = 2

Core voltage, low-current mode,

VCORE1(LPM) 2.0 V ≤DVCC ≤3.6 V 1.64 V

PMMCOREV = 1

Core voltage, low-current mode,

VCORE0(LPM) 1.8 V ≤DVCC ≤3.6 V 1.44 V

PMMCOREV = 0

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

PMM, SVS High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SVSHE = 0, DVCC = 3.6 V 0 nA

I(SVSH) SVS current consumption SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 200 nA

SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 1.5 µA

SVSHE = 1, SVSHRVL = 0 1.57 1.68 1.78

SVSHE = 1, SVSHRVL = 1 1.79 1.88 1.98

V(SVSH_IT–)SVSHon voltage level(1) V

SVSHE = 1, SVSHRVL = 2 1.98 2.08 2.21

SVSHE = 1, SVSHRVL = 3 2.10 2.18 2.31

SVSHE = 1, SVSMHRRL = 0 1.62 1.74 1.85

SVSHE = 1, SVSMHRRL = 1 1.88 1.94 2.07

SVSHE = 1, SVSMHRRL = 2 2.07 2.14 2.28

SVSHE = 1, SVSMHRRL = 3 2.20 2.30 2.42

V(SVSH_IT+) SVSHoff voltage level(1) V

SVSHE = 1, SVSMHRRL = 4 2.32 2.40 2.55

SVSHE = 1, SVSMHRRL = 5 2.52 2.70 2.88

SVSHE = 1, SVSMHRRL = 6 2.90 3.10 3.23

SVSHE = 1, SVSMHRRL = 7 2.90 3.10 3.23

SVSHE = 1, dVDVCC/dt = 10 mV/µs, 2.5

SVSHFP = 1

tpd(SVSH) SVSHpropagation delay µs

SVSHE = 1, dVDVCC/dt = 1 mV/µs, 20

SVSHFP = 0

SVSHE = 0 →112.5

SVSHFP = 1

t(SVSH) SVSHon/off delay time µs

SVSHE = 0 →1100

SVSHFP = 0

dVDVCC/dt DVCC rise time 0 1000 V/s

(1) The SVSHsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430x5xx/MSP430x6xx Family User's Guide (SLAU208) on recommended settings and use

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

PMM, SVM High Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SVMHE = 0, DVCC = 3.6 V 0 nA

I(SVMH) SVMHcurrent consumption SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0 200 nA

SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 1.5 µA

SVMHE = 1, SVSMHRRL = 0 1.62 1.74 1.85

SVMHE = 1, SVSMHRRL = 1 1.88 1.94 2.07

SVMHE = 1, SVSMHRRL = 2 2.07 2.14 2.28

SVMHE = 1, SVSMHRRL = 3 2.20 2.30 2.42

V(SVMH) SVMHon/off voltage level(1) SVMHE = 1, SVSMHRRL = 4 2.32 2.40 2.55 V

SVMHE = 1, SVSMHRRL = 5 2.52 2.70 2.88

SVMHE = 1, SVSMHRRL = 6 2.90 3.10 3.23

SVMHE = 1, SVSMHRRL = 7 2.90 3.10 3.23

SVMHE = 1, SVMHOVPE = 1 3.75

SVMHE = 1, dVDVCC/dt = 10 mV/µs, 2.5

SVMHFP = 1

tpd(SVMH) SVMHpropagation delay µs

SVMHE = 1, dVDVCC/dt = 1 mV/µs, 20

SVMHFP = 0

SVMHE = 0 →112.5

SVMHFP = 1

t(SVMH) SVMHon/off delay time µs

SVMHE = 0 →1100

SVMHFP = 0

(1) The SVMHsettings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage

Supervisor chapter in the MSP430x5xx/MSP430x6xx Family User's Guide (SLAU208) on recommended settings and use

PMM, SVS Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SVSLE = 0, PMMCOREV = 2 0 nA

I(SVSL) SVSLcurrent consumption SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200 nA

SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 2.0 µA

SVSLE = 1, dVCORE/dt = 10 mV/µs, 2.5

SVSLFP = 1

tpd(SVSL) SVSLpropagation delay µs

SVSLE = 1, dVCORE/dt = 1 mV/µs, 20

SVSLFP = 0

SVSLE = 0 →112.5

SVSLFP = 1

t(SVSL) SVSLon/off delay time µs

SVSLE = 0 →1100

SVSLFP = 0

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

PMM, SVM Low Side

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SVMLE = 0, PMMCOREV = 2 0 nA

I(SVML) SVMLcurrent consumption SVMLE = 1, PMMCOREV = 2, SVMLFP = 0 200 nA

SVMLE = 1, PMMCOREV = 2, SVMLFP = 1 1.5 µA

SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 2.5

tpd(SVML) SVMLpropagation delay µs

SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 20

SVMLE = 0 →1, SVMLFP = 1 12.5

t(SVML) SVMLon/off delay time µs

SVMLE = 0 →1, SVMLFP = 0 100

Wake-Up From Low Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PMMCOREV = SVSMLRRL = n, fMCLK ≥4.0 MHz 5

tWAKE-UP- Wake-up time from LPM2, LPM3, or where n = 0, 1, 2, or 3, µs

FAST LPM4 to active mode(1) fMCLK <4.0 MHz 6

SVSLFP = 1

PMMCOREV = SVSMLRRL = n,

tWAKE-UP- Wake-up time from LPM2, LPM3 or where n = 0, 1, 2, or 3, 150 165 µs

SLOW LPM4 to active mode(2) SVSLFP = 0

tWAKE-UP- Wake-up time from LPM4.5 to active 2 3 ms

LPM5 mode(3)

tWAKE-UP- Wake-up time from RST or BOR event to 2 3 ms

RESET active mode(3)

(1) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance

mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVMLin full

performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVMLwhile

operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx

Family User's Guide (SLAU208).

(2) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance

mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVMLare in normal mode (low current)

mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVMLwhile operating in LPM2, LPM3, and

LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide

(SLAU208).

(3) This value represents the time from the wakeup event to the reset vector execution.

Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

Internal: SMCLK, ACLK

fTA Timer_A input clock frequency External: TACLK 1.8 V/ 3 V 25 MHz

Duty cycle = 50% ±10%

All capture inputs.

tTA,cap Timer_A capture timing Minimum pulse width required for 1.8 V/ 3 V 20 ns

capture.

Timer_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

Internal: SMCLK, ACLK

fTB Timer_B input clock frequency External: TBCLK 1.8 V/ 3 V 25 MHz

Duty cycle = 50% ±10%

All capture inputs.

tTB,cap Timer_B capture timing Minimum pulse width required for 1.8 V/ 3 V 20 ns

capture.

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

USCI (UART Mode) Recommended Operating Conditions

PARAMETER CONDITIONS VCC MIN TYP MAX UNIT

Internal: SMCLK, ACLK

fUSCI USCI input clock frequency External: UCLK fSYSTEM MHz

Duty cycle = 50% ±10%

BITCLK clock frequency

fBITCLK 1 MHz

(equals baud rate in MBaud)

USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

2.2 V 50 600

tτUART receive deglitch time(1) ns

3 V 50 600

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized their width should exceed the maximum specification of the deglitch time.

USCI (SPI Master Mode) Recommended Operating Conditions

PARAMETER CONDITIONS VCC MIN TYP MAX UNIT

Internal: SMCLK, ACLK

fUSCI USCI input clock frequency fSYSTEM MHz

Duty cycle = 50% ±10%

USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(see Note (1),Figure 11 and Figure 12)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

SMCLK, ACLK

fUSCI USCI input clock frequency fSYSTEM MHz

Duty cycle = 50% ±10% 1.8 V 55

PMMCOREV = 0 ns

3 V 38

tSU,MI SOMI input data setup time 2.4 V 30

PMMCOREV = 3 ns

3 V 25

1.8 V 0

PMMCOREV = 0 ns

3 V 0

tHD,MI SOMI input data hold time 2.4 V 0

PMMCOREV = 3 ns

3 V 0

1.8 V 20

UCLK edge to SIMO valid, ns

CL= 20 pF, PMMCOREV = 0 3 V 18

tVALID,MO SIMO output data valid time(2) 2.4 V 16

UCLK edge to SIMO valid, ns

CL= 20 pF, PMMCOREV = 3 3 V 15

1.8 V -10

CL= 20 pF, PMMCOREV = 0 ns

3 V -8

tHD,MO SIMO output data hold time(3) 2.4 V -10

CL= 20 pF, PMMCOREV = 3 ns

3 V -8

(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).

For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in Figure 11 and Figure 12.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in

Figure 11 and Figure 12.

tSU,MI

tHD,MI

UCLK

SOMI

SIMO

tVALID,MO

tHD,MO

CKPL =0

CKPL =1

tLO/HI tLO/HI

1/fUCxCLK

tSU,MI

tHD,MI

UCLK

SOMI

SIMO

tVALID,MO

CKPL =0

CKPL =1

1/fUCxCLK

tHD,MO

tLO/HI tLO/HI

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Figure 11. SPI Master Mode, CKPH = 0

Figure 12. SPI Master Mode, CKPH = 1

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(see Note (1),Figure 13 and Figure 14)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

1.8 V 11

PMMCOREV = 0 ns

3 V 8

tSTE,LEAD STE lead time, STE low to clock 2.4 V 7

PMMCOREV = 3 ns

3 V 6

1.8 V 3

PMMCOREV = 0 ns

3 V 3

tSTE,LAG STE lag time, Last clock to STE high 2.4 V 3

PMMCOREV = 3 ns

3 V 3

1.8 V 66

PMMCOREV = 0 ns

3 V 50

tSTE,ACC STE access time, STE low to SOMI data out 2.4 V 36

PMMCOREV = 3 ns

3 V 30

1.8 V 30

PMMCOREV = 0 ns

3 V 23

STE disable time, STE high to SOMI high

tSTE,DIS impedance 2.4 V 16

PMMCOREV = 3 ns

3 V 13

1.8 V 5

PMMCOREV = 0 ns

3 V 5

tSU,SI SIMO input data setup time 2.4 V 2

PMMCOREV = 3 ns

3 V 2

1.8 V 5

PMMCOREV = 0 ns

3 V 5

tHD,SI SIMO input data hold time 2.4 V 5

PMMCOREV = 3 ns

3 V 5

UCLK edge to SOMI valid, 1.8 V 76

CL= 20 pF ns

3 V 60

PMMCOREV = 0

tVALID,SO SOMI output data valid time(2) UCLK edge to SOMI valid, 2.4 V 44

CL= 20 pF ns

3 V 40

PMMCOREV = 3 1.8 V 18

CL= 20 pF ns

PMMCOREV = 0 3 V 12

tHD,SO SOMI output data hold time(3) 2.4 V 10

CL= 20 pF ns

PMMCOREV = 3 3 V 8

(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).

For the master's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in Figure 11 and Figure 12.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 11

and Figure 12.

STE

UCLK

CKPL =0

CKPL =1

SOMI

SIMO

tSU,SI

tHD,SI

tVALID,SO

tSTE,LEAD

1/fUCxCLK

tLO/HI tLO/HI

tSTE,LAG

tSTE,DIS

tSTE,ACC

tHD,SO

STE

UCLK

CKPL =0

CKPL =1

SOMI

SIMO

tSU,SI

tHD,SI

tVALID,SO

tSTE,LEAD

1/fUCxCLK

tSTE,LAG

tSTE,DIS

tSTE,ACC

tHD,MO

tLO/HI tLO/HI

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Figure 13. SPI Slave Mode, CKPH = 0

Figure 14. SPI Slave Mode, CKPH = 1

SDA

SCL

tHD,DAT

tSU,DAT

tHD,STA

tHIGH

tLOW

tBUF

tHD,STA

tSU,STA

tSP

tSU,STO

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 15)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

Internal: SMCLK, ACLK

fUSCI USCI input clock frequency External: UCLK fSYSTEM MHz

Duty cycle = 50% ±10%

fSCL SCL clock frequency 2.2 V/3 V 0 400 kHz

fSCL ≤100 kHz 4.0

tHD,STA Hold time (repeated) START 2.2 V/3 V µs

fSCL >100 kHz 0.6

fSCL ≤100 kHz 4.7

tSU,STA Setup time for a repeated START 2.2 V/3 V µs

fSCL >100 kHz 0.6

tHD,DAT Data hold time 2.2 V/3 V 0 ns

tSU,DAT Data setup time 2.2 V/3 V 250 ns

fSCL ≤100 kHz 4.0

tSU,STO Setup time for STOP 2.2 V/3 V µs

fSCL >100 kHz 0.6

2.2 V 50 600

tSP Pulse width of spikes suppressed by input filter ns

3 V 50 600

Figure 15. I2C Mode Timing

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

10-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

AVCC and DVCC are connected together,

AVCC Analog supply voltage AVSS and DVSS are connected together, 1.8 3.6 V

V(AVSS) = V(DVSS) = 0 V

All ADC10_A pins: P1.0 to P1.5 and P3.6 and P3.7

V(Ax) Analog input voltage range(2) 0 AVCC V

terminals

Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0, 2.2 V 60 100

AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF µA

3 V 75 110

and reference buffer off = 00

Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1,

AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF 3 V 113 150 µA

on, reference buffer on = 01

IADC10_A Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,

AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF 3 V 105 140 µA

off, reference buffer on = 10, VEREF = 2.5 V

Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,

AVCC terminal, REF module SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF 3 V 70 110 µA

off, reference buffer off = 11, VEREF = 2.5 V

Only one terminal Ax can be selected at one time

CIInput capacitance from the pad to the ADC10_A capacitor array 2.2 V 3.5 pF

including wiring and pad.

AVCC >2.0V, 0 V ≤VAx ≤AVCC 36

RIInput MUX ON resistance kΩ

1.8V <AVCC <2.0V, 0 V ≤VAx ≤AVCC 96

(1) The leakage current is defined in the leakage current table with P6.x/Ax parameter.

(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR–for valid conversion results. The external

reference voltage requires decoupling capacitors. Two decoupling capacitors, 10 µF and 100 nF, should be connected to VeREF to

decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the

MSP430x5xx/MSP430x6xx Family User's Guide (SLAU208).

10-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

For specified performance of ADC10_A linearity

fADC10CLK 2.2 V/3 V 0.45 5 5.5 MHz

parameters

Internal ADC10_A

fADC10OSC ADC10DIV = 0, fADC10CLK = fADC10OSC 2.2 V/3 V 4.2 4.8 5.4 MHz

oscillator(1)

REFON = 0, Internal oscillator, 12 ADC10CLK

cycles, 10-bit mode 2.2 V/3 V 2.4 3.0

fADC10OSC = 4 MHz to 5 MHz

tCONVERT Conversion time µs

External fADC10CLK from ACLK, MCLK or SMCLK, (2)

ADC10SSEL ≠0

Turn on settling time of

tADC10ON See (3) 100 ns

the ADC RS= 1000 Ω, RI= 96 kΩ, CI= 3.5 pF(4) 1.8 V 3 µs

tSample Sampling time RS= 1000 Ω, RI= 36 kΩ, CI= 3.5 pF(4) 3 V 1 µs

(1) The ADC10OSC is sourced directly from MODOSC inside the UCS.

(2) 12 ×ADC10DIV ×1/fADC10CLK

(3) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already

settled.

(4) Approximately eight Tau (τ) are needed to get an error of less than ±0.5 LSB

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

10-Bit ADC, Linearity Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

1.4 V ≤(VeREF+ –VeREF–)min ≤1.6 V ±1.0

Integral

EI2.2 V/3 V LSB

linearity error 1.6 V <(VeREF+ –VeREF–)min ≤VAVCC ±1.0

Differential (VeREF+ –VeREF–)min ≤(VeREF+ –VeREF–),

ED2.2 V/3 V ±1.0 LSB

linearity error CVREF+ = 20 pF

(VeREF+ –VeREF–)min ≤(VeREF+ –VeREF–),

EOOffset error 2.2 V/3 V ±1.0 LSB

Internal impedance of source RS<100 Ω, CVREF+ = 20 pF

(VeREF+ –VeREF–)min ≤(VeREF+ –VeREF–),

EGGain error 2.2 V/3 V ±1.0 LSB

CVREF+ = 20 pF

Total unadjusted (VeREF+ –VREF–/VeREF–)min ≤(VeREF+ –VREF–/VeREF–),

ET2.2 V/3 V ±1.0 ±2.0 LSB

error CVREF+ = 20 pF

REF, External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

Positive external

VeREF+ VeREF+ >VeREF–(2) 1.4 AVCC V

reference voltage input

Negative external

VeREF–VeREF+ >VeREF–(3) 0 1.2 V

reference voltage input

(VeREF+ –Differential external VeREF+ >VeREF–(4) 1.4 AVCC V

VeREF–) reference voltage input 1.4 V ≤VeREF+ ≤VAVCC , VeREF–= 0 V,

fADC10CLK = 5 MHz, ADC10SHTx = 0x0001, 2.2 V/3 V ±8.5 ±26 µA

Conversion rate 200 ksps

IVeREF+ Static input current

IVeREF–1.4 V ≤VeREF+ ≤VAVCC , VeREF–= 0 V,

fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000, 2.2 V/3 V ±1µA

Conversion rate 20 ksps

Capacitance at VeREF+/-

CVREF+/- (5) 10 µF

terminal

(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also

the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VeREF to decouple the dynamic current required for an external

reference source if it is used for the ADC10_A. Also see the MSP430x5xx/MSP430x6xx Family User's Guide (SLAU208).

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

REF, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

REFVSEL = {2} for 2.5 V 3 V 2.51 ±1.5%

REFON = 1

Positive built-in reference REFVSEL = {1} for 2.0 V

VREF+ 3 V 1.99 ±1.5% V

voltage REFON = 1

REFVSEL = {0} for 1.5 V 2.2 V/ 3 V 1.5 ±1.5%

REFON = 1

REFVSEL = {0} for 1.5 V 2.2

AVCC minimum voltage,

AVCC(min) Positive built-in reference REFVSEL = {1} for 2.0 V 2.2 V

active REFVSEL = {2} for 2.5 V 2.7

fADC10CLK = 5.0 MHz

REFON = 1, REFBURST = 0, REFVSEL = 3 V 18 24 µA

{2} for 2.5 V

fADC10CLK = 5.0 MHz

Operating supply current

IREF+ REFON = 1, REFBURST = 0, REFVSEL = 3 V 15.5 21 µA

into AVCC terminal(2) {1} for 2.0 V

fADC10CLK = 5.0 MHz

REFON = 1, REFBURST = 0, REFVSEL = 3 V 13.5 21 µA

{0} for 1.5 V

Temperature coefficient of IVREF+ = 0 A ppm/

TCREF+ 30 50

built-in reference(3) REFVSEL = (0, 1, 2}, REFON = 1 °C

2.2 V 20 22

Operating supply current REFON = 0, INCH = 0Ah,

ISENSOR µA

into AVCC terminal(4) ADC10ON = N A, TA= 30°C3 V 20 22

2.2 V 770

ADC10ON = 1, INCH = 0Ah,

VSENSOR See (5) mV

TA= 30°C3 V 770

2.2 V 1.06 1.1 1.14

ADC10ON = 1, INCH = 0Bh,

VMID AVCC divider at channel 11 V

VMID is ~0.5 ×VAVCC 3 V 1.46 1.5 1.54

Sample time required if ADC10ON = 1, INCH = 0Ah,

tSENSOR(sample) 30 µs

channel 10 is selected(6) Error of conversion result ≤1 LSB

Sample time required if ADC10ON = 1, INCH = 0Bh,

tVMID(sample) 1µs

channel 11 is selected(7) Error of conversion result ≤1 LSB

AVCC = AVCC (min) - AVCC(max)

Power supply rejection ratio

PSRR_DC TA= 25 °C 120 µV/V

(dc) REFVSEL = (0, 1, 2}, REFON = 1

AVCC = AVCC (min) - AVCC(max)

Power supply rejection ratio TA= 25 °C

PSRR_AC 6.4 mV/V

(ac) f = 1 kHz, ΔVpp = 100 mV

REFVSEL = (0, 1, 2}, REFON = 1

Settling time of reference AVCC = AVCC (min) - AVCC(max)

tSETTLE 75 µs

voltage(8) REFVSEL = (0, 1, 2}, REFON = 0 →1

(1) The leakage current is defined in the leakage current table with P6.x/Ax parameter.

(2) The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a

conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.

(3) Calculated using the box method: (MAX(-40 to 85°C) –MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C–(–40°C)).

(4) The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is

high). When REFON = 1, ISENSOR is already included in IREF+.

(5) The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended in order to minimize the offset error

of the built-in temperature sensor.

(6) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).

(7) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.

(8) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Comparator B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

VCC Supply voltage 1.8 3.6 V

1.8 V 40

Comparator operating CBPWRMD = 00, CBON = 1, CBRSx = 00 2.2 V 30 50

supply current into AVCC.

IAVCC_COMP 3 V 40 65 µA

Excludes reference CBPWRMD = 01, CBON = 1, CBRSx = 00 2.2/3 V 10 17

resistor ladder. CBPWRMD = 10, CBON = 1, CBRSx = 00 2.2/3 V 0.1 0.5

CBREFACC = 0, CBREFLx = 01,

Quiescent current of 2.2/3 V 10 17 µA

CBRSx = 10, REFON = 0, CBON = 0

resistor ladder into AVCC.

IAVCC_REF Including REF module CBREFACC = 1, CBREFLx = 01, 2.2/3 V 22 µA

current. CBRSx = 10, REFON = 0, CBON = 0

Common mode input

VIC 0 VCC-1 V

range CBPWRMD = 00 ±20 mV

VOFFSET Input offset voltage CBPWRMD = 01, 10 ±10 mV

CIN Input capacitance 5 pF

ON - switch closed 3 4 kΩ

RSIN Series input resistance OFF - switch opened 50 MΩ

CBPWRMD = 00, CBF = 0 450 ns

Propagation delay,

tPD CBPWRMD = 01, CBF = 0 600 ns

response time CBPWRMD = 10, CBF = 0 50 µs

CBPWRMD = 00, CBON = 1, CBF = 1, 0.35 0.6 1.0 µs

CBFDLY = 00

CBPWRMD = 00, CBON = 1, CBF = 1, 0.6 1.0 1.8 µs

CBFDLY = 01

Propagation delay with

tPD,filter filter active CBPWRMD = 00, CBON = 1, CBF = 1, 1.0 1.8 3.4 µs

CBFDLY = 10

CBPWRMD = 00, CBON = 1, CBF = 1, 1.8 3.4 6.5 µs

CBFDLY = 11

CBON = 0 to CBON = 1 1 2 µs

CBPWRMD = 00, 01

tEN_CMP Comparator enable time CBON = 0 to CBON = 1 1.5 µs

CBPWRMD = 10

Resistor reference enable

tEN_REF CBON = 0 to CBON = 1 1 1.5 µs

time VIN ×VIN ×VIN ×

Reference voltage for a VIN = reference into resistor ladder.

VCB_REF (n+0.5) (n+1) (n+1.5) V

given tap n = 0 to 31 /32 /32 /32

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Ports PU.0 and PU.1

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

VUSB = 3.3 V ±10%, IOH = -25 mA.

VOH High-level output voltage Refer to Figure 17 for typical 2.4 V

characteristics.

VUSB = 3.3 V ±10%, IOL = 25 mA.

VOL Low-level output voltage Refer to Figure 16 for typical 0.4 V

characteristics.

VUSB = 3.3 V ±10%

VIH High-level input voltage Refer to Figure 18 for typical 2.0 V

characteristics.

VUSB = 3.3 V ±10%

VIL Low-level input voltage Refer to Figure 18 for typical 0.8 V

characteristics.

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2

VOL - Low-Level Output Voltage - V

IOL - Typical Low-Level Output Current - mA

V = 3.0 V

T = 85 ºC

V = 1.8 V

T = 85 ºC

V = 1.8 V

T = 25 ºC

V = 3.0 V

T = 25 ºC

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.5 1 1.5 2 2.5 3

VOH - High-Level Output Voltage - V

IOH - Typical High-Level Output Current - mA

V = 1.8 V

T = 85 ºC

V = 1.8 V

T = 25 ºC

V = 3.0 V

T = 85 ºC

V = 3.0 V

T = 25 ºC

TYPICAL PU.0, PU.1 INPUT THRESHOLD

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

1.8 2.2 2.6 3 3.4

VUSB Supply Voltage, VUSB - V

Input Threshold - V

VIT+, postive-going input threshold

VIT-, negative-going input threshold

TA= 25 °C, 85 °C

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Figure 16. Ports PU.0, PU.1 Typical Low-Level Output Characteristics

Figure 17. Ports PU.0, PU.1 Typical High-Level Output Characteristics

Figure 18. Ports PU.0, PU.1 Typical Input Threshold Characteristics

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

USB-Output Ports DP and DM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

VOH D+, D- single ended USB 2.0 load conditions 2.8 3.6 V

VOL D+, D- single ended USB 2.0 load conditions 0 0.3 V

Z(DRV) D+, D- impedance Including external series resistor of 27 Ω28 44 Ω

Full speed, differential, CL= 50 pF,

tRISE Rise time 4 20 ns

10%/90%, Rpu on D+

Full speed, differential, CL= 50 pF,

tFALL Fall time 4 20 ns

10%/90%, Rpu on D+

USB-Input Ports DP and DM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

V(CM) Differential input common mode range 0.8 2.5 V

Z(IN) Input impedance 300 kΩ

VCRS Crossover voltage 1.3 2.0 V

VIL Static SE input logic low level 0.8 V

VIH Static SE input logic high level 2.0 V

VDI Differential input voltage 0.2 V

USB-PWR (USB Power System)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

VLAUNCH VBUS detection threshold 3.75 V

VBUS USB bus voltage Normal operation 3.76 5.5 V

VUSB USB LDO output voltage 3.3 ±9% V

V18 Internal USB voltage(1) 1.8 V

Maximum external current from VUSB

IUSB_EXT USB LDO is on 12 mA

terminal(2)

IDET USB LDO current overload detection(3) 60 100 mA

Operating supply current into VBUS USB LDO on,

ISUSPEND 250 µA

terminal.(4) USB PLL disabled

USB LDO on,

Operating supply current into VBUS terminal. USB 1.8-V LDO disabled,

IUSB_LDO Represents the current of the 3.3 V LDO 1.8 V/3 V 60 µA

VBUS = 5 V,

only. USBDETEN = 0 or 1

USB LDO disabled,

Operating supply current into VBUS terminal. USB 1.8-V LDO disabled,

IVBUS_DETECT Represents the current of the VBUS 1.8 V/3 V 30 µA

VBUS >VLAUNCH,

detection logic. USBDETEN = 1

CBUS VBUS terminal recommended capacitance 4.7 µF

CUSB VUSB terminal recommended capacitance 220 nF

C18 V18 terminal recommended capacitance 220 nF

Within 2%, recommended

tENABLE Settling time VUSB and V18 2 ms

capacitances

RPUR Pullup resistance of PUR terminal(5) 70 110 150 Ω

(1) This voltage is for internal usages only. No external DC loading should be applied.

(2) This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB

operation.

(3) A current overload will be detected when the total current supplied from the USB LDO, including IUSB_EXT, exceeds this value.

(4) Does not include current contribution of Rpu and Rpd as outlined in the USB specification.

(5) This value, in series with an external resistor between PUR and D+, produces the Rpu as outlined in the USB specification.

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

USB-PLL (USB Phase Locked Loop)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

IPLL Operating supply current 7 mA

fPLL PLL frequency 48 MHz

fUPD PLL reference frequency 1.5 3 MHz

tLOCK PLL lock time 2 ms

tJitter PLL jitter 1000 ps

Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

PARAMETER MIN TYP MAX UNIT

CONDITIONS

DVCC(PGM/ERASE) Program and erase supply voltage 1.8 3.6 V

tREADMARGIN Read access time during margin mode 200 ns

IPGM Supply current from DVCC during program 3 5 mA

IERASE Supply current from DVCC during erase 2 6.5 mA

IMERASE, IBANK Supply current from DVCC during mass erase or bank erase 2.5 mA

tCPT Cumulative program time See (1) 16 ms

Program/erase endurance 104105cycles

tRetention Data retention duration TJ= 25°C 100 years

tWord Word or byte program time See (2) 64 85 µs

tBlock, 0 Block program time for first byte or word See (2) 49 65 µs

Block program time for each additional byte or word, except for last

tBlock, 1–(N–1) See (2) 37 49 µs

byte or word

tBlock, N Block program time for last byte or word See (2) 55 73 µs

Erase time for segment, mass erase, and bank erase when

tErase See (2) 23 32 ms

available.

(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

(2) These values are hardwired into the flash controller's state machine.

JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

PARAMETER MIN TYP MAX UNIT

CONDITIONS

fSBW Spy-Bi-Wire input frequency 2.2 V/3 V 0 20 MHz

tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V/3 V 0.025 15 µs

Spy-Bi-Wire enable time (TEST high to acceptance of first clock

tSBW, En 2.2 V/3 V 1 µs

edge)(1)

tSBW,Rst Spy-Bi-Wire return to normal operation time 15 100 µs

2.2 V 0 5 MHz

fTCK TCK input frequency - 4-wire JTAG(2) 3 V 0 10 MHz

Rinternal Internal pulldown resistance on TEST 2.2 V/3 V 45 60 80 kΩ

(1) Tools accessing the Spy-Bi-Wire interface need to wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the

first SBWTCK clock edge.

(2) fTCK may be restricted to meet the timing requirements of the module selected.

P1.0/TA0CLK/ACLK

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/TA0.3

P1.5/TA0.4

P1.6/TA1CLK/CBOUT

P1.7/TA1.0

Direction

0:Input

1:Output

P1SEL.x

P1DIR.x

P1IN.x

P1IRQ.x

Tomodule

Frommodule

P1OUT.x

Interrupt

Edge

Select

Set

P1SEL.x

P1IES.x

P1IFG.x

P1IE.x

DVSS

DVCC

P1REN.x PadLogic

P1DS.x

0:Lowdrive

1:Highdrive

Frommodule

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

INPUT/OUTPUT SCHEMATICS

Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Table 48. Port P1 (P1.0 to P1.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x

P1.0/TA0CLK/ACLK 0 P1.0 (I/O) I: 0; O: 1 0

TA0CLK 0 1

ACLK 1 1

P1.1/TA0.0 1 P1.1 (I/O) I: 0; O: 1 0

TA0.CCI0A 0 1

TA0.0 1 1

P1.2/TA0.1 2 P1.2 (I/O) I: 0; O: 1 0

TA0.CCI1A 0 1

TA0.1 1 1

P1.3/TA0.2 3 P1.3 (I/O) I: 0; O: 1 0

TA0.CCI2A 0 1

TA0.2 1 1

P1.4/TA0.3 4 P1.4 (I/O) I: 0; O: 1 0

TA0.CCI3A 0 1

TA0.3 1 1

P1.5/TA0.4 5 P1.5 (I/O) I: 0; O: 1 0

TA0.CCI4A 0 1

TA0.4 1 1

P1.6/TA1CLK/CBOUT 6 P1.6 (I/O) I: 0; O: 1 0

TA1CLK 0 1

CBOUT comparator B 1 1

P1.7/TA1.0 7 P1.7 (I/O) I: 0; O: 1 0

TA1.CCI0A 0 1

TA1.0 1 1

P2.0/TA1.1

P2.1/TA1.2

P2.2/TA2CLK/SMCLK

P2.3/TA2.0

P2.4/TA2.1

P2.5/TA2.2

P2.6/RTCCLK/DMAE0

P2.7/UB0STE/UCA0CLK

Direction

0:Input

1:Output

P2SEL.x

P2DIR.x

P2IN.x

Tomodule

Frommodule

P2OUT.x

Interrupt

Edge

Select

Set

P2SEL.x

P2IES.x

P2IFG.x

P2IE.x

DVSS

DVCC

P2REN.x PadLogic

P2DS.x

0:Lowdrive

1:Highdrive

Frommodule

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Table 49. Port P2 (P2.0 to P2.7) Pin Functions

CONTROL BITS/SIGNALS(1)

PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL.x

P2.0/TA1.1 0 P2.0 (I/O) I: 0; O: 1 0

TA1.CCI1A 0 1

TA1.1 1 1

P2.1/TA1.2 1 P2.1 (I/O) I: 0; O: 1 0

TA1.CCI2A 0 1

TA1.2 1 1

P2.2/TA2CLK/SMCLK 2 P2.2 (I/O) I: 0; O: 1 0

TA2CLK 0 1

SMCLK 1 1

P2.3/TA2.0 3 P2.3 (I/O) I: 0; O: 1 0

TA2.CCI0A 0 1

TA2.0 1 1

P2.4/TA2.1 4 P2.4 (I/O) I: 0; O: 1 0

TA2.CCI1A 0 1

TA2.1 1 1

P2.5/TA2.2 5 P2.5 (I/O) I: 0; O: 1 0

TA2.CCI2A 0 1

TA2.2 1 1

P2.6/RTCCLK/DMAE0 6 P2.6 (I/O) I: 0; O: 1 0

DMAE0 0 1

RTCCLK 1 1

P2.7/UCB0STE/UCA0CLK 7 P2.7 (I/O) I: 0; O: 1 0

UCB0STE/UCA0CLK(2) (3) X 1

(1) X = Don't care

(2) The pin direction is controlled by the USCI module.

(3) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI A0/B0 is forced

to 3-wire SPI mode if 4-wire SPI mode is selected.

P3.0/UCB0SIMO/UCB0SDA

P3.1/UCB0SOMI/UCB0SCL

P3.2/UCB0CLK/UCA0STE

P3.3/UCA0TXD/UCA0SIMO

P3.4/UCA0RXD/UCA0SOMI

Direction

0:Input

1:Output

P3SEL.x

P3DIR.x

P3IN.x

Tomodule

Frommodule

P3OUT.x

DVSS

DVCC

P3REN.x PadLogic

P3DS.x

0:Lowdrive

1:Highdrive

Frommodule

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Port P3, P3.0 to P3.4, Input/Output With Schmitt Trigger

Table 50. Port P3 (P3.0 to P3.7) Pin Functions

CONTROL BITS/SIGNALS(1)

PIN NAME (P3.x) x FUNCTION P3DIR.x P3SEL.x

P3.0/UCB0SIMO/UCB0SDA 0 P3.0 (I/O) I: 0; O: 1 0

UCB0SIMO/UCB0SDA(2) (3) X 1

P3.1/UCB0SOMI/UCB0SCL 1 P3.1 (I/O) I: 0; O: 1 0

UCB0SOMI/UCB0SCL(2) (3) X 1

P3.2/UCB0CLK/UCA0STE 2 P3.2 (I/O) I: 0; O: 1 0

UCB0CLK/UCA0STE(2) (4) X 1

P3.3/UCA0TXD/UCA0SIMO 3 P3.3 (I/O) I: 0; O: 1 0

UCA0TXD/UCA0SIMO(2) X 1

P3.4/UCA0RXD/UCA0SOMI 4 P3.4 (I/O) I: 0; O: 1 0

UCA0RXD/UCA0SOMI(2) X 1

(1) X = Don't care

(2) The pin direction is controlled by the USCI module.

(3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.

(4) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI A0/B0 is forced

to 3-wire SPI mode if 4-wire SPI mode is selected.

P4.0/P4MAP0

P4.1/P4MAP1

P4.2/P4MAP2

P4.3/P4MAP3

P4.4/P4MAP4

P4.5/P4MAP5

P4.6/P4MAP6

P4.7/P4MAP7

Direction

0:Input

1:Output

P4SEL.x

P4DIR.x

P4IN.x

toPortMappingControl

fromPortMappingControl

P4OUT.x

DVSS

DVCC

P4REN.x PadLogic

P4DS.x

0:Lowdrive

1:Highdrive

fromPortMappingControl

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger

Table 51. Port P4 (P4.0 to P4.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P4.x) x FUNCTION P4DIR.x(1) P4SEL.x P4MAPx

P4.0/P4MAP0 0 P4.0 (I/O) I: 0; O: 1 0 X

Mapped secondary digital function X 1 ≤30

P4.1/P4MAP1 1 P4.1 (I/O) I: 0; O: 1 0 X

Mapped secondary digital function X 1 ≤30

P4.2/P4MAP2 2 P4.2 (I/O) I: 0; O: 1 0 X

Mapped secondary digital function X 1 ≤30

P4.3/P4MAP3 3 P4.3 (I/O) I: 0; O: 1 0 X

Mapped secondary digital function X 1 ≤30

P4.4/P4MAP4 4 P4.4 (I/O) I: 0; O: 1 0 X

Mapped secondary digital function X 1 ≤30

P4.5/P4MAP5 5 P4.5 (I/O) I: 0; O: 1 0 X

Mapped secondary digital function X 1 ≤30

P4.6/P4MAP6 6 P4.6 (I/O) I: 0; O: 1 0 X

Mapped secondary digital function X 1 ≤30

P4.7/P4MAP7 7 P4.7 (I/O) I: 0; O: 1 0 X

Mapped secondary digital function X 1 ≤30

(1) The direction of some mapped secondary functions are controlled directly by the module. See Table 10 for specific direction control

information of mapped secondary functions.

P5.0/(A8/VeREF+)

P5.1/(A9/VeREF–)

P5SEL.x

P5DIR.x

P5IN.x

Tomodule

Frommodule

P5OUT.x

DVSS

DVCC

P5REN.x

PadLogic

P5DS.x

0:Lowdrive

1:Highdrive

Bus

Keeper

to/fromReference

to ADC10

INCHx=x

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger

Table 52. Port P5 (P5.0 and P5.1) Pin Functions

CONTROL BITS/SIGNALS(1)

PIN NAME (P5.x) x FUNCTION P5DIR.x P5SEL.x

P5.0/A8/VeREF+(2) 0 P5.0 (I/O)(3) I: 0; O: 1 0

A8/VeREF+(4) X 1

P5.1/A9/VeREF–(5) 1 P5.1 (I/O)(3) I: 0; O: 1 0

A9/VeREF–(6) X 1

(1) X = Don't care

(2) VeREF+ available on devices with ADC10_A.

(3) Default condition

(4) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC10_A when available.

(5) VeREF- available on devices with ADC10_A.

(6) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC10_A when available.

P5.2/XT2IN

P5SEL.2

P5DIR.2

P5IN.2

ModuleXIN

ModuleXOUT

P5OUT.2

DVSS

DVCC

P5REN.2

PadLogic

P5DS.2

0:Lowdrive

1:Highdrive

Bus

Keeper

ToXT2

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Port P5, P5.2, Input/Output With Schmitt Trigger

P5.3/XT2OUT

P5SEL.3

P5DIR.3

P5IN.3

ModuleXIN

ModuleXOUT

P5OUT.3

DVSS

DVCC

P5REN.3

PadLogic

P5DS.3

0:Lowdrive

1:Highdrive

Bus

Keeper

ToXT2

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Port P5, P5.3, Input/Output With Schmitt Trigger

Table 53. Port P5 (P5.2, P5.3) Pin Functions

CONTROL BITS/SIGNALS(1)

PIN NAME (P5.x) x FUNCTION P5DIR.x P5SEL.2 P5SEL.3 XT2BYPASS

P5.2/XT2IN 2 P5.2 (I/O) I: 0; O: 1 0 X X

XT2IN crystal mode(2) X 1 X 0

XT2IN bypass mode(2) X 1 X 1

P5.3/XT2OUT 3 P5.3 (I/O) I: 0; O: 1 0 X X

XT2OUT crystal mode(3) X 1 X 0

P5.3 (I/O)(3) X 1 X 1

(1) X = Don't care

(2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal

mode or bypass mode.

(3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as

general-purpose I/O.

P5.4/XIN

P5SEL.4

P5DIR.4

P5IN.4

ModuleXIN

ModuleXOUT

P5OUT.4

DVSS

DVCC

P5REN.4

PadLogic

P5DS.4

0:Lowdrive

1:Highdrive

Bus

Keeper

toXT1

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger

P5.5/XOUT

P5SEL.5

P5DIR.5

P5IN.5

ModuleXIN

ModuleXOUT

P5OUT.5

DVSS

DVCC

P5REN.5

PadLogic

P5DS.5

0:Lowdrive

1:Highdrive

Bus

Keeper

toXT1

XT1BYPASS

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

P6.0/CB0/(A0)

P6.1/CB1/(A1)

P6.2/CB2/(A2)

P6.3/CB3/(A3)

P6.4/CB4/(A4)

P6.5/CB5/(A5)

P6.6/CB6/(A6)

P6.7/CB7/(A7)

P6SEL.x

P6DIR.x

P6IN.x

Tomodule

Frommodule

P6OUT.x

DVSS

DVCC 1

P6DS.x

0:Lowdrive

1:Highdrive

toComparator_B

fromComparator_B

PadLogic

to ADC10

INCHx=x

Bus

Keeper

Direction

0:Input

1:Output

CBPD.x

P6REN.x

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Table 54. Port P5 (P5.4 and P5.5) Pin Functions

CONTROL BITS/SIGNALS(1)

PIN NAME (P7.x) x FUNCTION P5DIR.x P5SEL.4 P5SEL.5 XT1BYPASS

P5.4/XIN 4 P5.4 (I/O) I: 0; O: 1 0 X X

XIN crystal mode(2) X 1 X 0

XIN bypass mode(2) X 1 X 1

P5.5/XOUT 5 P5.5 (I/O) I: 0; O: 1 0 X X

XOUT crystal mode(3) X 1 X 0

P5.5 (I/O)(3) X 1 X 1

(1) X = Don't care

(2) Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal

mode or bypass mode.

(3) Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as

general-purpose I/O.

Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Table 55. Port P6 (P6.0 to P6.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P6.x) x FUNCTION P6DIR.x P6SEL.x CBPD

P6.0/CB0/(A0) 0 P6.0 (I/O) I: 0; O: 1 0 0

A0 (only on devices with ADC) X 1 X

CB0(1) X X 1

P6.1/CB1/(A1) 1 P6.1 (I/O) I: 0; O: 1 0 0

A1 (only on devices with ADC) X 1 X

CB1(1) X X 1

P6.2/CB2/(A2) 2 P6.2 (I/O) I: 0; O: 1 0 0

A2 (only on devices with ADC) X 1 X

CB2(1) X X 1

P6.3/CB3/(A3) 3 P6.3 (I/O) I: 0; O: 1 0 0

A3 (only on devices with ADC) X 1 X

CB3(1) X X 1

P6.4/CB4/(A4) 4 P6.4 (I/O) I: 0; O: 1 0 0

A4 (only on devices with ADC) X 1 X

CB4(2) X X 1

P6.5/CB5/(A5) 5 P6.5 (I/O) I: 0; O: 1 0 0

A5 (only on devices with ADC) X 1 X

CB5(2) X X 1

P6.6/CB6/(A6) 6 P6.6 (I/O) I: 0; O: 1 0 0

A6 (only on devices with ADC) X 1 X

CB6(2) X X 1

P6.7/CB7/(A7) 7 P6.7 (I/O) I: 0; O: 1 0 0

A7 (only on devices with ADC) X 1 X

CB7(2) X X 1

(1) Setting the CBPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input

buffer for that pin, regardless of the state of the associated CBPD.x bit.

(2) Setting the CBPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input

buffer for that pin, regardless of the state of the associated CBPD.x bit.

PUOPE 0

PUOUT0

PUSEL

Pad Logic

PU.0/

VUSB VSSU

PU.1/

PUOUT1

PUIN1

USB DM input

PUIN0

USB DP input

USB DM output

USB DP output

USB output enable

PUSEL

Pad Logic

PUR

VUSB VSSU

“1”

PUREN

PURIN

PUIPE

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Port PU.0/DP, PU.1/DM, PUR USB Ports

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Table 56. Port PU.0/DP, PU.1/DM Output Functions(1)

CONTROL BITS PIN NAME

PUSEL PUOPE PUOUT1 PUOUT0 PU.1/DM PU.0/DP

0 0 X X Output disabled Output disabled

0 1 0 0 Output low Output low

0 1 0 1 Output low Output high

0 1 1 0 Output high Output low

0 1 1 1 Output high Output high

1 X X X DM(2) DP(2)

(1) PU.1/DM and PU.0/DP inputs and outputs are supplied from VUSB. VUSB can be generated by the device using the integrated 3.3-V

LDO when enabled. VUSB can also be supplied externally when the 3.3-V LDO is not being used and is disabled.

(2) Output state set by the USB module.

Table 57. Port PU.0/DP, PU.1/DM Input Functions(1)

CONTROL BITS PIN NAME

PUSEL PUIPE PU.1/DM PU.0/DP

0 0 Input disabled Input disabled

0 1 Input enabled Input enabled

1 X DM input DP input

(1) PU.1/DM and PU.0/DP inputs and outputs are supplied from VUSB. VUSB can be generated by the

device using the integrated 3.3-V LDO when enabled. VUSB can also be supplied externally when the

3.3-V LDO is not being used and is disabled.

Table 58. Port PUR Input Functions

CONTROL BITS FUNCTION

PUSEL PUREN

Input disabled

0 0 Pull up disabled

Input disabled

0 1 Pull up enabled

Input enabled

1 0 Pull up disabled

Input enabled

1 1 Pull up enabled

PJ.0/TDO

FromJTAG

PJDIR.0

PJIN.0

FromJTAG

PJOUT.0

DVSS

DVCC

PJREN.0 PadLogic

PJDS.0

0:Lowdrive

1:Highdrive

DVCC

PJ.1/TDI/TCLK

PJ.2/TMS

PJ.3/TCK

FromJTAG

PJDIR.x

PJIN.x

FromJTAG

PJOUT.x

DVSS

DVCC

PJREN.x PadLogic

PJDS.x

0:Lowdrive

1:Highdrive

DVSS

ToJTAG

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output

Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Table 59. Port PJ (PJ.0 to PJ.3) Pin Functions

CONTROL BITS/

SIGNALS(1)

PIN NAME (PJ.x) x FUNCTION PJDIR.x

PJ.0/TDO 0 PJ.0 (I/O)(2) I: 0; O: 1

TDO(3) X

PJ.1/TDI/TCLK 1 PJ.1 (I/O)(2) I: 0; O: 1

TDI/TCLK(3) (4) X

PJ.2/TMS 2 PJ.2 (I/O)(2) I: 0; O: 1

TMS(3) (4) X

PJ.3/TCK 3 PJ.3 (I/O)(2) I: 0; O: 1

TCK(3) (4) X

(1) X = Don't care

(2) Default condition

(3) The pin direction is controlled by the JTAG module.

(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

DEVICE DESCRIPTORS

Table 60 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type.

Table 60. 'F5504 to 'F5510 Device Descriptor Table (1)

'F5510 'F5510 'F5509 'F5509 'F5508 'F5508 'F5507 'F5506 'F5505 'F5504

SIZE RGC RGZ RGC RGZ RGC RGZ

DESCRIPTION ADDRESS (bytes) VALUE VALUE VALUE VALUE VALUE VALUE VALUE VALUE VALUE VALUE

Info Block Info length 01A00h 1 06h 06h 06h 06h 06h 06h 06h 06h 06h 06h

CRC length 01A01h 1 06h 06h 06h 06h 06h 06h 06h 06h 06h 06h

CRC value 01A02h 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

Device ID 01A04h 1 31h 31h 3Ah 3Ah 39h 39h 38h 37h 36h 35h

Device ID 01A05h 1 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h

Hardware revision 01A06h 1 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

Firmware revision 01A07h 1 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

Die Record Die Record Tag 01A08h 1 08h 08h 08h 08h 08h 08h 08h 08h 08h 08h

Die Record length 01A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah

Lot/Wafer ID 01A0Ah 4 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

Die X position 01A0Eh 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

Die Y position 01A10h 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

Test results 01A12h 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

ADC10 ADC10 Calibration 01A14h 1 13h 13h 13h 13h 13h 13h 13h 13h 13h 13h

Calibration Tag

ADC10 Calibration 01A15h 1 10h 10h 10h 10h 10h 10h 10h 10h 10h 10h

length

ADC Gain Factor 01A16h 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

ADC Offset 01A18h 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

ADC 1.5-V Reference 01A1Ah 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

Temp. Sensor 30°C

ADC 1.5-V Reference 01A1Ch 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

Temp. Sensor 85°C

ADC 2.0-V Reference 01A1Eh 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

Temp. Sensor 30°C

ADC 2.0-V Reference 01A20h 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

Temp. Sensor 85°C

ADC 2.5-V Reference 01A22h 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

Temp. Sensor 30°C

ADC 2.5-V Reference 01A24h 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

Temp. Sensor 85°C

REF REF Calibration Tag 01A26h 1 12h 12h 12h 12h 12h 12h 12h 12h 12h 12h

Calibration

REF Calibration length 01A27h 1 06h 06h 06h 06h 06h 06h 06h 06h 06h 06h

REF 1.5-V Reference 01A28h 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

Factor

REF 2.0-V Reference 01A2Ah 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

Factor

REF 2.5-V Reference 01A2Ch 2 per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit

Factor

Peripheral Peripheral Descriptor 01A2Eh 1 02h 02h 02h 02h 02h 02h 02h 02h 02h 02h

Descriptor Tag

Peripheral Descriptor 01A2Fh 1 61h 61h 62h 62h 61h 61h 5Dh 5Eh 5Dh 5Dh

Length

08h 08h 08h 08h 08h 08h 08h 08h 08h 08h

Memory 1 2 8Ah 8Ah 8Ah 8Ah 8Ah 8Ah 8Ah 8Ah 8Ah 8Ah

0Ch 0Ch 0Ch 0Ch 0Ch 0Ch 0Ch 0Ch 0Ch 0Ch

Memory 2 2 86h 86h 86h 86h 86h 86h 86h 86h 86h 86h

0Eh 0Eh 0Eh 00Eh 0Eh 0Eh 0Eh 0Eh 0Eh 0Eh

Memory 3 2 2Ah 2Ah 2Ah 2Ah 2Ah 2Ah 2Ah 2Ah 2Ah 2Ah

(1) N/A = Not applicable

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Table 60. 'F5504 to 'F5510 Device Descriptor Table (1) (continued)

'F5510 'F5510 'F5509 'F5509 'F5508 'F5508 'F5507 'F5506 'F5505 'F5504

SIZE RGC RGZ RGC RGZ RGC RGZ

DESCRIPTION ADDRESS (bytes) VALUE VALUE VALUE VALUE VALUE VALUE VALUE VALUE VALUE VALUE

12h 12h 12h 12h 12h 12h 12h 12h 12h 12h

Memory 4 2 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch 2Ch

40h 40h 50h 50h 60h 60h 40h 50h 60h 70h

Memory 5 2 92h 92h 91h 91h 90h 90h 92h 91h 90h 8Eh

Memory 6 N/A N/A 8Eh 8Eh N/A N/A N/A 8Eh N/A N/A

delimiter 1 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

Peripheral count 1 20h 20h 20h 20h 20h 20h 1Eh 1Eh 1Eh 1Eh

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

MSP430CPUXV2 2 23h 23h 23h 23h 23h 23h 23h 23h 23h 23h

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

JTAG 2 09h 09h 09h 09h 09h 09h 09h 09h 09h 09h

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

SBW 2 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

EEM-S 2 03h 03h 03h 03h 03h 03h 03h 03h 03h 03h

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

TI BSL 2 FCh FCh FCh FCh FCh FCh FCh FCh FCh FCh

10h 10h 10h 10h 10h 10h 10h 10h 10h 10h

SFR 2 41h 41h 41h 41h 41h 41h 41h 41h 41h 41h

02h 02h 02h 02h 02h 02h 02h 02h 02h 02h

PMM 2 30h 30h 30h 30h 30h 30h 30h 30h 30h 30h

02h 02h 02h 02h 02h 02h 02h 02h 02h 02h

FCTL 2 38h 38h 38h 38h 38h 38h 38h 38h 38h 38h

01h 01h 01h 01h 01h 01h 01h 01h 01h 01h

CRC16 2 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

CRC16_RB 2 3Dh 3Dh 3Dh 3Dh 3Dh 3Dh 3Dh 3Dh 3Dh 3Dh

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

RAMCTL 2 44h 44h 44h 44h 44h 44h 44h 44h 44h 44h

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

WDT_A 2 40h 40h 40h 40h 40h 40h 40h 40h 40h 40h

01h 01h 01h 01h 01h 01h 01h 01h 01h 01h

UCS 2 48h 48h 48h 48h 48h 48h 48h 48h 48h 48h

02h 02h 02h 02h 02h 02h 02h 02h 02h 02h

SYS 2 42h 42h 42h 42h 42h 42h 42h 42h 42h 42h

03h 03h 03h 03h 03h 03h 03h 03h 03h 03h

REF 2 A0h A0h A0h A0h A0h A0h A0h A0h A0h A0h

01h 01h 01h 01h 01h 01h 01h 01h 01h 01h

Port Mapping 2 10h 10h 10h 10h 10h 10h 10h 10h 10h 10h

04h 04h 04h 04h 04h 04h 04h 04h 04h 04h

Port 1/2 2 51h 51h 51h 51h 51h 51h 51h 51h 51h 51h

02h 02h 02h 02h 02h 02h 02h 02h 02h 02h

Port 3/4 2 52h 52h 52h 52h 52h 52h 52h 52h 52h 52h

02h 02h 02h 02h 02h 02h 02h 02h 02h 02h

Port 5/6 2 53h 53h 53h 53h 53h 53h 53h 53h 53h 53h

0Eh 0Eh 0Eh 0Eh 0Eh 0Eh 0Eh 0Eh 0Eh 0Eh

JTAG 2 5Fh 5Fh 5Fh 5Fh 5Fh 5Fh 5Fh 5Fh 5Fh 5Fh

02h 02h 02h 02h 02h 02h 02h 02h 02h 02h

TA0 2 62h 62h 62h 62h 62h 62h 62h 62h 62h 62h

04h 04h 04h 04h 04h 04h 04h 04h 04h 04h

TA1 2 61h 61h 61h 61h 61h 61h 61h 61h 61h 61h

04h 04h 04h 04h 04h 04h 04h 04h 04h 04h

TB0 2 67h 67h 67h 67h 67h 67h 67h 67h 67h 67h

04h 04h 04h 04h 04h 04h 04h 04h 04h 04h

TA2 2 61h 61h 61h 61h 61h 61h 61h 61h 61h 61h

0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah

RTC 2 68h 68h 68h 68h 68h 68h 68h 68h 68h 68h

02h 02h 02h 02h 02h 02h 02h 02h 02h 02h

MPY32 2 85h 85h 85h 85h 85h 85h 85h 85h 85h 85h

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Table 60. 'F5504 to 'F5510 Device Descriptor Table (1) (continued)

'F5510 'F5510 'F5509 'F5509 'F5508 'F5508 'F5507 'F5506 'F5505 'F5504

SIZE RGC RGZ RGC RGZ RGC RGZ

DESCRIPTION ADDRESS (bytes) VALUE VALUE VALUE VALUE VALUE VALUE VALUE VALUE VALUE VALUE

04h 04h 04h 04h 04h 04h 04h 04h 04h 04h

DMA-3 2 47h 47h 47h 47h 47h 47h 47h 47h 47h 47h

0Ch 0Ch 0Ch 0Ch 0Ch 0Ch 10h 10h 10h 10h

USCI_A/B 2 90h 90h 90h 90h 90h 90h 90h 90h 90h 90h

04h 04h 04h 04h 04h 04h

USCI_A/B 2 N/A N/A N/A N/A

90h 90h 90h 90h 90h 90h

14h 14h 14h 14h 14h 14h 14h 14h 14h 14h

ADC10_A 2 D3h D3h D3h D3h D3h D3h D3h D3h D3h D3h

18h 18h 18h 18h 18h 18h

COMP_B 2 N/A N/A N/A N/A

A8h A8h A8h A8h A8h A8h

04h 04h 04h 04h 04h 04h 1Ch 1Ch 1Ch 1Ch

USB 2 98h 98h 98h 98h 98h 98h 98h 98h 98h 98h

Interrupts COMP_B 1 A8h A8h A8h A8h A8h A8h 01h 01h 01h 01h

TB0.CCIFG0 1 64h 64h 64h 64h 64h 64h 64h 64h 64h 64h

TB0.CCIFG1..6 1 65h 65h 65h 65h 65h 65h 65h 65h 65h 65h

WDTIFG 1 40h 40h 40h 40h 40h 40h 40h 40h 40h 40h

USCI_A0 1 90h 90h 90h 90h 90h 90h 01h 01h 01h 01h

USCI_B0 1 91h 91h 91h 91h 91h 91h 01h 01h 01h 01h

ADC10_A 1 D0h D0h D0h D0h D0h D0h D0h D0h D0h D0h

TA0.CCIFG0 1 60h 60h 60h 60h 60h 60h 60h 60h 60h 60h

TA0.CCIFG1..4 1 61h 61h 61h 61h 61h 61h 61h 61h 61h 61h

USB 1 98h 98h 98h 98h 98h 98h 98h 98h 98h 98h

DMA 1 46h 46h 46h 46h 46h 46h 46h 46h 46h 46h

TA1.CCIFG0 1 62h 62h 62h 62h 62h 62h 62h 62h 62h 62h

TA1.CCIFG1..2 1 63h 63h 63h 63h 63h 63h 63h 63h 63h 63h

P1 1 50h 50h 50h 50h 50h 50h 50h 50h 50h 50h

USCI_A1 1 92h 92h 92h 92h 92h 92h 92h 92h 92h 92h

USCI_B1 1 93h 93h 93h 93h 93h 93h 93h 93h 93h 93h

TA1.CCIFG0 1 66h 66h 66h 66h 66h 66h 66h 66h 66h 66h

TA1.CCIFG1..2 1 67h 67h 67h 67h 67h 67h 67h 67h 67h 67h

P2 1 51h 51h 51h 51h 51h 51h 51h 51h 51h 51h

RTC_A 1 68h 68h 68h 68h 68h 68h 68h 68h 68h 68h

delimiter 1 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Table 61. 'F5500 to 'F5503 Device Descriptor Table(1)

'F5503RGZ 'F5502RGZ 'F5501RGC 'F5500RGZ

SIZE

DESCRIPTION ADDRESS (bytes) VALUE VALUE VALUE VALUE

Info Block Info length 01A00h 1 06h 06h 06h 06h

CRC length 01A01h 1 06h 06h 06h 06h

CRC value 01A02h 2 per unit per unit per unit per unit

Device ID 01A04h 1 34h 33h 32h 3Bh

Device ID 01A05h 1 80h 80h 80h 80h

Hardware revision 01A06h 1 per unit per unit per unit per unit

Firmware revision 01A07h 1 per unit per unit per unit per unit

Die Record Die Record Tag 01A08h 1 08h 08h 08h 08h

Die Record length 01A09h 1 0Ah 0Ah 0Ah 0Ah

Lot/Wafer ID 01A0Ah 4 per unit per unit per unit per unit

Die X position 01A0Eh 2 per unit per unit per unit per unit

Die Y position 01A10h 2 per unit per unit per unit per unit

Test results 01A12h 2 per unit per unit per unit per unit

ADC10 Calibration Empty Tag 01A14h 1 05h 05h 05h 05h

Empty Tag length 01A15h 1 10h 10h 10h 10h

REF Calibration REF Calibration Tag 01A26h 1 12h 12h 12h 12h

REF Calibration length 01A27h 1 06h 06h 06h 06h

REF 1.5-V Reference Factor 01A28h 2 per unit per unit per unit per unit

REF 2.0-V Reference Factor 01A2Ah 2 per unit per unit per unit per unit

REF 2.5-V Reference Factor 01A2Ch 2 per unit per unit per unit per unit

Peripheral Peripheral Descriptor Tag 01A2Eh 1 02h 02h 02h 02h

Descriptor

Peripheral Descriptor Length 01A2Fh 1 5Dh 5Eh 5Dh 5Dh

08h 08h 08h 08h

Memory 1 2 8Ah 8Ah 8Ah 8Ah

0Ch 0Ch 0Ch 0Ch

Memory 2 2 86h 86h 86h 86h

0Eh 0Eh 0Eh 0Eh

Memory 3 2 2Ah 2Ah 2Ah 2Ah

12h 12h 12h 12h

Memory 4 2 2Ch 2Ch 2Ch 2Ch

40h 50h 60h 70h

Memory 5 2 92h 91 90h 8Eh

Memory 6 1 N/A 8E N/A N/A

delimiter 1 00h 00h 00h 00h

Peripheral count 1 1Eh 1Eh 1Eh 1Eh

00h 00h 00h 00h

MSP430CPUXV2 2 23h 23h 23h 23h

00h 00h 00h 00h

JTAG 2 09h 09h 09h 09h

00h 00h 00h 00h

SBW 2 0Fh 0Fh 0Fh 0Fh

00h 00h 00h 00h

EEM-S 2 03h 03h 03h 03h

00h 00h 00h 00h

TI BSL 2 FCh FCh FCh FCh

10h 10h 10h 10h

SFR 2 41h 41h 41h 41h

02h 02h 02h 02h

PMM 2 30h 30h 30h 30h

02h 02h 02h 02h

FCTL 2 38h 38h 38h 38h

01h 01h 01h 01h

CRC16 2 3Ch 3Ch 3Ch 3Ch

(1) N/A = Not applicable

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

Table 61. 'F5500 to 'F5503 Device Descriptor Table(1) (continued)

'F5503RGZ 'F5502RGZ 'F5501RGC 'F5500RGZ

SIZE

DESCRIPTION ADDRESS (bytes) VALUE VALUE VALUE VALUE

00h 00h 00h 00h

CRC16_RB 2 3Dh 3Dh 3Dh 3Dh

00h 00h 00h 00h

RAMCTL 2 44h 44h 44h 44h

00h 00h 00h 00h

WDT_A 2 40h 40h 40h 40h

01h 01h 01h 01h

UCS 2 48h 48h 48h 48h

02h 02h 02h 02h

SYS 2 42h 42h 42h 42h

03h 03h 03h 03h

REF 2 A0h A0h A0h A0h

01h 01h 01h 01h

Port Mapping 2 10h 10h 10h 10h

04h 04h 04h 04h

Port 1/2 2 51h 51h 51h 51h

02h 02h 02h 02h

Port 3/4 2 52h 52h 52h 52h

02h 02h 02h 02h

Port 5/6 2 53h 53h 53h 53h

0Eh 0Eh 0Eh 0Eh

JTAG 2 5Fh 5Fh 5Fh 5Fh

02h 02h 02h 02h

TA0 2 62h 62h 62h 62h

04h 04h 04h 04h

TA1 2 61h 61h 61h 61h

04h 04h 04h 04h

TB0 2 67h 67h 67h 67h

04h 04h 04h 04h

TA2 2 61h 61h 61h 61h

0Ah 0Ah 0Ah 0Ah

RTC 2 68h 68h 68h 68h

02h 02h 02h 02h

MPY32 2 85h 85h 85h 85h

04h 04h 04h 04h

DMA-3 2 47h 47h 47h 47h

0Ch 0Ch 0Ch 0Ch

USCI_A/B 2 90h 90h 90h 90h

04h 04h 04h 04h

USCI_A/B 2 90h 90h 90h 90h

ADC10_A 2 N/A N/A N/A N/A

2Ch 2Ch 2Ch 2Ch

COMP_B 2 A8h A8h A8h A8h

04h 04h 04h 04h

USB 2 98h 98h 98h 98h

Interrupts COMP_B 1 A8h A8h A8h A8h

TB0.CCIFG0 1 64h 64h 64h 64h

TB0.CCIFG1..6 1 65h 65h 65h 65h

WDTIFG 1 40h 40h 40h 40h

USCI_A0 1 01h 01h 01h 01h

USCI_B0 1 01h 01h 01h 01h

ADC10_A 1 01h 01h 01h 01h

TA0.CCIFG0 1 60h 60h 60h 60h

TA0.CCIFG1..4 1 61h 61h 61h 61h

USB 1 98h 98h 98h 98h

DMA 1 46h 46h 46h 46h

TA1.CCIFG0 1 62h 62h 62h 62h

TA1.CCIFG1..2 1 63h 63h 63h 63h

MSP430F550x, MSP430F5510

SLAS645F –JULY 2009–REVISED MARCH 2011

www.ti.com

Table 61. 'F5500 to 'F5503 Device Descriptor Table(1) (continued)

'F5503RGZ 'F5502RGZ 'F5501RGC 'F5500RGZ

SIZE

DESCRIPTION ADDRESS (bytes) VALUE VALUE VALUE VALUE

P1 1 50h 50h 50h 50h

USCI_A1 1 92h 92h 92h 92h

USCI_B1 1 93h 93h 93h 93h

TA1.CCIFG0 1 66h 66h 66h 66h

TA1.CCIFG1..2 1 67h 67h 67h 67h

P2 1 51h 51h 51h 51h

RTC_A 1 68h 68h 68h 68h

delimiter 1 00h 00h 00h 00h

MSP430F550x, MSP430F5510

www.ti.com

SLAS645F –JULY 2009–REVISED MARCH 2011

REVISION HISTORY

VERSION COMMENTS

SLAS645 Product Preview release

SLAS645A Changes throughout for updated Product Preview

SLAS645B Changes throughout for updated Product Preview

SLAS645C Updated Embedded Emulation Module (EEM, Version S) section

SLAS645D Changes throughout for Production Data release

Released BGA package

Corrected VCB_REF min and max values by swapping them as they were backward

SLAS645E Added IUSB_LDO and IVBUS_DETECT to USB-PWR table

Added QFN thermal pad connection to pinout drawing and terminal function table

Updated tEN_REF typ value from 0.3 to 1

Corrected 'F5504 to 'F5510 Device Descriptor Table (Table 60) addresses for ADC10 ADC Gain to Peripheral Descriptor

SLAS645F Tag

PACKAGE OPTION ADDENDUM

www.ti.com 2-Apr-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

MSP430F5500IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5500IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5501IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5501IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5502IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5502IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5503IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5503IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5504IPT ACTIVE LQFP PT 48 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5504IPTR ACTIVE LQFP PT 48 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5504IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5504IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5505IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5505IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5506IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5506IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5507IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

PACKAGE OPTION ADDENDUM

www.ti.com 2-Apr-2012

Addendum-Page 2

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

MSP430F5507IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5508IPT ACTIVE LQFP PT 48 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5508IPTR ACTIVE LQFP PT 48 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5508IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5508IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5508IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5508IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5508IZQE ACTIVE BGA

MICROSTAR

JUNIOR

ZQE 80 360 Green (RoHS

& no Sb/Br) SNAGCU Level-3-260C-168 HR

MSP430F5508IZQER ACTIVE BGA

MICROSTAR

JUNIOR

ZQE 80 2500 Green (RoHS

& no Sb/Br) SNAGCU Level-3-260C-168 HR

MSP430F5509IPT ACTIVE LQFP PT 48 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5509IPTR ACTIVE LQFP PT 48 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5509IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5509IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5509IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5509IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5509IZQE ACTIVE BGA

MICROSTAR

JUNIOR

ZQE 80 360 Green (RoHS

& no Sb/Br) SNAGCU Level-3-260C-168 HR

PACKAGE OPTION ADDENDUM

www.ti.com 2-Apr-2012

Addendum-Page 3

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

MSP430F5509IZQER ACTIVE BGA

MICROSTAR

JUNIOR

ZQE 80 2500 Green (RoHS

& no Sb/Br) SNAGCU Level-3-260C-168 HR

MSP430F5510IPT ACTIVE LQFP PT 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5510IPTR ACTIVE LQFP PT 48 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5510IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5510IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5510IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5510IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

MSP430F5510IZQE ACTIVE BGA

MICROSTAR

JUNIOR

ZQE 80 360 Green (RoHS

& no Sb/Br) SNAGCU Level-3-260C-168 HR

MSP430F5510IZQER ACTIVE BGA

MICROSTAR

JUNIOR

ZQE 80 2500 Green (RoHS

& no Sb/Br) SNAGCU Level-3-260C-168 HR

XMS430F5510IRGCR OBSOLETE VQFN RGC 64 TBD Call TI Call TI

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

PACKAGE OPTION ADDENDUM

www.ti.com 2-Apr-2012

Addendum-Page 4

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

MECHANICAL DATA

MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PT (S-PQFP-G48) PLASTIC QUAD FLATPACK

4040052/C 11/96

0,13 NOM

0,17

0,27

6,80

7,20

5,50 TYP

0,25

0,45

0,75

0,05 MIN

9,20

8,80

1,35

1,45

1,60 MAX

Gage Plane

Seating Plane

0,10

0°–7°

0,50 M

0,08

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. This may also be a thermally enhanced plastic package with leads conected to the die pads.

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic."Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP®Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265