IDT71V3578YS133PFGI - Integrated Device Technology

JANUARY 2004

DSC-5279/04

1

Features

◆◆

◆128K x 36, 256K x 18 memory configurations

◆◆

◆Supports high system speed:

Commercial and Industrial:

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

◆◆

◆LBO input selects interleaved or linear burst mode

◆◆

◆Self-timed write cycle with global write control (GW), byte write

enable (BWE), and byte writes (BWx)

◆◆

◆3.3V core power supply

◆◆

◆Power down controlled by ZZ input

◆◆

◆3.3V I/O

◆◆

◆Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

◆◆

◆Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array (fBGA)

Description

The IDT71V3576/78 are high-speed SRAMs organized as

128K x 36/256K x 18. The IDT71V3576/78 SRAMs contain write, data,

address and control registers. Internal logic allows the SRAM to generate

a self-timed write based upon a decision which can be left until the end of

the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V3576/78 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will be pipelined for one

cycle before it is available on the next rising clock edge. If burst mode

operation is selected (ADV=LOW), the subsequent three cycles of output

data will be available to the user on the next three rising clock edges. The

order of these three addresses are defined by the internal burst counter

and the LBO input pin.

The IDT71V3576/78 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

Pin Description Summary

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V3578.

A

0

-A

17

Address Inputs Input Synchronous

CE Chip Enab le Inp ut Synchronous

CS

0

, CS

1

Chip Se lects Inp ut Synchro nous

OE Output Enab le Inp ut As y nchro nous

GW Glo b al Wri te E nab l e Inp ut S ync hro nous

BWE Byte Write Enable Inp ut Synchrono us

BW

1

, BW

2

, BW

3

, BW

4

(1)

Indiv id ual Byte Write Se lects Inp ut Synchro nous

CLK Clock Input N/A

ADV Burst Add ress Ad vance Inp ut Synchro nous

ADSC Ad dre ss Status (Cache Co ntrolle r) Inp ut Synchronous

ADSP Ad dre ss Status (P ro ce sso r) Inp ut Synchro nous

LBO Line ar / Interle aved Burst Orde r Inp ut DC

TMS Test Mode Select Input Synchronous

TDI Te st Data Inp ut Inp ut Sy nc hro no us

TCK Te st Clock Inp ut N/A

TDO Te st Data O utp ut Outp ut Sy nc hro nous

TRST JTAG Reset (Optional) Input Asynchronous

ZZ Sleep Mode Input Asynchronous

I/O

0

-I/O

31

, I/O

P1

-I/O

P4

Data Inp ut / Outp ut I/ O Sy nc hro no us

V

DD

, V

DDQ

Co re Po wer, I/O P ower Supp ly N/A

V

SS

Ground Supply N/A

5279 tbl 01

128K x 36, 256K x 18

3.3V Synchronous SRAMs

3.3V I/O, Pipelined Outputs

Burst Counter, Single Cycle Deselect

IDT71V3576S

IDT71V3578S

IDT71V3576SA

IDT71V3578SA

6.42

2

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Definitions(1)

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

Sym bol Pi n Fun cti on I/ O Active Descri ption

A

0

-A

17

Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge

of CLK and ADSC Low or ADSP Lo w and CE Low.

ADSC Add re ss Status

(Cac he Co ntro lle r) ILOW

Synchron ous Address Status fro m Cache Co ntroller. ADSC i s an active LOW input that is us ed to lo ad

the ad dress re gisters with new addresses.

ADSP Add re ss Status

(Processor) ILOW

Synchronous Address Status from Processor. ADSP is an ac ti v e LOW in p ut that is u se d to l o ad the

address registers with new addresses. ADSP is gated by CE.

ADV Burst Ad dress

Advance ILOW

Synchronous Address Advance. ADV is an ac ti ve LO W in put that is us ed to adv anc e the i nte rnal b urs

t

co unter, contro lling burs t acce ss after the initial addre ss is loade d . When the inpu t is HIGH the b urst

c o un te r i s n o t i nc re m e n te d ; that is, the re i s no ad d re s s a d v an ce.

BWE Byte Write Enab le I LOW Synchronous byte write enab le gates the byte write inputs BW

1

-BW

4

. If BWE is LOW at the ris ing

edge of CLK then BWx inputs are passed to the ne xt stage in the circuit. If BWE i s H IG H th en th e

byte write inputs are blocked and only GW can initiate a write cycle.

BW

1

-BW

4

Indi v idual B y te

Write Enab les ILOW

Synchronous byte write enab les. BW

1

co ntrols I/O

0-7

, I/O

P1

, BW

2

controls I/O

8-15

, I/O

P2

, etc. Any active

byte write causes all outputs to b e disabled.

CE Chip Enab le I LOW Synchronous chip enab le. CE is used with CS

0

and CS

1

to enab l e the IDT71V3 576/ 78. CE al s o g ate s

ADSP.

CLK Cl o c k I N/ A Thi s is th e c l ock i np u t. Al l ti ming re fe r e nce s for th e d e vi c e ar e made with re s p e c t to thi s i np u t.

CS

0

Chip Sele ct 0 I HIGH Synchrono us active HIGH chip select. CS

0

is use d with CE and CS

1

to enab l e the c h ip .

CS

1

Chip S ele ct 1 I LOW Sy nchro no us active LOW chip se lec t. CS

1

is use d with CE and CS

0

to enab le the chip.

GW Glob al Write

Enable ILOW

Synchronous global write enable . This input will write all fo ur 9-bit d ata bytes when LOW on the rising

edge of CLK. GW supersedes individual byte write e nab les.

I/O

0

-I/O

31

I/O

P1

-I/O

P4

Da ta Input /Ou tp ut I/ O N/ A Synchro nous d ata input/output (I/O) pins. Both the data input path and data output path are registere d

and triggered by the rising edge of CLK.

LBO Line ar Burst Ord er I LOW Asy nc hrono us b urst o rd er se lec tio n input. Whe n LBO is HIGH, the interleaved burs t seq uence is

sele cted. When LBO is LOW the Linear burst sequence is selected. LBO is a s tatic input and mus t

not change state while the device is ope rating.

OE Output Enable I LOW A sy nc hrono us o utp ut e nab l e. Whe n OE is LOW the data output drivers are enabled on the I/O pins if

the chip is also s ele cte d. When OE is HIGH the I/ O p i ns are i n a high-i mpe d anc e s tate .

TMS Te st Mo d e Se lec t I N/ A Give s input comm and for TAP co ntrolle r. Samp led on ris ing e dg e of TDK. This pin has an inte rnal

pullup.

TDI Tes t Dat a In p ut I N/ A Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has

an inte rnal p ullup .

TCK Tes t Clock I N/A Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of

TCK, while test outputs are d riven from the falling edge of TCK. This pin has an internal pullup .

TDO Te st Data Ou tp ut O N/ A Serial o utput of re gis ters p laced between TDI and TDO. This output is active de pend ing on the state

of the TA P co ntro ller.

TRST JTAG Reset

(Optional) ILOW

Op tio na l As y nc hro nous J TA G re s e t. Can b e us e d to re s e t the TA P co ntrolle r, b ut no t req uire d. J TAG

re s e t o c c urs auto mati ca lly at p o we r up an d al s o re se ts us i ng TM S and TCK p e r IE EE 1149. 1. If no t

used TRST c an b e le ft flo ating . This pin has an i nte rnal p ullup. Only available in BGA p ackage .

ZZ Sleep Mode I HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

IDT71V 3576/ 78 to i ts l ow est p o we r c o ns ump tion l e ve l . Data re te ntion i s g uarant eed i n S le e p

Mo d e . This p i n has a n inte rnal p ull do wn.

V

DD

Power Supply N/A N/A 3.3V core power supply.

V

DDQ

Po we r Supply N/A N/A 3.3V I/O Supp ly.

V

SS

Ground N/A N/A Ground.

NC No Connect N/A N/A NC pins are not electrically connected to the device.

5279 tbl 02

6.42

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

3

Functional Block Diagram

A

0-

A

16/17

ADDRESS

REGISTER

CLR

A1*

A0* 17/18

2

17/18 A

2

–A

17

128K x 36/

256K x 18-

BIT

MEMORY

ARRAY

INTERNAL

ADDRESS

A

0

,A

1

BW

4

BW

3

BW

2

BW

1

Byte 1

Write Register

36/18 36/18

ADSP

ADV

CLK

ADSC

CS

0

CS

1

Byte 1

Write Driver

Byte 2

Write Driver

Byte 3

Write Driver

Byte 4

Write Driver

Byte 2

Write Register

Byte 3

Write Register

Byte 4

Write Register

9

GW

CE

BWE

LBO

I/O

0

— I/O

31

I/O

P1

—I/O

P4

OE

DATA INPUT

REGISTER

36/18

OUTPUT

BUFFER

OUTPUT

REGISTER

DQ

Enable

Register

Enable

Delay

Register

OE

Burst

Sequence

CEN

CLK EN

Q1

Q0

2

Burst

Logic

Binary

Counter

5279 drw 01

ZZ

Powerdown

,

JTAG

(SA Version)

TMS

TDI

TCK

TRST

(Optional)

TDO

6.42

4

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

100 Pin TQFP Capacitance

(TA = +25°C, f = 1.0MHz)

Recommended Operating

Temperature and Supply Voltage

Absolute Maximum Ratings(1)

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6 . This is a steady-state DC parameter that applies after the power supplies have

ramped up. Power supply sequencing is not necessary; however, the voltage

on any input or I/O pin cannot exceed VDDQ during power supply ramp up.

7. TA is the "instant on" case temperature.

Recommended DC Operating

Conditions

NOTES:

1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.

2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

Symbol Rating Comm erci al &

Industrial Unit

V

TERM

(2)

Terminal Voltage with

Re s p e ct to GND -0.5 to +4.6 V

V

TERM

(3,6)

Terminal Voltage with

Re s p e ct to GND -0. 5 to V

DD

V

TERM

(4,6)

Terminal Voltage with

Re s p e ct to GND -0.5 to V

DD

+0.5 V

V

TERM

(5,6)

Terminal Voltage with

Re s p e ct to GND -0.5 to V

DDQ

+0.5 V

T

A

(7)

Commercial

Operating Temperature -0 to +70

o

C

Industrial

Operating Temperature -40 to +85

o

C

T

BIAS

Temperature

Under Bias -55 to + 125

o

C

T

STG

Storage

Temperature -55 to +125

o

C

P

T

Po we r Dissip ati on 2.0 W

I

OUT

DC Outp ut Curre nt 50 mA

5279 tbl 03

Grade Temperature

(1)

V

SS

V

DD

V

DDQ

Co mme rc ial 0°C to +70° C 0V 3.3V ± 5% 3.3V± 5%

Industrial -40°C to +85°C 0V 3.3V± 5% 3.3V± 5%

52 79 t b l 04

Symbol Parameter Min. Typ. Max. Unit

V

DD

Co re S upply Volt age 3. 135 3.3 3. 465 V

V

DDQ

I/O Supply Voltage 3.135 3.3 3.465 V

V

SS

Supply Voltage 0 0 0 V

V

IH

I nput High Volta ge - Input s 2.0

____

V

DD

+0.3 V

V

IH

I nput High Volta ge - I/ O 2. 0

____

V

DDQ

+0.3

(1)

V

IL

I nput Low Vo lt age -0.3

(2)

____

0.8 V

5279 tbl 06

Symbol Parameter

(1)

Conditions Max. Unit

C

IN

Input Capacitance V

IN

= 3dV 5 pF

C

I/O

I/ O Cap ac itance V

OUT

= 3dV 7 pF

5279 tbl 07

119 BGA Capacitance

(TA = +25°C, f = 1.0MHz)

Symbol Parameter

(1)

Conditions Max. Unit

C

IN

Inp ut Capac itanc e V

IN

= 3dV 7 pF

C

I/O

I/ O Capac itanc e V

OUT

= 3dV 7 pF

5279 tbl 07a

NOTES:

1. TA is the "instant on" case temperature.

165 fBGA Capacitance

(TA = +25°C, f = 1.0MHz)

Symbol Parameter

(1)

Conditions Max. Unit

C

IN

Input Capacitance V

IN

= 3dV 7 pF

C

I/O

I/ O Cap ac itance V

OUT

= 3dV 7 pF

5279 tb l 07b

6.42

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

5

Pin Configuration – 128K x 36

TQFP

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

A

6

A

7

CE

CS

0

BW

4

BW

3

BW

2

BW

1

CS

1

V

DD

V

SS

CLK

GW

BWE

OE

ADSC

ADSP

ADV

A

8

A

9

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

NC

LBO

A

14

A

13

A

12

A

11

A

10

V

DD

V

SS

A

0

A

1

A

2

A

3

A

4

A

5

I/O

31

I/O

30

V

DDQ

V

SS

I/O

29

I/O

28

I/O

27

I/O

26

V

SS

V

DDQ

I/O

25

I/O

24

V

SS

V

DD

I/O

23

I/O

22

V

DDQ

V

SS

I/O

21

I/O

20

I/O

19

I/O

18

V

SS

V

DDQ

I/O

17

I/O

16

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

I/O

14

V

DDQ

V

SS

I/O

13

I/O

12

I/O

11

I/O

10

V

SS

V

DDQ

I/O

9

I/O

8

V

SS

V

DD

I/O

7

I/O

6

V

DDQ

V

SS

I/O

5

I/O

4

I/O

3

I/O

2

V

SS

V

DDQ

I/O

1

I/O

0

5279 drw 02

V

DD

/NC

(1)

I/O

15

I/O

P3

NC

I/O

P4

A

15

A

16

I/O

P1

NC

I/O

P2

ZZ

(2)

,

6.42

6

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration – 256K x 18

10099989796959493929190 8786858483828189 88

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

A

6

A

7

CE

CS

0

NC

BW

2

BW

1

CS

1

V

DD

V

SS

CLK

GW

BWE

OE

ADSC

ADSP

ADV

A

8

A

9

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

NC

LBO

A

15

A

14

A

13

A

12

A

11

V

DD

V

SS

A

0

A

1

A

2

A

3

A

4

A

5

NC

V

DDQ

V

SS

NC

I/O

P2

I/O

15

I/O

14

V

SS

V

DDQ

I/O

13

I/O

12

V

SS

V

DD

I/O

11

I/O

10

V

DDQ

V

SS

I/O

9

I/O

8

NC

V

SS

V

DDQ

NC

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

NC

V

DDQ

V

SS

NC

I/O

P1

I/O

7

I/O

6

V

SS

V

DDQ

I/O

5

I/O

4

V

SS

V

DD

I/O

3

I/O

2

V

DDQ

V

SS

I/O

1

I/O

0

NC

V

SS

V

DDQ

NC

5279 drw 03

V

DD

/NC

(1)

NC

A

16

A

17

NC

A

10

ZZ

(2)

,

TQFP

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

7

Pin Configuration – 256K x 18, 119 BGA

Pin Configuration – 128K x 36, 119 BGA

Top View

NOTES:

1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.

3. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

4. T7 can be left unconnected and the device will always remain in active mode.

1234567

AV

DDQ

A

6

A

4

ADSP A

8

A

16

V

DDQ

BNC CS

0

A

3

ADSC A

9

CS

1

NC

CA

7

A

2

V

DD

A

12

A

15

NC

DI/O

16

I/O

P3

V

SS

NC V

SS

I/O

P2

I/O

15

EI/O

17

I/O

18

V

SS

CE V

SS

I/O

13

I/O

14

FV

DDQ

I/O

19

V

SS

OE V

SS

I/O

12

V

DDQ

GI/O

20

I/O

21

BW

3

ADV BW

2

I/O

11

I/O

10

HI/O

22

I/O

23

V

SS

GW V

SS

I/O

9

I/O

8

JV

DDQ

V

DD

NC V

DD

NC V

DD

V

DDQ

KI/O

24

I/O

26

V

SS

CLK V

SS

I/O

6

I/O

7

LI/O

25

I/O

27

BW

4

NC BW

1

I/O

4

I/O

5

M

V

DDQ

I/O

28

V

SS

BWE V

SS

I/O

3

V

DDQ

NI/O

29

I/O

30

V

SS

A

1

V

SS

I/O

2

I/O

1

PI/O

31

I/O

P4

V

SS

A

0

V

SS

I/O

0

I/O

P1

RNC A

5

LBO V

DD

A

13

TNC NC A

10

A

11

A

14

NC

UV

DDQ

NC/TMS

(2)

NC/TDI

(2)

NC/TCK

(2)

NC/TDO

(2)

NC/TRST

(2,3)

V

DDQ

5279 drw 04

V

DD

/NC

(1)

NC

,

ZZ

(4)

1234567

AV

DDQ

A

6

A

4

ADSP A

8

A

16

V

DDQ

BNC CS

0

A

3

ADSC A

9

CS

1

NC

CA

7

A

2

V

DD

A

13

A

17

NC

DI/O

8

NC V

SS

NC V

SS

I/O

7

NC

ENC I/O

9

V

SS

CE V

SS

NC I/O

6

FV

DDQ

NC V

SS

OE V

SS

I/O

5

V

DDQ

GNC I/O

10

BW

2

ADV NC I/O

4

HI/O

11

NC V

SS

GW V

SS

I/O

3

NC

JV

DDQ

V

DD

NC V

DD

NC V

DD

V

DDQ

KNC I/O

12

V

SS

CLK V

SS

NC I/O

2

LI/O

13

NC NC BW

1

I/O

1

NC

M

V

DDQ

I/O

14

V

SS

BWE V

SS

NC V

DDQ

NI/O

15

NC V

SS

A

1

V

SS

I/O

0

NC

PNC I/O

P2

V

SS

A

0

V

SS

NC I/O

P1

RNC A

5

LBO V

DD

A

12

TNC A

10

A

15

NC A

14

A

11

NC

UV

DDQ

V

DDQ

5279 drw 05

NC

V

DD

/NC

(1)

V

SS

V

SS

,

ZZ

(4)

NC/TMS

(2)

NC/TDI

(2)

NC/TCK

(2)

NC/TDO

(2)

NC/TRST

(2,3)

6.42

8

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration – 256K x 18, 165 fBGA

Pin Configuration – 128K x 36, 165 fBGA

NOTES:

1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.

3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.

4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

5. H11 can be left unconnected and the device will always remain in active mode.

1234567891011

ANC

(2)

A

7

CE

1

BW

3

BW

2

CS

1

BWE ADSC AD V A

8

NC

BNC A

6

CS

0

BW

4

BW

1

CLK GW OE ADSP A

9

NC

(2)

CI/O

P3

NC V

DDQ

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDQ

NC I/O

P2

DI/O

17

I/O

16

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

15

I/O

14

EI/O

19

I/O

18

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

13

I/O

12

FI/O

21

I/O

20

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

11

I/O

10

GI/O

23

I/O

22

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

9

I/O

8

HV

DD

(1)

NC NC V

DD

V

SS

V

SS

V

SS

V

DD

NC NC ZZ

(5)

JI/O

25

I/O

24

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

7

I/O

6

KI/O

27

I/O

26

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

5

I/O

4

LI/O

29

I/O

28

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

3

I/O

2

MI/O

31

I/O

30

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

1

I/O

0

NI/O

P4

NC V

DDQ

V

SS NC/TRST

(3,4)

NC

(2)

NC V

SS

V

DDQ

NC I/O

P1

PNCNC

(2)

A

5

A

2

NC/TDI

(3)

A

1

NC/TDO

(3)

A

10

A

13

A

14

NC

(2)

RLBO NC

(2)

A

4

A

3

NC/TMS

(3)

A

0

NC/TCK

(3)

A

11

A

12

A

15

A

16

5279 tbl 17

1234567891011

ANC

(2)

A

7

CE

1

BW

2

NC CS

1

BWE ADSC ADV A

8

A

10

BNC A

6

CS

0

NC BW

1

CLK GW OE ADSP A

9

NC

(2)

CNC NCV

DDQ

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDQ

NC I/O

P1

DNC I/O

8

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

NC I/O

7

ENC I/O

9

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

NC I/O

6

FNCI/O

10

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

NC I/O

5

GNC I/O

11

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

NC I/O

4

HV

DD

(1)

NC NC V

DD

V

SS

V

SS

V

SS

V

DD

NC NC ZZ

(5)

JI/O

12

NC V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

3

NC

KI/O

13

NC V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

2

NC

LI/O

14

NC V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

1

NC

MI/O

15

NC V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

0

NC

NI/O

P2

NC V

DDQ

V

SS

NC/TRST

(3,4)

NC

(2)

NC V

SS

V

DDQ

NC NC

PNC NC

(2)

A

5

A

2

NC/TDI

(3)

A

1

NC/TDO

(3)

A

11

A

14

A

15

NC

(2)

RLBO NC

(2)

A

4

A

3

NC/TMS

(3)

A

0

NC/TCK

(3)

A

12

A

13

A

16

A

17

5279 tb l 17a

6.42

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

9

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(1)

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)

Figure 2. Lumped Capacitive Load, Typical Derating

Figure 1. AC Test Load

AC Test LoadAC Test Conditions

(VDDQ = 3.3V)

NOTE:

1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to V SS if they are not actively driven in the application.

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

V

DDQ

/2

50Ω

I

/O Z

0

=50Ω

5279 drw 06

,

1

2

3

4

20 30 50 100 200

∆tCD

(Typical, ns)

Capacitance (pF)

80

5

6

5279 drw 07

,

Symbol Parameter Test Conditions Min. Max. Unit

|I

LI

| Inp ut Le akag e Curre nt V

DD

= Max., V

IN

= 0V to V

DD

___

5µA

|I

LZZ

|ZZ, LBO and JTAG Input Leakage Current

(1)

V

DD

= Max., V

IN

= 0V to V

DD

___

30 µA

|I

LO

| Output Leakage Current V

OUT

= 0V to V

DDQ

, Device Deselected

___

5µA

V

OL

Output Lo w Voltage I

OL

= +8mA, V

DD

= Min.

___

0.4 V

V

OH

Outp ut High Voltage I

OH

= -8mA, V

DD

= Min. 2.4

___

V

5279 tbl 08

Symbol Parameter Test Conditions

150MHz 133MHz

UnitCom'l Ind Com'l Ind

I

DD

Operating Power Supply

Current De vice Sele cted , Outputs Op en, V

DD

= Max.,

V

DDQ

= Max., V

IN

> V

IH

or < V

IL

, f = f

MAX

(2)

295 305 250 260 mA

I

SB1

CMOS Standb y Powe r

Supply Current Devic e Desele cted, Outp uts Ope n, V

DD

= Max.,

V

DDQ

= Max., V

IN

> V

HD

or < V

LD

, f = 0

(2,3)

30 35 30 35 mA

I

SB2

Clo ck Running Powe r

Supply Current Devic e Desele cted, Outp uts Ope n, V

DD

= Max.,

V

DDQ

= Max., V

IN

> V

HD

or < V

LD

, f = f

MAX

(2,3)

105 115 100 110 mA

I

ZZ

Full Sleep Mode Supply

Current ZZ > V

HD,

V

DD

= Max. 30 35 30 35 mA

5279 tbl 09

Inp ut P ul se Le v e ls

Inp ut Ris e / Fal l Tim e s

Inp ut Timing Re fe re n ce Le v e l s

Output Timing Re ferenc e Le ve ls

AC Test Load

0 to 3V

2ns

1.5V

See Figure 1

52 79 t b l 10

6.42

10

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Synchronous Truth Table(1,3)

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. OE is an asynchronous input.

3. ZZ = low for this table.

Operation Address

Used

CE CS

0

CS

1

ADSP ADSC ADV GW BWE BWxOE

(2) CLK I/O

Deselected Cycle, Power Down NoneHXXX LXXXXX-HI-Z

Deselected Cycle, Power Down None LXHL XXXXXX-HI-Z

Deselected Cycle, Power Down None L LX L XXXXXX-HI-Z

Deselected Cycle, Power Down None LXH X LXXXXX -HI-Z

Deselected Cycle, Power Down None L LXX LXXXXX -HI-Z

Read Cycle, Begin Burst ExternalL HL L XXXXX L-D

OUT

Read Cycle, Begin Burst ExternalL HL L XXXXXH -HI-Z

Re ad Cyc le , Be g in B urst Exte rnal L H L H L X H H X L - D

OUT

Re ad Cyc le , Be g in B urst Exte rnal L H L H L X H L H L - D

OUT

Re ad Cyc le , Be g in B urst Exte rnal L H L H L X H L H H - HI-Z

Write Cycle, Begin Burst External L H L H L X H L L X - D

IN

Write Cycle, Begin Burst External L H L H L X L X X X - D

IN

Re ad Cyc le , Co ntinue Burs t Ne xt X X X H H L H H X L - D

OUT

Re ad Cyc le , Co ntinue Burs t Ne xt X X X H H L H H X H - HI-Z

Re ad Cyc le , Co ntinue Burs t Ne xt X X X H H L H X H L - D

OUT

Re ad Cyc le , Co ntinue Burs t Ne xt X X X H H L H X H H - HI-Z

Re ad Cyc le , Co ntinue Burs t Ne xt H X X X H L H H X L - D

OUT

Re ad Cyc le , Co ntinue Burs t Ne xt H X X X H L H H X H - HI-Z

Re ad Cyc le , Co ntinue Burs t Ne xt H X X X H L H X H L - D

OUT

Re ad Cyc le , Co ntinue Burs t Ne xt H X X X H L H X H H - HI-Z

Write Cyc le, Co ntinue B urs t Ne xt X X X H H L H L L X - D

IN

Write Cycle, Continue Burst NextXXXH H L L XXX -D

IN

Write Cyc le, Co ntinue B urs t Ne xt H X X X H L H L L X - D

IN

Write Cycle, Continue Burst NextHXXX HL LXXX-D

IN

Re ad Cyc le , Sus p end B urst Curre nt X X X H H H H H X L - D

OUT

Re ad Cyc le , Sus p end B urst Curre nt X X X H H H H H X H - HI-Z

Re ad Cyc le , Sus p end B urst Curre nt X X X H H H H X H L - D

OUT

Re ad Cyc le , Sus p end B urst Curre nt X X X H H H H X H H - HI-Z

Re ad Cyc le , Sus p end B urst Curre nt H X X X H H H H X L - D

OUT

Re ad Cyc le , Sus p end B urst Curre nt H X X X H H H H X H - HI-Z

Re ad Cyc le , Sus p end B urst Curre nt H X X X H H H X H L - D

OUT

Re ad Cyc le , Sus p end B urst Curre nt H X X X H H H X H H - HI-Z

Write Cycle, Suspend Burst Current X X X H H H H L L X - D

IN

Write Cycle, Suspend Burst Current X X X H H H L X X X - D

IN

Write Cycle, Suspend Burst Current H X X X H H H L L X - D

IN

Write Cycle, Suspend Burst Current H X X X H H L X X X - D

IN

5279 tbl 11

6.42

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

11

Linear Burst Sequence Table (LBO=VSS)

Synchronous Write Function Truth Table(1, 2)

Asynchronous Truth Table(1)

Interleaved Burst Sequence Table (LBO=VDD)

NOTES:

1 . L = VIL, H = VIH, X = Don’t Care.

2. BW3 and BW4 are not applicable for the IDT71V3578.

3. Multiple bytes may be selected during the same cycle.

NOTES:

1 . L = VIL, H = VIH, X = Don’t Care.

2. Synchronous function pins must be biased appropriately to satisfy operation requirements.

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

Operation GW BWE BW

1

BW

2

BW

3

BW

4

Read HHXXXX

Read HLHHHH

Write all Byte s L X X X X X

Write all Byte s H L L L L L

Writ e B y te 1

(3)

HLLHHH

Writ e B y te 2

(3)

HLHLHH

Writ e B y te 3

(3)

HLHHLH

Writ e B y te 4

(3)

HLHHHL

5279 tbl 12

Sequence 1 Sequence 2 Sequence 3 Sequence 4

A1 A0 A1 A0 A1 A0 A1 A0

First Address 0 0 0 1 1 0 1 1

Second Address 0 1 1 0 1 1 0 0

Third Address 1 0 1 1 0 0 0 1

Fourth Address

(1)

11000110

5279 tbl 15

Sequence 1 Sequence 2 Sequence 3 Sequence 4

A1 A0 A1 A0 A1 A0 A1 A0

First Address 0 0 0 1 1 0 1 1

Second Address 0 1 0 0 1 1 1 0

Third Address 1 0 1 1 0 0 0 1

Fourth Address

(1)

11100100

5279 tbl 14

Operation

(2)

OE ZZ I/O Status Power

Re ad L L Data Out Ac tive

Read H L High-Z Active

Write X L Hig h-Z – Data In Ac ti ve

Deselected X L High-Z Standby

Sleep Mode X H High-Z Sle ep

5279 tbl 13

6.42

12

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)

NOTES:

1. Measured as HIGH above VIH and LOW below VIL.

2. Transition is measured ±200mV from steady-state.

3. Device must be deselected when powered-up from sleep mode.

4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.

150MHz 133MHz

Symbol Parameter Min. Max. Min. Max. Unit

t

CYC

Clock Cycle Time 6.7

____

7.5

____

ns

t

CH

(1)

Clo c k Hig h Puls e Wi dth 2. 6

____

3

____

ns

t

CL

(1)

Clock Low Pulse Width 2.6

____

3

____

ns

Output Parameters

t

CD

Cloc k Hig h to Valid Data

____

3.8

____

4.2 ns

t

CDC

Clo c k Hig h to Data Chang e 1. 5

____

1.5

____

ns

t

CLZ

(2)

Clo c k Hig h to Outp ut Acti ve 0

____

0

____

ns

t

CHZ

(2)

Clo ck Hig h to Data Hig h-Z 1. 5 3. 8 1. 5 4.2 ns

t

OE

Outp ut Enab le Ac ce ss Time

____

3.8

____

4.2 ns

t

OLZ

(2)

Output Enable Low to Outp ut Active 0

____

0

____

ns

t

OHZ

(2)

Output Enable Hig h to Outp ut Hig h-Z

____

3.8

____

4.2 ns

Set Up Times

t

SA

Address Setup Time 1.5

____

1.5

____

ns

t

SS

Address Status Setup Time 1.5

____

1.5

____

ns

t

SD

Data In S e tup Time 1. 5

____

1.5

____

ns

t

SW

Write Setup Time 1.5

____

1.5

____

ns

t

SAV

Address Advance Setup Time 1.5

____

1.5

____

ns

t

SC

Chip Enable/Sele ct S etup Time 1.5

____

1.5

____

ns

Hold Times

t

HA

Address Hold Time 0.5

____

0.5

____

ns

t

HS

Ad d ress Status Hold Tim e 0.5

____

0.5

____

ns

t

HD

Data In Ho l d Ti me 0. 5

____

0.5

____

ns

t

HW

Write Hold Time 0. 5

____

0.5

____

ns

t

HAV

Address Advance Hold Time 0.5

____

0.5

____

ns

t

HC

Chip Enable/Select Hold Time 0.5

____

0.5

____

ns

S leep Mode an d Co nfig urati on Parameters

t

ZZPW

ZZ Pulse Width 100

____

100

____

ns

t

ZZR

(3)

ZZ Re c ov e ry Ti m e 100

____

100

____

ns

t

CFG

(4)

Config uration Se t-up Time 27

____

30

____

ns

5279 tbl 16

6.42

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

13

NOTES:

1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence

of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.

2. ZZ input is LOW and LBO is Don't Care for this cycle.

3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

Timing Waveform of Pipelined Read Cycle(1,2)

t

CHZ

t

SA

t

SC

t

HS

G

W,BWE,BWx

t

SW

t

CL

t

SAV

t

HW

t

HAV

CLK

ADSC

(1)

ADDRESS

t

CYC

t

CH

t

HA

t

HC

t

OE

t

OHZ

OEt

CD

t

OLZ

O1(Ax)

DATA

OUT

t

CDC

O1(Ay)O3(Ay)O2(Ay)

O2(Ay)

t

CLZ

ADV

CE,CS

1

(Note3)

Pipelined

ReadBurstPipelinedRead

Output

Disabled

AxAy

t

SS

O1(Ay)

(Burstwrapsaround

toitsinitialstate)

O4(Ay)

5279drw08

ADSP

ADVHIGHsuspends

burst

,

6.42

14

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

NOTES:

1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.

2. ZZ input is LOW and LBO is Don't Care for this cycle.

3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents

the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.

Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)

CLK

ADSP

A

DDRESS

GW

ADV

OE

DATA

OUT

t

CYC

t

CH

t

CL

t

HA

t

SW

t

HW

t

CLZ

AxAyAz

t

HS

I1(Ay)

t

SD

t

HD

t

OLZ

t

CD

t

CDC

DATA

IN

(2)

t

OE

O1(Az)

SingleReadPipelinedBurstRead

Pipelined

Write

O1(Ax)

t

OHZ

t

SS

t

SA

O3(Az)

O2(Az)

5279drw09

t

CD

,

6.42

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

15

NOTES:

1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.

2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external

address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined

by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.

3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

Timing Waveform of Write Cycle No. 1 - GW Controlled(1,2,3)

A

DDRESS

CLK

ADSP

ADSC

t

CYC

t

SS

t

HS

t

CH

t

CL

t

HA

t

SA

AxAyAz

ADV

D

ATA

OUT

OE

t

HC

t

SD

I1(Ax)I1(Az)

I2(Ay)

tHD

t

OHZ

DATA

IN

t

HAV

O3(Aw)O4(Aw)

CE,CS

1

t

HW

GWt

SW

(Note3)

I2(Az)

BurstWrite

BurstReadBurstWrite

Single

Write

I3(Az)

I4(Ay)

I3(Ay)

I2(Ay)

t

SAV

(ADVHIGHsuspendsburst)

I1(Ay)

GWisignoredwhenADSPinitiatesacycleandissampledonthenextclockrisingedge

t

SC

5279drw10

,

6.42

16

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2 - Byte Controlled(1,2,3)

A

DDRESS

CLK

ADSP

ADSC

t

CYC

t

SS

t

HS

t

CH

t

CL

t

HA

t

SA

AxAy

t

HW

BWx

ADV

DATA

OUT

OE

t

HC

t

SD

Single

WriteBurstWrite

I1(Ax)I2(Ay)I2(Ay)

(ADVsuspendsburst)

I2(Az)

tHD

Burst

ReadExtended

BurstWrite

t

OHZ

DATA

IN

t

SAV

t

SW

O4(Aw)

CE,CS

1

t

HW

BWEt

SW

(Note3)

I1(Az)

Az

I4(Ay)

I1(Ay)I4(Ay)

I3(Ay)

t

SC

BWEisignoredwhenADSPinitiatesacycleandissampledonnextclockrisingedge

BWxisignoredwhenADSPinitiatesacycleandissampledonnextclockrisingedge

I3(Az)

O3(Aw)

5279drw11

,

NOTES:

1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.

2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external

address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined

by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.

3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

6.42

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

17

Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)

t

CYC

t

SS

t

CL

t

CH

t

HA

t

SA

t

SC

t

HC

t

OE

t

OLZ

t

HS

CLK

ADSP

ADSC

A

DDRESS

GW

CE,CS

1

ADV

DATA

OUT

OE

ZZ

SingleReadSnoozeMode

tZZPW

5279drw12

O1(Ax)

Ax

(Note4)

tZZR

Az

,

NOTES:

1. Device must power up in deselected Mode

2. LBO is Don't Care for this cycle.

3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.

4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

6.42

18

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

CLK

ADSP

GW,BWE,BWx

CE, CS

1

CS

0

ADDRESS

ADSC

DATA

OUT

OE

Av Aw Ax Ay Az

(Av) (Aw) (Ax) (Ay)

5279 drw 14

,

Non-Burst Read Cycle Timing Waveform

NOTES:

1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.

NOTES:

1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.

4. For write cycles, ADSP and ADSC have different limitations.

Non-Burst Write Cycle Timing Waveform

CLK

ADSP

GW

CE, CS

1

CS

0

ADDRESS

ADSC

DATA

IN

Av Aw Ax AzAy

(Av) (Aw) (Ax) (Az)(Ay)

5279 drw 15

,

6.42

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

19

JTAG Interface Specification (SA Version only)

TCK

Device Inputs

(1)

/

TDI/TMS

D

evice Outputs

(2)

/

TDO

TRST

(3)

t

JCD

t

JDC

t

JRST

t

JS

t

JH

t

JCYC

t

JRSR

t

JF

t

JCL

t

JR

t

JCH

M5279 drw 01

x

Symbol Parameter Min. Max. Units

t

JCYC

JTAG Clock Input Perio d 100

____

ns

t

JCH

JTAG Clock HIGH 40

____

ns

t

JCL

JTAG Clock Low 40

____

ns

t

JR

JTAG Clock Rise Time

____

5

(1)

ns

t

JF

JTAG Clock Fall Time

____

5

(1)

ns

t

JRST

JTAG Reset 50

____

ns

t

JRSR

JTAG Reset Recovery 50

____

ns

t

JCD

J TAG Data Outp ut

____

20 ns

t

JDC

JTAG Data Output Hol d 0

____

ns

t

JS

JTAG Setup 25

____

ns

t

JH

JTAG Hold 25

____

ns

I5 2 79 tb l 01

Reg i ster Nam e Bi t S i ze

Instruction (IR) 4

Bypass (BYR) 1

JTA G Id entific atio n (JIDR) 32

B ound ary Scan (BS R) Note (1)

I5279 tbl 03

NOTES:

1. Device inputs = All device inputs except TDI, TMS and TRST.

2. Device outputs = All device outputs except TDO.

3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.

NOTE:

1. The Boundary Scan Descriptive Language (BSDL) file for this device is available

by contacting your local IDT sales representative.

JTAG AC Electrical

Characteristics(1,2,3,4)

Scan Register Sizes

NOTES:

1. Guaranteed by design.

2. AC Test Load (Fig. 1) on external output signals.

3. Refer to AC Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.

6.42

20

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

Instruction Field Value Description

Revision Number (31:28) 0x2 Reserved for version number.

IDT De vic e ID (27:12) 0x238, 0x23A Defines IDT part numb er 71V3576SA and 71V3578SA, resp e ctive ly.

IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT.

ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register.

I5279 tbl 02

JTAG Identification Register Definitions (SA Version only)

Instruction Description OPCODE

EXTEST Forces contents of the bound ary scan cells onto the device outputs

(1)

.

Plac es the bo undary sc an re giste r (BSR) be twe en TDI and TDO. 0000

SAMPLE/PRELOAD

Plac es the bo undary sc an re giste r (BSR) be twe en TDI and TDO.

SAMPLE allows data from device inputs

(2)

and outputs

(1)

to be captured

in the b ound ary sc an ce lls and shifted serially thro ugh TDO. PRELOAD

all ow s d ata to be inp ut se rially into the b ound ary sc an c el ls v ia the TDI.

0001

DEVICE_ID Lo ad s the J TAG ID re g iste r (J IDR) with the v e ndo r ID co d e and p lace s

the register betwee n TDI and TDO. 0010

HIGHZ Places the bypass register (BYR) between TDI and TDO. Forces all

de vice output driv ers to a High-Z state. 0011

RESERVED

S eve ral c om b inatio ns are re se rv ed . Do n o t us e co de s o ther than tho se

id entifie d fo r E XTE ST, SA MP LE/ PRE LOA D, DE VICE_ID, HIGHZ, CLAMP,

VALIDATE an d B YPAS S i nstruc tio ns.

0100

RESERVED 0101

RESERVED 0110

RESERVED 0111

CLAMP Uses BYR. Forces contents of the bound ary scan cells onto the device

outputs. Places the byp ass registe r (BYR) between TDI and TDO. 1000

RESERVED

Same as ab ove.

1001

RESERVED 1010

RESERVED 1011

RESERVED 1100

VALIDATE Automatically loaded into the instruction register whenever the TAP

contro lle r p asses thro ugh the CAPTURE-IR state. The lowe r two b its '01'

are mandate d by the IEE E s td . 1149.1 s p ec ific atio n. 1101

RESERVED Same as ab ove . 1110

BYPASS The BYPASS ins truction is us ed to truncate the b ound ary sc an reg ister

as a single b it in le ngth. 1111

I5 2 79 tb l 04

Available JTAG Instructions

6.42

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

21

Ordering Information

100-pin Plastic Thin Quad Flatpack (TQFP)

119BallGridArray(BGA)

165 Fine Pitch Ball Grid Array (fBGA)

S

Power

X

Speed

XX

Package

PF*

BG

BQ

IDT XXX

150

133 Frequency in Megahertz

5279 drw 13

Device

Type

71V3576

71V3578 128K x 36 Pipelined Burst Synchronous SRAM with 3.3V I/O

256K x 18 Pipelined Burst Synchronous SRAM with 3.3V I/O

,

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Blank

I

X

Process/

Temperature

Range

S

SA Standard Power

Standard Power with JTAG Interface

Blank

YFirst generation or current stepping

Second generation die step

X

GRestricted hazardous substance device

* Note: JTAG (SA version) is not available with 100-pin TQFP package.

Package Information

100-Pin Thin Quad Plastic Flatpack (TQFP)

119 Ball Grid Array (BGA)

165 Fine Pitch Ball Grid Array (fBGA)

Information available on the IDT website

6.42

22

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Datasheet Document History

7/26/99 Updated to new format

9/17/99 Pg. 8 Revised ISB1 and IZZ for speeds 100–200MHz

Pg. 11 Revised tCDC (min.) at 166MHz

Pg. 18 Added 119 BGA package diagram

Pg. 20 Added Datasheet Document History

12/31/99 Pg. 1, 8, 11, 19 Removed 166, 183, and 200MHz speed grade offerings

(see IDT71V35761 and IDT71V35781)

Pg. 1, 4, 8, 11, 19 Added Industrial Temperature range offerings

04/04/00 Pg.18 Added 100TQFP Package Diagram Outline

Pg. 4 Add capacitancce table for the BGA package; Add Industrial temperature to table;

Insert note to Absolute Max Rating and Recommended Operating Temperature tables

Pg. 7 Add note to BGA pin configurations; corrected typo in pinout

06/01/00 Add new package offering, 13 x 15mm fBGA

Pg. 20 Correct BG119 Package Diagram Outline

07/15/00 Pg. 7 Add note reference to BG119 pinout

Pg. 8 Add DNU reference note to BQ165 pinout

Pg. 20 Update BG119 Package Diagram Outline Dimensions

10/25/00 Remove Preliminary Status

Pg. 8 Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST

04/22/03 Pg. 4 Updated 165 BGA table information from TBD to 7

06/30/03 Pg. 1,2,3,5-9 Updated datasheet with JTAG information

Pg. 5-8 Removed note for NC pins (38,39(PF package); L4, U4 (BG package) H2, N7 (BQ package))

requiring NC or connection to Vss.

Pg. 19,20 Added two pages of JTAG Specification, AC Electrical, Definitions and Instructions

Pg. 21-23 Removed old package information from the datasheet

Pg. 24 Updated ordering information with JTAG and Y stepping information. Added information

regarding packages available IDT website.

01/ /04 Pg.21 Added "Restricted hazardous substance device" to ordering information.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com

San Jose, CA 95138 408-284-8200 800-345-7015

fax: 408-284-2775

www.idt.com