NJW1110
– 1
–
9-Input 3-Output Stereo Audio Selector
!
!!
!
GENERAL DESCRIPTION !
!!
!
PACKAGE OUTLINE
NJW1110 is a 9-input 3-output stereo audio selector.
It includes three independent 9input-1output stereo
audio selectors and adjustable gain buffers.
NJW1110 performs superior audio characteristics
such as low distortion, low output noise and low
crosstalk. All of internal status and variables are
controlled by I
2
C BUS interface. And the slave
address selector is available for using two chips on
same serial Bus line. It is suitable for latest TV system
and others.
!
!!
!
APPLICATIONS
•FPD TV
•Car Audio System
•Monitor
!
!!
!
FEATURES
• Operating Voltage 7.5 to 15V
• Operating Current 8mA typ.
• 9-Input, 3-Output Stereo Audio Selector
• Low Distortion 0.0007% typ.
• Low Output Noise 116dBV typ.
• Low Crosstalk 110dB typ.
• Channel Separation 110dB typ.
• Variable Gain Buffer 0, 3 to 8dB/0.5dB step
• I
2
C Bus Interface (Comply with fast mode and 3V I/F)
• Selectable 2-Slave Address
• Bi-CMOS Technology
• Package Outline SSOP32
!
!!
!
BLOCK DIAGRAM
NJW1110V
26 25 2432 31 30 29 28 27 19 18 1723 22 21 20
7 8 9 1 2 3 4 5 6 14 15 1610 11 12 13
Vre f
I
2
C
Control
Logic
++++ +
++ + + +
GND
+
10µF10
µF10
µF10
µF10µF
100µF
10µF10
µF10
µF10
µF10µF
InA1 InA2 InA3 InA4 OutA3
InB1 InB2 InB3 InB4 V+
SCLSDA
8dB to 3dB
/ 0.5dBs tep
Gain
8dB to 3dB
/ 0.5dBs tep
Gain
GND
ADR
+
10µF
OutA2
+
10µF
OutA1
+
10µF
+
10µF
OutB3OutB2OutB1
+
10µF
8dB to 3dB
/ 0.5dBstep
Gain
8dB to 3dB
/ 0.5dBstep
Gain
8dB to 3dB
/ 0.5dBstep
Gain
8dB to 3dB
/ 0.5dBstep
Gain
+
10µF
InB5
+
10µF
InB6
+
10µF
InB7
+
10µF
InB8
+
10µF
InB9
++++
10µF10
µF10
µF10
µF
InA5 InA6 InA7 InA8
+
10µF
InA9
GND
50KΩX18
MUTE
MUTE
NJW1110
– 2 –
!
!!
! PIN CONFIGURATION
No. Symbol Function No. Symbol Function
1 InA1 Ach Input 1 17 V+ Power Supply Terminal
2 InA2
Ach Input 2
18 ADR Slave address setting terminal
3 InA3
Ach Input 3
19 GND GND Terminal
4 InA4
Ach Input 4
20 OutB3 Bch Output 3
5 InA5
Ach Input 5
21 OutB2 Bch Output 2
6 InA6
Ach Input 6
22 OutB1 Bch Output 1
7 InA7
Ach Input 7
23 Vref Reference Voltage
8 InA8
Ach Input 8
24 InB9
Bch Input 9
9 InA9
Ach Input 9
25 InB8
Bch Input 8
10 GND GND Terminal 26 InB7
Bch Input 7
11 OutA1 Ach Output 1 27 InB6
Bch Input 6
12 OutA2 Ach Output 2 28 InB5
Bch Input 5
13 OutA3 Ach Output 3 29 InB4
Bch Input 4
14 GND GND Terminal 30 InB3
Bch Input 3
15 SDA SDA Data Input (I
2
C BUS) 31 InB2
Bch Input 2
16 SCL SCL Clock Input (I
2
C BUS) 32 InB1
Bch Input 1
16
32
31
30
29
28
27
26
25
24
23
20
21
22
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
InA1
InA2
InA3
InA4
InB1
InB2
InB3
InB4
OutA1 OutB1
SDA
SCL
GND
Vref
V+
ADR 18
16 17
InA5
InA6
InA7
InA8
InB5
InB6
InB7
InB8
InA9 InB9
OutA2 OutB2
OutA3 OutB3
GND
GND
NJW1110
– 3 –
!
!!
!
ABSOLUTE MAXIMUM RATING (Ta=25°C)
PARAMETER SYMBOL RATING UNIT
Power Supply Voltage V
+
16 V
Maximum input voltage
V
IM
0 to V+
(∗)
V
Power Dissipation P
D
800
NOTE: EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting
mW
Operating Temperature Range Topr -40 to +85 °C
Storage Temperature Range Tstg -40 to +125 °C
(∗)
For the maximum input voltage less than V+.
!
!!
!
RECOMMENDED OPERATING CONDITIONS (Ta=25°C)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Operating Voltage V
+
- 7.5 9.0 15.0 V
!
!!
!
ELECTRICAL CHARACTERISTICS
♦
♦♦
♦Power Supply (Ta=25°C, V
+
=9V)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Supply Current I
CC
No Signal 4.0 8.0 12.0 MA
Reference Voltage V
REF
No Signal 4.0 4.5 5.0 V
♦
♦♦
♦AC CHARACTERISTICS (Ta=25°C, V
+
=9V, V
IN
=0dBV (0dBV=1Vrms), f=1kHz, R
L
=47k
Ω
)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Maximum Output Voltage V
OM
THD=1% 6.0
(2.0)
8.0
(2.5)
- dBV
(Vrms)
Voltage Gain 1 G
V1
- -1.0 0 1.0
Voltage Gain 2 G
V2
V
IN
=200mVrms, Gain=6dB 5.0 6.0 7.0
dB
Total Harmonic Distortion 1 THD1 BW=400Hz-30kHz - 0.001 0.02
Total Harmonic Distortion 2 THD2 f=10kHz, BW=400Hz-30kHz - 0.003 -
Total Harmonic Distortion 3 THD3 V
+
=12V, BW=400Hz-30kHz - 0.0007 -
%
Output Noise V
NO
Rg=0Ω, A-Weighted - -116
(1.6)
-106
(5.0)
dBV
(µVrms)
Cross Talk 1 CT1 Rg=0Ω, A-Weighted - -110 -
Cross Talk 2 CT2 Rg=0Ω, f=20kHz - -90 -
dB
Channel Separation 1 CS1 Rg=0Ω, A-Weighted - -110 -
Channel Separation 2 CS2 Rg=0Ω, f=20kHz - -90 -
dB
BW: Band Width
♦
♦♦
♦Logic Control Characteristics (Ta=25°C, V
+
=9V)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
High Level Input Voltage V
ADRH
ADR Terminal 2.5 - V
+
Low Level Input Voltage V
ADRL
ADR Terminal 0 - 1.5
V
NJW1110
– 4 –
!TIMING ON THE I
2
C BUS (SDA,SCL)
!CHARACTERISTICS OF I/O STAGES FOR I
2
C BUS (SDA,SCL)
I
2
C BUS Load Conditions
STANDARD MODE : Pull up resistance 4kΩ (Connected to +5V), Load capacitance 200pF (Connected to GND)
FAST MODE : Pull up resistance 4k
Ω
(Connected to +5V), Load capacitance 50pF (Connected to GND)
Standard mode Fast mode
PARAMETER SYMBOL
MIN. TYP. MAX. MIN. TYP. MAX.
UNIT
Low Level Input Voltage V
IL
0.0 - 1.5 0.0 - 1.5 V
High Level Input Voltage V
IH
2.7 - 5.0 2.7 - 5.0 V
Low level output voltage (3mA at SDA pin) V
OL
0 - 0.4 0 - 0.4 V
Input current each I/O pin with an input voltage
between 0.1V
DD
and 0.9V
DDmax
I
i
-10 - 10 -10 - 10 µA
SDA
SCL
t
f
t
HD:STA
t
LOW
t
r
t
HD:DAT
t
HIGH
t
f
t
SU:DAT
S
t
SU:STA
t
HD:STA
t
SP
t
SU:STO
Sr
t
r
t
BUF
PS
NJW1110
– 5 –
!CHARACTERISTICS OF BUS LINES (SDA,SCL) FOR I
2
C-BUS DEVICES
Standard mode Fast mode
PARAMETER SYMBOL
MIN. TYP. MAX. MIN. TYP. MAX.
UNIT
SCL clock frequency f
SCL
- - 100 - - 400 kHz
Hold time (repeated) START condition. t
HD:STA
4.0 - - 0.6 - - µs
Low period of the SCL clock t
LOW
4.7 - - 1.3 - - µs
High period of the SCL clock t
HIGH
4.0 - - 0.6 - - µs
Set-up time for a repeated START condition t
SU:STA
4.7 - - 0.6 - - µs
Data hold time
NOTE)
t
HD:DAT
0 - - 0 - - µs
Data set-up time t
SU:DAT
250 - - 100 - - ns
Rise time of both SDA and SCL signals t
r
- - 1000 - - 300 ns
Fall time of both SDA and SCL signals t
f
- - 300 - - 300 ns
Set-up time for STOP condition t
SU:STO
4.0 - - 0.6 - - µs
Bus free time between a STOP and START condition t
BUF
4.7 - - 1.3 - - µs
Capacitive load for each bus line C
b
- - 400 - - 400 pF
Noise margin at the Low level V
nL
0.5 - - 0.5 - - V
Noise margin at the High level
V
nH
1 - - 1 - -
V
C
b
; total capacitance of one bus line in pF.
NOTE). Data hold time : t
HD:DAT
Please hold the Data Hold Time (t
HD:DAT
) to 300ns or more to avoid status of unstable at SCL falling edge.
The SDA block in the NJW1110 does not hold data. Add external data-delay-circuit of the SDA terminal, in case of not
providing a hold time of at least 300nsec for the SDA in the master device.
The time-consists of the data-delay-circuit of the SDA terminal are as follows.
(a) Low level ! High level : T
LH
≈ R
P
*C
D
(b) High level ! Low level : T
HL
≈ R
D
*C
D
In addition, Schottky barrier diode (SBD) influences a Low level at the Acknowledge. Therefore choose the low forward
voltage (Vf) as much as possible.
MA STER
SCL
SDA
V
DD
R
P
R
P
R
D
SBD
C
D
NJW1110
NJW1110
– 6 –
!
!!
! DEFINITION OF I
2
C REGISTER
♦
♦♦
♦I
2
C BUS FORMAT
MSB LSB MSB LSB MSB LSB
S Slave Address A Select Address A Data A P
1bit 8bit 1bit 8bit 1bit 8bit 1bit 1bit
S: Starting Term
A: Acknowledge Bit
P: Ending Term
♦
♦♦
♦ SLAVE ADDRESS
MSB LSB
1 0 0 1 0 1 0 R/W
94H(ADR=Low)
1 0 0 1 0 1 1 R/W
96H(ADR=High)
R/W=0: Receive Only
R/W=0: Write mode for register setting
R/W=1: Not available
♦
♦♦
♦ CONTROL REGISTER TABLE
The select address and sets each function.
The auto increment function cycles the select address as follows.
00H
→
01H
→
02H
→
00H
BIT
Select
Address D7 D6 D5 D4 D3 D2 D1 D0
00H Variable Gain Buffer for OUT1 Input selector for OUT1
01H Variable Gain Buffer for OUT2 Input selector for OUT2
02H Variable Gain Buffer for OUT3 Input selector for OUT3
♦
♦♦
♦ CONTROL REGISTER DEFAULT VALUE
Control register default value is all “0”.
BIT
Select
Address D7 D6 D5 D4 D3 D2 D1 D0
00H 0 0 0 0 0 0 0 0
01H 0 0 0 0 0 0 0 0
02H 0 0 0 0 0 0 0 0
NJW1110
– 7 –
!
!!
! INPUT SELECTOR
"
""
" INPUT SELECTOR SETTING (OUT1:00H, OUT2:01H, OUT3:02H)
Signal Select
D3 D2 D1 D0
Mute 0 0 0 0
InA1/InB1 0 0 0 1
InA2/InB2 0 0 1 0
InA3/InB3 0 0 1 1
InA4/InB4 0 1 0 0
InA5/InB5 0 1 0 1
InA6/InB6 0 1 1 0
InA7/InB7 0 1 1 1
InA8/InB8 1 0 0 0
InA9/InB9 1 0 0 1
!
!!
! VARIABLE GAIN BUFFER
"
""
" VARIABLE GAIN BUFFER SETTING (OUT1:00H, OUT2:01H, OUT3:02H)
Gain (dB)
D7 D6 D5 D4
0 0 0 0 0
3.0 0 0 0 1
3.5 0 0 1 0
4.0 0 0 1 1
4.5 0 1 0 0
5.0 0 1 0 1
5.5 0 1 1 0
6.0 0 1 1 1
6.5 1 0 0 0
7.0 1 0 0 1
7.5 1 0 1 0
8.0 1 0 1 1
NJW1110
– 8 –
!
!!
! APPLICATION CIRCUIT
26 25 2432 31 30 29 28 27 19 18 1723 22 21 20
7 8 9 1 2 3 4 5 6 14 15 1610 11 12 13
Vre f
I
2
C
Control
Logic
++++ +
++ + + +
GND
+
10µF10
µF10
µF10
µF10µF
100µF
10µF10
µF10
µF10
µF10µF
InA1 In A2 In A3 In A4 OutA3
InB1 InB2 InB3 InB4 V+
SCLSDA
8dB to 3dB
/ 0.5dBstep
Gain
8dB to 3dB
/ 0.5dBstep
Gain
GND
ADR
+
10µF
OutA2
+
10µF
OutA1
+
10µF
+
10µF
OutB3OutB2Ou tB1
+
10µF
8dB to 3dB
/ 0.5dBstep
Gain
8dB to 3dB
/ 0.5dBstep
Gain
8dB to 3dB
/ 0.5dBstep
Gain
8dB to 3dB
/ 0.5dBstep
Gain
+
10µF
InB5
+
10µF
InB6
+
10µF
InB7
+
10µF
InB8
+
10µF
InB9
++++
10µF10
µF10
µF10
µF
InA5 InA6 InA7 InA8
+
10µF
InA9
GND
50KΩX18
MUTE
MUTE
NJW1110
– 9 –
!
!!
! TYPICAL CHARACTERISTICS
Maximum Output Voltage vs Frequency
V
+
=9V, THD =1%, I/O: INA1- 1Aout
2.2
2.4
2.6
2.8
10 100 1000 10000 100000
Frequency [Hz]
Maximum Output Voltage [Vrms
]
-40
o
C-20
o
C25
o
C
50
o
C85
o
C
Output Voltage vs Load Resistance
V
+
=9V, f=1kH z, VOL= 0dB,
I/O: INA1-1Aout ,T= 85,50,25,- 20,- 40
o
C
1
2
3
4
100 1000 10000 100000
RL[Ω]
Maximum Output Voltage [Vrms
]
-40
o
C
85
o
C
25
o
C
-20
o
C
Volum e Gain Output vs Volum e Setting
V
+
=9V, Vi n=1Vrms
f=1kHz, I/O: INA1-1Aout, T=85,50,25,-20,-40
o
C
0
1
2
3
4
5
6
7
8
012345678
Volume Setting [dB]
Volume Gain Output [dB]
ICC vs Supply Voltage
No signal
0
5
10
0 5 10 15 20
Supply Voltage [V]
ICC [mA
]
-20
o
C
0 to 85
o
C
-40
o
C
VREF vs Supply Voltage
No sig nal, T=85,50,25,-20,-40
o
C
0
5
10
0 5 10 15 20
Supply Voltage [V]
VREF[V]
Maximum Output Voltage vs Supply Voltage
V
+
=9V, T HD= 1%,I/O: IN A1- 1Aout,T= 85,50,25,- 20,- 40
o
C
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0 5 10 15 20
Supply Voltage [+V]
Maximum Output Voltage [Vrms
]
NJW1110
– 10 –
!
!!
! TYPICAL CHARACTERISTICS
Volume Gain output vs Frequency
V
+
=9V, Vin=1Vrms,
I/O: IN A1-1Aout, T= 85,50,25,- 20,- 40
o
C
-1
0
1
2
3
4
5
6
7
8
9
10
10 100 1000 10000 100000 1000000
Frequency [Hz]
Volume Gain Output [dB]
VOL= 8dB
VOL= 6dB
VOL= 3dB
VOL= 0dB
THD+N vs Inp u t V o ltage
V
+
=9V, BW:10-22kHz(f=100Hz), 400-30kHz(f=1kHz, 10kHz),
I/O: INA1-1Aout, T=85,50,25,-20,-40
o
C
0.0001
0.001
0.01
0.1
1
10
0.01 0.1 1 10
Input Voltage [Vrms]
THD+N [%
]
f=10kHz
f=100Hz
f=1kHz
THD+N vs Input Voltage
V
+
=9V, f=1kHz, BW:400-30kHz, I/O: INA1-1Aout
T=85,50,25,-20,-40℃
0.0001
0.001
0.01
0.1
1
10
0.01 0.1 1 10
Input Voltage [Vrms]
THD+N [%
]
VOL= 8dB
VOL= 6dB
VOL= 3dB
VOL=0dB
THD+N vs Fr e que n cy
V
+
=9V, f=1kHz, BW:10- 80kHz, Vin=1Vrms
I/O: IN A1-1Aout, T= 85,50,25,- 20,- 40
o
C
0.0001
0.001
0.01
0.1
1
10
10 100 1000 10000 100000
Frequency [Hz]
THD+N [%
]
Cross Talk vs Frequency
V
+
=9V, Vin=1Vrms, VOL=0dB, BW:10-80kHz,
I/O: IN A13456789-1Aout,Sel ect channel :INA2, T= 25
o
C
-120
-100
-80
-60
-40
10 100 1000 10000 100000
Frequency [Hz]
Cross Talk[dB
]
Rg=0Ω
Rg=620Ω
Rg=3.3kΩ
Rg=5.1kΩ
Channel Separation vs Frequency
V
+
=9V, Vi n=1Vrms, VOL=0dB, BW:10- 80kHz,
I/O: INB1-1Aout, T=25
o
C
-120
-100
-80
-60
-40
10 100 1000 10000 100000
Frequency [Hz]
Channel Separation[dB]
Rg=0Ω
Rg=620Ω
Rg=3.3kΩ
Rg=5.1kΩ
NJW1110
– 11 –
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
