©2001 Fairch ild Semicond uctor C orpo ration HUF75321P3, HUF75321S3S Rev. B
HUF75321P3, HUF75321S3S
35A, 55 V, 0.034 Ohm, N-Channel UltraFET
Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
inno vat ive UltraFET ® process . This
advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstandi ng performance . This device is capable
of withstanding high ene r gy in the ava lanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
v oltage bus switches, and power manag ement in portab le
and battery-operated products.
Formerly developmental type TA75321.
Features
• 35A, 55V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Models
- Thermal Impedance SPICE and SABER Models
A vailable on the WEB at: www .fairchildsemi.com
• Peak Cu rrent vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “G uid eli ne s for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC TO-220AB JEDEC TO-263AB
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Autom otive HUF A series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 an d QS9000 quality systems c e rtification.
Ordering Information
PART NUMBER PACKAGE BRAND
HUF75321P3 TO-220AB 75321P
HUF75321S3S TO-263AB 75321S
NOTE: When ordering, use the entire part number . Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF75321S3ST.
D
G
S
DRAIN
SOURCE
GATE
DRAIN
(FLANGE)
DRAIN
(FLANGE)
GATE
SOURCE
Data Sheet December 2001
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©2001 Fairch ild Semicond uctor C orpo ration HUF75321P3, HUF75321S3S Rev. B
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . VDSS 55 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . VDGR 55 V
Gate to Source Vo ltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 35
Figure 4 A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
0.625 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG -55 t o 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
CAUTION: Str esses above those l isted in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess on ly rating and operation o f the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TC = 25oC, Unles s Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source B reakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 55 - - V
Zero Gate Vo ltage Drain C urrent IDSS VDS = 50V, VGS = 0V - - 1 µA
VDS = 45V, VGS = 0V, TC = 150oC--250µA
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V
Drain to Source On Resist ance rDS(ON) ID = 35A, VGS = 10V (Figure 9) - 0.028 0.034 Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case RθJC (Figure 3) - - 1.6 oC/W
Thermal Resistance Junction to Ambient RθJA TO-220, TO-263 - - 62 oC/W
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time tON VDD = 30V, ID ≅ 35A,
RL = 0.86Ω, VGS = 10V,
RGS = 25Ω
--100ns
Turn-On De lay Time td(ON) -11- ns
Rise Time tr-55- ns
Turn-Off De lay Time td(OFF) -47- ns
Fall Tim e tf-66- ns
Turn-Off T ime tOFF --170ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 30V,
ID ≅ 35A,
RL = 0.86Ω
Ig(REF) = 1.0mA
(Figure 13)
-3644nC
Gate Charge at 10V Qg(10) VGS = 0V to 10V - 21 26 nC
Threshold Gate Charge Qg(TH) VGS = 0 V to 2V - 1.3 1.6 nC
Gate to Source Gate C harge Qgs -3-nC
Reverse Transfer Capacitance Qgd -9-nC
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CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
- 680 - pF
Output Capacitance COSS - 270 - pF
Reverse Transfer Capacitance CRSS -60-pF
Electrical Specifications TC = 25oC, Unles s Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to D rain Diode Volt age VSD ISD = 35A - - 1.25 V
Reverse Recovery Time trr ISD = 35A, dISD/dt = 100A/µs--59ns
Reverse Recovered Charge QRR ISD = 35A, dISD/dt = 100A/µs--82nC
Typical Performance Curves
FIGURE 1. NORMALIZED PO WER DISSIPA TI ON vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125 17
5
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
10
20
30
50 75 100 125 150 175
025
40
t, RECTANGULAR PULSE DURATION (s)
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1t2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
10-4 10-3 10-2 10-1 100101
10-5
0.1
1
2
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
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FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA NOT E: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. TRANSFER CHARA C TERISTICS
Typical Performance Curves (Continued)
101
100
10-1
10-2
10-3
10-4
10-5
10
100
500 TC = 25oC
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
VGS = 20V
10
100
300
10 100
11 200
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
TJ = MAX RATED
TC = 25oC
100µs
10ms
1ms
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
VDSS(MAX) = 55V
SINGLE PULSE
0.10.001
300
10
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVAL ANCHE (ms)
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
0.01
1
100
03.04.57.
5
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 5V
0
15
30
75
6.01.5
60
45
VGS = 6V
VGS = 1 0V
VGS = 2 0V
VGS = 8 V
VGS = 7 V
TC = 25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0 3.0 4.5 6.0 7.
5
1.5
0
15
30
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
75
45
60
-55oC
175oC
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FIGURE 9. NORMALIZED DRAIN T O SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED GATE THRESHOLD VOLTA GE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN T O SOURCE BREAKDO WN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOT E: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Typical Performance Curves (Continued)
1.0
1.5
2.0
2.5
-40 0 40 80 120 160 200
0.5-80
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
VGS = 10V, ID = 35A
PULSE DURATION = 80µs
DUTY CYCLE = 0 .5% MAX
0.8
1.0
1.2
-40 0 40 80 120 160 200
0.6
-80
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
0.9
1.0
1.1
1.2
-40 0 40 80 120 160 200-80
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
ID = 250µA
BREAKDOWN VOLTAGE
800
400
00 1020304050
C, CAPACITANCE (pF)
600
VDS, DRAIN TO SOURCE VOLTAGE (V)
200
CISS
COSS
CRSS
60
1000 VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
10
8
6
4
0
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = 30V
2
15 200
Qg, GATE CHARGE (nC)
510
ID = 35A
ID = 17.5A
ID = 8.75A
WAVEFORMS IN
DESCENDING ORDER:
25
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Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PE AK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
RL
VGS +
-
VDS
VDD
DUT
IG(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20
V
VDS
VGS
I
g(REF)
0
0
Qgs Qgd
VGS
RL
RGS DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
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©2001 Fairch ild Semicond uctor C orpo ration HUF75321P3, HUF75321S3S Rev. B
PSPICE Ele ctrical Model
.SUBCKT HUF75321P 2 1 3 ; rev 4/29/98
CA 12 8 9.96e-10
CB 15 14 9.83e-10
CIN 6 8 6.18e-10
DBODY 7 5 DBODYMOD
DBRE AK 5 11 D B REAK MOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 59.54
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTH R ES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRA IN 2 5 1e- 9
LGATE 1 9 3.57e-9
LSOURCE 3 7 4.25e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 5.50e-3
RGATE 9 20 2.25
RLDRAIN 2 5 10
RLGATE 1 9 35.7
RLSOURCE 3 7 42.5
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 16.30e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTE M P 18 19 RVTE MPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMO D
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMO D
VBAT 22 1 9 DC 1
ESL C 51 50 VAL UE={( V(5,51 )/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*101),2.5))}
.MODEL DBOD YMOD D (IS = 7.47e-13 RS = 6.45e-3 TRS1 = 2.01e-3 TRS2 = 1.21e-6 CJO = 1.02e-9 TT = 3.21e-8 M = 0 .50)
.MODEL DBREAKMOD D (RS = 2.01e- 1TRS1 = 3.62e- 3TRS2 = 6.01e-7)
.MODEL DPLCAPMOD D (CJO = 9.0e-1 0IS = 1e-3 0N = 10 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 1.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.25)
.MODEL MST ROMOD NMOS (VTO = 3.65 KP = 32.00 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD N MOS ( VTO = 2 .91 KP = 0. 07 IS = 1e-3 0 N = 10 TO X = 1 L = 1u W = 1u RG = 22.5 RS = 0 . 1 )
.MODEL RBREAK MOD RES (TC1 = 1.05e - 3TC2 = 1.21e-7)
.MODEL RDRAINMOD RES (TC1 = 2.40e-2 TC2 = 1.02e-6)
.MODEL RSLCMOD RES (TC1 = 2.07e-4 TC2 = 4.67e-5)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 =0)
.MODEL RVTHRESMOD RE S (TC = -3.01e-3 TC2 = -8.85e-6)
.MODEL RVTEMPMO D RE S (TC1 = -1.96e- 3TC2 = 1.39e-6)
.MODEL S1AMOD VS WITCH (RON = 1e-5 ROFF = 0.1 VO N = -7.85 VOFF = -4.85)
.MODEL S1BMOD VS WITCH (RON = 1e-5 ROFF = 0.1 VO N = -4.85 VOFF = -7.85)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0. 1 VON = 0.00 VOFF= 3.00)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0. 1 VON = 3.00 VOFF= 0.00)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New P SPICE Sub-Circu i t for the Power MOSFET Feat uring Global
Temperature Options; IEEE Po wer Electronics Specialist Conference Records, 1991, writ ten by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
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SABER Electrical Model
REV April 1998
template huf75321p n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 7.47e-13, cjo = 1.02e-9, tt = 3.21e-8, m = 0.5 )
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 9e-10, is = 1e-3 0, n = 10, m = 0.85)
m..model mmedmod = (type=_n, vto = 3.25, kp = 1.75, is = 1e-30, to x = 1)
m..model mstrongmod = (type=_n, vto = 3.65, kp = 32, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.91, kp = 0.07, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.85, voff = -4.85)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -4.85, voff = -7.85)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 3.0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 3.0, voff = 0)
c.ca n12 n8 = 9.96e-10
c.cb n15 n14 = 9.83e-10
c.cin n6 n8 = 6.18e-10
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dpl capmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lga te n1 n9 =3.57e- 9
l.lsourc e n3 n7 = 4.25e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = 1.21e-7
res.rdbody n71 n5 = 6.45e-3, tc1 = 2.01e-3, tc2 = 1.21e-6
res.rdbreak n72 n5 = 2.01e-1, tc1 = 3.62e-3, tc2 = 6.01e-7
res.rdrain n50 n16 = 5.5e-3, tc1 = 2.4e-2, tc2 = 1.02e-6
res.rgate n9 n20 = 2.25
res.r ldrain n2 n5 = 10
res.rlgate n1 n9 = 35.7
res.rlsource n3 n7 = 42.5
res.rs lc1 n5 n51 = 1e-6, tc1 = 2.07e-4, tc2 = 4.67e-5
res.r slc2 n5 n50 = 1e3
res. rsour c e n8 n7 = 16. 3e-3, tc 1 = 0, tc2 = 0
res.rv temp n18 n19 = 1, tc1 = -1.96e- 3, tc2 = 1.39e-6
res.rvthres n22 n8 = 1, tc1 = -3.01e-3, tc2 = -8.85e-6
spe.ebreak n11 n7 n17 n18 = 59.54
spe.e ds n14 n8 n5 n8 = 1
spe.e gs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/101))** 2.5))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
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SPICE Thermal Model
REV 24 February 1999
HUF75321P
CTHERM1 th 6 2.7e-3
CTHERM2 6 5 3 .7e-3
CTHERM3 5 4 1 .2e-2
CTHERM4 4 3 3 .8e-3
CTHERM5 3 2 1 .4e-2
CTHERM6 2 tl 10.55
RTHERM1 th 6 1.10e-2
RTHERM2 6 5 2 .72e-2
RTHERM3 5 4 7 .67e-2
RTHERM4 4 3 4 .30e-1
RTHERM5 3 2 6 .49e-1
RTHERM6 2 tl 8.61e-2
SABER Thermal Model
SABER thermal model HUF75321P
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm 1 t h 6 = 2.7e-3
ctherm.ctherm 2 6 5 = 3.7e- 3
ctherm.ctherm 3 5 4 = 1.2e- 2
ctherm.ctherm 4 4 3 = 3.8- 3
ctherm.ctherm 5 3 2 = 1.4e- 2
ctherm.ctherm6 2 tl = 10.55
rtherm.rtherm1 th 6 = 1.10e-3
rtherm.rtherm2 6 5 = 2.72e-2
rtherm.rtherm3 5 4 = 7.67e-2
rtherm.rtherm4 4 3 = 4.30e-1
rtherm.rtherm5 3 2 = 6.49e-1
rtherm.rtherm6 2 t l = 8.61e- 2
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
HUF75321P3, HUF75321S3S
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