MF1085-03
Technical Manual
CMOS 4-BIT SINGLE CHIP MICROCOMPUTER
S1C63158 Technical Hardware
S1C63158
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any
liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such
as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there
is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
© SEIKO EPSON CORPORATION 2001, All rights reserved.
Revisions and Additions for this manual
Section
7.1
A.1
A.2
A.3
Page
109
122
125
127
Item
Absolute Maximum Rating
(5) CR oscillation frequency adjusting control
(6) CR oscillation frequency monitor pins
Table A.2.1 I/O connector pin assignment
(3) Functional precautions
Contents
A rated value was modified.
The sentence was deleted.
The diagram was revised.
The table was revised.
The sentence was deleted.
The diagram was revised.
Chapter
7
Appendix
S1C63158 Technical Manual
The information of the product number change
Configuration of product number
Devices
Comparison table between new and previous number
S1C63 Family processors
Starting April 1, 2001, the product number has been changed as listed below. Please use the new
product number when you place an order. For further information, please contact Epson sales
representative.
S1 C 63158 F 0A01
Packing specification
Specification
Package (D: die form; F: QFP)
Model number
Model name (C: microcomputer, digital products)
Product classification (S1: semiconductor)
Development tools
S5U1 C 63000 A1 1
Packing specification
Version (1: Version 1 ∗2)
Tool type (A1: Assembler Package ∗1)
Corresponding model number
(63000: common to S1C63 Family)
Tool classification (C: microcomputer use)
Product classification
(S5U1: development tool for semiconductor products)
∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)
∗2: Actual versions are not written in the manuals.
Previous No.
E0C63158
E0C63256
E0C63358
E0C63P366
E0C63404
E0C63406
E0C63408
E0C63F408
E0C63454
E0C63455
E0C63458
E0C63466
E0C63P466
New No.
S1C63158
S1C63256
S1C63358
S1C6P366
S1C63404
S1C63406
S1C63408
S1C6F408
S1C63454
S1C63455
S1C63458
S1C63466
S1C6P466
S1C63 Family peripheral products
Previous No.
E0C63467
E0C63557
E0C63558
E0C63567
E0C63F567
E0C63658
E0C63666
E0C63F666
E0C63A08
E0C63B07
E0C63B08
E0C63B58
New No.
S1C63467
S1C63557
S1C63558
S1C63567
S1C6F567
S1C63658
S1C63666
S1C6F666
S1C63A08
S1C63B07
S1C63B08
S1C63B58
Previous No.
E0C5250
E0C5251
New No.
S1C05250
S1C05251
Comparison table between new and previous number of development tools
Development tools for the S1C63 Family Development tools for the S1C63/88 Family
Previous No.
ADP63366
ADP63466
ASM63
GAM63001
ICE63
PRC63001
PRC63002
PRC63004
PRC63005
PRC63006
PRC63007
URS63366
New No.
S5U1C63366X
S5U1C63466X
S5U1C63000A
S5U1C63000G
S5U1C63000H1
S5U1C63001P
S5U1C63002P
S5U1C63004P
S5U1C63005P
S5U1C63006P
S5U1C63007P
S5U1C63366Y
Previous No.
ADS00002
GWH00002
URM00002
New No.
S5U1C88000X1
S5U1C88000W2
S5U1C88000W1
S1C63 Family
00
00
S1C63158 TECHNICAL MANUAL EPSON i
CONTENTS
CONTENTS
CHAPTER 1OUTLINE ________________________________________________ 1
1.1 Features.........................................................................................................1
1.2 Block Diagram ..............................................................................................2
1.3 Pin Layout Diagram .....................................................................................3
1.4 Pin Description .............................................................................................4
1.5 Mask Option.................................................................................................. 4
CHAPTER 2POWER SUPPLY AND INITIAL RESET ____________________________ 7
2.1 Power Supply ................................................................................................7
2.1.1 Voltage <VD1> for oscillation circuit and internal circuits ...................... 7
2.1.2 Voltage source for oscillation system voltage regulator............................ 8
2.1.3 Voltage sour ce for A/D con verter............................................................... 8
2.2 Initial Reset ................................................................................................... 9
2.2.1 Reset terminal (RESET) ............................................................................. 9
2.2.2 Simultaneous low input to terminals K00–K03 ........................................ 10
2.2.3 Internal register at initial resetting........................................................... 10
2.2.4 Terminal settings at initial resetting ......................................................... 11
2.3 Test Terminal (TEST) ...................................................................................11
CHAPTER 3 CPU, ROM, RAM________________________________________ 12
3.1 CPU..............................................................................................................12
3.2 Code ROM....................................................................................................12
3.3 RAM .............................................................................................................12
CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION__________________________ 14
4.1 Memory Map................................................................................................14
4.2 Setting of Power Supply and Operating Mode ............................................21
4.2.1 Control of supply voltage .......................................................................... 21
4.2.2 Operating mode for the oscillation system voltage regulator
and the internal operating voltage ........................................................... 21
4.2.3 Operating mode for A/D converter ........................................................... 22
4.2.4 I/O memory of power supply and operating mode ................................... 23
4.2.5 Programming notes ................................................................................... 24
4.3 Watchdog Timer ...........................................................................................25
4.3.1 Configuration of watchdog timer.............................................................. 25
4.3.2 Interrupt function ...................................................................................... 25
4.3.3 I/O memory of watchdog timer ................................................................. 26
4.3.4 Programming notes ................................................................................... 26
4.4 Oscillation Circuit ....................................................................................... 27
4.4.1 Configuration of oscillation circuit .......................................................... 27
4.4.2 OSC1 oscillation circuit............................................................................ 28
4.4.3 OSC3 oscillation circuit............................................................................ 29
4.4.4 Switching of operating voltage ................................................................. 30
4.4.5 Clock frequency and instruction execution time....................................... 31
4.4.6 I/O memory of oscillation circuit.............................................................. 31
4.4.7 Programming notes ................................................................................... 32
ii EPSON S1C63158 TECHNICAL MANUAL
CONTENTS
4.5 Input Ports (K00–K03, K10–K13 and K20) ................................................ 33
4.5.1 Configuration of input ports ..................................................................... 33
4.5.2 Interrupt function ...................................................................................... 34
4.5.3 Mask option ............................................................................................... 35
4.5.4 I/O memory of input ports......................................................................... 36
4.5.5 Programming notes ................................................................................... 39
4.6 Output Ports (R00–R03, R10–R13 and R20–R23) ......................................40
4.6.1 Configuration of output ports ................................................................... 40
4.6.2 Mask option ............................................................................................... 40
4.6.3 High impedance control ............................................................................ 41
4.6.4 Special output ............................................................................................ 41
4.6.5 I/O memory of output ports....................................................................... 43
4.6.6 Programming notes ................................................................................... 45
4.7 I/O Ports (P00–P03, P10–P13, P20–P23, P30–P33 and P40–P43)..........46
4.7.1 Configuration of I/O ports ........................................................................ 46
4.7.2 Mask option ............................................................................................... 47
4.7.3 I/O control registers and input/output mode ............................................ 47
4.7.4 Pull-up during input mode ........................................................................ 47
4.7.5 I/O memory of I/O ports............................................................................ 48
4.7.6 Programming note..................................................................................... 51
4.8 Clock Timer .................................................................................................. 52
4.8.1 Configuration of clock timer ..................................................................... 52
4.8.2 Data reading and hold function ................................................................ 52
4.8.3 Interrupt function ...................................................................................... 53
4.8.4 I/O memory of clock timer ........................................................................ 54
4.8.5 Programming notes ................................................................................... 56
4.9 A/D Converter .............................................................................................. 57
4.9.1 Characteristics and configuration of A/D converter ................................ 57
4.9.2 Terminal configuration of A/D converter.................................................. 57
4.9.3 Mask option ............................................................................................... 58
4.9.4 Control of A/D converter........................................................................... 58
4.9.5 Interrupt function ...................................................................................... 60
4.9.6 I/O memory of A/D converter.................................................................... 61
4.9.7 Programming notes ................................................................................... 63
4.10 Programmable Timer ................................................................................... 64
4.10.1 Configuration of programmable timer.................................................... 64
4.10.2 Tow separate 8-bit timer (MODE16 = "0") operation........................... 65
4.10.2.1 Setting of initial value and counting down .............................. 65
4.10.2.2 Counter mode............................................................................ 66
4.10.2.3 Setting of input clock in timer mode......................................... 67
4.10.2.4 Interrupt function...................................................................... 68
4.10.2.5 Setting of TOUT output............................................................. 68
4.10.2.6 Transfer rate setting for serial interface .................................. 69
4.10.3 One channel
×
16-bit timer (MODE16 = "1") operation ...................... 69
4.10.3.1 Setting of initial value and counting down .............................. 69
4.10.3.2 Counter mode............................................................................ 70
4.10.3.3 Setting of input clock in timer mode......................................... 71
4.10.3.4 Interrupt function...................................................................... 72
4.10.3.5 Setting of TOUT output............................................................. 72
4.10.3.6 Transfer rate setting for serial interface .................................. 73
4.10.4 I/O memory of prog rammable timer ....................................................... 74
4.10.5 Programming notes ................................................................................. 79
4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)................................................ 80
4.11.1 Configuration of serial interface ............................................................ 80
4.11.2 Mask option ............................................................................................. 81
4.11.3 Master mode and slave mode of serial interface.................................... 81
4.11.4 Data input/output and interrupt function ............................................... 82
S1C63158 TECHNICAL MANUAL EPSON iii
CONTENTS
4.11.5 I/O memory of serial interface................................................................ 85
4.11.6 Programming notes ................................................................................. 88
4.12 Buzzer Output Circuit .................................................................................. 89
4.12.1 Configuration of buzzer output circuit.................................................... 89
4.12.2 Mask option ............................................................................................. 89
4.12.3 Control of buzzer output.......................................................................... 90
4.12.4 I/O memory of buzzer output circuit ....................................................... 91
4.12.5 Programming note................................................................................... 91
4.13 SVD (Supply Voltage Detection) Circuit...................................................... 92
4.13.1 Configuration of SVD circuit .................................................................. 92
4.13.2 SVD operation ......................................................................................... 92
4.13.3 I/O memory of SVD circuit...................................................................... 93
4.13.4 Programming notes ................................................................................. 93
4.14 Interrupt and HALT .....................................................................................94
4.14.1 Interrupt factor........................................................................................ 96
4.14.2 Interrupt mask ......................................................................................... 97
4.14.3 Interrupt vector ....................................................................................... 97
4.14.4 I/O memory of interrupt .......................................................................... 98
4.14.5 Programming notes ................................................................................ 100
CHAPTER 5SUMMARY OF NOTES ______________________________________ 101
5.1 Notes for Low Current Consumption..........................................................101
5.2 Summary of Notes by Function...................................................................102
5.3 Precautions on Mounting ...........................................................................106
CHAPTER 6BASIC EXTERNAL WIRING DIAGRAM ___________________________ 108
CHAPTER 7ELECTRICAL CHARACTERISTICS _______________________________ 109
7.1 Absolute Maximum Rating.......................................................................... 109
7.2 Recommended Operating Conditions......................................................... 109
7.3 DC Characteristics .....................................................................................110
7.4 Analog Circuit Characteristics and Power Current Consumption ............111
7.5 Oscillation Characteristics......................................................................... 112
7.6 Serial Interface AC Characteristics ...........................................................115
7.7 Timing Chart ............................................................................................... 116
CHAPTER 8PACKAGE _______________________________________________ 117
8.1 Plastic Package ...........................................................................................117
8.2 Ceramic Package for Test Samples.............................................................119
CHAPTER 9PAD LAYOUT ____________________________________________ 120
9.1 Diagram of Pad Layout...............................................................................120
9.2 Pad Coordinates.......................................................................................... 120
APPENDIX
S5U1C63000P M
ANUAL
(P
ERIPHERAL
C
IRCUIT
B
OARD
FOR
S1C63158/358/P366) _
121
A.1 Names and Functions of Each Part ............................................................121
A.2 Connecting to the Target System ................................................................124
A.3 Usage Precautions ...................................................................................... 126
A.3.1 Operational precautions .......................................................................... 126
A.3.2 Differences with the actual IC ................................................................. 126
S1C63158 TECHNICAL MANUAL EPSON 1
CHAPTER 1: OUTLINE
CHAPTER 1OUTLINE
The S1C63158 is a microcomputer which has a high-performance 4-bit CPU S1C63000 as the core
CPU, ROM (8,192 words × 13 bits), RAM (512 words × 4 bits), serial interface, watchdog timer, program-
mable timer, time base counter (1 system), SVD circuit, a 4-channel A/D converter and a special input
port that can implement key position discrimination function using with the A/D converter. The
S1C63158 features low voltage/high speed (4 MHz Max.) operation and low current consumption (2 µA
Typ. in HALT mode), this makes it suitable for battery driven portable equipment such as a head phone
stereo.
1.1 Features
OSC1 oscillation circuit ......................
32.768 kHz (Typ.) Crystal oscillation circuit or CR oscillation circuit (∗1)
OSC3 oscillation circuit ...................... 2 MHz (Typ.) CR or Ceramic oscillation circuit (∗1)
Instruction set ..................................... Basic instruction: 46 types (411 instructions with all)
Addressing mode: 8 types
Instruction execution time................... During operation at 32.768 kHz: Min. 61 µsec
During operation at 4 MHz: Min. 0.5 µsec
ROM capacity ..................................... Code ROM: 8,192 words × 13 bits
RAM capacity...................................... Data memory: 512 words × 4 bits
Input port............................................. 9 bits 8 bits (Pull-up resistors may be supplemented ∗1)
1 bit (Input interrupt for key position sensing by A/D)
Output port.......................................... 12 bits (It is possible to switch the 2 bits to special output ∗2)
I/O port................................................ 20 bits (It is possible to switch the 4 bits to serial input/output ∗2)
(It is possible to switch the 4 bits to A/D input ∗2)
Serial interface.................................... 1 port (8-bit clock synchronous system)
Time base counter.............................. 1 system (Clock timer)
Programmable timer ........................... Built-in, 2 channels × 8 bits, with event counter function
or 1 channel × 16 bits (∗2)
Watchdog timer................................... Built-in
A/D converter...................................... 8-bit resolution
Maximum error: ±3 LSB, A/D clock: Max. 1MHz
(0.9 to 3.6 V, VC2 mode should be set when the supply voltage is 1.6 V or less.)
Buzzer output...................................... Buzzer frequency: 2 kHz or 4 kHz (∗2), 2 Hz interval (∗2)
Supply voltage detection (SVD) circuit.. 16 values, programmable (1.05 V to 2.60 V)
External interr upt ................................ Input port interrupt: 2 systems
Key sensing interrupt: 1 system
Internal interr upt ................................. Clock timer interrupt: 4 systems
Programmable timer interrupt: 2 systems
Serial interface interrupt: 1 system
A/D converter: 1 system
Power supply voltage.......................... 0.9 V to 3.6 V
Operating temperature range ............. -20°C to 85°C
Current consumption (Typ.) ................ Single clock:
During HALT (32 kHz) 1.5 V (normal mode) 2 µA
During operation (32 kHz) 1.5 V (normal mode) 4 µA
Twin clock:
During operation (4 MHz) 3.0 V (normal mode) 900 µA
Package .............................................. QFP12-48pin, QFP13-64pin (plastic) or chip
∗1: Can be selected with mask option
∗2: Can be selected with software
2EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 1: OUTLINE
1.2 Block Diagram
OSC1
OSC2
OSC3
OSC4
VDD
VC2
CA~CB
VD1
VSS
BZ
R00~R03
R10~R13
R20~R23
K00~K03
K10~K13
K20
TEST
AVDD
AVSS
AVREF
RESET
P00~P03
P10~P13
P20~P23
P30~P33
P40~P43
Core CPU S1C63000
ROM
8,192 words × 13 bits System Reset
Control
Interrupt
Generator
OSC
RAM
512 words × 4 bits
Power
Controller
Output Port
Buzzer
Output
SVD
Clock
Timer
Programmable
Timer/Counter
Input Port
A/D
Serial Interface
I/O Port
Fig. 1.2.1 Block diagram
S1C63158 TECHNICAL MANUAL EPSON 3
CHAPTER 1: OUTLINE
1.3 Pin Layout Diagram
QFP12-48pin
2536
13
24
INDEX
121
48
37 No.
1
2
3
4
5
6
7
8
9
10
11
12
Pin name
VSS
OSC1
OSC2
VD1
OSC3
OSC4
VDD
RESET
TEST
AVREF
CB
CA
No.
13
14
15
16
17
18
19
20
21
22
23
24
Pin name
VC2
P43
P42
P41
P40
P23
P22
P21
P20
P13
P12
P11
No.
25
26
27
28
29
30
31
32
33
34
35
36
Pin name
P10
P03
P02
P01
P00
R13
R12
R11
R10
R03
R02
N.C.
No.
37
38
39
40
41
42
43
44
45
46
47
48
Pin name
R01
R00
BZ
K00
K01
K02
K03
K10
K11
K12
K13
K20
N.C.: No Connection
Fig. 1.3.1 Pin layout diagram (QFP12-48pin)
QFP13-64pin
3348
17
32
INDEX
161
64
49
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin name
VSS
OSC1
OSC2
VD1
OSC3
OSC4
VDD
RESET
TEST
AVDD
AVSS
AVREF
CB
CA
VC2
N.C.
No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin name
P43
P42
P41
P40
P33
P32
P31
P30
P23
P22
P21
P20
P13
P12
P11
P10
No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin name
P03
P02
P01
P00
R23
R22
R21
R20
R13
R12
R11
R10
R03
R02
N.C.
N.C.
No.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin name
N.C.
N.C.
N.C.
R01
R00
BZ
K00
K01
K02
K03
K10
K11
K12
K13
K20
N.C.
N.C.: No Connection
Fig. 1.3.2 Pin layout diagram (QFP13-64pin)
4EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 1: OUTLINE
1.4 Pin Description
Table 1.4.1 Pin description
Pin name
VDD
VSS
VD1
VC2
CA, CB
OSC1
OSC2
OSC3
OSC4
K00–K03
K10–K13
K20
P00–P03
P10–P13
P20–P23
P30–P33 ∗1
P40–P43
R00
R01
R02
R03
R10–R13
R20–R23 ∗1
AVDD ∗2
AVSS ∗2
AVREF
BZ
RESET
TEST
Function
Power (+) supply pin
Power (–) supply pin
Oscillation/internal logic system regulated voltage output pin
Booster power supply pin
Boosting capacitor connecting pin
Crystal or CR oscillation input pin (selected by mask option)
Crystal or CR oscillation output pin (selected by mask option)
CR or ceramic oscillation input pin (selected by mask option)
CR or ceramic oscillation output pin (selected by mask option)
Input port
Input port
Input port (key-position detect interrupt port)
I/O port
I/O port (switching to serial I/F input/output is possible by software)
I/O port
I/O port
I/O port (can be used as A/D converter inputs)
Output port
Output port
Output port (switching to TOUT output is possible by software)
Output port (switching to FOUT output is possible by software)
Output port
Output port
Power (+) supply pin for A/D converter
Power (–) supply pin for A/D converter
Reference voltage for A/D converter
Buzzer output pin
Initial reset input pin
Testing input pin
QFP12-48
7
1
4
13
12, 11
2
3
5
6
40–43
44–47
48
29–26
25–22
21–18
–
17–14
38
37
35
34
33–30
–
–
–
10
39
8
9
QFP13-64
7
1
4
15
14, 13
2
3
5
6
55–58
59–62
63
36–33
32–29
28–25
24–21
20–17
53
52
46
45
44–41
40–37
10
11
12
54
8
9
In/Out
–
–
–
–
–
I
O
I
O
I
I
I
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
–
–
–
O
I
I
Pin No.
∗1: P30–P33 and R20–R23 are not available in the QFP12-48pin package.
∗2: In the QFP12-48pin package, AVDD and AVSS are connected with VDD and VSS inside of the IC, respectively.
1.5 Mask Option
Mask options shown below are provided for the S1C63158. Several hardware specifications are prepared
in each mask option, and one of them can be selected according to the application. The function option
generator winfog, that has been prepared as the development software tool of S1C63158, is used for this
selection. Mask pattern of the IC is finally generated based on the data created by the winfog. Refer to the
"S5U1C63000A Manual" for the winfog.
<Functions selectable with S1C63158 mask options>
(1) Shipping form
A plastic package (QFP12-48pin or QFP13-64pin) or chip form may be selected.
(2) External reset by simultaneous LOW input to the input port (K00–K03)
This function resets the IC when several keys are pressed simultaneously. The mask option is used to
select whether this function is used or not. Further when the function is used, a combination of the
input ports (K00–K03), which are connected to the keys to be pressed simultaneously, can be selected.
Refer to Section 2.2.2, "Simultaneous low input to terminals K00–K03", for details.
S1C63158 TECHNICAL MANUAL EPSON 5
CHAPTER 1: OUTLINE
(3) Time authorize circuit for the simultaneous LOW input reset function
When using the external reset function (shown in 2 above), using the time authorize circuit or not can
be selected by the mask option. The reset function works only when the input time of simultaneous
LOW is more than the rule time if the time authorize circuit is being used. Refer to Section 2.2.2,
"Simultaneous low input to terminals K00–K03", for details.
(4) Input port pull-up resistor
The mask option is used to select whether the pull-up resistor is supplemented to the input ports or not.
It is possible to select for each bit of the input ports. Refer to Section 4.5.3, "Mask option", for details.
(5) Output specification of the output port
Either complementary output or N-channel open drain output can be selected as the output specifica-
tion for the output ports R10–R13 and R20–R23. The selection is done in 4-bit units (R10–R13 and R20–
R23). The output ports R00–R03 can only be used as complementary output. Refer to Section 4.6.2,
"Mask option", for details.
(6) Output specification / pull-up resistor of the I/O ports
Either complementary output or N-channel open drain output may be selected as the output specifi-
cation when the I/O ports are in the output mode. Furthermore, whether or not the pull-up resistors
working in the input mode are supplemented can be selected. These selections are done in 1-bit units
or 4-bit units according to the I/O port.
1-bit unit: P20, P21, P22, P23, P30, P31, P32, P33, P40, P41, P42, P43
4-bit unit: P10–P13
∗ P00–P03 are fixed at complementary output and pull-up resistor input.
Refer to Section 4.7.2, "Mask option", for details.
(7) Synchronous clock polarity in the serial interface
The polarity of the synchronous clock SCLK and the SRDY signal in slave mode of the serial interface
is selected by the mask option. Either positive polarity or negative polarity can be selected. Refer to
Section 4.11.2, "Mask option", for details.
(8) Polarity of the buzzer output signal
It is possible to select the polarity of the buzzer signal output from the BZ terminal. Select either
positive polarity or negative polarity according to the external drive transistor to be used. Refer to
Section 4.12.2, "Mask option", for details.
(9) OSC1 oscillation frequency
Either crystal oscillation circuit or CR oscillation circuit may be selected as the OSC1 oscillation
circuit. Refer to Section 4.4.2, "OSC1 oscillation circuit", for details.
(10) OSC3 oscillation circuit
Either CR oscillation circuit or ceramic oscillation circuit may be selected as the OSC3 oscillation
circuit. It is also possible to disable the OSC3 oscillation circuit by selecting "Not used". Refer to
Section 4.4.3, "OSC3 oscillation circuit", for details.
<Mask option list>
The following is the option list for the S1C63158. Multiple selections are available in each option item as
indicated in the option list. Refer to Chapter 4, "Peripheral Circuits and Operation", to select the specifica-
tions that meet the application system. Be sure to select the specifications for unused functions too,
according to the instruction provided. Use winfog in the S5U1C63000A package for this selection. Refer to
the "S5U1C63000A Manual" for details.
1. PACKAGE TYPE SELECT
■■ 1. Chip
■■ 2. QFP12-48
■■ 3. QFP13-64
2. OSC3 SYSTEM CLOCK
■■ 1. Not Use
■■ 2. Use <Ceramic (2 MHz)>
■■ 3. Use <CR (2 MHz)>
6EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 1: OUTLINE
3. OSC1 SYSTEM CLOCK
■■ 1. Crystal (32.768 kHz)
■■ 2. CR
4. MULTIPLE KEY ENTRY RESET COMBINATION
■■ 1. Not Use
■■ 2. Use <K00, K01, K02, K03>
■■ 3. Use <K00, K01, K02>
■■ 4. Use <K00, K01>
5. MULTIPLE KEY ENTRY RESET TIME AUTHORIZE
■■ 1. Not Use
■■ 2. Use
6. INPUT PORT PULL UP RESISTOR
• K00 ■■ 1. With Resistor ■■ 2. Gate Direct
• K01 ■■ 1. With Resistor ■■ 2. Gate Direct
• K02 ■■ 1. With Resistor ■■ 2. Gate Direct
• K03 ■■ 1. With Resistor ■■ 2. Gate Direct
• K10 ■■ 1. With Resistor ■■ 2. Gate Direct
• K11 ■■ 1. With Resistor ■■ 2. Gate Direct
• K12 ■■ 1. With Resistor ■■ 2. Gate Direct
• K13 ■■ 1. With Resistor ■■ 2. Gate Direct
• K20 ■■ 1. With Resistor ■■ 2. Gate Direct
7. OUTPUT PORT OUTPUT SPECIFICATION
• R1x ■■ 1. Complementary ■■ 2. Nch-OpenDrain
• R2x ■■ 1. Complementary ■■ 2. Nch-OpenDrain
8. I/O PORT OUTPUT SPECIFICATION
• P1x ■■ 1. Complementary ■■ 2. Nch-OpenDrain
• P20 ■■ 1. Complementary ■■ 2. Nch-OpenDrain
• P21 ■■ 1. Complementary ■■ 2. Nch-OpenDrain
• P22 ■■ 1. Complementary ■■ 2. Nch-OpenDrain
• P23 ■■ 1. Complementary ■■ 2. Nch-OpenDrain
• P30 ■■ 1. Complementary ■■ 2. Nch-OpenDrain
• P31 ■■ 1. Complementary ■■ 2. Nch-OpenDrain
• P32 ■■ 1. Complementary ■■ 2. Nch-OpenDrain
• P33 ■■ 1. Complementary ■■ 2. Nch-OpenDrain
• P40 ■■ 1. Complementary ■■ 2. Nch-OpenDrain
• P41 ■■ 1. Complementary ■■ 2. Nch-OpenDrain
• P42 ■■ 1. Complementary ■■ 2. Nch-OpenDrain
• P43 ■■ 1. Complementary ■■ 2. Nch-OpenDrain
9. I/O PORT PULL UP RESISTOR
• P1x ■■ 1. With Resistor ■■ 2. Gate Direct
• P20 ■■ 1. With Resistor ■■ 2. Gate Direct
• P21 ■■ 1. With Resistor ■■ 2. Gate Direct
• P22 ■■ 1. With Resistor ■■ 2. Gate Direct
• P23 ■■ 1. With Resistor ■■ 2. Gate Direct
• P30 ■■ 1. With Resistor ■■ 2. Gate Direct
• P31 ■■ 1. With Resistor ■■ 2. Gate Direct
• P32 ■■ 1. With Resistor ■■ 2. Gate Direct
• P33 ■■ 1. With Resistor ■■ 2. Gate Direct
• P40 ■■ 1. With Resistor ■■ 2. Gate Direct
• P41 ■■ 1. With Resistor ■■ 2. Gate Direct
• P42 ■■ 1. With Resistor ■■ 2. Gate Direct
• P43 ■■ 1. With Resistor ■■ 2. Gate Direct
10. SERIAL PORT INTERFACE POLARITY
■■ 1. Positive
■■ 2. Negative
11. SOUND GENERATOR POLARITY FOR OUTPUT
■■ 1. Positive
■■ 2. Negative
S1C63158 TECHNICAL MANUAL EPSON 7
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
CHAPTER 2POWER SUPPLY AND INITIAL RESET
2.1 Pow er Supply
The S1C63158 operating power voltage is as follows:
0.9 V to 3.6 V
Note: • When a voltage within 0.9 V to 1.35 V is used as the operating power voltage, software control is
necessary (see Section 4.2).
The S1C63158 operates by supplying a single power source voltage within the above range between
VDD/AVDD and VSS/AVSS. The S1C63158 itself generates the voltage necessary for all the internal circuits
by the built-in power supply circuits shown in Table 2.1.1.
Table 2.1.1 Power supply circuits
Circuit
Oscillation and internal circuits
Oscillation system voltage regulator
A/D converter
Power supply circuit
Oscillation system voltage regulator
Supply voltage (V
DD
) or voltage booster circuit (V
C2
)
Analog supply voltage (AV
DD
) and
supply voltage (V
DD
) or voltage booster circuit (V
C2
)
Output voltage
V
D1
V
DD
or V
C2
AV
DD
and
V
DD
or V
C2
Note: • Do not drive external loads with the output voltage from the internal power supply circuits.
•See Chapter 7, "Electrical Characteristics", for voltage values and drive capability.
AV
DD
V
DD
External
power
supply
V
C2
CA
CB
V
C2
V
DD
OSC1–4
Voltage booster
circuit
V
D1
V
D1
V
SS
AV
SS
Oscillation system
voltage regulator Oscillation circuit
Internal circuit
SVD circuit
A/D converter
+
Fig. 2.1.1 Configuration of power supply
2.1.1 Voltage <VD1> for oscillation circuit and internal circuits
VD1 is a voltage for the oscillation circuit and the internal logic circuits, and is generated by the oscillation
system voltage regulator for stabilizing the oscillation. The S1C63158 is designed with twin clock specifi-
cation; it has two types of oscillation circuits OSC1 and OSC3 built-in. Use OSC1 clock for normal opera-
tion, and switch it to OSC3 by the software when high-speed operation is necessary. When switching the
clock, the operating voltage VD1 must be switched by the software to stabilize the operation of the
oscillation circuit and internal circuits. The oscillation system voltage regulator can output the following
two types of VD1 voltage. It should be set at the value according to the oscillation circuit and oscillation
frequency by the software.
1. Operation with OSC1 clock: VD1 = 1.3 V
2. Operation with OSC3 clock: VD1 = 2.1 V
Refer to Section 4.4, "Oscillation Circuit", for the VD1 switching procedure.
However, since the VD1 voltage value is fixed at 2.1 V when CR oscillation is selected for the OSC1
oscillation circuit by mask option and the OSC3 oscillation circuit (CR or ceramic oscillation) is also used,
it is not necessary to switch VD1 by software. When the OSC3 oscillation circuit is not used, the OSC1
oscillation circuit can operate with 1.3 V of VD1 even if CR oscillation is selected.
8EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.1.2 Voltage source for oscillation system voltage regulator
(1) VC2 mode (booster mode)
The S1C63158 operates with 0.9–3.6 V supply voltage. However, a minimum 1.35 V supply voltage
during single clock operation (OSC1) or a minimum 2.2 V during twin clock operation (OSC3, 2 MHz
Typ.) is needed for the oscillation system voltage regulator. Therefore, when operating with the
following supply voltage (VDD), switch the power source for driving the oscillation system voltage
regulator to VC2.
• During single clock operation (OSC1): VDD = 0.9–1.35 V (VC2 = 1.8–2.7 V)
When the supply voltage is more than needed for operation, do not set in this mode because the VC2
mode will increases current consumption to the oscillation system voltage regulator.
Note: Set the VC2 mode when a supply voltage drop is detected by the SVD circuit, such as during heavy
load operation (driving buzzer or lamp) or by battery life. (
∗
)
(2) Normal mode
In this mode, the oscillation system voltage regulator directly operates by the power supply voltage
VDD within the range of 1.35–3.6 V (2.2–3.6 V when the OSC3 clock is used) without changing the
power source to VC2. At initial reset, this mode is set.
Table 2.1.2.1 Corr espondence between power supply volta g e and oper ating mode (oscillation system volta ge r agulator)
Power supply
circuit
Oscillation system
voltage regulator
Operating
condition
OSC1
OSC3, 4 MHz
Power supply voltage V
DD
(V)
0.9–1.35 1.35–2.2 2.2–3.6
V
C2
mode Normal mode ∗
Cannot work Normal mode
∗ See above Note in V
C2
mode.
Refer to Section 4.2, " Setting of Power Supply and Operating Mode", for setting procedure of the operat-
ing mode.
2.1.3 Voltage source for A/D converter
(1) VC2 mode (booster mode)
The A/D converter operates with 0.9–3.6 V supply voltage. However, a minimum 1.6 V supply
voltage is required for the A/D converter maximum error within ±3 LSB. Therefore, when operating
with a 1.6 V or less of supply voltage (VDD), switch the power source for driving the A/D converter
circuit to VC2.
(2) Normal mode
In this mode, the A/D converter circuit directly operates by the power supply voltage VDD above 1.6
V without changing the power source to VC2.
Table 2.1.4.1 Correspondence between power supply voltage and operating mode (A/D converter)
Circuit
A/D converter
Power supply voltage V
DD
(V)
0.9–1.6 1.6–3.6
V
C2
mode Normal mode
S1C63158 TECHNICAL MANUAL EPSON 9
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2 Initial Reset
To initialize the S1C63158 circuits, initial reset must be executed. There are two ways of doing this.
(1) External initial reset by the RESET terminal
(2) External initial reset by simultaneous low input to terminals K00–K03 (mask option)
When the power is turned on, be sure to initialize using the above reset function. The circuit operation
cannot be guaranteed if the IC starts operating by only turning the power on.
Figure 2.2.1 shows the configuration of the initial reset circuit.
RESET
K00
K01
K02
K03
OSC2
OSC1
RQ
S
Internal
initial
reset
Divider
V
DD
1 Hz
2 Hz
V
DD
OSC1
oscillation
circuit
Noise
reject
circuit
Time
authorize
circuit
Mask option
Mask option
Fig. 2.2.1 Configuration of initial reset circuit
2.2.1 Reset terminal (RESET)
Initial reset can be executed externally by setting the reset terminal to a low level (VSS). After that the
initial reset is released by setting the reset terminal to a high level (VDD) and the CPU starts operation.
The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS
latch is designed to be released by a 2 Hz signal that is divided by the OSC1 clock. Therefore in normal
operation, a maximum of 250 msec (when fOSC1 = 32.768 kHz) is needed until the internal initial reset is
released after the reset terminal goes to high level. Be sure to maintain a reset input of 0.1 msec or more.
However, when turning the power on, the reset terminal should be set at a low level as in the timing
shown in Figure 2.2.1.1.
V
DD
RESET
2.0 msec or more
1.3 V
0.5•V
DD
0.1•V
DD
or less (low level)
Power on
Fig. 2.2.1.1 Initial reset at power on
The reset terminal should be set to 0.1•VDD or less (low level) until the supply voltage becomes 1.3 V or
more.
After that, a level of 0.5•VDD or less should be maintained more than 2.0 msec.
10 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2.2 Simultaneous low input to terminals K00–K03
Another way of executing initial reset externally is to input a low signal simultaneously to the input ports
(K00–K03) selected with the mask option.
Since this initial reset passes through the noise reject circuit, maintain the specified input port terminals at
low level for at least 1.5 msec (when the oscillation frequency fOSC1 is 32.768 kHz) during normal opera-
tion. The noise reject circuit does not operate immediately after turning the power on until the oscillation
circuit starts oscillating. Therefore, maintain the specified input port terminals at low level until the
oscillation starts.
Table 2.2.2.1 shows the combinations of input ports (K00–K03) that can be selected with the mask option.
Table 2.2.2.1 Combinations of input ports
Not use
K00∗K01∗K02∗K03
K00∗K01∗K02
K00∗K01
1
2
3
4
When, for instance, mask option 2 (K00∗K01∗K02∗K03) is selected, initial reset is executed when the
signals input to the four ports K00–K03 are all low at the same time. When 3 or 4 is selected, the initial
reset is done when a key entry including a combination of selected input ports is made.
Further, the time authorize circuit can be selected with the mask option. The time authorize circuit checks
the input time of the simultaneous low input and performs initial reset if that time is the defined time (1
to 2 sec) or more.
If using this function, make sure that the specified ports do not go low at the same time during ordinary
operation.
2.2.3 Internal register at initial resetting
Initial reset initializes the CPU as shown in
Table 2.2.3.1.
The registers and flags which are not initial-
ized by initial reset should be initialized in
the program if necessary.
In particular, the stack pointers SP1 and SP2
must be set as a pair because all the interrupts
including NMI are masked after initial reset
until both the SP1 and SP2 stack pointers are
set with software.
When data is written to the EXT register, the
E flag is set and the following instruction will
be executed in the extended addressing mode.
If an instruction which does not permit
extended operation is used as the following
instruction, the operation is not guaranteed.
Therefore, do not write data to the EXT
register for initialization only.
Refer to the "S1C63000 Core CPU Manual" for
extended addressing and usable instructions.
Table 2.2.3.1 Initial values
Name
Data register A
Data register B
Extension register EXT
Index register X
Index register Y
Program counter
Stack pointer SP1
Stack pointer SP2
Zero flag
Carry flag
Interrupt flag
Extension flag
Queue register
CPU core
Symbol
A
B
EXT
X
Y
PC
SP1
SP2
Z
C
I
E
Q
Number of bits
4
4
8
16
16
16
8
8
1
1
1
1
16
Setting value
Undefined
Undefined
Undefined
Undefined
Undefined
0110H
Undefined
Undefined
Undefined
Undefined
0
0
Undefined
Name
RAM
Display memory
Other pheripheral circuits
Peripheral circuits
Number of bits
4
4
–
Setting value
Undefined
Undefined
∗
∗ See Section 4.1, "Memory Map".
S1C63158 TECHNICAL MANUAL EPSON 11
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2.4 Terminal settings at initial resetting
The output port (R) terminals and I/O port (P) terminals are shared with special output terminals, input/
output terminals of the serial interface and input terminals of the A/D converter. These functions are
selected by the software. At initial reset, these terminals are set to the general purpose output port
terminals and I/O port terminals. Set them according to the system in the initial routine. In addition, take
care of the initial status of output terminals when designing a system.
Table 2.2.4.1 shows the list of the shared terminal settings.
Table 2.2.4.1 List of shared terminal settings
Special output
TOUT FOUT
TOUT
FOUT
Serial I/F
Master Slave
SIN(I) SIN(I)
SOUT(O) SOUT(O)
SCLK(O) SCLK(I)
SRDY(O)
Terminal
name
R00
R01
R02
R03
R10–R13
R20–R23
P00–P03
P10
P11
P12
P13
P20–P23
P30–P33
P40
P41
P42
P43
Terminal status
at initial reset
R00 (High output)
R01 (High output)
R02 (High output)
R03 (High output)
R10–R13 (High output)
R20–R23 (High output)
P00–P03 (Input & Pull-up)
P10 (Input & Pull-up ∗)
P11 (Input & Pull-up ∗)
P12 (Input & Pull-up ∗)
P13 (Input & Pull-up ∗)
P20–P23 (Input & Pull-up ∗)
P30–P33 (Input & Pull-up ∗)
P40 (Input & Pull-up ∗)
P41 (Input & Pull-up ∗)
P42 (Input & Pull-up ∗)
P43 (Input & Pull-up ∗)
A/D
converter
AD0(I)
AD1(I)
AD2(I)
AD3(I)
∗ When "with pull-up" is selected by mask option (high impedance when "gate direct" is selected)
For setting procedure of the functions, see explanations for each of the peripheral circuits.
2.3 Test Terminal (TEST)
This is the terminal used for the factory inspection of the IC. During normal operation, connect the TEST
terminal to VDD.
12 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 3: CPU, ROM, RAM
CHAPTER 3 CPU, ROM, RAM
3.1 CPU
The S1C63158 has a 4-bit core CPU S1C63000 built-in as its CPU part.
Refer to the "S1C63000 Core CPU Manual" for the S1C63000.
Note:
The SLP instruction cannot be used because the SLEEP operation is not assumed in the S1C63158.
3.2 Code ROM
The built-in code ROM is a mask ROM for loading programs, and has a capacity of 8,192 steps × 13 bits.
The core CPU can linearly access the program space up to step FFFFH from step 0000H, however, the
program area of the S1C63158 is step 0000H to step 1FFFH. The program start address after initial reset is
assigned to step 0110H. The non-maskable interrupt (NMI) vector and hardware interrupt vectors are
allocated to step 0100H and steps 0102H–010EH, respectively.
0000H
1FFFH
2000H
FFFFH
0000H
0100H
0102H
010EH
0110H
Program area
NMI vector
Hardware
interrupt vectors
Program start address
Program area
ROM
Unused area
13 bits
S1C63000 core CPU
program space
S1C63158
program area
Fig. 3.2.1 Configuration of code ROM
3.3 RAM
The RAM is a data memory for storing various kinds of data, and has a capacity of 512 words × 4 bits.
The RAM area is assigned to addresses 0000H to 01FFH on the data memory map. Addresses 0100H to
01FFH are 4-bit/16-bit data accessible areas and in other areas it is only possible to access 4-bit data.
When programming, keep the following points in mind.
(1) Part of the RAM area is used as a stack area for subroutine call and register evacuation, so pay
attention not to overlap the data area and stack area.
(2) The S1C63000 core CPU handles the stack using the stack pointer for 4-bit data (SP2) and the stack
pointer for 16-bit data (SP1).
16-bit data are accessed in stack handling by SP1, therefore, this stack area should be allocated to the
area where 4-bit/16-bit access is possible (0100H to 01FFH). The stack pointers SP1 and SP2 change
cyclically within their respective range: the range of SP1 is 0000H to 03FFH and the range of SP2 is
0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more
exceeding the 4-bit/16-bit accessible range in the S1C63158 or it may be set to 00FFH or less. Memory
accesses except for stack operations by SP1 are 4-bit data access.
After initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and
SP2 are set by software. Further, if either SP1 or SP2 is re-set when both are set already, the interrupts
including NMI are masked again until the other is re-set. Therefore, the settings of SP1 and SP2 must
be done as a pair.
S1C63158 TECHNICAL MANUAL EPSON 13
CHAPTER 3: CPU, ROM, RAM
(3) Subroutine calls use 4 words (for PC evacuation) in the stack area for 16-bit data (SP1). Interrupts use
4 words (for PC evacuation) in the stack area for 16-bit data (SP1) and 1 word (for F register evacua-
tion) in the stack area for 4-bit data.
0000H
00FFH
0100H
01FFH
4 bits
4-bit access area
(SP2 stack area)
4/16-bit access area
(SP1 stack area)
Fig. 3.3.1 Configuration of data RAM
14 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
CHAPTER 4
P
ERIPHERAL
C
IRCUITS
AND
O
PERATION
The peripheral circuits of S1C63158 (timer, A/D, I/O, etc.) are interfaced with the CPU in the
memory mapped I/O method. Thus, all the peripheral circuits can be controlled by accessing the I/O
memory on the memory map using the memory operation instructions. The following sections explain
the detailed operation of each peripheral circuit.
4.1 Memory Map
The S1C63158 data memory consists of 512-word RAM and 73-word peripheral I/O memory area. Figure
4.1.1 shows the overall memory map of the S1C63158, and Tables 4.1.1(a)–(f) the peripheral circuits' (I/O
space) memory maps.
0000H
0200H
FF00H
FFFFH
RAM area
Unused area
Peripheral I/O area
Fig. 4.1.1 Memory map
Note: Memory is not implemented in unused areas within the memory map. Further, some non-imple-
mentation areas and unused (access prohibition) areas exist in the peripheral I/O area. If the
program that accesses these areas is generated, its operation cannot be guaranteed. Refer to the
I/O memory maps shown in Tables 4.1.1 (a)–(f) for the peripheral I/O area.
S1C63158 TECHNICAL MANUAL EPSON 15
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (a) I/O memory map (FF00H–FF28H)
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
FF01H
VADSEL VDSEL 0 DBON
R R/WR/W
VADSEL
VDSEL
0
∗
3
DBON
0
0
–
∗
2
0
V
C2
V
C2
On
V
DD
V
DD
Off
Power source selection for A/D converter
Power supply selection for oscillation system voltage regulator
Unused
Voltage booster circuit On/Off
FF06H
FOUTE 0 FOFQ1 FOFQ0
R/W R R/W
FOUTE
0
∗
3
FOFQ1
FOFQ0
0
–
∗
2
0
0
Enable Disable
FOUT output enable
Unused
FOUT
frequency
selection
FF05H
00SVDDT SVDON
R R/W
0
∗
3
0
∗
3
SVDDT
SVDON
–
∗
2
–
∗
2
0
0
Low
On
Normal
Off
Unused
Unused
SVD evaluation data
SVD circuit On/Off
FF07H
00WDEN WDRST
R/W WR
0
∗
3
0
∗
3
WDEN
WDRST
∗
3
–
∗
2
–
∗
2
1
Reset
Enable
Reset
Disable
Invalid
Unused
Unused
Watchdog timer enable
Watchdog timer reset (writing)
FF04H
SVDS3 SVDS2 SVDS1 SVDS0
R/W
SVDS3
SVDS2
SVDS1
SVDS0
0
0
0
0
SVD criteria voltage setting
FF00H
CLKCHG OSCC 0 VDC
R R/WR/W
CLKCHG
OSCC
0
∗
3
VDC
0
0
–
∗
2
0
OSC3
On
2.1 V
OSC1
Off
1.3 V
CPU clock switch
OSC3 oscillation On/Off
Unused
CPU operating voltage switch (1.3 V: OSC1, 2.1 V: OSC3)
FF20H
SIK03 SIK02 SIK01 SIK00
R/W
SIK03
SIK02
SIK01
SIK00
0
0
0
0
Enable
Enable
Enable
Enable
Disable
Disable
Disable
Disable
K00–K03 interrupt selection register
FF21H
K03 K02 K01 K00
R
K03
K02
K01
K00
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
K00–K03 input port data
FF22H
KCP03 KCP02 KCP01 KCP00
R/W
KCP03
KCP02
KCP01
KCP00
1
1
1
1
K00–K03 input comparison register
FF24H
SIK13 SIK12 SIK11 SIK10
R/W
SIK13
SIK12
SIK11
SIK10
0
0
0
0
Enable
Enable
Enable
Enable
Disable
Disable
Disable
Disable
K10–K13 interrupt selection register
FF25H
K13 K12 K11 K10
R
K13
K12
K11
K10
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
K10–K13 input port data
FF26H
KCP13 KCP12 KCP11 KCP10
R/W
KCP13
KCP12
KCP11
KCP10
1
1
1
1
K10–K13 input comparison register
0
1.05
8
1.95
1
1.10
9
2.00
2
1.15
10
2.05
3
1.20
11
2.10
4
1.25
12
2.20
5
1.30
13
2.30
6
1.40
14
2.50
7
1.60
15
2.60
[SVDS3–0]
Voltage(V)
[SVDS3–0]
Voltage(V)
0
fOSC1/64 1
fOSC1/8 2
fOSC1
3
fOSC3
[FOFQ1, 0]
Frequency
FF28H
000SIK20
R R/W
0
∗
3
0
∗
3
0
∗
3
SIK20
–
∗
2
–
∗
2
–
∗
2
0 Enable Disable
Unused
Unused
Unused
K20 interrupt selection register
Remarks
∗1Initial value at initial reset
∗2Not set in the circuit
∗3Constantly "0" when being read
16 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (b) I/O memory map (FF29H–FF44H)
D3 D2 D1 D0 Name Init
∗1
10
Address Comment
Register
FF30H
R03HIZ R02HIZ R01HIZ R00HIZ
R/W
R03HIZ
R02HIZ
R01HIZ
R00HIZ
0
0
0
0
High-Z
High-Z
High-Z
High-Z
Output
Output
Output
Output
R03 output high impedance control (FOUTE=0)
FOUT output high impedance control (FOUTE=1)
R02 output high impedance control (PTOUT=0)
TOUT output high impedance control (PTOUT=1)
R01 output high impedance control
R00 output high impedance control
FF31H
R03 R02 R01 R00
R/W
R03
R02
R01
R00
1
1
1
1
High
High
High
High
Low
Low
Low
Low
R03 output port data (FOUTE=0)
Fix at "1" when FOUT is used
R02 output port data (PTOUT=0)
Fix at "1" when TOUT is used
R01 output port data
R00 output port data
FF32H
000R1HIZ
R R/W
0
∗
3
0
∗
3
0
∗
3
R1HIZ
–
∗
2
–
∗
2
–
∗
2
0 High-Z Output
FF33H
R13 R12 R11 R10
R/W
R13
R12
R11
R10
1
1
1
1
High
High
High
High
Low
Low
Low
Low
R10–R13 output port data
FF40H
IOC03 IOC02 IOC01 IOC00
R/W
IOC03
IOC02
IOC01
IOC00
0
0
0
0
Output
Output
Output
Output
Input
Input
Input
Input
P00–P03 I/O control register
FF41H
PUL03 PUL02 PUL01 PUL00
R/W
PUL03
PUL02
PUL01
PUL00
1
1
1
1
On
On
On
On
Off
Off
Off
Off
P00–P03 pull-up control register
FF42H
P03 P02 P01 P00
R/W
P03
P02
P01
P00
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
P00–P03 I/O port data
Unused
Unused
Unused
K20 input port data
Unused
Unused
Unused
K20 input comparison register
FF29H
000K20
R
0
∗
3
0
∗
3
0
∗
3
K20
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High Low
FF2AH
000KCP20
R R/W
0
∗
3
0
∗
3
0
∗
3
KCP20
–
∗
2
–
∗
2
–
∗
2
1
FF2BH
000SENON
R R/W
0
∗
3
0
∗
3
0
∗
3
SENON
–
∗
2
–
∗
2
–
∗
2
1OnOff
Unused
Unused
Unused
Key sense On/Off control
FF34H
000R2HIZ
R R/W
0
∗
3
0
∗
3
0
∗
3
R2HIZ
–
∗
2
–
∗
2
–
∗
2
0 High-Z Output
Unused
Unused
Unused
R2 output high impedance control
Unused
Unused
Unused
R1 output high impedance control
FF35H
R23 R22 R21 R20
R/W
R23
R22
R21
R20
1
1
1
1
High
High
High
High
Low
Low
Low
Low
R20–R23 output port data
FF44H
IOC13 IOC12 IOC11 IOC10
R/W
IOC13
IOC12
IOC11
IOC10
0
0
0
0
Output
Output
Output
Output
Input
Input
Input
Input
P13 I/O control register
functions as a general-purpose register when SIF (slave) is selected
P12 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
P11 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
P10 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
S1C63158 TECHNICAL MANUAL EPSON 17
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (c) I/O memory map (FF45H–FF51H)
D3 D2 D1 D0 Name Init ∗110
Address Comment
Register
FF48H
IOC23 IOC22 IOC21 IOC20
R/W
IOC23
IOC22
IOC21
IOC20
0
0
0
0
Output
Output
Output
Output
Input
Input
Input
Input
P20–P23 I/O control register
FF49H
PUL23 PUL22 PUL21 PUL20
R/W
PUL23
PUL22
PUL21
PUL20
1
1
1
1
On
On
On
On
Off
Off
Off
Off
P20–P23 pull-up control register
FF4AH
P23 P22 P21 P20
R/W
P23
P22
P21
P20
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
P20–P23 I/O port data
FF4CH
IOC33 IOC32 IOC31 IOC30
R/W
IOC33
IOC32
IOC31
IOC30
0
0
0
0
Output
Output
Output
Output
Input
Input
Input
Input
P30–P33 I/O control register
FF4DH
PUL33 PUL32 PUL31 PUL30
R/W
PUL33
PUL32
PUL31
PUL30
1
1
1
1
On
On
On
On
Off
Off
Off
Off
P30–P33 pull-up control register
FF4EH
P33 P32 P31 P30
R/W
P33
P32
P31
P30
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
P30–P33 I/O port data
FF45H
PUL13 PUL12 PUL11 PUL10
R/W
PUL13
PUL12
PUL11
PUL10
1
1
1
1
On
On
On
On
Off
Off
Off
Off
P13 pull-up control register
functions as a general-purpose register when SIF (slave) is selected
P12 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF (master) is selected
SCLK (I) pull-up control register when SIF (slave) is selected
P11 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF is selected
P10 pull-up control register (ESIF=0)
SIN pull-up control register
when SIF is selected
FF46H
P13 P12 P11 P10
R/W
P13
P12
P11
P10
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
P13 I/O port data
functions as a general-purpose register when SIF (slave) is selected
P12 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
P11 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
P10 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
FF50H
IOC43 IOC42 IOC41 IOC40
R/W
IOC43
IOC42
IOC41
IOC40
0
0
0
0
Output
Output
Output
Output
Input
Input
Input
Input
P43 I/O control register (PAD3=0)
functions as a general-purpose register when A/D is enabled
P42 I/O control register (PAD2=0)
functions as a general-purpose register when A/D is enabled
P41 I/O control register (PAD1=0)
functions as a general-purpose register when A/D is enabled
P40 I/O control register (PAD0=0)
functions as a general-purpose register when A/D is enabled
FF51H
PUL43 PUL42 PUL41 PUL40
R/W
PUL43
PUL42
PUL41
PUL40
1
1
1
1
On
On
On
On
Off
Off
Off
Off
P43 pull-up control register (PAD3=0)
functions as a general-purpose register when A/D is enabled
P42 pull-up control register (PAD2=0)
functions as a general-purpose register when A/D is enabled
P41 pull-up control register (PAD1=0)
functions as a general-purpose register when A/D is enabled
P40 pull-up control register (PAD0=0)
functions as a general-purpose register when A/D is enabled
18 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (d) I/O memory map (FF52H–FFC3H)
D3 D2 D1 D0 Name Init ∗110
Address Comment
Register
R R/W
FF64H
0 ENON BZFQ BZON 0
∗
3
ENON
BZFQ
BZON
–
∗
2
0
0
0
On
2 kHz
On
Off
4 kHz
Off
Unused
2 Hz intervai On/Off
Buzzer frequency selection
Buzzer output On/Off
R/W
FF72H
SD3 SD2 SD1 SD0 SD3
SD2
SD1
SD0
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
MSB
Serial I/F transmit/receive data (low-order 4 bits)
LSB
R/W
FF73H
SD7 SD6 SD5 SD4 SD7
SD6
SD5
SD4
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
MSB
Serial I/F transmit/receive data (high-order 4 bits)
LSB
W R/WR
FF78H
00TMRST TMRUN 0
∗
3
0
∗
3
TMRST
∗
3
TMRUN
–
∗
2
–
∗
2
Reset
0
Reset
Run
Invalid
Stop
Unused
Unused
Clock timer reset (writing)
Clock timer Run/Stop
R
FF79H
TM3 TM2 TM1 TM0 TM3
TM2
TM1
TM0
0
0
0
0
Clock timer data (16 Hz)
Clock timer data (32 Hz)
Clock timer data (64 Hz)
Clock timer data (128 Hz)
R
FF7AH
TM7 TM6 TM5 TM4 TM7
TM6
TM5
TM4
0
0
0
0
Clock timer data (1 Hz)
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
0
Slave
2
OSC1/2
1
PT
3
OSC1
[SCS1, 0]
Clock
[SCS1, 0]
Clock
FF71H
SDP SCPS SCS1 SCS0
R/W
SDP
SCPS
SCS1
SCS0
0
0
0
0
MSB first LSB first
Serial I/F data input/output permutation
Serial I/F clock phase selection
–Negative polarity (mask option)
–Positive polarity (mask option)
Serial I/F
clock mode selection
FF70H
0 ESOUT SCTRG ESIF
R R/W
0
∗
3
ESOUT
SCTRG
ESIF
–
∗
2
0
0
0
Enable
Trigger
Run
SIF
Disable
Invalid
Stop
I/O
Unused
SOUT enable/disable control
Serial I/F clock trigger (writing)
Serial I/F clock status (reading)
Serial I/F enable (P1 port function selection)
CHSEL
PTOUT
CKSEL1
CKSEL0
0
0
0
0
Timer1
On
OSC3
OSC3
Timer0
Off
OSC1
OSC1
TOUT output channel selection
TOUT output control
Prescaler 1 source clock selection
Prescaler 0 source clock selection
R/W
FFC1H
CHSEL PTOUT CKSEL1 CKSEL0
MODEL16
EVCNT
FCSEL
PLPOL
0
0
0
0
16 bit
×
1
Event ct.
With NR
8 bit
×
2
Timer
No NR
8 bit × 2 or 16 bit × 1 timer mode selection
Timer 0 counter mode selection
Timer 0 function selection (for event counter mode)
Timer 0 pulse polarity selection (for event counter mode)
R R/W
FFC0H
MODE16 EVCNT FCSEL PLPOL
FF52H
P43 P42 P41 P40
R/W
P43
P42
P41
P40
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
P43 I/O port data (PAD3=0)
functions as a general-purpose register when A/D is enabled
P42 I/O port data (PAD2=0)
functions as a general-purpose register when A/D is enabled
P41 I/O port data (PAD1=0)
functions as a general-purpose register when A/D is enabled
P40 I/O port data (PAD0=0)
functions as a general-purpose register when A/D is enabled
PTPS01
PTPS00
PTRST0
∗
3
PTRUN0
0
0
–
∗
2
0
Reset
Run
Invalid
Stop
Prescaler 0
division ratio
selection
Timer 0 reset (reload)
Timer 0 Run/Stop
W R/WR/W
FFC2H
PTPS01 PTPS00 PTRST0 PTRUN0
0
1/1 1
1/4 2
1/32 3
1/256
[PTPS01, 00]
Division ratio
PTPS11
PTPS10
PTRST1
∗
3
PTRUN1
0
0
–
∗
2
0
Reset
Run
Invalid
Stop
Prescaler 1
division ratio
selection
Timer 1 reset (reload)
Timer 1 Run/Stop
W R/WR/W
FFC3H
PTPS11 PTPS10 PTRST1 PTRUN1
0
1/1 1
1/4 2
1/32 3
1/256
[PTPS11, 10]
Division ratio
S1C63158 TECHNICAL MANUAL EPSON 19
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (e) I/O memory map (FFC4H–FFE3H)
Address Comment
D3 D2
Register
D1 D0 Name Init ∗110
RLD03
RLD02
RLD01
RLD00
0
0
0
0
MSB
Programmable timer 0 reload data (low-order 4 bits)
LSB
R/W
FFC4H
RLD03 RLD02 RLD01 RLD00
RLD07
RLD06
RLD05
RLD04
0
0
0
0
MSB
Programmable timer 0 reload data (high-order 4 bits)
LSB
R/W
FFC5H
RLD07 RLD06 RLD05 RLD04
RLD13
RLD12
RLD11
RLD10
0
0
0
0
MSB
Programmable timer 1 reload data (low-order 4 bits)
LSB
R/W
FFC6H
RLD13 RLD12 RLD11 RLD10
RLD17
RLD16
RLD15
RLD14
0
0
0
0
MSB
Programmable timer 1 reload data (high-order 4 bits)
LSB
R/W
FFC7H
RLD17 RLD16 RLD15 RLD14
PTD03
PTD02
PTD01
PTD00
0
0
0
0
MSB
Programmable timer 0 data (low-order 4 bits)
LSB
R
FFC8H
PTD03 PTD02 PTD01 PTD00
PTD07
PTD06
PTD05
PTD04
0
0
0
0
MSB
Programmable timer 0 data (high-order 4 bits)
LSB
R
FFC9H
PTD07 PTD06 PTD05 PTD04
PTD13
PTD12
PTD11
PTD10
0
0
0
0
MSB
Programmable timer 1 data (low-order 4 bits)
LSB
R
FFCAH
PTD13 PTD12 PTD11 PTD10
PTD17
PTD16
PTD15
PTD14
0
0
0
0
MSB
Programmable timer 1 data (high-order 4 bits)
LSB
R
FFCBH
PTD17 PTD16 PTD15 PTD14
ADRUN
ADCLK
CHS1
CHS0
0
0
0
0
Start
OSC3
Invalid
OSC1
W R/W
FFD0H
ADRUN ADCLK CHS1 CHS0
PAD3
PAD2
PAD1
PAD0
0
0
0
0
Enable
Enable
Enable
Enable
Disable
Disable
Disable
Disable
R/W
FFD1H
PAD3 PAD2 PAD1 PAD0
ADDR3
ADDR2
ADDR1
ADDR0
–
∗
2
–
∗
2
–
∗
2
–
∗
2
R
FFD2H
ADDR3 ADDR2 ADDR1 ADDR0
ADDR7
ADDR6
ADDR5
ADDR4
–
∗
2
–
∗
2
–
∗
2
–
∗
2
R
FFD3H
ADDR8 ADDR6 ADDR5 ADDR4
A/D Run/Off control
A/D input clock selection
A/D input
channel
selection
P43 input channel enable/disable control
P42 input channel enable/disable control
P41 input channel enable/disable control
P40 input channel enable/disable control
A/D converted data (D0–D3)
A/D converted data (D4–D7)
0
P40 1
P41 3
P43
2
P42
[CHS1, 0]
Input channel
FFE2H
00EIPT1 EIPT0
R R/W
0
∗
3
0
∗
3
EIPT1
EIPT0
–
∗
2
–
∗
2
0
0
Enable
Enable
Mask
Mask
Unused
Unused
Interrupt mask register (Programmable timer 1)
Interrupt mask register (Programmable timer 0)
FFE3H
000EISIF
R R/W
0
∗
3
0
∗
3
0
∗
3
EISIF
–
∗
2
–
∗
2
–
∗
2
0 Enable Mask
Unused
Unused
Unused
Interrupt mask register (Serial I/F)
20 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (f) I/O memory map (FFE4H–FFF7H)
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
FFE6H
EIT3 EIT2 EIT1 EIT0
R/W
EIT3
EIT2
EIT1
EIT0
0
0
0
0
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Interrupt mask register (Clock timer 1 Hz)
Interrupt mask register (Clock timer 2 Hz)
Interrupt mask register (Clock timer 8 Hz)
Interrupt mask register (Clock timer 16 Hz)
FFE7H
000EIAD
R R/W
0
∗
3
0
∗
3
0
∗
3
EIAD
–
∗
2
–
∗
2
–
∗
2
0 Enable Mask
Unused
Unused
Unused
Interrupt mask register (A/D converter)
FFE4H
000EIK0
R R/W
0
∗
3
0
∗
3
0
∗
3
EIK0
–
∗
2
–
∗
2
–
∗
2
0 Enable Mask
Unused
Unused
Unused
Interrupt mask register (K00–K03)
FFE5H
00EIK2 EIK1
R R/W
0
∗
3
0
∗
3
EIK2
EIK1
–
∗
2
–
∗
2
0
0
Enable
Enable
Mask
Mask
Unused
Unused
Interrupt mask register (K20)
Interrupt mask register (K10–K13)
FFF6H
IT3 IT2 IT1 IT0
R/W
IT3
IT2
IT1
IT0
0
0
0
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Interrupt factor flag (Clock timer 1 Hz)
Interrupt factor flag (Clock timer 2 Hz)
Interrupt factor flag (Clock timer 8 Hz)
Interrupt factor flag (Clock timer 16 Hz)
FFF2H
00IPT1 IPT0
R R/W
0
∗
3
0
∗
3
IPT1
IPT0
–
∗
2
–
∗
2
0
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Unused
Interrupt factor flag (Programmable timer 1)
Interrupt factor flag (Programmable timer 0)
FFF7H
000IAD
R R/W
0
∗
3
0
∗
3
0
∗
3
IAD
–
∗
2
–
∗
2
–
∗
2
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Unused
Unused
Interrupt factor flag (A/D converter)
FFF3H
000ISIF
R R/W
0
∗
3
0
∗
3
0
∗
3
ISIF
–
∗
2
–
∗
2
–
∗
2
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Unused
Unused
Interrupt factor flag (Serial I/F)
FFF4H
000IK0
R R/W
0
∗
3
0
∗
3
0
∗
3
IK0
–
∗
2
–
∗
2
–
∗
2
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Unused
Unused
Interrupt factor flag (K00–K03)
FFF5H
00IK2 IK1
R R/W
0
∗
3
0
∗
3
IK2
IK1
–
∗
2
–
∗
2
0
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Unused
Interrupt factor flag (K20)
Interrupt factor flag (K10–K13)
S1C63158 TECHNICAL MANUAL EPSON 21
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Setting of Power Supply and Operating Mode)
4.2 Setting of Pow er Supply and Operating Mode
This section explains how to control the operating mode according to the supply voltage. Refer to Section
2.1, "Power Supply" for the configuration of the power supply circuit.
4.2.1 Control of supply voltage
When the voltage value necessary to drive the oscillation system voltage regulator is not provided from
the power supply voltage supplied externally (VDD ≤ 1.35 V), the S1C63158 drives the power supply
circuit using the voltage VC2 generated by the voltage booster circuit. The supply voltage VC2 is con-
trolled using the register DBON.
• For normal operation: Set DBON = "0"
• To use VC2 supply voltage: Set DBON = "1"
The supply voltage VC2 is common to the oscillation system voltage regulator and the A/D converter
circuit. Therefore when using the VC2 voltage for either of these circuits, turn on the voltage booster
circuit. The VC2 voltage is output from the voltage booster circuit.
The oscillation system voltage regulator and the A/D converter can independently select the drive
voltage between VDD and VC2. This operation mode is controlled using the register VDSEL for the
oscillation system voltage regulator and the register VADSEL for the A/D converter. By writing "1" to the
register, VC2 is selected as the drive voltage and writing "0" selects VDD. Approximately 100 msec is
necessary until the VC2 voltage stables after turning the voltage booster ON by the DBON. Therefore, the
operating mode should be switched as in the following sequence.
Normal mode
→
VC2 mode
1. Turn the voltage booster ON (set DBON = "1").
2. Maintain 100 msec or more.
3. Set "1" in the VDSEL (for the oscillation system voltage regulator) or VADSEL (for the A/D converter).
VC2 mode
→
Normal mode
1. Set "0" in the VDSEL or VADSEL.
2. Turn the voltage booster OFF (set DBON = "0").
∗DBON should be kept at "1" if neither VDSEL or VADSEL is set to "0".
Note: • If the power supply voltage is out of the specified voltage range for an operating mode, do not
switch into the operating mode. It may cause malfunction or increase current consumption.
•When operating the S1C63158 with a 0.9–1.35 V power supply voltage, software control is
necessary. Set the oscillation system voltage regulator into the VC2 mode. When 1.35 V or more
power supply voltage is used, do not set the oscillation system voltage regulator into the VC2
mode. At initial reset the normal mode is set.
•When using the A/D converter circuit with a 0.9–1.6 V power supply voltage, software control is
necessary. Set the A/D converter circuit into the VC2 mode. When 1.6 V or more power supply
voltage is used, don't set the A/D converter circuit into the VC2 mode. At initial reset the normal
mode is set.
4.2.2 Operating mode for the oscillation system voltage regulator
and the internal operating voltage
The oscillation system voltage regulator generates the operating voltage VD1 for the oscillation circuit and
internal logic circuits. This VD1 voltage must be switched according to the oscillation circuit to be used.
Further the operating mode for the oscillation system voltage regulator must be switched according to
the power supply voltage.
Control of VD1 and the oscillation circuit will be explained in Section 4.4, "Oscillation Circuit". This
section explains the operating mode for the oscillation system voltage regulator that must be set before
controlling them. The following shows the setting contents according to the power supply voltage and
the oscillation circuit.
22 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Setting of Power Supply and Operating Mode)
Table 4.2.2.1 Power supply voltage and operating mode
Power supply
circuit
Oscillation system
voltage regulator
Operating
condition
OSC1
OSC3, 4 MHz
Power supply voltage VDD (V)
0.9–1.35 1.35–2.2 2.2–3.6
VC2 mode Normal mode ∗
Cannot work Normal mode
Operating
voltage VD1
1.3 V
2.1 V
*Set the VC2 mode when a supply voltage drop is detected by the SVD circuit, such as during a
heavy load operation (driving buzzer or lamp) or by battery deletion.
(1)Power supply voltag e VDD = 0.9 V to 1.35 V
When the power supply voltage is in this range, the oscillation system voltage regulator can operate
only in the VC2 mode.
Set the VC2 mode with software, and do not change it to another mode during operation.
(2)Power supply voltag e VDD = 1.35 V to 2.2 V
When the CPU operates with the OSC1 clock (OSC3 oscillation circuit is OFF), the oscillation system
voltage regulator can operate in the normal mode. Do not to set in the VC2 mode, since the VC2 mode
increases current consumption.
(3)Power supply voltag e VDD = 2.2 V to 3.6 V
When the power supply voltage is in this range, the oscillation system voltage regulator can always
operate in the normal mode regardless of the oscillation circuit setting. Be sure not to set in the VC2
mode.
The OSC3 oscillation circuit can be used in this voltage range.
4.2.3 Operating mode for A/D converter
The A/D converter uses AVDD for the analog block and VDD or VC2 as the power source for internal
control circuit.
Table 4.2.3.1 Power supply voltage and operating mode
Circuit
A/D converter
Power supply voltage V
DD
(V)
0.9–1.6 1.6–3.6
V
C2
mode Normal mode
(1)Power supply voltag e VDD = 0.9 V to 1.6 V
When the power supply voltage is in this range, VADSEL should be set to "1", to choose VC2 as the
A/D converter power. This control is necessary to ensure the conversion accuracy.
(2)Power supply voltag e VDD = 1.6 V to 3.6 V
When the power supply voltage is in this range, it is possible to operate in the normal mode. Do not
set in the VC2 mode.
S1C63158 TECHNICAL MANUAL EPSON 23
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Setting of Power Supply and Operating Mode)
4.2.4 I/O memory of power supply and operating mode
Table 4.2.4.1 shows the I/O addresses and control bits for the power supply and the operation mode.
Table 4.2.4.1 Control bits of power supply and operating mode
Address Comment
D3 D2
Register
D1 D0 Name Init ∗110
FF01H
VADSEL VDSEL 0 DBON
R R/WR/W
VADSEL
VDSEL
0
∗
3
DBON
0
0
–
∗
2
0
VC2
VC2
On
VDD
VDD
Off
Power source selection for A/D converter
Power supply selection for oscillation system voltage regulator
Unused
Voltage booster circuit On/Off
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
DBON: Booster control (ON/OFF) register (FF01H•D0)
Controls the voltage booster circuit.
When "1" is written: Booster ON
When "0" is written: Booster OFF
Reading: Valid
When the power supply voltage is in a range of 0.9 to 1.35 V, generate VC2 using the voltage booster to
drive the internal power supply circuit. When "1" is written to the DBON register, the voltage booster
generates VC2. When "0" is written, boosting is not performed. When the power supply voltage is 1.35 V
or more, do not use the voltage VC2 for oscillation system voltage regulator. However, this does not apply
when the battery voltage falls by heavy load such as driving a buzzer and turning a lamp on.
When the power supply voltage is 1.6 V or more, do not use the voltage VC2 for the A/D converter.
At initial reset, this register is set to "0".
VDSEL: Power supply selection register for oscillation system voltage regulator (FF01H•D2)
Selects the power supply for the oscillation system voltage regulator.
When "1" is written: VC2
When "0" is written: VDD
Reading: Valid
When "1" is written to the VDSEL register, the oscillation system voltage regulator enters the VC2 mode
and operates with VC2 output from the voltage booster. When "0" is written to the VDSEL register, the
oscillation system voltage regulator operates with VDD and the operating mode changes to the normal
mode.
When switching from the normal mode to the VC2 mode, the VDSEL register should be set to "1" after
taking a 100 msec or longer interval for the VC2 to stabilize from setting the DBON register to "1".
At initial reset, this register is set to "0".
VADSEL: Power supply selection register for A/D converter (FF01H•D3)
Selects the power supply for the A/D converter.
When "1" is written: VC2
When "0" is written: VDD
Reading: Valid
When "1" is written to the VADSEL register, the A/D converter enters the VC2 mode and operates with
VC2 output from the voltage booster. When "0" is written to the VADSEL register, the A/D converter
operates with VDD and the operating mode changes to the normal mode.
When switching from the normal mode to the VC2 mode, the VADSEL register should be set to "1" after
taking a 100 msec or longer interval for the VC2 to stabilize from setting the DBON register to "1".
At initial reset, this register is set to "0".
When using the A/D converter with a 1.6 V or less power supply voltage, set the VC2 mode.
24 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Setting of Power Supply and Operating Mode)
4.2.5 Programming notes
(1) When driving the S1C63158 with a 0.9–1.35 V power supply voltage, software control is necessary. Set
the oscillation system voltage regulator to the VC2 mode. When 1.35 V or more power supply voltage
is used, do not set the oscillation system voltage regulator into the VC2 mode.
(2) When using the A/D converter with a 0.9–1.6 V power supply voltage, software control is necessary.
Set the A/D converter voltage circuit to the VC2 mode. When 1.6 V or more power supply voltage is
used, do not set the A/D converter circuit into the VC2 mode.
(3) If the power supply voltage is out of the specified voltage range for an operating mode, do not switch
to the operating mode. It may cause malfunction or increase current consumption.
(4) When switching from the normal mode to the VC2 mode, the VDSEL and/or VADSEL registers should
be set to "1" after taking a 100 msec or longer interval for the VC2 to stabilize from switching the
DBON register to "1".
(5) When switching from the VC2 mode to the normal mode, use separate instructions to switch the mode
(VDSEL = "0" or VADSEL = "0") and turn the voltage booster OFF (DBON = "0"). Simultaneous
processing with a single instruction may cause malfunction.
(6) The OSC3 oscillation circuit can operate only in the normal mode with a power supply voltage from
2.2 V to 3.6 V.
S1C63158 TECHNICAL MANUAL EPSON 25
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer)
4.3 Watchdog Timer
4.3.1 Configuration of watchdog timer
The S1C63158 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC1 as
the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the
software. The watchdog timer must be reset cyclically by the software while it operates. If the watchdog
timer is not reset in at least 3–4 seconds, it generates a non-maskable interrupt (NMI) to the CPU.
Figure 4.3.1.1 is the block diagram of the watchdog timer.
Watchdog timer
Non-maskable
interrupt (NMI)
OSC1 dividing signal 256 Hz
Watchdog timer enable signal
Watchdog timer reset signal
Fig. 4.3.1.1 Watchdog timer block diagram
The watchdog timer contains a 10-bit binary counter, and generates the non-maskable interrupt when the
last stage of the counter (0.25 Hz) overflows.
Watchdog timer reset processing in the program's main routine enables detection of program overrun,
such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is
incorporated where periodic processing takes place, just as for the timer interrupt routine.
The watchdog timer operates in the HALT mode. If a HALT status continues for 3–4 seconds, the non-
maskable interrupt releases the HALT status.
4.3.2 Interrupt function
If the watchdog timer is not reset periodically, the non-maskable interrupt (NMI) is generated to the core
CPU. Since this interrupt cannot be masked, it is accepted even in the interrupt disable status (I flag =
"1"). However, it is not accepted when the CPU is in the interrupt mask state until SP1 and SP2 are set as a
pair, such as after initial reset or during re-setting the stack pointer. The interrupt vector of NMI is
assigned to 0100H in the program memory.
26 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer)
4.3.3 I/O memory of watchdog timer
Table 4.3.3.1 shows the I/O address and control bits for the watchdog timer.
Table 4.3.3.1 Control bits of watchdog timer
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
FF07H
00WDEN WDRST
R/W WR
0
∗
3
0
∗
3
WDEN
WDRST
∗
3
–
∗
2
–
∗
2
1
Reset
Enable
Reset
Disable
Invalid
Unused
Unused
Watchdog timer enable
Watchdog timer reset (writing)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
WDEN: Watchdog timer enable register (FF07H•D1)
Selects whether the watchdog timer is used (enabled) or not (disabled).
When "1" is written: Enabled
When "0" is written: Disabled
Reading: Valid
When "1" is written to the WDEN register, the watchdog timer starts count operation. When "0" is written,
the watchdog timer does not count and does not generate the interrupt (NMI).
At initial reset, this register is set to "1".
WDRST: Watchdog timer reset (FF07H•D0)
Resets the watchdog timer.
When "1" is written: Watchdog timer is reset
When "0" is written: No operation
Reading: Always "0"
When "1" is written to WDRST, the watchdog timer is reset and restarts immediately after that. When "0"
is written, no operation results.
This bit is dedicated for writing, and is always "0" for reading.
4.3.4 Programming notes
(1) When the watchdog timer is being used, the software must reset it within 3-second cycles.
(2) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled
state (not used) before generating an interrupt (NMI) if it is not used.
S1C63158 TECHNICAL MANUAL EPSON 27
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.4 Oscillation Circuit
4.4.1 Configuration of oscillation circuit
The S1C63158 has two oscillation circuits (OSC1 and OSC3). OSC1 is either a crystal or a CR oscillation
circuit that supplies the operating clock to the CPU and peripheral circuits. OSC3 is either a CR or a
ceramic oscillation circuit. When processing with the S1C63158 requires high-speed operation, the CPU
operating clock can be switched from OSC1 to OSC3 by the software. To stabilize operation of the internal
circuits, the operating voltage VD1 must be switched according to the oscillation circuit to be used. Figure
4.4.1.1 is the block diagram of this oscillation system.
Oscillation circuit control signal
CPU clock selection signal
To CPU
To peripheral circuits
Clock
switch
Oscillation system
voltage regulator
OSC3
oscillation circuit
OSC1
oscillation circuit
Operating voltage selection signal
VD1
Divider
Fig. 4.4.1.1 Oscillation system block diagram
28 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.4.2 OSC1 oscillation circuit
The OSC1 oscillation circuit generates the main clock for the CPU and the peripheral circuits. Either the
crystal oscillation circuit or the CR oscillation circuit can be selected as the circuit type by mask option.
The oscillation frequency of the crystal oscillation circuit is 32.768 kHz (Typ.) and the CR oscillation
circuit is 60 kHz (Typ.).
Figure 4.4.2.1 is the block diagram of the OSC1 oscillation circuit.
(b) CR oscillation circuit
Fig. 4.4.2.1 OSC1 oscillation circuit
As shown in Figure 4.4.2.1, the crystal oscillation circuit can be configured simply by connecting the
crystal oscillator (X'tal) of 32.768 kHz (Typ.) between the OSC1 and OSC2 terminals and the trimmer
capacitor (CGX) between the OSC1 and VSS terminals when crystal oscillation is selected.
The CR oscillation circuit can be configured simply by connecting the resistor RCR1 between the OSC1
and OSC2 terminals when CR oscillation is selected. See Chapter 7, "Electrical Characteristics" for resis-
tance value of RCR1.
Note: • The current consumption of CR oscillation is larger than crystal oscillation.
•Be aware that the CR oscillation frequency changes slightly.
Pay special attention to the circuits that use fOSC1 as the source clock, such as the timer (time
lag), the LCD frame frequency (display quality, flicker in low frequency) and the sound generator
(sound quality).
(a) Crystal oscillation circuit
VSS
CGX
X'tal
OSC2
OSC1
R
RDX
CDX
To CPU
(and peripheral circuits)
FX
VSS
OSC2
OSC1
CCR
To CPU
(and peripheral circuits)
RCR1
S1C63158 TECHNICAL MANUAL EPSON 29
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.4.3 OSC3 oscillation circuit
The S1C63158 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Typ. 2 MHz)
for high speed operation and the source clock for peripheral circuits needing a high speed clock (pro-
grammable timer, FOUT output). The mask option enables selection of either the CR or ceramic oscilla-
tion circuit. When CR oscillation is selected, only a resistance is required as an external element. When
ceramic oscillation is selected, a ceramic oscillator and two capacitors (gate and drain capacitance) are
required.
Figure 4.4.3.1 is the block diagram of the OSC3 oscillation circuit.
(a) CR oscillation circuit
(b) Ceramic oscillation circuit
Fig. 4.4.3.1 OSC3 oscillation circuit
As shown in Figure 4.4.3.1, the CR oscillation circuit can be configured simply by connecting the resistor
RCR2 between the OSC3 and OSC4 terminals when CR oscillation is selected. See Chapter 7, "Electrical
Characteristics" for resistance value of RCR2.
When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the
ceramic oscillator (Typ. 2 MHz) between the OSC3 and OSC4 terminals, capacitor CGC between the OSC3
and OSC4 terminals, and capacitor CDC between the OSC4 and VSS terminals. For both CGC and CDC,
connect capacitors that are about 100 pF. To reduce current consumption of the OSC3 oscillation circuit,
oscillation can be stopped by the software (OSCC register).
CCR
OSC3
OSC4
RCR2
VSS
CGC
CDC
Ceramic
OSC4
OSC3
R
RDC
FC
To CPU
(and some peripheral circuits)
Oscillation circuit control signal
To CPU
(and some peripheral circuits)
Oscillation circuit control signal
30 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.4.4 Switching of operating voltage
The CPU system clock is switched to OSC1 or OSC3 by the software (CLKCHG register). In this case, to
obtain stable operation, the operating voltage VD1 for the internal circuits must be switched by the
software (VDC register). As described in Section 4.2, "Setting of Power Supply and Operating Mode", the
oscillation system voltage regulator that generates VD1 must be set in an appropriate operating mode
according to the supply voltage.
Table 4.4.4.1 shows the correspondence of the system clock, operating voltage VD1 and operating mode
for the oscillation system voltage regulator.
Table 4.4.4.1 System clock and operating voltage
Operating
condition
OSC1
OSC3, 4 MHz
Power supply voltage V
DD
(V)
0.9–1.35 1.35–2.2 2.2–3.6
V
C2
mode Normal mode ∗
Cannot work Normal mode
Operating
voltage V
D1
1.3 V
2.1 V
*Set the VC2 mode when a power supply voltage drop is detected by the SVD circuit, such as
during a heavy load operation (driving buzzer or lamp) or by battery deletion.
When switching the operating voltage and the system clock, properly set the operating mode for the
oscillation system voltage regulator before and after. (See Section 4.2, "Setting of Power Supply and
Operation Mode".)
When OSC3 is to be used as the CPU system clock, it should be done as the following procedure using
the software: first switch the operating mode (if necessary) and the operating voltage VD1, turn the OSC3
oscillation ON after waiting 2.5 msec or more for the above operation to stabilize, switch the clock after
waiting 5 msec or more for oscillation stabilization.
When switching from OSC3 to OSC1, turn the OSC3 oscillation circuit OFF after switching the clock then
set the operating voltage VD1 to 1.3 V. After that, switch the operating mode if necessary.
OSC1
→
OSC3 OSC3
→
OSC1
1. Set operation mode for OSC3. ∗1. Set CLKCHG to "0" (OSC3 → OSC1).
2. Set VDC to "1" (1.3 V → 2.1 V). 2. Set OSCC to "0" (OSC3 oscillation OFF).
3. Maintain 2.5 msec or more. 3. Set VDC to "0" (2.1 V → 1.3 V).
4. Set OSCC to "1" (OSC3 oscillation ON). 4. Set operation mode for OSC1. ∗
5. Maintain 5 msec or more.
6. Set CLKCHG to "1" (OSC1 → OSC3). (∗: Should be done only when necessary.)
However, since the VD1 voltage value is fixed at 2.1 V when CR oscillation is selected for the OSC1
oscillation circuit by mask option and the OSC3 oscillation circuit (CR or ceramic oscillation) is also used,
it is not necessary to switch VD1 by software. When the OSC3 oscillation circuit is not used, the OSC1
oscillation circuit can operate with 1.3 V of VD1 even if CR oscillation is selected.
The following shows the operating mode settings for the oscillation system voltage regulator depending
on the power supply voltage.
(1)Power supply voltag e VDD = 0.9 V to 1.35 V
When the power supply voltage is in this range, the oscillation system voltage regulator can be
operated only in the VC2 mode.
(2)Power supply voltag e VDD = 1.35 V to 2.2 V
When the system clock is OSC1, operate the oscillation system voltage regulator in the normal mode.
(3)Power supply voltag e VDD = 2.2 V to 3.6 V
When the power supply voltage is in this range, the oscillation system voltage regulator can always
be operated in the normal mode regardless of the system clock selection. Therefore, it is nor necessary
to switch the operating mode before and after switching the system clock.
S1C63158 TECHNICAL MANUAL EPSON 31
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.4.5 Clock frequency and instruction execution time
Table 4.4.5.1 shows the instruction execution time according to each frequency of the system clock.
Table 4.4.5.1 Clock frequency and instruction execution time
Clock frequency
OSC1: 32.768 kHz
OSC1: 60 kHz
OSC3: 4 MHz
Instruction execution time (µsec)
1-cycle instruction 2-cycle instruction 3-cycle instruction
61 122 183
33 66 100
0.5 1 1.5
4.4.6 I/O memory of oscillation circuit
Table 4.4.6.1 shows the I/O address and the control bits for the oscillation circuit.
Table 4.4.6.1 Control bits of oscillation circuit
Address Comment
D3 D2
Register
D1 D0 Name Init ∗110
FF00H
CLKCHG
OSCC 0 VDC
R R/WR/W
CLKCHG
OSCC
0
∗
3
VDC
0
0
–
∗
2
0
OSC3
On
2.1 V
OSC1
Off
1.3 V
CPU clock switch
OSC3 oscillation On/Off
Unused
CPU operating voltage switch (1.3 V: OSC1, 2.1 V: OSC3)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
VDC: CPU operating voltage switching register (FF00H•D0)
It is used to switch the operating voltage VD1, when the crystal oscillation circuit has been selected as the
OSC1 oscillation circuit by mask option.
When "1" is written: 2.1 V (for OSC3 operation)
When "0" is written: 1.3 V (for OSC1 operation)
Reading: Valid
When switching the CPU system clock, the operating voltage VD1 should also be switched according to
the clock.
When switching from OSC1 to OSC3, first set VD1 to 2.1 V. After that maintain 2.5 msec or more, and then
turn the OSC3 oscillation ON.
When switching from OSC3 to OSC1, set VD1 to 1.3 V after switching to OSC1 and turning the OSC3
oscillation OFF.
However, since the VD1 voltage value is fixed at 2.1 V when CR oscillation is selected for the OSC1
oscillation circuit by mask option and the OSC3 oscillation circuit (CR or ceramic oscillation) is also used,
it is not necessary to switch VD1 by software. When the OSC3 oscillation circuit is not used, the OSC1
oscillation circuit can operate with 1.3 V of VD1 even if CR oscillation is selected.
At initial reset, this register is set to "0".
OSCC: OSC3 oscillation control register (FF00H•D2)
Controls oscillation ON/OFF for the OSC3 oscillation circuit.
When "1" is written: OSC3 oscillation ON
When "0" is written: OSC3 oscillation OFF
Reading: Valid
When it is necessary to operate the CPU at high speed, set OSCC to "1". At other times, set it to "0" to
reduce current consumption. Furthermore, when the crystal oscillation circuit has been selected as the
OSC1 oscillation circuit by mask option, it is necessary to switch the operating voltage VD1 when turning
the OSC3 oscillation circuit ON and OFF
At initial reset, this register is set to "0".
32 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
CLKCHG: CPU system clock switching register (FF00H•D3)
The CPU's operation clock is selected with this register.
When "1" is written: OSC3 clock is selected
When "0" is written: OSC1 clock is selected
Reading: Valid
When the CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0".
After turning the OSC3 oscillation ON (OSCC = "1"), switching of the clock should be done after waiting
5 msec or more.
When VD1 is 1.3 V (VDC = "0") and when OSC3 oscillation is OFF (OSCC = "0"), setting of CLKCHG = "1"
becomes invalid and switching to OSC3 is not performed. When the CR oscillation circuit has been
selected as the OSC1 oscillation circuit by mask option, setting VDC to "0" makes no difference.
At initial reset, this register is set to "0".
4.4.7 Programming notes
(1) When switching the CPU system clock from OSC1 to OSC3, first set VD1. After that maintain 2.5 msec
or more, and then turn the OSC3 oscillation ON.
When switching from OSC3 to OSC1, set VD1 after switching to OSC1 and turning the OSC3 oscilla-
tion OFF. However, when the CR oscillation circuit has been selected as the OSC1 oscillation circuit, it
is not necessary to set VD1.
(2) It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabi-
lizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a
minimum of 5 msec have elapsed since the OSC3 oscillation went ON.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics
and conditions of use, so allow ample margin when setting the wait time.
(3) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3
oscillation OFF. An error in the CPU operation can result if this processing is performed at the same
time by the one instruction.
(4) Since the VD1 voltage value is fixed at 2.1 V when CR oscillation is selected for the OSC1 oscillation
circuit by mask option and the OSC3 oscillation circuit (CR or ceramic oscillation) is also used, it is not
necessary to switch VD1 by software. When the OSC3 oscillation circuit is not used, the OSC1 oscilla-
tion circuit can operate with 1.3 V of VD1 even if CR oscillation is selected.
S1C63158 TECHNICAL MANUAL EPSON 33
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.5 Input Ports (K00–K03, K10–K13 and K20)
4.5.1 Configuration of input ports
The S1C63158 has nine bits general-purpose input ports. Each of the input port terminals (K00–K03, K10–
K13, K20) provides internal pull-up resistor. Pull-up resistor can be selected for each bit with the mask
option.
Figure 4.5.1.1 shows the configuration of input port (K00–K03, K10–K13).
Figure 4.5.1.2 shows the configuration of input port (K20).
Kxx
Mask option
Address
VDD
Interrupt
request
Data bus
VSS
Fig. 4.5.1.1 Configuration of input port (K00–K03, K10–K13)
K20
Mask option
VDD
Interrupt
request
Data bus
VSS
Key sense
ON/OFF control
Address
Address
Fig. 4.5.1.2 Configuration of input port (K20)
Selection of "With pull-up resistor" with the mask option suits input from the push switch, key matrix,
and so forth. When "Gate direct" is selected, the port can be used for slide switch input and interfacing
with other LSIs.
34 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.5.2 Interrupt function
All nine bits of the input ports (K00–K03, K10–K13, K20) provide the interrupt function. The conditions
for issuing an interrupt can be set by the software. Further, whether to mask the interrupt function can be
selected by the software. The input interrupts are divided into three systems: K0 (K00–K03), K1 (K10–
K13) and K20 systems.
Figure 4.5.2.1 shows the configuration of K00–K03 (K10–K13) interrupt circuit.
Figure 4.5.2.2 shows the configuration of K20 interrupt circuit.
Data bus
Input comparison
register (KCP00, 10)
K00, 10
Interrupt
request
Interrupt selection
register (SIK00, 10)
Address
Address
Address
Address
Interrupt factor
flag (IK0, 1)
K01, 11
K02, 12
K03, 13
Interrupt mask
register (EIK0, 1)
Address
Fig. 4.5.2.1 Input interrupt circuit configuration (K00–K03, K10–K13)
Data bus
Input comparison
register (KCP20)
K20
Interrupt
request
Interrupt selection
register (SIK20)
Address
Address
Address Address
Interrupt factor
flag (IK2)
Interrupt mask
register (EIK2)
Address
Fig. 4.5.2.2 Input interrupt circuit configuration (K20)
S1C63158 TECHNICAL MANUAL EPSON 35
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
The interrupt selection register (SIK) and input comparison register (KCP) are individually set for the
input ports K00–K03, K10–K13 and K20, and can specify the terminals for generating interrupt and
interrupt timing.
The interrupt selection registers (SIK00–SIK03, SIK10–SIK13, SIK20) select what input of K00–K03, K10–
K13 and K20 to use for the interrupt. Writing "1" into an interrupt selection register incorporates that
input port into the interrupt generation conditions. The changing the input port where the interrupt
selection register has been set to "0" does not affect the generation of the interrupt.
The input interrupt timing can select that the interrupt be generated at the rising edge of the input or that
it be generated at the falling edge according to the set value of the input comparison registers (KCP00–
KCP03, KCP10–KCP13, KCP20).
By setting these two conditions, the interrupt for K00–K03, K10–K13 or K20 is generated when input
ports in which an interrupt has been enabled by the input selection registers and the contents of the input
comparison registers have been changed from matching to no matching.
The interrupt mask registers (EIK0, EIK1, EIK2) enable the interrupt mask to be selected for K00–K03,
K10–K13 and K20.
When the interrupt is generated, the interrupt factor flag (IK0, IK1, IK2) is set to "1".
Figure 4.5.2.3 shows an example of an interrupt for K00–K03.
Interrupt selection register
SIK03
1
SIK02
1
SIK01
1
SIK00
0
Input port
(1)
(Initial value)
Interrupt generation
K03
1
K02
0
K01
1
K00
0
Input comparison register
KCP03
1
KCP02
0
KCP01
1
KCP00
0
With the above setting, the interrupt of K00–K03 is generated under the following condition:
(2) K03
1
K02
0
K01
1
K00
1
(3) K03
0
K02
0
K01
1
K00
1
(4) K03
0
K02
1
K01
1
K00
1
Because K00 interrupt is set to disable, interrupt will be
generated when no matching occurs between the
contents of the 3 bits K01–K03 and the 3 bits input
comparison register KCP01–KCP03.
Fig. 4.5.2.3 Example of interrupt of K00–K03
K00 interrupt is disabled by the interrupt selection register (SIK00), so that an interrupt does not occur at
(2). At (3), K03 changes to "0"; the data of the terminals that are interrupt enabled no longer match the
data of the input comparison registers, so that interrupt occurs. As already explained, the condition for
the interrupt to occur is the change in the port data and contents of the input comparison registers from
matching to no matching. Hence, in (4), when the no matching status changes to another no matching
status, an interrupt does not occur. Further, terminals that have been masked for interrupt do not affect
the conditions for interrupt generation.
4.5.3 Mask option
Internal pull-up resistor can be selected for each of the nine bits of the input ports (K00–K03, K10–K13,
K20) with the input port mask option.
When "Gate direct" is selected, take care that the floating status does not occur for the input. Select "With
pull-up resistor" for input ports that are not being used.
36 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.5.4 I/O memory of input ports
Table 4.5.4.1 shows the I/O addresses and the control bits for the input ports.
Table 4.5.4.1 Control bits of input ports
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
FF20H
SIK03 SIK02 SIK01 SIK00
R/W
SIK03
SIK02
SIK01
SIK00
0
0
0
0
Enable
Enable
Enable
Enable
Disable
Disable
Disable
Disable
K00–K03 interrupt selection register
FF21H
K03 K02 K01 K00
R
K03
K02
K01
K00
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
K00–K03 input port data
FF22H
KCP03 KCP02 KCP01 KCP00
R/W
KCP03
KCP02
KCP01
KCP00
1
1
1
1
K00–K03 input comparison register
FF24H
SIK13 SIK12 SIK11 SIK10
R/W
SIK13
SIK12
SIK11
SIK10
0
0
0
0
Enable
Enable
Enable
Enable
Disable
Disable
Disable
Disable
K10–K13 interrupt selection register
FF25H
K13 K12 K11 K10
R
K13
K12
K11
K10
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
K10–K13 input port data
FF26H
KCP13 KCP12 KCP11 KCP10
R/W
KCP13
KCP12
KCP11
KCP10
1
1
1
1
K10–K13 input comparison register
FFE4H
000EIK0
R R/W
0
∗
3
0
∗
3
0
∗
3
EIK0
–
∗
2
–
∗
2
–
∗
2
0 Enable Mask
Unused
Unused
Unused
Interrupt mask register (K00–K03)
FFF4H
000IK0
R R/W
0
∗
3
0
∗
3
0
∗
3
IK0
–
∗
2
–
∗
2
–
∗
2
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Unused
Unused
Interrupt factor flag (K00–K03)
FF28H
000SIK20
R R/W
0
∗
3
0
∗
3
0
∗
3
SIK20
–
∗
2
–
∗
2
–
∗
2
0 Enable Disable
Unused
Unused
Unused
K20 interrupt selection register
Unused
Unused
Unused
K20 input port data
Unused
Unused
Unused
K20 input comparison register
FF29H
000K20
R
0
∗
3
0
∗
3
0
∗
3
K20
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High Low
FF2AH
000KCP20
R R/W
0
∗
3
0
∗
3
0
∗
3
KCP20
–
∗
2
–
∗
2
–
∗
2
1
FFE5H
00EIK2 EIK1
R R/W
0
∗
3
0
∗
3
EIK2
EIK1
–
∗
2
–
∗
2
0
0
Enable
Enable
Mask
Mask
Unused
Unused
Interrupt mask register (K20)
Interrupt mask register (K10–K13)
FFF5H
00IK2 IK1
R R/W
0
∗
3
0
∗
3
IK2
IK1
–
∗
2
–
∗
2
0
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Unused
Interrupt factor flag (K20)
Interrupt factor flag (K10–K13)
FF2BH
000SENON
R R/W
0
∗
3
0
∗
3
0
∗
3
SENON
–
∗
2
–
∗
2
–
∗
2
1OnOff
Unused
Unused
Unused
Key sense On/Off control
*1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read
S1C63158 TECHNICAL MANUAL EPSON 37
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
K00–K03: K0 por t input port data (FF21H)
K10–K13: K1 por t input port data (FF25H)
K20: K20 port input port data (FF29H•D0)
Input data of the input port terminals can be read with these registers.
When "1" is read: High level
When "0" is read: Low level
Writing: Invalid
The reading is "1" when the terminal voltage of the nine bits of the input ports (K00–K03, K10–K13, K20)
goes high (VDD), and "0" when the voltage goes low (VSS).
These bits are dedicated for reading, so writing cannot be done.
SIK00–SIK03: K0 por t interrupt selection register (FF20H)
SIK10–SIK13: K1 por t interrupt selection register (FF24H)
SIK20: K20 port interrupt selection register (FF28H•D0)
Selects the ports to be used for the K00–K03, K10–K13 and K20 input interrupts.
When "1" is written: Enable
When "0" is written: Disable
Reading: Valid
Enables the interrupt for the input ports (K00–K03, K10–K13, K20) for which "1" has been written into the
interrupt selection registers (SIK00–SIK03, SIK10–SIK13, SIK20). The input port set for "0" does not affect
the interrupt generation condition.
At initial reset, these registers are set to "0".
KCP00–KCP03: K0 port input comparison register (FF22H)
KCP10–KCP13: K1 port input comparison register (FF26H)
KCP20: K20 port input comparison register (FF2AH•D0)
Interrupt conditions for terminals K00–K03, K10–K13 and K20 can be set with these registers.
When "1" is written: Falling edge
When "0" is written: Rising edge
Reading: Valid
The interrupt conditions can be set for the rising or falling edge of input for each of the nine bits (K00–
K03, K10–K13, K20), through the input comparison registers (KCP00–KCP03, KCP10–KCP13, KCP20).
For KCP00–KCP03, a comparison is done only with the ports that are enabled by the interrupt among
K00–K03 by means of the SIK00–SIK03 registers. For KCP10–KCP13, a comparison is done only with the
ports that are enabled by the interrupt among K10–K13 by means of the SIK10–SIK13 registers. For
KCP20, a comparison is done only when the K20 port has been enabled by means of the SIK20 register.
At initial reset, these registers are set to "0".
EIK0: K0 input interrupt mask register (FFE4H•D0)
EIK1: K1 input interrupt mask register (FFE5H•D0)
EIK2: K20 input interrupt mask register (FFE5H•D1)
Masking the interrupt of the input port can be selected with these registers.
When "1" is written: Enable
When "0" is written: Mask
Reading: Valid
With these registers, masking of the input port interrupt can be selected for each of the three systems
(K00–K03, K10–K13, K20).
At initial reset, these registers are set to "0".
38 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
IK0: K0 input interrupt factor flag (FFF4H•D0)
IK1: K1 input interrupt factor flag (FFF5H•D0)
IK2: K20 input interrupt factor flag (FFF5H•D1)
These flags indicate the occurrence of input interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
The interrupt factor flags IK0, IK1 and IK2 are associated with K00–K03, K10–K13 and K20, respectively.
From the status of these flags, the software can decide whether an input interrupt has occurred.
The interrupt factor flag is set to "1" when the interrupt condition is established regardless of the inter-
rupt mask register setting. However, the interrupt does not occur to the CPU when the interrupt is
masked.
These flags are reset to "0" by writing "1" to them.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".
SENON: K20 port key sense ON/OFF control (FF2BH•D0)
Controls the key sense function.
When "1" is written: On
When "0" is written: Off
Reading: Valid
When using K20 as a general purpose input port, fix this register at "1" (On).
When K20 is used for the key sense function, set SENON on during the key sense stage. If any key is
pressed (see Figure 4.5.4.1), the K20 port generates an interrupt to the CPU. Then set SENON to off (K20
port key sense OFF), turn the outside N-P-N transistor on using an output port and start the A/D con-
verter. The A/D converter converts the input voltage that varies according to the pressed key into a
digital value. The software can discriminates which key was pressed from the conversion result. After
that, turn SENON off to reduce current consumption.
V
DD
R1
R
R2 R3
A/D IN
K20
Output SENON
register
Generate
an interrupt
Key set
MCU
Fig. 4.5.4.1 Key position sensing circuit
S1C63158 TECHNICAL MANUAL EPSON 39
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
This chart is an example of the circuit that discriminates the pressed key with only two wires connected
between the MCU chip and the key set. It is useful to reduce the connection wires when the key set
location is far from the MCU chip.
Operation: The keys are connected to the ground via a resistor that is different from other keys. So each
key will generate a different voltage for inputting to the A/D converter.
Pressing a key generates an interrupt to the MCU. The interrupt turns the transistor on using
the output port and starts A/D conversion. The MCU can discriminate the pressed key using
the digital value converted by the A/D converter.
4.5.5 Programming notes
(1) When input ports are changed from low to high by pull-up resistors, the rise of the waveform is
delayed on account of the time constant of the pull-up resistor and input gate capacitance. Hence,
when fetching input ports, set an appropriate waiting time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-up resistance 300 kΩ
(2) The K13 terminal functions as the clock input terminal for the programmable timer, and the input
signal is shared with the input port and the programmable timer. Therefore, when the K13 terminal is
set to the clock input terminal for the programmable timer, take care of the interrupt setting.
(3) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
40 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
4.6 Output Ports (R00–R03, R10–R13 and R20–R23)
4.6.1 Configuration of output ports
The S1C63158 has 12 bits general output ports.
Output specifications of the output ports can be selected individually with the mask option. Two kinds of
output specifications are available: complementary output and N-channel open drain output.
Figure 4.6.1.1 shows the configuration of the output port.
VDD
VSS
Rxx
Data bus
Address
Data register
Address
High impedance
control register
Mask option
(R00–R03 are fixed at complementary output.)
Fig. 4.6.1.1 Configuration of output port
The R02 and R03 output terminals are shared with special output terminals (TOUT, FOUT), and this
function is selected by the software.
At initial reset, these are all set to the general purpose output port.
Table 4.6.1.1 shows the setting of the output terminals by function selection.
Table 4.6.1.1 Function setting of output terminals
Terminal
name
R00
R01
R02
R03
R10–R13
R20–R23
Terminal status
at initial reset
R00 (High output)
R01 (High output)
R02 (High output)
R03 (High output)
R10–R13 (High output)
R20–R23 (High output)
Special output
TOUT FOUT
R00 R00
R01 R01
TOUT
FOUT
R10–R13 R10–R13
R20–R23 R20–R23
When using the output port (R02, R03) as the special output port, the data register must be fixed at "1"
and the high impedance control register must be fixd at "0" (data output).
4.6.2 Mask option
Output specifications of the output ports can be selected with the mask option.
The output specifications of the output ports R10–R13 and R20–R23 can be selected from either comple-
mentary output or N-channel open drain output individually (in 4-bit units). The output ports R00–R03
can only be used as complementary output.
However, when N-channel open drain output is selected, do not apply a voltage exceeding the power
supply voltage to the output port.
S1C63158 TECHNICAL MANUAL EPSON 41
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
4.6.3 High impedance control
The terminal output status of the output ports can be set to a high impedance status. This control is done
using the high impedance control registers.
The high impedance control registers are provided to correspond with the output ports as shown below.
High impedance control register Corresponding output port
R00HIZ R00 (1-bit)
R01HIZ R01 (1-bit)
R02HIZ R02 (1-bit)
R03HIZ R03 (1-bit)
R1HIZ R10–R13 (4-bit)
R2HIZ R20–R23 (4-bit)
When "1" is written to the high impedance control register, the corresponding output port terminal goes
into high impedance status. When "0" is written, the port outputs a signal according to the data register.
4.6.4 Special output
In addition to the regular DC output, special output can be selected for the output ports R02 and R03 as
shown in Table 4.6.4.1 with the software.
Figure 4.6.4.1 shows the configuration of the R02 and R03 output ports.
Table 4.6.4.1 Special output
Terminal
R03
R02
Special output
FOUT
TOUT
Output control register
FOUTE
PTOUT
Data bus
Register
PTOUT
Register
R02
TOUT
R02
(TOUT)
Register
FOUTE
Register
R03
Register
R03HIZ
Register
R02HIZ
FOUT
R03
(FOUT)
Fig. 4.6.4.1 Configuration of R02 and R03 output ports
At initial reset, the output port data register is set to "1" and the high impedance control register is set to
"0". Consequently, the output terminal goes high (VDD).
When using the output port (R02, R03) as the special output port, fix the data register (R02, R03) at "1"
and the high impedance control register (R02HIZ, R03HIZ) at "0" (data output). The respective signal
should be turned ON and OFF using the special output control register.
Note: • Be aware that the output terminal is fixed at a low (VSS) level the same as the DC output if "0" is
written to the R02 and R03 registers when the special output has been selected.
•Be aware that the output terminal shifts into high impedance status when "1" is written to the
high impedance control register (R02HIZ, R03HIZ).
42 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
•TOUT (R02)
The R02 terminal can output a TOUT signal.
The TOUT signal is the clock that is output from the programmable timer, and can be used to provide
a clock signal to an external device.
To output the TOUT signal, fix the R02 register at "1" and the R02HIZ register at "0", and turn the
signal ON and OFF using the PTOUT register. It is, however, necessary to control the programmable
timer.
Refer to Section 4.10, "Programmable Timer" for details of the programmable timer.
Note: A hazard may occur when the TOUT signal is turned ON and OFF.
Figure 4.6.4.2 shows the output waveform of the TOUT signal.
R02HIZ register
R02 register
PTOUT register
TOUT output
Fix at "0"
Fix at "1"
"1""0" "0"
Fig. 4.6.4.2 Output waveform of TOUT signal
• FOUT (R03)
The R03 terminal can output a FOUT signal.
The FOUT signal is a clock (fOSC1 or fOSC3) that is output from the oscillation circuit or a clock that the
fOSC1 clock has divided in the internal circuit, and can be used to provide a clock signal to an external
device.
To output the FOUT signal, fix the R03 register at "1" and the R03HIZ register at "0", and turn the
signal ON and OFF using the FOUTE register.
The frequency of the output clock may be selected from among 4 types shown in Table 4.6.4.2 by
setting the FOFQ0 and FOFQ1 registers.
Table 4.6.4.2 FOUT clock frequency
FOFQ1
1
1
0
0
FOFQ0
1
0
1
0
Clock frequency
f
OSC3
f
OSC1
f
OSC1
× 1/8
f
OSC1
× 1/64
fOSC1: Clock that is output from the OSC1 oscillation circuit
fOSC3: Clock that is output from the OSC3 oscillation circuit
When fOSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation
circuit before output.
Refer to Section 4.4, "Oscillation Circuit", for the control and notes.
Note: A hazard may occur when the FOUT signal is turned ON and OFF.
Figure 4.6.4.3 shows the output waveform of the FOUT signal.
R03HIZ register
R03 register
FOUTE register
FOUT output
Fix at "0"
Fix at "1"
"1""0" "0"
Fig. 4.6.4.3 Output waveform of FOUT signal
S1C63158 TECHNICAL MANUAL EPSON 43
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
4.6.5 I/O memory of output ports
Table 4.6.5.1 shows the I/O addresses and control bits for the output ports.
Table 4.6.5.1 Control bits of output ports
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
FF06H
FOUTE 0 FOFQ1 FOFQ0
R/W R R/W
FOUTE
0
∗
3
FOFQ1
FOFQ0
0
–
∗
2
0
0
Enable Disable
FOUT output enable
Unused
FOUT
frequency
selection
CHSEL
PTOUT
CKSEL1
CKSEL0
0
0
0
0
Timer1
On
OSC3
OSC3
Timer0
Off
OSC1
OSC1
TOUT output channel selection
TOUT output control
Prescaler 1 source clock selection
Prescaler 0 source clock selection
R/W
FFC1H
CHSEL PTOUT CKSEL1 CKSEL0
0
f
OSC1
/64 1
f
OSC1
/8 2
f
OSC1
3
f
OSC3
[FOFQ1, 0]
Frequency
FF30H
R03HIZ R02HIZ R01HIZ R00HIZ
R/W
R03HIZ
R02HIZ
R01HIZ
R00HIZ
0
0
0
0
High-Z
High-Z
High-Z
High-Z
Output
Output
Output
Output
R03 output high impedance control (FOUTE=0)
FOUT output high impedance control (FOUTE=1)
R02 output high impedance control (PTOUT=0)
TOUT output high impedance control (PTOUT=1)
R01 output high impedance control
R00 output high impedance control
FF31H
R03 R02 R01 R00
R/W
R03
R02
R01
R00
1
1
1
1
High
High
High
High
Low
Low
Low
Low
R03 output port data (FOUTE=0)
Fix at "1" when FOUT is used
R02 output port data (PTOUT=0)
Fix at "1" when TOUT is used
R01 output port data
R00 output port data
FF32H
000R1HIZ
R R/W
0
∗
3
0
∗
3
0
∗
3
R1HIZ
–
∗
2
–
∗
2
–
∗
2
0 High-Z Output
Unused
Unused
Unused
R1 output high impedance control
FF33H
R13 R12 R11 R10
R/W
R13
R12
R11
R10
1
1
1
1
High
High
High
High
Low
Low
Low
Low
R10–R13 output port data
FF34H
000R2HIZ
R R/W
0
∗
3
0
∗
3
0
∗
3
R2HIZ
–
∗
2
–
∗
2
–
∗
2
0 High-Z Output
Unused
Unused
Unused
R2 output high impedance control
FF35H
R23 R22 R21 R20
R/W
R23
R22
R21
R20
1
1
1
1
High
High
High
High
Low
Low
Low
Low
R20–R23 output port data
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
R00HIZ–R03HIZ: R0 por t high impedance control register (FF30H)
R1HIZ: R1 port high impedance control register (FF32H•D0)
R2HIZ: R2 port high impedance control register (FF34H•D0)
Controls high impedance output of the output port.
When "1" is written: High impedance
When "0" is written: Data output
Reading: Valid
By writing "0" to the high impedance control register, the corresponding output terminal outputs accord-
ing to the data register. When "1" is written, it shifts into high impedance status.
When the output ports R02 and R03 are used for special output (TOUT, FOUT), fix the R02HIZ register
and the R03HIZ register at "0" (data output).
At initial reset, these registers are set to "0".
44 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
R00–R03: R0 output port data register (FF31H)
R10–R13: R1 output port data register (FF33H)
R20–R23: R2 output port data register (FF35H)
Set the output data for the output ports.
When "1" is written: High level output
When "0" is written: Low level output
Reading: Valid
The output port terminals output the data written in the corresponding data registers without changing
it. When "1" is written to the register, the output port terminal goes high (VDD), and when "0" is written,
the output port terminal goes low (VSS).
When the output ports R02 and R03 are used for special output (TOUT, FOUT), fix the R02 register and
the R03 register at "1".
At initial reset, these registers are all set to "1".
FOUTE: FOUT output control register (FF06H•D3)
Controls the FOUT output.
When "1" is written: FOUT output ON
When "0" is written: FOUT output OFF
Reading: Valid
By writing "1" to the FOUTE register when the R03 register has been set to "1" and the R03HIZ register
has been set to "0", an FOUT signal is output from the R03 terminal. When "0" is written, the R03 terminal
goes high (VDD).
When using the R03 output port for DC output, fix this register at "0".
At initial reset, this register is set to "0".
FOFQ0, FOFQ1: FOUT frequency selection register (FF06H•D0, D1)
Selects a frequency of the FOUT signal.
Table 4.6.5.2 FOUT clock frequency
FOFQ1
1
1
0
0
FOFQ0
1
0
1
0
Clock frequency
f
OSC3
f
OSC1
f
OSC1
× 1/8
f
OSC1
× 1/64
At initial reset, this register is set to "0".
PTOUT: TOUT output control register (FFC1H•D2)
Controls the TOUT output.
When "1" is written: TOUT output ON
When "0" is written: TOUT output OFF
Reading: Valid
By writing "1" to the PTOUT register when the R02 register has been set to "1" and the R02HIZ register
has been set to "0", the TOUT signal is output from the R02 terminal. When "0" is written, the R02 termi-
nal goes high (VDD).
When using the R02 output port for DC output, fix this register at "0".
At initial reset, this register is set to "0".
S1C63158 TECHNICAL MANUAL EPSON 45
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
4.6.6 Programming notes
(1) When using the output port (R02, R03) as the special output port, fix the data register (R02, R03) at "1"
and the high impedance control register (R02HIZ, R03HIZ) at "0" (data output).
Be aware that the output terminal is fixed at a low (VSS) level the same as the DC output if "0" is
written to the R02 and R03 registers when the special output has been selected.
Be aware that the output terminal shifts into high impedance status when "1" is written to the high
impedance control register (R02HIZ, R03HIZ).
(2) A hazard may occur when the FOUT signal and the TOUT signal are turned ON and OFF.
(3) When fOSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation
circuit before output.
Refer to Section 4.4, "Oscillation Circuit", for the control and notes.
46 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
4.7 I/O Ports (P00–P03, P10–P13, P20–P23, P30–P33 and P40–P43)
4.7.1 Configuration of I/O ports
The S1C63158 has 20 bits general-purpose I/O ports. Figure 4.7.1.1 shows the configuration of the I/O
port.
Address
Data
register
Data bus
P
Address
Address
Address
I/O control
register (IOC)
Pull-up control
register (PUL)
Mask option
VDD
Fig. 4.7.1.1 Configuration of I/O port
The P10–P13 I/O port terminals are shared with the serial interface input/output terminals and this
function is selected by the software. The P40–P43 I/O port terminals are shared with the A/D converter
input terminals and this function is also selected by the software.
At initial reset, these are all set to the I/O port.
Table 4.7.1.1 shows the setting of the input/output terminals by function selection.
Table 4.7.1.1 Function setting of input/output terminals
Terminal
name
P00–P03
P10
P11
P12
P13
P20–P23
P30–P33
P40
P41
P42
P43
Terminal status
at initial reset
P00–P03 (Input & pull-up)
P10 (Input & pull-up ∗)
P11 (Input & pull-up ∗)
P12 (Input & pull-up ∗)
P13 (Input & pull-up ∗)
P20–P23 (Input & pull-up ∗)
P30–P33 (Input & pull-up ∗)
P40 (Input & Pull-up ∗)
P41 (Input & Pull-up ∗)
P42 (Input & Pull-up ∗)
P43 (Input & Pull-up ∗)
Serial I/F
Master Slave
P00–P03 P00–P03
SIN(I) SIN(I)
SOUT(O) SOUT(O)
SCLK(O) SCLK(I)
P13 SRDY(O)
P20–P23 P20–P23
P30–P33 P30–P33
A/D
converter
P00–P03
P20–P23
P30–P33
AD0(I)
AD1(I)
AD2(I)
AD3(I)
∗When "with pull-up resistor" is selected by the mask option
(high impedance when "gate direct" is set)
When these ports are used as I/O ports, the ports can be set to either input mode or output mode (in 1-bit
unit). Modes can be set by writing data to the I/O control registers.
Refer to Section 4.11, "Serial Interface", for control of the serial interface.
Refer to Section 4.9, "A/D Converter", for control of the A/D converter.
S1C63158 TECHNICAL MANUAL EPSON 47
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
4.7.2 Mask option
In the I/O ports, the output specification during output mode can be selected from either complementary
output or N-channel open drain output by mask option. The mask option also enables selection of
whether the pull-up resistor is used or not during input mode. They are selected in 1-bit units or 4-bit
units according to the terminal group.
Ports to be selected in 1-bit units: P20, P21, P22, P23, P30, P31, P32, P33, P40, P41, P42, P43
Ports to be selected in 4-bit units: P10–P13
∗ P00–P03 are fixed at complementary output and pull-up resistor input.
When N-channel open drain output is selected, do not apply a voltage exceeding the power supply
voltage to the port.
When "without pull-up" during the input mode is selected, take care that the floating status does not
occur.
This option is effective even when I/O ports are used for input/output of the serial interface or input of
the A/D converter. When using the A/D converter, select "without pull-up" for the port corresponding to
the A/D channel to be used.
4.7.3 I/O control registers and input/output mode
Input or output mode can be set for the I/O ports by writing data into the corresponding I/O control
registers IOCxx.
To set the input mode, write "0" to the I/O control register. When an I/O port is set to input mode, it
becomes high impedance status and works as an input port.
However, when the pull-up explained in the following section has been set by software, the input line is
pulled up only during this input mode.
To set the output mode, write "1" is to the I/O control register. When an I/O port is set to output mode , it
works as an output port, it outputs a high level (VDD) when the port output data is "1", and a low level
(VSS) when the port output data is "0".
If perform the read out in each mode; when output mode, the register value is read out, and when input
mode, the port value is read out.
At initial reset, the I/O control registers are set to "0", and the I/O ports enter the input mode.
The I/O control registers of the ports that are set as input/output for the serial interface and A/D
converter can be used as general purpose registers that do not affect the I/O control. (See Table 4.7.1.1.)
4.7.4 Pull-up during input mode
A pull-up resistor that operates during the input mode is built into each I/O port of the S1C63158. Mask
option can set the use or non-use of this pull-up. The pull-up resistor becomes effective by writing "1" to
the pull-up control register PULxx that corresponds to each port, and the input line is pulled up during
the input mode. When "0" has been written, no pull-up is done.
At initial reset, the pull-up control registers are set to "1".
The pull-up control registers of the ports in which "without pull-up" have been selected can be used as
general purpose registers. Even when "with pull-up" has been selected, the pull-up control registers of
the ports that are set as input/output for the serial interface can be used as general purpose registers that
do not affect the pull-up control. (See Table 4.7.1.1.)
The pull-up control registers of the port, that are set as input for the serial interface, function the same as
the I/O port.
48 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
4.7.5 I/O memory of I/O ports
Tables 4.7.5.1(a) and (b) show the I/O addresses and the control bits for the I/O ports.
Table 4.7.5.1(a) Control bits of I/O ports (1)
D3 D2 D1 D0 Name Init
∗1
10
Address Comment
Register
FF40H
IOC03 IOC02 IOC01 IOC00
R/W
IOC03
IOC02
IOC01
IOC00
0
0
0
0
Output
Output
Output
Output
Input
Input
Input
Input
P00–P03 I/O control register
FF44H
IOC13 IOC12 IOC11 IOC10
R/W
IOC13
IOC12
IOC11
IOC10
0
0
0
0
Output
Output
Output
Output
Input
Input
Input
Input
P13 I/O control register
functions as a general-purpose register when SIF (slave) is selected
P12 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
P11 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
P10 I/O control register (ESIF=0)
functions as a general-purpose register when SIF is selected
FF46H
P13 P12 P11 P10
R/W
P13
P12
P11
P10
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
P13 I/O port data
functions as a general-purpose register when SIF (slave) is selected
P12 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
P11 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
P10 I/O port data (ESIF=0)
functions as a general-purpose register when SIF is selected
FF41H
PUL03 PUL02 PUL01 PUL00
R/W
PUL03
PUL02
PUL01
PUL00
1
1
1
1
On
On
On
On
Off
Off
Off
Off
P00–P03 pull-up control register
FF42H
P03 P02 P01 P00
R/W
P03
P02
P01
P00
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
P00–P03 I/O port data
FF45H
PUL13 PUL12 PUL11 PUL10
R/W
PUL13
PUL12
PUL11
PUL10
1
1
1
1
On
On
On
On
Off
Off
Off
Off
P13 pull-up control register
functions as a general-purpose register when SIF (slave) is selected
P12 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF (master) is selected
SCLK (I) pull-up control register when SIF (slave) is selected
P11 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF is selected
P10 pull-up control register (ESIF=0)
SIN pull-up control register
when SIF is selected
FF48H
IOC23 IOC22 IOC21 IOC20
R/W
IOC23
IOC22
IOC21
IOC20
0
0
0
0
Output
Output
Output
Output
Input
Input
Input
Input
P20–P23 I/O control register
FF49H
PUL23 PUL22 PUL21 PUL20
R/W
PUL23
PUL22
PUL21
PUL20
1
1
1
1
On
On
On
On
Off
Off
Off
Off
P20–P23 pull-up control register
FF4AH
P23 P22 P21 P20 P23
P22
P21
P20
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
P20–P23 I/O port data
FF4CH
IOC33 IOC32 IOC31 IOC30
R/W
IOC33
IOC32
IOC31
IOC30
0
0
0
0
Output
Output
Output
Output
Input
Input
Input
Input
P30–P33 I/O control register
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
S1C63158 TECHNICAL MANUAL EPSON 49
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
Table 4.7.5.1(b) Control bits of I/O ports (2)
D3 D2 D1 D0 Name Init
∗1
10
Address Comment
Register
FF4DH
PUL33 PUL32 PUL31 PUL30
R/W
PUL33
PUL32
PUL31
PUL30
1
1
1
1
On
On
On
On
Off
Off
Off
Off
P30–P33 pull-up control register
FF4EH
P33 P32 P31 P30
R/W
P33
P32
P31
P30
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
P30–P33 I/O port data
FF50H
IOC43 IOC42 IOC41 IOC40
R/W
IOC43
IOC42
IOC41
IOC40
0
0
0
0
Output
Output
Output
Output
Input
Input
Input
Input
P43 I/O control register (PAD3=0)
functions as a general-purpose register when A/D is enabled
P42 I/O control register (PAD2=0)
functions as a general-purpose register when A/D is enabled
P41 I/O control register (PAD1=0)
functions as a general-purpose register when A/D is enabled
P40 I/O control register (PAD0=0)
functions as a general-purpose register when A/D is enabled
FF51H
PUL43 PUL42 PUL41 PUL40
R/W
PUL43
PUL42
PUL41
PUL40
1
1
1
1
On
On
On
On
Off
Off
Off
Off
P43 pull-up control register (PAD3=0)
functions as a general-purpose register when A/D is enabled
P42 pull-up control register (PAD2=0)
functions as a general-purpose register when A/D is enabled
P41 pull-up control register (PAD1=0)
functions as a general-purpose register when A/D is enabled
P40 pull-up control register (PAD0=0)
functions as a general-purpose register when A/D is enabled
FF52H
P43 P42 P41 P40
R/W
P43
P42
P41
P40
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
P43 I/O port data (PAD3=0)
functions as a general-purpose register when A/D is enabled
P42 I/O port data (PAD2=0)
functions as a general-purpose register when A/D is enabled
P41 I/O port data (PAD1=0)
functions as a general-purpose register when A/D is enabled
P40 I/O port data (PAD0=0)
functions as a general-purpose register when A/D is enabled
PAD3
PAD2
PAD1
PAD0
0
0
0
0
Enable
Enable
Enable
Enable
Disable
Disable
Disable
Disable
R/W
FFD1H
PAD3 PAD2 PAD1 PAD0
P43 input channel enable/disable control
P42 input channel enable/disable control
P41 input channel enable/disable control
P40 input channel enable/disable control
FF70H
0 ESOUT SCTRG ESIF
R R/W
0
∗
3
ESOUT
SCTRG
ESIF
–
∗
2
0
0
0
Enable
Trigger
Run
SIF
Disable
Invalid
Stop
I/O
Unused
SOUT enable/disable control
Serial I/F clock trigger (writing)
Serial I/F clock status (reading)
Serial I/F enable (P1 port function selection)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
ESIF: Serial interface enable register (FF70H•D0)
Selects function for P10–P13.
When "1" is written: Serial interface input/output port
When "0" is written: I/O port
Reading: Valid
When using the serial interface, write "1" to this register and when P10–P13 are used as the I/O port,
write "0". The configuration of the terminals within P10–P13 that are used for the serial interface is
decided by the mode selected with the SCS1 and SCS0 registers (see Section 4.11).
In the slave mode, all the P10–P13 ports are set to the serial interface input/output port. In the master
mode, P10–P12 are set to the serial interface input/output port and P13 can be used as the I/O port.
At initial reset, this register is set to "0".
50 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
PAD0–PAD3: A/D input channel enable/disable control register (FFD1H)
Selects function for P40–P43.
When "1" is written: A/D converter input
When "0" is written: I/O port
Reading: Valid
When using the A/D converter, write "1" to the register. PAD0–PAD3 correspond to P40–P43, respectively.
When using a port from P40 to P43 as an I/O port, write "0" to the corresponding PAD register.
At initial reset, this register is set to "0".
P00–P03: P0 I/O port data register (FF42H)
P10–P13: P1 I/O port data register (FF46H)
P20–P23: P2 I/O port data register (FF4AH)
P30–P33: P3 I/O port data register (FF4EH)
P40–P43: P4 I/O port data register (FF52H)
I/O port data can be read and output data can be set through these registers.
• When writing data
When "1" is written: High level
When "0" is written: Low level
When an I/O port is set to the output mode, the written data is output unchanged from the I/O port
terminal. When "1" is written as the port data, the port terminal goes high (VDD), and when "0" is written,
the terminal goes low (VSS).
Port data can be written also in the input mode.
• When reading data
When "1" is read: High level
When "0" is read: Low level
The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage
level being input to the port terminal can be read out; in the output mode the register value can be read.
When the terminal voltage is high (VDD) the port data that can be read is "1", and when the terminal
voltage is low (VSS) the data is "0".
When "with pull-up resistor" has been selected with the mask option and the PUL register is set to "1", the
built-in pull-up resister goes ON during input mode, so that the I/O port terminal is pulled up.
The data registers of the ports that are set as input/output for the serial interface or A/D converter can be
used as general purpose registers that do not affect the input/output.
Note: When in the input mode, I/O ports are changed from low to high by pull-up resistor, the rise of the
waveform is delayed on account of the time constant of the pull-up resistor and input gate capaci-
tance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10
×
C
×
R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-up resistance 300 k
Ω
S1C63158 TECHNICAL MANUAL EPSON 51
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
IOC00–IOC03: P0 port I/O control register (FF40H)
IOC10–IOC13: P1 port I/O control register (FF44H)
IOC20–IOC23: P2 port I/O control register (FF48H)
IOC30–IOC33: P3 port I/O control register (FF4CH)
IOC40–IOC43: P4 port I/O control register (FF50H)
The input and output modes of the I/O ports are set with these registers.
When "1" is written: Output mode
When "0" is written: Input mode
Reading: Valid
The input and output modes of the I/O ports are set in 1-bit unit.
Writing "1" to the I/O control register makes the corresponding I/O port enter the output mode, and
writing "0" induces the input mode.
At initial reset, these registers are all set to "0", so the I/O ports are in the input mode.
The I/O control registers of the ports that are set as input/output for the serial interface or A/D con-
verter can be used as general purpose registers that do not affect the input/output.
PUL00–PUL03: P0 port pull-up control register (FF41H)
PUL10–PUL13: P1 port pull-up control register (FF45H)
PUL20–PUL23: P2 port pull-up control register (FF49H)
PUL30–PUL33: P3 port pull-up control register (FF4DH)
PUL40–PUL43: P4 port pull-up control register (FF51H)
The pull-up during the input mode are set with these registers.
When "1" is written: Pull-up ON
When "0" is written: Pull-up OFF
Reading: Valid
The built-in pull-up resistor which is turned ON during input mode is set to enable in 1-bit units. (The
pull-up resistor is included into the ports selected by the mask option.)
By writing "1" to the pull-up control register, the corresponding I/O ports are pulled up (during input
mode), while writing "0" turns the pull-up function OFF.
At initial reset, these registers are all set to "1", so the pull-up function is set to ON.
The pull-up control registers of the ports in which the pull-up resistor is not included become the general
purpose register. The registers of the ports that are set as input/output for the serial interface or A/D
converter can also be used as general purpose registers that do not affect the pull-up control.
The pull-up control registers of the port that are set as input for the serial interface function the same as
the I/O port.
4.7.6 Programming note
When in the input mode, I/O ports are changed from low to high by pull-up resistor, the rise of the
waveform is delayed on account of the time constant of the pull-up resistor and input gate capacitance.
Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-up resistance 300 kΩ
52 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.8 Clock Timer
4.8.1 Configuration of clock timer
The S1C63158 has a built-in clock timer that uses OSC1 (crystal oscillator) as the source oscillator. The
clock timer is configured of an 8-bit binary counter that serves as the input clock, fOSC1 divided clock
output from the prescaler. Timer data (128–16 Hz and 8–1 Hz) can be read out by the software.
Figure 4.8.1.1 is the block diagram for the clock timer.
128 Hz–16 Hz
Data bus
16 Hz, 8 Hz, 2 Hz, 1 Hz
256 Hz
Clock timer reset signal
Divider
Interrupt
request
Interrupt
control
8 Hz–1 Hz
Clock timer RUN/STOP signal
Clock timer
OSC1
oscillation circuit
(fOSC1)
Fig. 4.8.1.1 Block diagram for the clock timer
Ordinarily, this clock timer is used for all types of timing functions such as clocks.
Note: When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the
frequencies and times differ from the values described in this section because the oscillation
frequency will be 60 kHz (Typ.). Therefore, the clock timer can not be used for the clock function.
4.8.2 Data reading and hold function
The 8 bits timer data are allocated to the address FF79H and FF7AH.
<FF79H> D0: TM0 = 128 Hz D1: TM1 = 64 Hz D2: TM2 = 32 Hz D3: TM3 = 16 Hz
<FF7AH> D0: TM4 = 8 Hz D1: TM5 = 4 Hz D2: TM6 = 2 Hz D3: TM7 = 1 Hz
Since the clock timer data has been allocated to two addresses, a carry is generated from the low-order
data within the count (TM0–TM3: 128–16 Hz) to the high-order data (TM4–TM7: 8–1 Hz). When this carry
is generated between the reading of the low-order data and the high-order data, a content combining the
two does not become the correct value (the low-order data is read as FFH and the high-order data
becomes the value that is counted up 1 from that point).
The high-order data hold function in the S1C63158 is designed to operate to avoid this. This function
temporarily stops the counting up of the high-order data (by carry from the low-order data) at the point
where the low-order data has been read and consequently the time during which the high-order data is
held is the shorter of the two indicated here following.
1. Period until it reads the high-order data.
2. 0.48–1.5 msec, fOSC1 = 32.768 kHz (Varies due to the read timing.)
Note: Since the low-order data is not held when the high-order data has previously been read, the low-
order data should be read first.
S1C63158 TECHNICAL MANUAL EPSON 53
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.8.3 Interrupt function
The clock timer can cause interrupts at the falling edge of 16 Hz, 8 Hz, 2 Hz and 1 Hz signals. Software
can set whether to mask any of these frequencies.
Figure 4.8.3.1 is the timing chart of the clock timer.
Address
FF79H
FF7AH
16 Hz interrupt request
8 Hz interrupt request
2 Hz interrupt request
1 Hz interrupt request
Bit
D0
D1
D2
D3
D0
D1
D2
D3
frequency Clock timer timing chart
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
1 Hz
Fig. 4.8.3.1 Timing chart of clock timer
As shown in Figure 4.8.3.1, interrupt is generated at the falling edge of the frequencies (16 Hz, 8 Hz, 2 Hz,
1 Hz). At this time, the corresponding interrupt factor flag (IT0, IT1, IT2, IT3) is set to "1". Selection of
whether to mask the separate interrupts can be made with the interrupt mask registers (EIT0, EIT1, EIT2,
EIT3). However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at
the falling edge of the corresponding signal.
54 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.8.4 I/O memory of clock timer
Table 4.8.4.1 shows the I/O addresses and the control bits for the clock timer.
Table 4.8.4.1 Control bits of clock timer
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
W R/WR
FF78H
00TMRST TMRUN 0
∗
3
0
∗
3
TMRST
∗
3
TMRUN
–
∗
2
–
∗
2
Reset
0
Reset
Run
Invalid
Stop
Unused
Unused
Clock timer reset (writing)
Clock timer Run/Stop
R
FF79H
TM3 TM2 TM1 TM0 TM3
TM2
TM1
TM0
0
0
0
0
Clock timer data (16 Hz)
Clock timer data (32 Hz)
Clock timer data (64 Hz)
Clock timer data (128 Hz)
R
FF7AH
TM7 TM6 TM5 TM4 TM7
TM6
TM5
TM4
0
0
0
0
Clock timer data (1 Hz)
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
FFE6H
EIT3 EIT2 EIT1 EIT0
R/W
EIT3
EIT2
EIT1
EIT0
0
0
0
0
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Interrupt mask register (Clock timer 1 Hz)
Interrupt mask register (Clock timer 2 Hz)
Interrupt mask register (Clock timer 8 Hz)
Interrupt mask register (Clock timer 16 Hz)
FFF6H
IT3 IT2 IT1 IT0
R/W
IT3
IT2
IT1
IT0
0
0
0
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Interrupt factor flag (Clock timer 1 Hz)
Interrupt factor flag (Clock timer 2 Hz)
Interrupt factor flag (Clock timer 8 Hz)
Interrupt factor flag (Clock timer 16 Hz)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
TM0–TM7: Timer data (FF79H, FF7AH)
The 128–1 Hz timer data of the clock timer can be read out with these registers. These eight bits are read
only, and writing operations are invalid.
By reading the low-order data (FF79H), the high-order data (FF7AH) is held until reading or for 0.48–1.5
msec (one of shorter of them).
At initial reset, the timer data is initialized to "00H".
TMRST: Clock timer reset (FF78H•D1)
This bit resets the clock timer.
When "1" is written: Clock timer reset
When "0" is written: No operation
Reading: Always "0"
The clock timer is reset by writing "1" to TMRST. When the clock timer is reset in the RUN status, opera-
tion restarts immediately. Also, in the STOP status the reset data is maintained. No operation results
when "0" is written to TMRST.
This bit is write-only, and so is always "0" at reading.
S1C63158 TECHNICAL MANUAL EPSON 55
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
TMRUN: Clock timer RUN/STOP control register (FF78H•D0)
Controls RUN/STOP of the clock timer.
When "1" is written: RUN
When "0" is written: STOP
Reading: Valid
The clock timer enters the RUN status when "1" is written to the TMRUN register, and the STOP status
when "0" is written.
In the STOP status, the timer data is maintained until the next RUN status or the timer is reset. Also,
when the STOP status changes to the RUN status, the data that is maintained can be used for resuming
the count.
At initial reset, this register is set to "0".
EIT0: 16 Hz interrupt mask register (FFE6H•D0)
EIT1: 8 Hz interrupt mask register (FFE6H•D1)
EIT2: 2 Hz interrupt mask register (FFE6H•D2)
EIT3: 1 Hz interrupt mask register (FFE6H•D3)
These registers are used to select whether to mask the clock timer interrupt.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
The interrupt mask registers (EIT0, EIT1, EIT2, EIT3) are used to select whether to mask the interrupt to
the separate frequencies (16 Hz, 8 Hz, 2 Hz, 1 Hz).
At initial reset, these registers are set to "0".
IT0: 16 Hz interrupt factor flag (FFF6H•D0)
IT1: 8 Hz interrupt factor flag (FFF6H•D1)
IT2: 2 Hz interrupt factor flag (FFF6H•D2)
IT3: 1 Hz interrupt factor flag (FFF6H•D3)
These flags indicate the status of the clock timer interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
The interrupt factor flags (IT0, IT1, IT2, IT3) correspond to the clock timer interrupts of the respective
frequencies (16 Hz, 8 Hz, 2 Hz, 1 Hz). The software can judge from these flags whether there is a clock
timer interrupt. However, even if the interrupt is masked, the flags are set to "1" at the falling edge of the
signal.
These flags are reset to "0" by writing "1" to them.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".
56 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.8.5 Programming notes
(1) Be sure to read timer data in the order of low-order data (TM0–TM3) then high-order data (TM4–
TM7).
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(3) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequen-
cies and times differ from the values described in this section because the oscillation frequency will be
60 kHz (Typ.). Therefore, the clock timer can not be used for the clock function.
S1C63158 TECHNICAL MANUAL EPSON 57
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
4.9 A/D Converter
4.9.1 Characteristics and configuration of A/D converter
The S1C63158 has a built-in A/D converter with the following characteristics.
• Conversion method: Successive-approximation type
• Resolution: 8 bits
Maximum error: ±3 LSB, A/D clock: f ≤ 1 MHz
(0.9 to 3.6 V, VC2 mode should be used if VDD ≤ 1.6V)
• Input channels: Maximum 4 channels
• Conversion time: Minimum 21 µsec (during operation at 1 MHz)
• Setting of analog conversion voltage range is possible with reference voltage terminal (AVREF)
• A/D conversion result is possible to read from 8-bit data register
• Sample & hold circuit built-in
• A/D conversion completion generates an interrupt
Figure 4.9.1.1 shows the configuration of the A/D converter.
AD0 (P40)
AD1 (P41)
AD2 (P42)
AD3 (P43)
Analog
mux
AVDD
AVREF
AVSS
8-bit
D/A converter SAR Converted
data
Clock
selector
Comparator
Sample & hold
Control
circuit
+
–
fOSC1 or fOSC3/2
Data bus
Interrupt
circuit
OSC3
oscillator
fOSC3/2
OSC1
oscillator
fOSC1
1/2
Fig. 4.9.1.1 Configuration of A/D converter
4.9.2 Terminal configuration of A/D converter
The terminals used with the A/D converter are as follows:
AVDD, AVSS (power supply terminal)
The AVDD and AVSS terminals are power supply terminals for the A/D converter. The voltage should be
input as AVDD ≤ VDD and AVSS = VSS.
AVREF (reference voltage input terminal)
The AVREF terminal is the reference voltage terminal of the analog block. Input voltage range of the A/D
conversion is decided by this input (AVSS–AVREF). The voltage should be input as AVREF ≤ AVDD.
AD0–AD3 (analog input terminal)
The analog input terminals AD0–AD3 are shared with the I/O port terminals P40–P43. Therefore, it is
necessary to set them for the A/D converter by software when using them as analog input terminals. This
setting can be done for each terminal. (Refer to Section 4.9.4 for setting.)
At initial reset, all the terminals are set in the I/O port terminals.
Analog voltage value AVIN that can be input is in the range of AVSS ≤ AVIN ≤ AVREF.
58 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
4.9.3 Mask option
The analog input terminals of the A/D converter are shared with the I/O port terminals P40–P43.
Therefore, the terminal specification of the A/D converter is decided by setting the I/O port mask option.
Select "Without pull-up" for the port corresponding to the channel to be used to obtain the conversion
precision.
4.9.4 Control of A/D converter
(1)Setting of A/D input terminal
When using the A/D converter, it is necessary to set up the terminals used for analog input from the
P40–P43 initialized as the I/O port terminals. Four terminals can all be used as analog input termi-
nals.
The PAD (PAD0–PAD3) register is used to set analog input terminals. When the PAD register bits are
set to "1", the corresponding terminals function as the analog input terminals.
At initial reset, these terminals are all set in the I/O port terminals, and each terminal goes to a high
impedance. Table 4.9.4.1 Correspondence between A/D input terminal and PAD register
Terminal
P40 (AD0)
P41 (AD1)
P42 (AD2)
P43 (AD3)
A/D input enable /disable
PAD0
PAD1
PAD2
PAD3
Comment
(2)Setting of input clock
The clock selector selects the A/D conversion clock from OSC1 or OSC3 according to the value
written in the ADCLK register. Table 4.9.4.2 shows the input clock selection with the ADCLK register.
Table 4.9.4.2 Input clock selection
ADCLK
0
1
Clock source
OSC1
OSC3/2
The clock selector outputs the selected clock to the A/D converter by writing "1" to the ADRUN
register.
Note: • When the supply voltage is in the range of 2.2 to 3.6 V, the input clock can be selected from
OSC1 or OSC3. When the supply voltage is in the range of 0.9 to 2.2 V, OSC1 can only be
selected.
• The A/D clock freguency must be 1 MHz or less.
•Be sure to select (change) the input clock while the A/D converter is stopped. Changing the
clock during A/D operation may cause malfunction.
•To prevent malfunction, do not start A/D conversion (writing "1" to the ADRUN register) when the
A/D conversion clock is not being output from the clock selector, and do not turn the clock off
during A/D conversion.
S1C63158 TECHNICAL MANUAL EPSON 59
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
(3)Input signal selection
The analog signals from the AD0 (P40)–AD3 (P43) terminals are input to the multiplexer, and the
analog input channel for A/D conversion is selected by software. This selection can be done using the
CHS register as shown in Table 4.9.4.3.
Table 4.9.4.3 Selection of analog input channel
Input channel
AD3 (P43)
AD2 (P42)
AD1 (P41)
AD0 (P40)
CHS1
1
1
0
0
CHS0
1
0
1
0
(4)A/D conversion operation
An A/D conversion starts by writing "1" to the ADRUN register (FFD0H•D3). However, when the
supply voltage is 1.6 V or less, the VC2 mode must be set by writing "1" to the VADSEL register before
starting A/D conversion.
For example, when performing A/D conversion using AD1 as the analog input, write "1" (0, 1) to the
CHS register (CHS1, CHS0). However, it is necessary that the P41 terminal has been set as an analog
input terminal. Then write "1" to the ADRUN register. The A/D converter start converting of the
analog signal input to the AD1 terminal.
The built-in sample/hold circuit starts sampling of the analog input specified from tAD after writing.
When the sampling is completed, the held analog input voltage is converted into a 8-bit digital value
in successive-approximation architecture.
The conversion result is loaded into the ADDR (ADDR0–ADDR7) register. ADDR0 is the LSB and
ADDR7 is the MSB.
Note: If the CHS register selects an input channel which is not included in the analog input terminals set
by the PAD register (the PAD register can select several terminals simultaneously), the A/D
conversion does not result in a correct converted value.
Example)
Terminal setting: PAD3=1, PAD2–PAD0=0 (AD3 terminal is used)
Selection of input channel: CHS1=0, CHS0=0 (AD0 is selected)
In a setting like this, the A/D conversion result will be invalid because the contents of the settings are
not matched.
Figure 4.9.4.1 shows the flow chart for starting an A/D conversion.
Set PAD0–PAD3
Enable A/D input channel
Set CHS1, CHS0
Select A/D input channel
Set ADCLK
Select A/D input clock
Set ADRUN to "1"
Start A/D conversion
Fig. 4.9.4.1 Flowchart for starting A/D conversion
60 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
An A/D conversion is completed when the conversion result is loaded into the ADDR register. At that
point, the A/D converter generates an interrupt (explained in the next section).
Figure 4.9.4.2 shows the timing chart of A/D conversion.
Writing to ADRUN register
Input sampling
SAR
ADDR register
Interrupt request t
AD
Sampling time
8tCLK tAD:
tCLK:
0 to 1tCLK
Input clock cycle
Conversion result
A/D conversion time
20tCLK+tAD
Fig. 4.9.4.2 Timing chart of A/D conversion
4.9.5 Interrupt function
The A/D converter can generate an interrupt when an A/D conversion has completed.
Figure 4.9.5.1 shows the configuration of the A/D converter interrupt circuit.
The A/D converter sets the interrupt factor flag IAD to "1" immediately after storing the conversion
result to the ADDR register.
At this time, if the interrupt mask register EIAD is "1" , an interrupt is generated to the CPU.
By setting the EIAD register to "0", the interrupt to the CPU can be disabled. However, the interrupt
factor flag is set to "1" when an A/D conversion has completed regardless of the interrupt mask register
setting.
The interrupt factor flag set in "1" is reset to "0" by writing "1".
The interrupt vector for the A/D conversion completion has been set in 010EH.
Data bus
Interrupt
request
Address
A/D conversion
completion Interrupt factor flag
IAD
Address
Interrupt mask
register EIAD
Fig. 4.9.5.1 Configuration of A/D converter interrupt circuit
S1C63158 TECHNICAL MANUAL EPSON 61
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
4.9.6 I/O memory of A/D converter
Table 4.9.6.1 shows the I/O addresses and the control bits for the A/D converter.
Table 4.9.6.1 Control bits of A/D converter
Address Comment
D3 D2
Register
D1 D0 Name Init ∗110
PAD3
PAD2
PAD1
PAD0
0
0
0
0
Enable
Enable
Enable
Enable
Disable
Disable
Disable
Disable
R/W
FFD1H
PAD3 PAD2 PAD1 PAD0
ADDR3
ADDR2
ADDR1
ADDR0
–
∗
2
–
∗
2
–
∗
2
–
∗
2
R
FFD2H
ADDR3 ADDR2 ADDR1 ADDR0
ADDR7
ADDR6
ADDR5
ADDR4
–
∗
2
–
∗
2
–
∗
2
–
∗
2
R
FFD3H
ADDR7 ADDR6 ADDR5 ADDR4
P43 input channel enable/disable control
P42 input channel enable/disable control
P41 input channel enable/disable control
P40 input channel enable/disable control
A/D converted data (D0–D3)
A/D converted data (D4–D7)
FFE7H
000EIAD
R R/W
0
∗
3
0
∗
3
0
∗
3
EIAD
–
∗
2
–
∗
2
–
∗
2
0 Enable Mask
Unused
Unused
Unused
Interrupt mask register (A/D converter)
FFF7H
000IAD
R R/W
0
∗
3
0
∗
3
0
∗
3
IAD
–
∗
2
–
∗
2
–
∗
2
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Unused
Unused
Interrupt factor flag (A/D converter)
ADRUN
ADCLK
CHS1
CHS0
0
0
0
0
Start
OSC3
Invalid
OSC1
W R/W
FFD0H
ADRUN ADCLK CHS1 CHS0
A/D Run/Off control
A/D input clock selection
A/D input
channel
selection
0
P40 1
P41 3
P43
2
P42
[CHS1, 0]
Input channel
FF01H
VADSEL VDSEL 0 DBON
R R/WR/W
VADSEL
VDSEL
0
∗
3
DBON
0
0
–
∗
2
0
V
C2
V
C2
On
V
DD
V
DD
Off
Power source selection for A/D converter
Power supply selection for oscillation system voltage regulator
Unused
Voltage booster circuit On/Off
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
PAD0–PAD3: A/D converter input control register (FFD1H)
Sets the P40–P43 terminals as the analog input terminals for the A/D converter.
When "1" is written: A/D converter input
When "0" is written: I/O port
Reading: Valid
When "1" is written to PADn, the P4n terminal is set to the analog input terminal ADn. (n=0–3)
When "0" is written, the terminal is used with the I/O port.
At initial reset, this register is set to "0" (I/O port).
ADCLK: A/D converter clock source selection register (FFD0H•D2)
Selects the clock source for the A/D converter.
When "1" is written: OSC3
When "0" is written: OSC1
Reading: Valid
When "1" is written to ADCLK, OSC3 is selected as the clock source for the A/D converter. However, the
supply voltage must be 2.2 V or more.
When "0" is written, OSC1 is selected.
At initial reset, this register is set to "0" (OSC1).
62 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
CHS0, CHS1: Analog input channel selection register (FFD0H•D0, D1)
Selects an analog input channel.
Table 4.9.6.3 Selection of analog input channel
Input channel
AD3 (P43)
AD2 (P42)
AD1 (P41)
AD0 (P40)
CHS1
1
1
0
0
CHS0
1
0
1
0
At initial reset, this register is set to "0" (AD0).
VADSEL: A/D power source selection register (FF01H•D3)
Selects the power supply for the A/D converter.
When "1" is written: VC2
When "0" is written: VDD
Reading: Valid
When "1" is written to the VADSEL register, the A/D converter operates with the VC2 voltage output from
the LCD voltage booster. Use VC2 when the supply voltage is 1.6 V or less. To generate VC2, write "1" to
the LPWR register (FF60H•D0) and wait at least 100 msec to stabilize the VC2 voltage.
When "0" is written, the A/D converter operates with VDD. In this case, VDD must be 1.6 V or more.
At initial reset, this register is set to "0" (VDD).
ADRUN: A/D conversion control (FFD0H•D3)
Starts an A/D conversion.
When "1" is written: Start
When "0" is written: No operation
Reading: Invalid
When "1" is written to ADRUN, the A/D converter starts A/D conversion of the channel selected by the
CHS register and stores the conversion result to the ADDR register.
At initial reset, this bit is set to "0".
ADDR0–ADDR7: A/D conversion result (FFD2H/lower 4 bits, FFD3H/upper 4 bits)
A/D conversion result is stored.
ADDR0 is the LSB and ADDR7 is the MSB.
At initial reset, data is undefined.
EIAD: A/D converter interrupt mask register (FFE7H•D0)
This register is used to select whether to mask the A/D converter interrupt or not.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
Writing "1" to the EIAD register enables the A/D converter interrupt and writing "0" disables the inter-
rupt.
At initial reset, this register is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
IAD: A/D converter interrupt factor flag (FFF7H•D0)
This flag indicates the status of the A/D converter interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
IAD is the A/D converter interrupt factor flag that is set when an A/D conversion has finished. The
software can judge from this flag whether there is an A/D converter interrupt or not. This flag is set to "1"
even if the interrupt is masked.
This flag is reset to "0" by writing "1".
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, this flag is set to "0".
4.9.7 Programming notes
(1) When supply voltage is 1.6 V or less, it is necessary to set the A/D converter circuit into the VC2 mode
by writting "1" to VADSEL register befor starting A/D conversion.
(2) The A/D converter can operate by inputting the clock from the clock selector. Therefore, it is neces-
sary to select the clock source and to turn the clock output on before starting A/D conversion. Fur-
thermore, it is also necessary that the OSC3 oscillation circuit is operating when using the OSC3 clock.
(3) When using the OSC3 clock as the A/D conversion clock, do not stop the OSC3 oscillation circuit
during A/D conversion. If the OSC3 oscillation circuit stops, correct A/D conversion result cannot be
obtained.
(4) The input clock and analog input terminals should be set when the A/D converter stops. Changing
these settings in the A/D converter operation may cause errors.
(5) To prevent malfunction, do not start A/D conversion (writing "1" to the ADRUN register) when the
A/D conversion clock is not being output from the clock selector, and do not turn the clock off during
A/D conversion.
(6) If the CHS register selects an input channel which is not included in the analog input terminals set by
the PAD register (the PAD register can select several terminals simultaneously), the A/D conversion
does not result in a correct converted value.
(7) During A/D conversion, do not operate the P4n terminals which are not used for analog inputs of the
A/D converter (for input/output of digital signals). It affects the A/D conversion precision.
64 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10 Programmable Timer
4.10.1 Configuration of programmable timer
The S1C63158 has two 8-bit programmable timer systems (timer 0 and timer 1) built-in.
Timer 0 and timer 1 are composed of 8-bit presettable down counters and they can be used as 8-bit × 2
channel programmable timers or a 16-bit × 1 channel programmable timer by software setting. Timer 0
also has an event counter function using the K13 input port terminal.
Figure 4.10.1.1 shows the configuration of the programmable timer.
The programmable timer is designed to count down from the initial value set in the counter with soft-
ware. An underflow according to the initial value occurs by counting down and is used for the following
functions:
•Presetting the initial value to the counter to generate the periodical underflow signal
• Generating an interrupt
• Generating a TOUT signal output from the R02 output port terminal
• Generating the synchronous clock source for the serial interface (timer 1 underflow is used, and it is
possible to set the transfer rate)
Reload data register
RLD00–RLD07
Data buffer
PTD00–PTD07
Input port
K13
PTRUN0
FCSEL
PLPOL
Programmable timer 0
PTPS00
PTPS01
8-bit
down counter
Prescaler
Selector
CKSEL0
Timer 0 Run/Stop
K13
Clock
control
circuit
EVCNT
Event counter mode setting
Timer function setting
Pulse polarity setting
Prescaler
setting
Underflow
signal
Data buffer
PTD10–PTD17
Programmable timer 1
PTPS10
PTPS11
8-bit
down counter
Prescaler
Clock
control
circuit
Prescaler
setting
Underflow
signal
Data bus
Interrupt
request
CHSEL
TOUT (R02)
Serial interface
Selector
CKSEL1
Timer 1 Run/Stop
PTRST0
Timer 0 reset
PTRST1
Timer 1 reset
2,048
Hz
Divider
OSC3
oscillation
circuit
Interrupt
control
circuit
OSC1
oscillation
circuit
f
OSC3
f
OSC1
PTRUN1
1/2
PTOUT
Selector
Output port
R02
Reload data register
RLD10–RLD17
1/2
MODE16
MODE16
Fig. 4.10.1.1 Configuration of programmable timer
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.2 Tow separate 8-bit timer (MODE16 = "0") operation
4.10.2.1 Setting of initial value and counting down
Timers 0 and 1 each have a down counter and reload data register.
The reload data registers RLD00–RLD07 (timer 0) and RLD10–RLD17 (timer 1) are used to set the initial
value to the down counter.
By writing "1" to the timer reset bit PTRST0 (timer 0) or PTRST1 (timer 1), the down counter loads the
initial value set in the reload register RLD. Therefore, down-counting is executed from the stored initial
value by the input clock.
The registers PTRUN0 (timer 0) and PTRUN1 (timer 1) are provided to control the RUN/STOP for timers
0 and 1. By writing "1" to the register after presetting the reload data to the down counter, the down
counter starts counting down. Writing "0" stops the input count clock and the down counter stops
counting. This control (RUN/STOP) does not affect the counter data. The counter maintains its data
while stopped, and can restart counting continuing from that data.
The counter data can be read via the data buffers PTD00–PTD07 (timer 0) and PTD10–PTD17 (timer 1) in
optional timing. However, the counter has the data hold function the same as the clock timer, that holds
the high-order data when the low-order data is read in order to prevent the borrowing operation between
low- and high-order reading, therefore be sure to read the low-order data first.
The counter reloads the initial value set in the reload data register RLD when an underflow occurs
through the count down. It continues counting down from the initial value after reloading.
In addition to reloading the counter, this underflow signal controls the interrupt generation, pulse (TOUT
signal) output and clock supplying to the serial interface.
PTRUN0 (1)
PTRST0 (1)
RLD00–07 (10–17)
Input clock
PTD07 (17)
PTD06 (16)
PTD05 (15)
PTD04 (14)
PTD03 (13)
PTD02 (12)
PTD01 (11)
PTD00 (10)
A6H F3H
Preset Reload &
Interrupt generation
Fig. 4.10.2.1.1 Basic operation timing of down counter
66 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.2.2 Counter mode
The programmable timer can operate in two counter modes, timer mode and event counter mode. It can
be selected by software.
(1)Timer mode
The timer mode counts down using the prescaler output as an input clock. In this mode, the program-
mable timer operates as a periodical timer using the OSC1 or OSC3 oscillation clock as a clock source.
Timer 0 can operate in both the timer mode and the event counter mode. The mode can be switched
using the timer 0 counter mode selection register EVCNT. When the EVCNT register is set to "0",
timer 0 operates in the timer mode.
Timer 1 operates only in the timer mode.
At initial reset, this mode is set.
Refer to Section 4.10.2.1, "Setting of initial value and counting down" for basic operation and control.
The input clock in the timer mode is generated by the prescaler built into the programmable timer.
The prescaler generates the input clock by dividing the OSC1 or OSC3 oscillation clock. Refer to the
next section for setting the input clock.
(2)Event counter mode
The timer 0 has an event counter function that counts an external clock input to the input port K13.
This function is selected by writing "1" to the timer 0 counter mode selection register EVCNT. The
timer 1 operates only in the timer mode, and cannot be used as an event counter.
In the event counter mode, the clock is supplied to timer 0 from outside of the IC, therefore, the
settings of the timer 0 prescaler division ratio selection registers PTPS00 and PTPS01 and the settings
of the timer 0 source clock selection register CKSEL0 become invalid.
Count down timing can be selected from either the falling or rising edge of the input clock using the
timer 0 pulse polarity selection register PLPOL. When "0" is written to the PLPOL register, the falling
edge is selected, and when "1" is written, the rising edge is selected. The count down timing is shown
in Figure 4.10.2.2.1.
K13 input
Count data n n-1 n-2 n-3 n-4 n-5 n-6
PLPOL
EVCNT
01
1
PTRUN0
Fig. 4.10.2.2.1 Timing chart in event counter mode
The event counter mode also includes a noise reject function to eliminate noise such as chattering on
the external clock (K13 input signal). This function is selected by writing "1" to the timer 0 function
selection register FCSEL.
When "with noise rejector" is selected, an input pulse width for both low and high levels must be 0.98
msec or more to count reliably. (The noise rejecter allows the counter to input the clock at the second
falling edge of the internal 2,048 Hz signal after changing the input level of the K13 input port
terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec or less.)
Figure 4.10.2.2.2 shows the count down timing with noise rejecter.
S1C63158 TECHNICAL MANUAL EPSON 67
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
Counter
input clock
Counter data n n-1 n-2 n-3
K13 input
2,048 Hz
When PLPOL register is set to "0"
Fig. 4.10.2.2.2 Count down timing with noise rejecter
The operation of the event counter mode is the same as the timer mode except it uses the K13 input as
the clock.
Refer to Section 4.10.2.1, "Setting of initial value and counting down" for basic operation and control.
4.10.2.3 Setting of input clock in timer mode
Timer 0 and timer 1 each include a prescaler. The prescalers generate the input clock for each timer by
dividing the source clock supplied from the OSC1 or OSC3 oscillation circuit.
The source clock (OSC1 or OSC3) and the division ratio of the prescaler can be selected with software for
timer 0 and timer 1 individually.
The set input clock is used for the count clock during operation in the timer mode. When the timer 0 is
used in the event counter mode, the following settings become invalid.
The input clock is set in the following sequence.
(1) Selection of source clock
Select the source clock input to each prescaler from either OSC1 or OSC3. This selection is done using
the source clock selection registers CKSEL0 (timer 0) and CKSEL1 (timer 1); when "0" is written to the
register, OSC1 is selected and when "1" is written, OSC3 is selected.
When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time interval of several msec to several 10 msec from turning the circuit ON until the oscillation
stabilizes. Therefore, allow an adequate interval from turning the OSC3 oscillation circuit ON to
starting the programmable timer. Refer to Section 4.4, "Oscillation Circuit", for the control and notes of
the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the OFF state.
(2) Selection of prescaler division ratio
Select the division ratio for each prescaler from among 4 types. This selection is done using the
prescaler division ratio selection registers PTPS00/PTPS01 (timer 0) and PTPS10/PTPS11 (timer 1).
Table 4.10.2.3.1 shows the correspondence between the setting value and the division ratio.
Table 4.10.2.3.1 Selection of prescaler division ratio
PTPS11
PTPS01
1
1
0
0
PTPS10
PTPS00
1
0
1
0
Prescaler division ratio
Source clock / 256
Source clock / 32
Source clock / 4
Source clock / 1
By writing "1" to the register PTRUN0 (timer 0) or PTRUN1 (timer 1), the prescaler inputs the source
clock and outputs the clock divided by the selected division ratio. The counter starts counting down
by inputting the clock.
68 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.2.4 Interrupt function
The programmable timer can generate an interrupt due to an underflow of the timer 0 and timer 1. See
Figure 4.10.2.1.1 for the interrupt timing.
An underflow of timer 0 and timer 1 sets the corresponding interrupt factor flag IPT0 (timer 0) or IPT1
(timer 1) to "1", and generates an interrupt. The interrupt can also be masked by setting the correspond-
ing interrupt mask register EIPT0 (timer 0) or EIPT1 (timer 1). However, the interrupt factor flag is set to
"1" by an underflow of the corresponding timer regardless of the interrupt mask register setting.
4.10.2.5 Setting of TOUT output
The programmable timer can generate a TOUT signal due to an underflow of timer 0 or timer 1. The
TOUT signal is generated by dividing the underflows in 1/2. It is possible to select which timer's under-
flow is to be used by the TOUT output channel selection register CHSEL. When "0" is written to the
CHSEL register, timer 0 is selected and when "1" is written, timer 1 is selected.
Figure 4.10.2.5.1 shows the TOUT signal waveform when the channel is changed.
Timer 0 underflow
Timer 1 underflow
CHSEL 0 1
TOUT output (R02)
Fig. 4.10.2.5.1 TOUT signal waveform at channel change
The TOUT signal can be output from the R02 output port terminal. Programmable clocks can be supplied
to external devices.
Figure 4.10.2.5.2 shows the configuration of the output port R02.
Data bus
Register
PTOUT
Register
R02
TOUT
R02
(TOUT)
Register
R02HIZ
Fig. 4.10.2.5.2 Configuration of R02
The output of a TOUT signal is controlled by the PTOUT register. When "1" is written to the PTOUT
register, the TOUT signal is output from the R02 output port terminal and when "0" is written, the
terminal goes to a high (VDD) level. However, the data register R02 must always be "1" and the high
impedance control register R02HIZ must always be "0" (data output state).
Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2 cycle is
generated when the signal is turned ON and OFF by setting the register.
Figure 4.10.2.5.3 shows the output waveform of the TOUT signal.
R02HIZ register
R02 register
PTOUT register
TOUT output
Fix at "0"
Fix at "1"
"1""0" "0"
Fig. 4.10.2.5.3 Output waveform of the TOUT signal
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.2.6 Transfer rate setting for serial interface
The signal that is made from underflows of timer 1 by dividing them in 1/2, can be used as the clock
source for the serial interface.
The programmable timer outputs the clock to the serial interface by setting timer 1 into RUN state
(PTRUN1 = "1"). It is not necessary to control with the PTOUT register.
PTRUN1
Timer 1 underflow
Source clock for serial I/F
Fig. 4.10.2.6.1 Synchronous clock of serial interface
A setting value for the RLD1X register according to a transfer rate is calculated by the following expres-
sion:
RLD1X = fosc / (2 ∗ bps ∗ division ratio of the prescaler) - 1
fosc:Oscillation frequency (OSC1/OSC3)
bps:Transfer rate
(00H can be set to RLD1X)
4.10.3 One channel
×
16-bit timer (MODE16 = "1") operation
Timer 0 and timer 1 are chained together to form 16-bit down counter low byte in timer 0, high byte in
timer 1.
4.10.3.1 Setting of initial value and counting down
Timers 0 and 1 each have a down counter and reload data register.
The reload data registers RLD00–RLD07 (timer 0) and RLD10–RLD17 (timer 1) are used to set the initial
value to the down counter.
By writing "1" to the timer reset bit PTRST0 (timer 0) or PTRST1 (timer 1), the down counter loads the
initial value set in the reload register RLD. Therefore, down-counting is executed from the stored initial
value by the input clock.
The register PTRUN0 (timer 0) is used to control the RUN/STOP for timers 0 and 1. By writing "1" to the
register after presetting the reload data to the down counter, the down counter starts counting down.
Writing "0" stops the input count clock and the down counter stops counting. This control (RUN/STOP)
does not affect the counter data. The counter maintains its data while stopped, and can restart counting
continuing from that data.
The counter data can be read via the data buffers PTD00–PTD07 (timer 0) and PTD10–PTD17 (timer 1) in
optional timing. However, the counter has the data hold function the same as the clock timer, that holds
the high-order data when the low-order data is read in order to prevent the borrowing operation between
low- and high-order reading, therefore be sure to read the low-order data first.
The counter reloads the initial value set in the reload data register RLD when an underflow occurs
through the count down. It continues counting down from the initial value after reloading.
In addition to reloading the counter, this underflow signal controls the interrupt generation, pulse (TOUT
signal) output and clock supplying to the serial interface.
70 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.3.2 Counter mode
The programmable timer can operate in two counter modes, timer mode and event counter mode. It can
be selected by software.
(1)Timer mode
The timer mode counts down using the prescaler output as an input clock. In this mode, the program-
mable timer operates as a periodical timer using the OSC1 or OSC3 oscillation clock as a clock source.
The programmable timer can operate in both the timer mode and the event counter mode. The mode
can be switched using the timer 0 counter mode selection register EVCNT. When the EVCNT register
is set to "0", the programmable timer operates in the timer mode.
At initial reset, this mode is set.
Refer to Section 4.10.3.1, "Setting of initial value and counting down" for basic operation and control.
The input clock in the timer mode is generated by the prescaler built into the programmable timer.
The prescaler generates the input clock by dividing the OSC1 or OSC3 oscillation clock. Refer to the
next section for setting the input clock.
(2)Event counter mode
The programmable timer has an event counter function that counts an external clock input to the
input port K13. This function is selected by writing "1" to the timer 0 counter mode selection register
EVCNT.
In the event counter mode, the clock is supplied to timer 0 from outside of the IC, therefore, the
settings of the timer 0 prescaler division ratio selection registers PTPS00 and PTPS01 and the settings
of the timer 0 source clock selection register CKSEL0 become invalid.
Count down timing can be selected from either the falling or rising edge of the input clock using the
timer 0 pulse polarity selection register PLPOL. When "0" is written to the PLPOL register, the falling
edge is selected, and when "1" is written, the rising edge is selected. The count down timing is shown
in Figure 4.10.3.2.1.
K13 input
Count data n n-1 n-2 n-3 n-4 n-5 n-6
PLPOL
EVCNT
01
1
PTRUN0
Fig. 4.10.3.2.1 Timing chart in event counter mode
The event counter mode also includes a noise reject function to eliminate noise such as chattering on
the external clock (K13 input signal). This function is selected by writing "1" to the timer 0 function
selection register FCSEL.
When "with noise rejector" is selected, an input pulse width for both low and high levels must be 0.98
msec or more to count reliably. (The noise rejecter allows the counter to input the clock at the second
falling edge of the internal 2,048 Hz signal after changing the input level of the K13 input port
terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec or less.)
Figure 4.10.3.2.2 shows the count down timing with noise rejecter.
S1C63158 TECHNICAL MANUAL EPSON 71
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
Counter
input clock
Counter data n n-1 n-2 n-3
K13 input
2,048 Hz
When PLPOL register is set to "0"
Fig. 4.10.3.2.2 Count down timing with noise rejecter
The operation of the event counter mode is the same as the timer mode except it uses the K13 input as
the clock.
Refer to Section 4.10.3.1, "Setting of initial value and counting down" for basic operation and control.
4.10.3.3 Setting of input clock in timer mode
The 16 bit programmable timer include a prescaler. The prescalers generate the input clock for this
programmable timer by dividing the source clock supplied from the OSC1 or OSC3 oscillation circuit.
The source clock (OSC1 or OSC3) and the division ratio of the prescaler can be selected with software.
The set input clock is used for the count clock during operation in the timer mode. When the 16 bit
programmable timer is used in the event counter mode, the following settings become invalid.
The input clock is set in the following sequence.
(1) Selection of source clock
Select the source clock input to the prescaler from either OSC1 or OSC3. This selection is done using
the source clock selection register CKSEL0 (timer 0); when "0" is written to the register, OSC1 is
selected and when "1" is written, OSC3 is selected.
When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time interval of several msec to several 10 msec from turning the circuit ON until the oscillation
stabilizes. Therefore, allow an adequate interval from turning the OSC3 oscillation circuit ON to
starting the programmable timer. Refer to Section 4.4, "Oscillation Circuit", for the control and notes of
the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the OFF state.
(2) Selection of prescaler division ratio
Select the division ratio for the prescaler from among 4 types. This selection is done using the
prescaler division ratio selection registers PTPS00/PTPS01 (timer 0). Table 4.10.3.3.1 shows the
correspondence between the setting value and the division ratio.
Table 4.10.3.3.1 Selection of prescaler division ratio
PTPS01
1
1
0
0
PTPS00
1
0
1
0
Prescaler division ratio
Source clock / 256
Source clock / 32
Source clock / 4
Source clock / 1
By writing "1" to the register PTRUN0 (timer 0), the prescaler inputs the source clock and outputs the
clock divided by the selected division ratio. The counter starts counting down by inputting the clock.
72 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.3.4 Interrupt function
The programmable timer can generate an interrupt due to an underflow.
An underflow of this 16 bit programmable timer sets the corresponding interrupt factor flag IPT1 (timer
1) to "1", and generates an interrupt. The interrupt can also be masked by setting the corresponding
interrupt mask register EIPT1 (timer 1). However, the interrupt factor flag is set to "1" by an underflow of
the corresponding timer regardless of the interrupt mask register setting.
4.10.3.5 Setting of TOUT output
The programmable timer can generate a TOUT signal due to an underflow of this 16 bit programmable
timer. The TOUT signal is generated by dividing the underflows in 1/2.
The TOUT signal can be output from the R02 output port terminal. Programmable clocks can be supplied
to external devices.
Figure 4.10.3.5.1 shows the configuration of the output port R02.
Data bus
Register
PTOUT
Register
R02
TOUT
R02
(TOUT)
Register
R02HIZ
Fig. 4.10.3.5.1 Configuration of R02
The output of a TOUT signal is controlled by the PTOUT register. When "1" is written to the PTOUT
register, the TOUT signal is output from the R02 output port terminal and when "0" is written, the
terminal goes to a high (VDD) level. However, the data register R02 must always be "1" and the high
impedance control register R02HIZ must always be "0" (data output state).
Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2 cycle is
generated when the signal is turned ON and OFF by setting the register.
Figure 4.10.3.5.2 shows the output waveform of the TOUT signal.
R02HIZ register
R02 register
PTOUT register
TOUT output
Fix at "0"
Fix at "1"
"1""0" "0"
Fig. 4.10.3.5.2 Output waveform of the TOUT signal
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.3.6 Transfer rate setting for serial interface
The signal that is made from underflows of the 16 bit programmable timer by dividing them in 1/2, can
be used as the clock source for the serial interface.
The programmable timer outputs the clock to the serial interface by setting this 16 bit programmable
timer into RUN state (PTRUN0 = "1"). It is not necessary to control with the PTOUT register.
PTRUN0
16 bit programmable timer underfrow
Source clock for serial I/F
Fig. 4.10.3.6.1 Synchronous clock of serial interface
A setting value for the RLD1X register according to a transfer rate is calculated by the following expres-
sion:
RLD1X, RLD0X = fosc / (2 ∗ bps ∗ division ratio of the prescaler) - 1
fosc:Oscillation frequency (OSC1/OSC3)
bps:Transfer rate
(00H can be set to RLD1X)
74 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.4 I/O memory of programmable timer
Table 4.10.4.1 shows the I/O addresses and the control bits for the programmable timer.
Table 4.10.4.1 Control bits of programmable timer
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
CHSEL
PTOUT
CKSEL1
CKSEL0
0
0
0
0
Timer1
On
OSC3
OSC3
Timer0
Off
OSC1
OSC1
TOUT output channel selection
TOUT output control
Prescaler 1 source clock selection
Prescaler 0 source clock selection
R/W
FFC1H
CHSEL PTOUT CKSEL1 CKSEL0
PTPS01
PTPS00
PTRST0
∗
3
PTRUN0
0
0
–
∗
2
0
Reset
Run
Invalid
Stop
Prescaler 0
division ratio
selection
Timer 0 reset (reload)
Timer 0 Run/Stop
W R/WR/W
FFC2H
PTPS01 PTPS00 PTRST0 PTRUN0
0
1/1 1
1/4 2
1/32 3
1/256
[PTPS01, 00]
Division ratio
PTPS11
PTPS10
PTRST1
∗
3
PTRUN1
0
0
–
∗
2
0
Reset
Run
Invalid
Stop
Prescaler 1
division ratio
selection
Timer 1 reset (reload)
Timer 1 Run/Stop
W R/WR/W
FFC3H
PTPS11 PTPS10 PTRST1 PTRUN1
RLD03
RLD02
RLD01
RLD00
0
0
0
0
MSB
Programmable timer 0 reload data (low-order 4 bits)
LSB
R/W
FFC4H
RLD03 RLD02 RLD01 RLD00
RLD07
RLD06
RLD05
RLD04
0
0
0
0
MSB
Programmable timer 0 reload data (high-order 4 bits)
LSB
R/W
FFC5H
RLD07 RLD06 RLD05 RLD04
RLD13
RLD12
RLD11
RLD10
0
0
0
0
MSB
Programmable timer 1 reload data (low-order 4 bits)
LSB
R/W
FFC6H
RLD13 RLD12 RLD11 RLD10
RLD17
RLD16
RLD15
RLD14
0
0
0
0
MSB
Programmable timer 1 reload data (high-order 4 bits)
LSB
R/W
FFC7H
RLD17 RLD16 RLD15 RLD14
PTD03
PTD02
PTD01
PTD00
0
0
0
0
MSB
Programmable timer 0 data (low-order 4 bits)
LSB
R
FFC8H
PTD03 PTD02 PTD01 PTD00
PTD07
PTD06
PTD05
PTD04
0
0
0
0
MSB
Programmable timer 0 data (high-order 4 bits)
LSB
R
FFC9H
PTD07 PTD06 PTD05 PTD04
PTD13
PTD12
PTD11
PTD10
0
0
0
0
MSB
Programmable timer 1 data (low-order 4 bits)
LSB
R
FFCAH
PTD13 PTD12 PTD11 PTD10
PTD17
PTD16
PTD15
PTD14
0
0
0
0
MSB
Programmable timer 1 data (high-order 4 bits)
LSB
R
FFCBH
PTD17 PTD16 PTD15 PTD14
0
1/1 1
1/4 2
1/32 3
1/256
[PTPS11, 10]
Division ratio
FFE2H
00EIPT1 EIPT0
R R/W
0
∗
3
0
∗
3
EIPT1
EIPT0
–
∗
2
–
∗
2
0
0
Enable
Enable
Mask
Mask
Unused
Unused
Interrupt mask register (Programmable timer 1)
Interrupt mask register (Programmable timer 0)
FFF2H
00IPT1 IPT0
R R/W
0
∗
3
0
∗
3
IPT1
IPT0
–
∗
2
–
∗
2
0
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Unused
Interrupt factor flag (Programmable timer 1)
Interrupt factor flag (Programmable timer 0)
MODEL16
EVCNT
FCSEL
PLPOL
0
0
0
0
16 bit
×
1
Event ct.
With NR
8 bit
×
2
Timer
No NR
8 bit × 2 or 16 bit × 1 timer mode selection
Timer 0 counter mode selection
Timer 0 function selection (for event counter mode)
Timer 0 pulse polarity selection (for event counter mode)
R R/W
FFC0H
MODE16 EVCNT FCSEL PLPOL
*1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read
S1C63158 TECHNICAL MANUAL EPSON 75
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
CKSEL0: Prescaler 0 source clock selection register (FFC1H•D0)
CKSEL1: Prescaler 1 source clock selection register (FFC1H•D1)
Selects the source clock of the prescaler.
When "1" is written: OSC3 clock
When "0" is written: OSC1 clock
Reading: Valid
The source clock for the prescaler is selected from OSC1 or OSC3. When "0" is written to the CKSEL0
register, the OSC1 clock is selected as the input clock for the prescaler 0 (for timer 0) and when "1" is
written, the OSC3 clock is selected.
Same as above, the source clock for prescaler 1 is selected by the CKSEL1 register.
When the event counter mode is selected to timer 0, the setting of the CKSEL0 register becomes invalid.
At initial reset, these registers are set to "0".
PTPS00, PTPS01: Timer 0 prescaler division ratio selection register (FFC2H•D2, D3)
PTPS10, PTPS11: Timer 1 prescaler division ratio selection register (FFC3H•D2, D3)
Selects the division ratio of the prescaler.
Two bits of PTPS00 and PTPS01 are the prescaler division ratio selection register for timer 0, and two bits
of PTPS10 and PTPS11 are for timer 1. The prescaler division ratios that can be set by these registers are
shown in Table 4.10.4.2.
Table 4.10.4.2 Selection of prescaler division ratio
PTPS11
PTPS01
1
1
0
0
PTPS10
PTPS00
1
0
1
0
Prescaler division ratio
Source clock / 256
Source clock / 32
Source clock / 4
Source clock / 1
When the event counter mode is selected to timer 0, the setting of the PTPS00 and PTPS01 becomes
invalid.
At initial reset, these registers are set to "0".
EVCNT: Timer 0 counter mode selection register (FFC0H•D2)
Selects a counter mode for timer 0.
When "1" is written: Event counter mode
When "0" is written: Timer mode
Reading: Valid
The counter mode for timer 0 is selected from either the event counter mode or timer mode. When "1" is
written to the EVCNT register, the event counter mode is selected and when "0" is written, the timer
mode is selected.
At initial reset, this register is set to "0".
MODE16: 8-bit × 2 or 16-bit × 1 timer mode selection register (FFC0H•D3)
Selects 8-bit × 2 channels mode (timer 0 and timer 1) or 16-bit × 1 channel mode.
When "1" is written: 16-bit × 1 channel
When "0" is written: 8-bit × 2 channels (timer 0 and timer 1)
Reading: Valid
When 8-bit × 2 channels is selected, timer 0 and timer 1 can be used independently.
When 16-bit × 1 channel is selected, timer 0 and timer 1 are chained together and are used as a 16-bit
programmable timer. The clock is input to timer 0 and interrupts will be generated from timer 1.
At initial reset, this register is set to "0".
76 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
FCSEL: Timer 0 function selection register (FFC0H•D1)
Selects whether the noise rejector of the clock input circuit will be used or not in the event counter mode.
When "1" is written: With noise rejecter
When "0" is written: Without noise rejecter
Reading: Valid
When "1" is written to the FCSEL register, the noise rejecter is used and counting is done by an external
clock (K13) with 0.98 msec or more pulse width. (The noise rejecter allows the counter to input the clock
at the second falling edge of the internal 2,048 Hz signal after changing the input level of the K13 input
port terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec or less.)
When "0" is written to the FCSEL register, the noise rejector is not used and the counting is done directly
by an external clock input to the K13 input port terminal.
Setting of this register is effective only when timer 0 is used in the event counter mode.
At initial reset, this register is set to "0".
PLPOL: Timer 0 pulse polarity selection register (FFC0H•D0)
Selects the count pulse polarity in the event counter mode.
When "1" is written: Rising edge
When "0" is written: Falling edge
Reading: Valid
The count timing in the event counter mode (timer 0) is selected from either the falling edge of the
external clock input to the K13 input port terminal or the rising edge. When "0" is written to the PLPOL
register, the falling edge is selected and when "1" is written, the rising edge is selected.
Setting of this register is effective only when timer 0 is used in the event counter mode.
At initial reset, this register is set to "0".
RLD00–RLD07: Timer 0 reload data register (FFC4H, FFC5H)
RLD10–RLD17: Timer 1 reload data register (FFC6H, FFC7H)
Sets the initial value for the counter.
The reload data written in this register is loaded to the respective counters. The counter counts down
using the data as the initial value for counting.
Reload data is loaded to the counter when the counter is reset by writing "1" to the PTRST0 or PTRST1
register, or when counter underflow occurs.
At initial reset, these registers are set to "00H".
PTD00–PTD07: Timer 0 counter data (FFC8H, FFC9H)
PTD10–PTD17: Timer 1 counter data (FFCAH, FFCBH)
Count data in the programmable timer can be read from these latches.
The low-order 4 bits of the count data in timer 0 can be read from PTD00–PTD03, and the high-order data
can be read from PTD04–PTD07. Similarly, for timer 1, the low-order 4 bits can be read from PTD10–
PTD13, and the high-order data can be read from PTD14–PTD17.
Since the high-order 4 bits are held by reading the low-order 4 bits, be sure to read the low-order 4 bits
first.
Since these latches are exclusively for reading, the writing operation is invalid.
At initial reset, these counter data are set to "00H".
S1C63158 TECHNICAL MANUAL EPSON 77
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
PTRST0: Timer 0 reset (reload) (FFC2H•D1)
PTRST1: Timer 1 reset (reload) (FFC3H•D1)
Resets the timer and presets reload data to the counter.
When "1" is written: Reset
When "0" is written: No operation
Reading: Always "0"
By writing "1" to PTRST0, the reload data in the reload register PLD00–PLD07 is preset to the counter in
timer 0. Similarly, the reload data in PLD10–PLD17 is preset to the counter in timer 1 by PTRST1.
When the counter is preset in the RUN status, the counter restarts immediately after presetting. In the
case of STOP status, the reload data is preset to the counter and is maintained.
No operation results when "0" is written.
Since these bits are exclusively for writing, always set to "0" during reading.
PTRUN0: Timer 0 RUN/STOP control register (FFC2H•D0)
PTRUN1: Timer 1 RUN/STOP control register (FFC3H•D0)
Controls the RUN/STOP of the counter.
When "1" is written: RUN
When "0" is written: STOP
Reading: Valid
The counter in timer 0 starts counting down by writing "1" to the PTRUN0 register and stops by writing
"0".
In STOP status, the counter data is maintained until the counter is reset or is set in the next RUN status.
When STOP status changes to RUN status, the data that has been maintained can be used for resuming
the count.
Same as above, the timer 1 counter is controlled by the PTRUN1 register.
At initial reset, these registers are set to "0".
CHSEL: TOUT output channel selection register (FFC1H•D3)
Selects the channel used for TOUT signal output.
When "1" is written: Timer 1
When "0" is written: Timer 0
Reading: Valid
This register selects which timer's underflow (timer 0 or timer 1) is used to generate a TOUT signal. When
"0" is written to the CHSEL register, timer 0 is selected and when "1" is written, timer 1 is selected. In the
16-bit × 2 channels mode (MODE16 = "1"), timer 1 is always selected regardless of this register setting.
At initial reset, this register is set to "0".
PTOUT: TOUT output control register (FFC1H•D2)
Turns TOUT signal output ON and OFF.
When "1" is written: ON
When "0" is written: OFF
Reading: Valid
PTOUT is the output control register for the TOUT signal. When "1" is written to the register, the TOUT
signal is output from the output port terminal R02 and when "0" is written, the terminal goes to a high
(VDD) level. However, the data register R02 must always be "1" and the high impedance control register
R02HIZ must always be "0" (data output state).
At initial reset, this register is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
EIPT0: Timer 0 interrupt mask register (FFE2H•D0)
EIPT1: Timer 1 interrupt mask register (FFE2H•D1)
These registers are used to select whether to mask the programmable timer interrupt or not.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
Timer 0 and timer 1 interrupts can be masked individually by the interrupt mask registers EIPT0 (timer 0)
and EIPT1 (timer 1).
At initial reset, these registers are set to "0".
IPT0: Timer 0 interrupt factor flag (FFF2H•D0)
IPT1: Timer 1 interrupt factor flag (FFF2H•D1)
These flags indicate the status of the programmable timer interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
The interrupt factor flags IPT0 and IPT1 correspond to timer 0 and timer 1 interrupts, respectively. The
software can judge from these flags whether there is a programmable timer interrupt. However, even if
the interrupt is masked, the flags are set to "1" by the underflows of the corresponding counters.
These flags are reset to "0" by writing "1" to them.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.5 Programming notes
(1) When reading counter data, be sure to read the low-order 4 bits (PTD00–PTD03, PTD10–PTD13) first.
Furthermore, the high-order 4 bits (PTD04–PTD07, PTD14–PTD17) should be read within 0.73 msec of
reading the low-order 4 bits (PTD00–PTD03, PTD10–PTD13).
For the 16 bit × 1 mode, be sure to read as following sequence:
(PTD00–PTD03) → (PTD04–PTD07) → (PTD10–PTD13) → (PTD14–PTD17)
The read sequence time should be within 1.46 msec.
(2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge
of the input clock after writing to the PTRUN0/PTRUN1 register. Consequently, when "0" is written to
the PTRUN0/PTRUN1 register, the timer enters STOP status at the point where the counter is
decremented (-1). The PTRUN0/PTRUN1 register maintains "1" for reading until the timer actually
stops.
Figure 4.10.5.1 shows the timing chart for the RUN/STOP control.
PTRUN0/PTRUN1 (WR)
PTD0X/PTD1X 42H 41H 40H 3FH 3EH 3DH
PTRUN0/PTRUN1 (RD)
Input clock
"1" (RUN)
writing
"0" (STOP)
writing
Fig. 4.10.5.1 Timing chart for RUN/STOP control
It is the same even in the event counter mode. Therefore, be aware that the counter does not enter
RUN/STOP status if a clock is not input after setting the RUN/STOP control register (PTRUN0).
(3) Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2
cycle is generated when the signal is turned ON and OFF by setting the register.
(4) When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time interval of several msec to several 10 msec from turning the circuit ON until the oscillation
stabilizes. Therefore, allow an adequate interval from turning the OSC3 oscillation circuit ON to
starting the programmable timer. Refer to Section 4.4, "Oscillation Circuit", for the control and notes of
the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the OFF state.
(5) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
4.11.1 Configuration of serial interface
The S1C63158 has a synchronous clock type 8 bits serial interface built-in.
The configuration of the serial interface is shown in Figure 4.11.1.1.
The CPU, via the 8-bit shift register, can read the serial input data from the SIN terminal. Moreover, via
the same 8-bit shift register, it can convert parallel data to serial data and output it to the SOUT terminal.
The synchronous clock for serial data input/output may be set by selecting by software any one of three
types of master mode (internal clock mode: when the S1C63158 is to be the master for serial input/
output) and a type of slave mode (external clock mode: when the S1C63158 is to be the slave for serial
input/output).
Also, when the serial interface is used at slave mode, SRDY signal which indicates whether or not the
serial interface is available to transmit or receive can be output to the SRDY terminal.
SD0–SD7
SIN
(P10)
SCLK
or
SCLK
(P12)
SCS0 SCS1
Output
latch
Serial I/F interrupt
control circuit Interrupt
request
SOUT
(P11)
SRDY
or
SRDY
(P13)
SCTRG
Serial I/F
activating
circuit
fOSC1
Serial clock
counter
Serial clock
selector
Serial clock
generator
Shift register (8 bits)
Programmable
timer 1 underflow
signal
SCPS
ESOUT
Fig. 4.11.1.1 Configuration of serial interface
The input/output ports of the serial interface are shared with the I/O ports P10–P13, and function of
these ports can be selected through the software.
P10–P13 terminals and serial input/output correspondence are as follows:
Master mode Slave mode
P10 = SIN (I) P10 = SIN (I)
P11 = SOUT (O) P11 = SOUT (O)
P12 = SCLK (O) P12 = SCLK (I)
P13 = I/O port (I/O) P13 = SRDY (O)
Note: At initial reset, P10–P13 are set to I/O ports.
When using the serial interface, switch the function (ESIF = "1") in the initial routine.
The SOUT (data output) signal passes through a tri-state buffer. To output serial data, write "1" to the
ESOUT register to set the buffer in data output status. When the ESOUT register is set to "0", the SOUT
signal is disabled and the SOUT terminal goes high-impedance status.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.11.2 Mask option
(1)Terminal specification
Since the input/output terminals of the serial interface is shared with the I/O ports (P10–P13), the
mask option that selects the output specification for the I/O port is also applied to the serial interface.
The output specification of the terminals SOUT, SCLK (during the master mode) and SRDY (during
the slave mode) that are used as output in the input/output port of the serial interface is respectively
selected by the mask options of P11, P12 and P13. Either complementary output or N-channel open
drain output can be selected as the output specification. However, when N-channel open drain output
is selected, do not apply a voltage exceeding the power supply voltage to the terminal.
Furthermore, the pull-up resistor for the SIN terminal and the SCLK terminal (during slave mode)
that are used as input terminals can be selected by the mask options of P10 and P12.
When "Gate dirct" is selected, take care that the floating status does not occur.
(2)Polarity of synchronous clock and ready signal
Polarity of the synchronous clock and the ready signal that is output in the slave mode can be selected
from either positive polarity (high active, SCLK & SRDY) or negative polarity (low active, SCLK &
SRDY).
When operating the serial interface in the slave mode, the synchronous clock is input from a external
device. Be aware that the terminal specification is pull-up only and a pull-down resistor cannot be
built in if positive polarity is selected.
In the following explanation, it is assumed that negative polarity (SCLK, SRDY) has been selected.
4.11.3 Master mode and slave mode of serial interface
The serial interface of the S1C63158 has two types of operation mode: master mode and slave mode.
The master mode uses an internal clock as the synchronous clock for the built-in shift register, and
outputs this internal clock from the SCLK (P12) terminal to control the external (slave side) serial device.
In the slave mode, the synchronous clock output from the external (master side) serial device is input
from the SCLK (P12) terminal and it is used as the synchronous clock for the built-in shift register.
The master mode and slave mode are selected by writing data to the SCS1 and SCS0 registers.
When the master mode is selected, a synchronous clock may be selected from among 3 types as shown in
Table 4.11.3.1.
Table 4.11.3.1 Synchronous clock selection
SCS1
1
1
0
0
SCS0
1
0
1
0
Mode
Master mode
Slave mode
Synchronous clock
OSC1
OSC1 /2
Programmable timer
External clock
When the programmable timer is selected, the signal that is generated by dividing the underflow signal
of the programmable timer (timer 1) in 1/2 is used as the synchronous clock. In this case, the program-
mable timer must be controlled before operating the serial interface. Refer to Section 4.10, "Programmable
Timer" for the control of the programmable timer.
At initial reset, the slave mode (external clock mode) is selected.
Moreover, the synchronous clock, along with the input/output of the 8-bit serial data, is controlled as
follows:
• In the master mode, after output of 8 clocks from the SCLK (P12) terminal, clock output is automati-
cally suspended and the SCLK (P12) terminal is fixed at high level.
• In the slave mode, after input of 8 clocks to the SCLK (P12) terminal, subsequent clock inputs are
masked.
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A sample basic serial input/output portion connection is shown in Figure 4.11.3.1.
S1C63158
SCLK
SOUT
SIN
Input terminal
External
serial device
CLK
SOUT
SIN
READY
S1C63158
SCLK
SOUT
SIN
SRDY
External
serial device
CLK
SOUT
SIN
Input terminal
(a) Master mode (b) Slave mode
Fig. 4.11.3.1 Sample basic connection of serial input/output section
4.11.4 Data input/output and interrupt function
The serial interface of S1C63158 can input/output data via the internal 8-bit shift register. The shift
register operates by synchronizing with either the synchronous clock output from the SCLK (P12)
terminal (master mode), or the synchronous clock input to the SCLK (P12) terminal (slave mode).
The serial interface generates an interrupt on completion of the 8-bit serial data input/output. Detection
of serial data input/output is done by counting of the synchronous clock SCLK; the clock completes
input/output operation when 8 counts (equivalent to 8 cycles) have been made and then generates an
interrupt.
The serial data input/output procedure is explained below:
(1)Serial data output procedure and interrupt
The S1C63158 serial interface is capable of outputting parallel data as serial data, in units of 8 bits.
By setting the parallel data to the data registers SD0–SD3 (FF72H) and SD4–SD7 (FF73H) and writing
"1" to SCTRG bit (FF70H•D1), it synchronizes with the synchronous clock and the serial data is output
to the SOUT (P11) terminal. The synchronous clock used here is as follows: in the master mode,
internal clock which is output to the SCLK (P12) terminal while in the slave mode, external clock
which is input from the SCLK (P12) terminal.
Shift timing of serial data is as follows:
•When negative polarity is selected for the synchronous clock (mask option):
The serial data output to the SOUT (P11) terminal changes at the falling edge of the clock input or
output from/to the SCLK (P12) terminal. The data in the shift register is shifted at the falling edge of
the SCLK signal when the SCPS register (FF71H•D2) is "1" and is shifted at the rising edge of the
SCLK signal when the SCPS register is "0".
• When positive polarity is selected for the synchronous clock (mask option):
The serial data output to the SOUT (P11) terminal changes at the rising edge of the clock input or
output from/to the SCLK (P12) terminal. The data in the shift register is shifted at the rising edge of
the SCLK signal when the SCPS register is "1" and is shifted at the falling edge of the SCLK signal
when the SCPS register is "0".
When the output of the 8-bit data from SD0 to SD7 is completed, the interrupt factor flag ISIF
(FFF3H•D0) is set to "1" and an interrupt occurs. Moreover, the interrupt can be masked by the
interrupt mask register EISIF (FFE3H•D0). However, regardless of the interrupt mask register setting,
the interrupt factor flag is set to "1" after output of the 8-bit data.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
(2)Serial data input procedure and interrupt
The S1C63158 serial interface is capable of inputting serial data as parallel data, in units of 8 bits.
The serial data is input from the SIN (P10) terminal, synchronizes with the synchronous clock, and is
sequentially read in the 8-bit shift register. As in the above item (1), the synchronous clock used here is
as follows: in the master mode, internal clock which is output to the SCLK (P12) terminal while in the
slave mode, external clock which is input from the SCLK (P12) terminal.
Shift timing of serial data is as follows:
•When negative polarity is selected for the synchronous clock (mask option):
The serial data is read into the built-in shift register at the falling edge of the SCLK signal when the
SCPS register is "1" and is read at the rising edge of the SCLK signal when the SCPS register is "0". The
shift register is sequentially shifted as the data is fetched.
•When positive polarity is selected for the synchronous clock (mask option):
The serial data is read into the built-in shift register at the rising edge of the SCLK signal when the
SCPS register is "1" and is read at the falling edge of the SCLK signal when the SCPS register is "0".
The shift register is sequentially shifted as the data is fetched.
When the input of the 8-bit data from SD0 to SD7 is completed, the interrupt factor flag ISIF is set to
"1" and an interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask
register EISIF. However, regardless of the interrupt mask register setting, the interrupt factor flag is
set to "1" after input of the 8-bit data.
The data input in the shift register can be read from data registers SD0–SD7 by software.
(3)Serial data input/output permutation
The S1C63158 allows the input/output permutation of serial data to be selected by the SDP register
(FF71H•D3) as to either LSB first or MSB first. The block diagram showing input/output permutation
in case of LSB first and MSB first is provided in Figure 4.11.4.1. The SDP register should be set before
setting data to SD0–SD7.
SIN
SIN
Address [FF73H]
Address [FF72H] Address [FF73H]
Address [FF72H]
Output
latch
Output
latch
SOUT
SOUT
SD3 SD2 SD1 SD0
SD4 SD5 SD6 SD7
SD7 SD6 SD5 SD4
SD0 SD1 SD2 SD3
(LSB first)
(MSB first)
Fig. 4.11.4.1 Serial data input/output permutation
(4)SRDY signal
When the S1C63158 serial interface is used in the slave mode (external clock mode), SRDY signal is
used to indicate whether the internal serial interface is available to transmit or receive data for the
master side (external) serial device. SRDY signal is output from the SRDY (P13) terminal.
Output timing of SRDY signal is as follows:
• When negative polarity is selected (mask option):
SRDY signal goes "0" (low) when the S1C63158 serial interface is available to transmit or receive data;
normally, it is at "1" (high).
SRDY signal changes from "1" to "0" immediately after "1" is written to SCTRG and returns from "0" to
"1" when "0" is input to the SCLK (P12) terminal (i.e., when the serial input/output begins transmit-
ting or receiving data). Moreover, when high-order data is read from or written to SD4–SD7, the SRDY
signal returns to "1".
• When positive polarity is selected (mask option):
SRDY signal goes "1" (high) when the S1C63158 serial interface is available to transmit or receive data;
normally, it is at "0" (low).
SRDY signal changes from "0" to "1" immediately after "1" is written to SCTRG and returns from "1" to
"0" when "1" is input to the SCLK (P12) terminal (i.e., when the serial input/output begins transmit-
ting or receiving data). Moreover, when high-order data is read from or written to SD4–SD7, the SRDY
signal returns to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
(5)Timing chart
The S1C63158 serial interface timing charts are shown in Figures 4.11.4.2 and 4.11.4.3.
SCTRG (W)
SCTRG (R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SRDY (Slave mode)
SCTRG (W)
SCTRG (R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SRDY (Slave mode)
(b) When SCPS = "0"
Fig. 4.11.4.2 Serial interface timing chart (when synchronous clock is negative polarity SCLK)
SCTRG (W)
SCTRG (R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SRDY (Slave mode)
SCTRG (W)
SCTRG (R)
SCLK
SIN
8-bit shift register
SOUT
ISIF
SRDY (Slave mode)
(b) When SCPS = "0"
Fig. 4.11.4.3 Serial interface timing chart (when synchronous clock is positive polarity SCLK)
(a) When SCPS = "1"
(a) When SCPS = "1"
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.11.5 I/O memory of serial interface
Table 4.11.5.1 shows the I/O addresses and the control bits for the serial interface.
Table 4.11.5.1 Control bits of serial interface
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
FF45H
PUL13 PUL12 PUL11 PUL10
R/W
PUL13
PUL12
PUL11
PUL10
1
1
1
1
On
On
On
On
Off
Off
Off
Off
P13 pull-up control register
functions as a general-purpose register when SIF (slave) is selected
P12 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF (master) is selected
SCLK (I) pull-up control register when SIF (slave) is selected
P11 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF is selected
P10 pull-up control register (ESIF=0)
SIN pull-up control register
when SIF is selected
R/W
FF72H
SD3 SD2 SD1 SD0 SD3
SD2
SD1
SD0
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
MSB
Serial I/F transmit/receive data (low-order 4 bits)
LSB
R/W
FF73H
SD7 SD6 SD5 SD4 SD7
SD6
SD5
SD4
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
MSB
Serial I/F transmit/receive data (high-order 4 bits)
LSB
0
Slave
2
OSC1/2
1
PT
3
OSC1
[SCS1, 0]
Clock
[SCS1, 0]
Clock
FF71H
SDP SCPS SCS1 SCS0
R/W
SDP
SCPS
SCS1
SCS0
0
0
0
0
MSB first LSB first
Serial I/F data input/output permutation
Serial I/F clock phase selection
–Negative polarity (mask option)
–Positive polarity (mask option)
Serial I/F
clock mode selection
FFE3H
000EISIF
R R/W
0
∗
3
0
∗
3
0
∗
3
EISIF
–
∗
2
–
∗
2
–
∗
2
0 Enable Mask
Unused
Unused
Unused
Interrupt mask register (Serial I/F)
FFF3H
000ISIF
R R/W
0
∗
3
0
∗
3
0
∗
3
ISIF
–
∗
2
–
∗
2
–
∗
2
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Unused
Unused
Interrupt factor flag (Serial I/F)
FF70H
0 ESOUT SCTRG ESIF
R R/W
0
∗
3
ESOUT
SCTRG
ESIF
–
∗
2
0
0
0
Enable
Trigger
Run
SIF
Disable
Invalid
Stop
I/O
Unused
SOUT enable/disable control
Serial I/F clock trigger (writing)
Serial I/F clock status (reading)
Serial I/F enable (P1 port function selection)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
ESIF: Serial interface enable register (P1 port function selection) (FF70H•D0)
Sets P10–P13 to the input/output port for the serial interface.
When "1" is written: Serial interface
When "0" is written: I/O port
Reading: Valid
When "1" is written to the ESIF register, P10, P11, P12 and P13 function as SIN, SOUT, SCLK, SRDY,
respectively.
In the slave mode, the P13 terminal functions as SRDY output terminal, while in the master mode, it
functions as the I/O port terminal.
At initial reset, this register is set to "0".
Note: A hazard may occur from the P12 (SCLK) terminal when ESIF is set to "1". Therefore, wait at least
10 µsec after setting ESIF to "1" before starting a serial data transfer.
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ESOUT: SOUT enable/disable control register (FF70H•D2)
Enables output of the SOUT signal.
When "1" is written: Enabled
When "0" is written: Disabled
Reading: Valid
When "1" is written to the ESOUT register, the SOUT terminal can output serial data. When "0" is written,
the SOUT terminal goes high-impedance status.
At initial reset, this register is set to "0".
PUL10: SIN (P10) pull-up control register (FF45H•D0)
PUL12: SCLK (P12) pull-up control register (FF45H•D2)
Sets the pull-up of the SIN terminal and the SCLK terminals (in the slave mode).
When "1" is written: Pull-up ON
When "0" is written: Pull-up OFF
Reading: Valid
Sets the pull-up resistor built into the SIN (P10) and SCLK (P12) terminals to ON or OFF. (Pull-up resistor
is only built in the port selected by mask option.)
SCLK pull-up is effective only in the slave mode. In the master mode, the PUL12 register can be used as a
general purpose register.
At initial reset, these registers are set to "1" and pull-up goes ON.
SCS1, SCS0: Clock mode selection register (FF71H•D0, D1)
Selects the synchronous clock (SCLK) for the serial interface.
Table 4.11.5.2 Synchronous clock selection
SCS1
1
1
0
0
SCS0
1
0
1
0
Mode
Master mode
Slave mode
Synchronous clock
OSC1
OSC1 /2
Programmable timer
External clock
Synchronous clock (SCLK) is selected from among the above 4 types: 3 types of internal clock and
external clock.
When the programmable timer is selected, the signal that is generated by dividing the underflow signal
of the programmable timer (timer 1) in 1/2 is used as the synchronous clock. In this case, the program-
mable timer must be controlled before operating the serial interface. Refer to Section 4.10, "Programmable
Timer" for the control of the programmable timer.
At initial reset, external clock is selected.
SCPS: Clock phase selection register (FF71H•D2)
Selects the timing for reading in the serial data input from the SIN (P10) terminal.
• When negative polarity is selected:
When "1" is written: Falling edge of SCLK
When "0" is written: Rising edge of SCLK
Reading: Valid
• When positive polarity is selected:
When "1" is written: Rising edge of SCLK
When "0" is written: Falling edge of SCLK
Reading: Valid
Select whether the fetching for the serial input data to registers (SD0–SD7) at the rising edge or falling
edge of the synchronous signal.
S1C63158 TECHNICAL MANUAL EPSON 87
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Pay attention to the polarity of the synchronous clock selected by the mask option because the selection
content is different.
The input data fetch timing may be selected but output timing for output data is fixed at the falling edge
of SCLK (when negative polarity is selected) or at the rising edge of SCLK (when positive polarity is
selected).
At initial reset, this register is set to "0".
SDP: Data input/output permutation selection register (FF71H•D3)
Selects the serial data input/output permutation.
When "1" is written: MSB first
When "0" is written: LSB first
Reading: Valid
Select whether the data input/output permutation will be MSB first or LSB first.
At initial reset, this register is set to "0".
SCTRG: Clock trigger/status (FF70H•D1)
This is a trigger to start input/output of synchronous clock (SCLK).
• When writing
When "1" is written: Trigger
When "0" is written: No operation
When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK)
input/output is started.
As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be performed
prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writ-
ing/reading on data registers SD0–SD7.) In addition, be sure to enable the serial interface with the ESIF
register before setting the trigger.
Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from perform-
ing trigger input multiple times, as leads to malfunctioning.
Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the
trigger.
• When reading
When "1" is read: RUN (during input/output the synchronous clock)
When "0" is read: STOP (the synchronous clock stops)
Writing: Invalid
When this bit is read, it indicates the status of serial interface clock.
After "1" is written to SCTRG, this value is latched till serial interface clock stops (8 clock counts). There-
fore, if "1" is read, it indicates that the synchronous clock is in input/output operation.
When the synchronous clock input/output is completed, this latch is reset to "0".
At initial reset, this bit is set to "0".
SD0–SD3, SD4–SD7: Serial interface data register (FF72H, FF73H)
These registers are used for writing and reading serial data.
• When writing
When "1" is written: High level
When "0" is written: Low level
Write data to be output in these registers. The register data is converted into serial data and output from
the SOUT (P11) terminal; data bits set at "1" are output as high (VDD) level and data bits set at "0" are
output as low (VSS) level.
88 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
• When reading
When "1" is read: High level
When "0" is read: Low level
The serial data input from the SIN (P10) terminal can be read from these registers.
The serial data input from the SIN (P10) terminal is converted into parallel data, as a high (VDD) level bit
into "1" and as a low (VSS) level bit into "0", and is loaded to these registers. Perform data reading only
while the serial interface is not running (i.e., the synchronous clock is neither being input or output).
At initial reset, these registers are undefined.
EISIF: Interrupt mask register (FFE3H•D0)
Masking the interrupt of the serial interface can be selected with this register.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
With this register, it is possible to select whether the serial interface interrupt is to be masked or not.
At initial reset, this register is set to "0".
ISIF: Interrupt factor flag (FFF3H•D0)
This flag indicates the occurrence of serial interface interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
Writing: Invalid
From the status of this flag, the software can decide whether the serial interface interrupt.
This flag is set to "1" after an 8-bit data input/output even if the interrupt is masked.
This flag is reset to "0" by writing "1" to it.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, this flag is set to "0".
4.11.6 Programming notes
(1) Perform data writing/reading to the data registers SD0–SD7 only while the serial interface is not
running (i.e., the synchronous clock is neither being input or output).
(2) As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be
performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated
through data writing/reading on data registers SD0–SD7.) In addition, be sure to enable the serial
interface with the ESIF register before setting the trigger.
Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from
performing trigger input multiple times, as leads to malfunctioning. Moreover, when the synchronous
clock SCLK is external clock, start to input the external clock after the trigger.
(3) Setting of the input/output permutation (MSB first/LSB first) with the SDP register should be done
before setting data to SD0–SD7.
(4) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(5) Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is
used as the clock source of the programmable timer or in the slave mode.
S1C63158 TECHNICAL MANUAL EPSON 89
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Buzzer Output Circuit)
4.12 Buzzer Output Circuit
4.12.1 Configuration of buzzer output circuit
The S1C63158 is capable of generating buzzer signal to drive a piezo-electric buzzer. The buzzer signal is
output from the BZ terminal by software control. Furthermore, the buzzer signal frequency can be set to 2
kHz or 4 kHz with 2 Hz interval by software.
Figure 4.12.1.1 shows the configuration of the buzzer output circuit.
f
OSC1
BZ
2 kHz
4 kHz
Selector Buzzer output
control circuit
BZONBZFQ
Divider
ENON
Fig. 4.12.1.1 Configuration of buzzer output circuit
4.12.2 Mask option
Polarity of the buzzer signal output from the BZ terminal can be selected as either positive polarity or
negative polarity. Figure 4.12.2.1 shows each output circuit configuration and the output waveform.
When positive polarity is selected, the BZ terminal goes to a low (VSS) level when the buzzer signal is not
output. Select positive polarity when driving a piezo buzzer by externally connecting an NPN transistor.
When negative polarity is selected, the BZ terminal goes to a high (VDD) level when the buzzer signal is not
output. Select negative polarity when driving a piezo buzzer by externally connecting a PNP transistor.
V
DD
V
SS
Buzzer signal
BZ
V
SS
V
DD
Piezo
(a) When positive polarity is selected
V
DD
V
SS
Buzzer signal
BZ
V
SS
V
DD
Piezo
(b) When negative polarity is selected
Fig. 4.12.2.1 Configuration of output circuit
90 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Buzzer Output Circuit)
4.12.3 Control of buzzer output
The buzzer signal frequency is selected by the buzzer frequency selection register BZFQ. When "1" is
written to the BZFQ register, the frequency is set to 2 kHz. When "0" is written, it is set to 4 kHz. This
signal is generated by dividing the fOSC1.
fOSC1 2 kHz 4 kHz
32.768 kHz fOSC1 /16 fOSC1 /8
The buzzer signal is output from the BZ terminal by writing "1" to the buzzer output control register
BZON.
When negative polarity is selected, the BZ terminal goes to a high (VDD) level by writing "0" to the BZON
register. When positive polarity is selected, the BZ terminal goes to a low (VSS) level by writing "0".
BZON register
Buzzer output (BZ)
Negative polarity
Buzzer output (BZ)
Positive polarity
"1""0" "0"
Fig. 4.12.3.1 Timing chart of buzzer signal output
2 Hz intervals can be added to the buzzer signal when "1" is written to the ENON register.
BZON register
ENON register
Buzzer output
2 Hz
"1""0" "0"
"1""0" "0"
2 Hz
Fig. 4.12.3.2 2 Hz interval
Note: Since it generates a buzzer signal that is out of synchronization with the BZON register, hazards
may at times be produced when the signal goes ON/OFF due to the setting of the BZON register.
S1C63158 TECHNICAL MANUAL EPSON 91
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Buzzer Output Circuit)
4.12.4 I/O memory of buzzer output circuit
Table 4.12.4.1 shows the I/O address and the control bits for the buzzer output circuit.
Table 4.12.4.1 Control bits of buzzer output circuit
D3 D2 D1 D0 Name Init ∗110
Address Comment
Register
R R/W
FF64H
0 ENON BZFQ BZON 0
∗
3
ENON
BZFQ
BZON
–
∗
2
0
0
0
On
2 kHz
On
Off
4 kHz
Off
Unused
2 Hz interval On/Off
Buzzer frequency selection
Buzzer output On/Off
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
ENON: Inter val ON/OFF control register (FF64H•D2)
Controls the addition of a 2 Hz interval onto the buzzer signal.
When "1" is written: ON
When "0" is written: OFF
Reading: Valid
Writing "1" into the ENON causes a 2 Hz ON/OFF interval to be added during buzzer signal output.
When "0" has been written, a 2 Hz ON/OFF interval is not added.
At initial reset, this register is set to "0".
BZFQ: Buzz er frequency selection register (FF64H•D1)
Selects the buzzer signal frequency.
When "1" is written: 2 kHz
When "0" is written: 4 kHz
Reading: Valid
When "1" is written to BZFQ, the frequency is set to 2 kHz. When "0" is written, it is set to 4 kHz.
At initial reset, this register is set to "0".
BZON: Buzzer output control (ON/OFF) register (FF64H•D0)
Controls the buzzer signal output.
When "1" is written: Buzzer output ON
When "0" is written: Buzzer output OFF
Reading: Valid
When "1" is written to BZON, the buzzer signal is output from the BZ terminal. When "0" is written, the
BZ terminal goes to a high (VDD) level (when negative polarity is selected by mask option) or to a low
(VSS) level (when positive polarity is selected by mask option).
At initial reset, this register is set to "0".
4.12.5 Programming note
Since it generates a buzzer signal that is out of synchronization with the BZON register, hazards may at
times be produced when the signal goes ON/OFF due to the setting of the BZON register.
92 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit)
4.13 SVD (Supply Voltage Detection) Circuit
4.13.1 Configuration of SVD circuit
The S1C63158 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the
source voltage lowers. Turning the SVD circuit ON/OFF and the SVD criteria voltage setting can be done
with software.
Figure 4.13.1.1 shows the configuration of the SVD circuit.
V
SVD circuit
Detection output
Data bus
DD
V
SS
SVDDT
SVDON
SVDS3
|
SVDS0
Criteria voltage
setting circuit
Fig. 4.13.1.1 Configuration of SVD circuit
4.13.2 SVD operation
The SVD circuit compares the criteria voltage set by software and the supply voltage (VDD–VSS) and sets
its results into the SVDDT latch. By reading the data of this SVDDT latch, it can be determined by means
of software whether the supply voltage is normal or has dropped.
The criteria voltage can be set for the 16 types shown in Table 4.13.2.1 by the SVDS3–SVDS0 registers.
Table 4.13.2.1 Criteria voltage setting
SVDS3
0
0
0
0
0
0
0
0
SVDS2
1
1
1
1
0
0
0
0
SVDS1
1
1
0
0
1
1
0
0
SVDS0
1
0
1
0
1
0
1
0
Criteria
voltage (V)
1.60
1.40
1.30
1.25
1.20
1.15
1.10
1.05
SVDS3
1
1
1
1
1
1
1
1
SVDS2
1
1
1
1
0
0
0
0
SVDS1
1
1
0
0
1
1
0
0
SVDS0
1
0
1
0
1
0
1
0
Criteria
voltage (V)
2.60
2.50
2.30
2.20
2.10
2.05
2.00
1.95
When the SVDON register is set to "1", source voltage detection by the SVD circuit is executed. As soon as
the SVDON register is reset to "0", the result is loaded to the SVDDT latch and the SVD circuit goes OFF.
To obtain a stable detection result, the SVD circuit must be ON for at least l00 µsec. So, to obtain the SVD
detection result, follow the programming sequence below.
1. Set SVDON to "1"
2. Maintain for 100 µsec minimum
3. Set SVDON to "0"
4. Read SVDDT
When the SVD circuit is ON, the IC draws a large current, so keep the SVD circuit off unless it is.
S1C63158 TECHNICAL MANUAL EPSON 93
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit)
4.13.3 I/O memory of SVD circuit
Table 4.13.3.1 shows the I/O addresses and the control bits for the SVD circuit.
Table 4.13.3.1 Control bits of SVD circuit
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
FF05H
00SVDDT SVDON
R R/W
0
∗
3
0
∗
3
SVDDT
SVDON
–
∗
2
–
∗
2
0
0
Low
On
Normal
Off
Unused
Unused
SVD evaluation data
SVD circuit On/Off
FF04H
SVDS3 SVDS2 SVDS1 SVDS0
R/W
SVDS3
SVDS2
SVDS1
SVDS0
0
0
0
0
SVD criteria voltage setting
0
1.05
8
1.95
1
1.10
9
2.00
2
1.15
10
2.05
3
1.20
11
2.10
4
1.25
12
2.20
5
1.30
13
2.30
6
1.40
14
2.50
7
1.60
15
2.60
[SVDS3–0]
Voltage(V)
[SVDS3–0]
Voltage(V)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
SVDS3–SVDS0: SVD criteria voltage setting register (FF04H)
Criteria voltage for SVD is set as shown in Table 4.13.2.1.
At initial reset, this register is set to "0".
SVDON: SVD control (ON/OFF) register (FF05H•D0)
Turns the SVD circuit ON and OFF.
When "1" is written: SVD circuit ON
When "0" is written: SVD circuit OFF
Reading: Valid
When the SVDON register is set to "1", a source voltage detection is executed by the SVD circuit. As soon
as SVDON is reset to "0", the result is loaded to the SVDDT latch. To obtain a stable detection result, the
SVD circuit must be ON for at least l00 µsec.
At initial reset, this register is set to "0".
SVDDT: SVD data (FF05H•D1)
This is the result of supply voltage detection.
When "0" is read: Supply voltage (VDD–VSS) ≥ Criteria voltage
When "1" is read: Supply voltage (VDD–VSS) < Criteria voltage
Writing: Invalid
The result of supply voltage detection at time of SVDON is set to "0" can be read from this latch.
At initial reset, SVDDT is set to "0".
4.13.4 Programming notes
(1) To obtain a stable detection result, the SVD circuit must be ON for at least l00 µsec. So, to obtain the
SVD detection result, follow the programming sequence below.
1. Set SVDON to "1"
2. Maintain for 100 µsec minimum
3. Set SVDON to "0"
4. Read SVDDT
(2) The SVD circuit should normally be turned OFF because SVD operation increase current consump-
tion.
94 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
4.14 Interrupt and HALT
<Interrupt types>
The S1C63158 provides the following interrupt functions.
External interrupt: • Input interrupt (3 systems)
Internal interrupt: • Watchdog timer interrupt (NMI, 1 system)
• Programmable timer interrupt (2 systems)
• Serial interface interrupt (1 system)
• Timer interrupt (4 systems)
• A/D converter interrupt (1 system)
To authorize interrupt, the interrupt flag must be set to "1" (EI) and the necessary related interrupt mask
registers must be set to "1" (enable).
When an interrupt occurs the interrupt flag is automatically reset to "0" (DI), and interrupts after that are
inhibited.
The watchdog timer interrupt is an NMI (non-maskable interrupt), therefore, the interrupt is generated
regardless of the interrupt flag setting. Also the interrupt mask register is not provided. However, it is
possible to not generate NMI since software can stop the watchdog timer operation.
Figure 4.14.1 shows the configuration of the interrupt circuit.
Note: After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1
and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine.
Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of
them is set, all the interrupts including NMI are masked and interrupts cannot be accepted until the
other one is set.
<HALT>
The S1C63158 has HALT functions that considerably reduce the current consumption when it is not
necessary.
The CPU enters HALT status when the HALT instruction is executed.
In HALT status, the operation of the CPU is stopped. However, timers continue counting since the
oscillation circuit operates. Reactivating the CPU from HALT status is done by generating a hardware
interrupt request including NMI.
S1C63158 TECHNICAL MANUAL EPSON 95
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
K10
KCP10
SIK10
K11
KCP11
SIK11
K12
KCP12
SIK12
K13
KCP13
SIK13
K20
KCP20
SIK20
IK1
EIK1
IK2
EIK2
IT3
EIT3
IT2
EIT2
IT1
EIT1
IT0
EIT0
IAD
EIAD
IPT0
EIPT0
IPT1
EIPT1
Interrupt
vector
generation
circuit
Program counter
(low-order 4 bits)
INT
interrupt request
NMI
interrupt request
Watchdog timer
Interrupt factor flag
Interrupt mask register
Input comparison register
Interrupt selection register
Interrupt flag
ISIF
EISIF
K00
KCP00
SIK00
K01
KCP01
SIK01
K02
KCP02
SIK02
K03
KCP03
SIK03
IK0
EIK0
Fig. 4.14.1 Configuration of the interrupt circuit
96 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
4.14.1 Interrupt factor
Table 4.14.1.1 shows the factors for generating interrupt requests.
The interrupt flags are set to "1" depending on the corresponding interrupt factors.
The CPU operation is interrupted when an interrupt factor flag is set to "1" if the following conditions are
established.
• The corresponding mask register is "1" (enabled)
• The interrupt flag is "1" (EI)
The interrupt factor flag is reset to "0" when "1" is written.
At initial reset, the interrupt factor flags are reset to "0".
∗Since the watchdog timer's interrupt is NMI, the interrupt is generated regardless of the setting above,
and no interrupt factor flag is provided.
Table 4.14.1.1 Interrupt factors
Interrupt factor
Programmable timer 1 (counter = 0)
Programmable timer 0 (counter = 0)
Serial interface (8-bit data input/output completion)
K00–K03 input (falling edge or rising edge)
K10–K13 input (falling edge or rising edge)
K20 input (falling edge or rising edge)
Clock timer 1 Hz (falling edge)
Clock timer 2 Hz (falling edge)
Clock timer 8 Hz (falling edge)
Clock timer 16 Hz (falling edge)
A/D converter
IPT1
IPT0
ISIF
IK0
IK1
IK2
IT3
IT2
IT1
IT0
IAD
(FFF2H•D1)
(FFF2H•D0)
(FFF3H•D0)
(FFF4H•D0)
(FFF5H•D0)
(FFF5H•D1)
(FFF6H•D3)
(FFF6H•D2)
(FFF6H•D1)
(FFF6H•D0)
(FFF7H•D0)
Interrupt factor flag
Note: After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be
sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to
the interrupt enabled state.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
4.14.2 Interrupt mask
The interrupt factor flags can be masked by the corresponding interrupt mask registers.
The interrupt mask registers are read/write registers. They are enabled (interrupt authorized) when "1" is
written to them, and masked (interrupt inhibited) when "0" is written to them.
At initial reset, the interrupt mask register is set to "0".
Table 4.14.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags.
Table 4.14.2.1 Interrupt mask registers and interrupt factor flags
IPT1
IPT0
ISIF
IK0
IK1
IK2
IT3
IT2
IT1
IT0
IAD
(FFF2H•D1)
(FFF2H•D0)
(FFF3H•D0)
(FFF4H•D0)
(FFF5H•D0)
(FFF5H•D1)
(FFF6H•D3)
(FFF6H•D2)
(FFF6H•D1)
(FFF6H•D0)
(FFF7H•D0)
Interrupt factor flag
EIPT1
EIPT0
EISIF
EIK0
EIK1
EIK2
EIT3
EIT2
EIT1
EIT0
EIAD
(FFE2H•D1)
(FFE2H•D0)
(FFE3H•D0)
(FFE4H•D0)
(FFE5H•D0)
(FFE5H•D1)
(FFE 6H•D3)
(FFE6H•D2)
(FFE6H•D1)
(FFE6H•D0)
(FFE7H•D0)
Interrupt mask register
4.14.3 Interrupt vector
When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program
being executed is terminated, the interrupt processing is executed in the following order.
1The content of the flag register is evacuated, then the I flag is reset.
2The address data (value of program counter) of the program to be executed next is saved in the stack
area (RAM).
3The interrupt request causes the value of the interrupt vector (0100H–010EH) to be set in the program
counter.
4The program at the specified address is executed (execution of interrupt processing routine by
software).
Table 4.14.3.1 shows the correspondence of interrupt requests and interrupt vectors.
Table 4.14.3.1 Interrupt request and interrupt vectors
Interrupt vector
0100H
0104H
0106H
0108H
010AH
010CH
010EH
Interrupt factor
Watchdog timer
Programmable timer
Serial interface
K00–K03 input
K10–K13 input, K20 input
Clock timer
A/D converter
Priority
High
Low
The four low-order bits of the program counter are indirectly addressed through the interrupt request.
98 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
4.14.4 I/O memory of interrupt
Tables 4.14.4.1(a) and (b) show the I/O addresses and the control bits for controlling interrupts.
Table 4.14.4.1(a) Control bits of interrupt (1)
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
FF20H
SIK03 SIK02 SIK01 SIK00
R/W
SIK03
SIK02
SIK01
SIK00
0
0
0
0
Enable
Enable
Enable
Enable
Disable
Disable
Disable
Disable
K00–K03 interrupt selection register
FF22H
KCP03 KCP02 KCP01 KCP00
R/W
KCP03
KCP02
KCP01
KCP00
1
1
1
1
K00–K03 input comparison register
FF24H
SIK13 SIK12 SIK11 SIK10
R/W
SIK13
SIK12
SIK11
SIK10
0
0
0
0
Enable
Enable
Enable
Enable
Disable
Disable
Disable
Disable
K10–K13 interrupt selection register
FF26H
KCP13 KCP12 KCP11 KCP10
R/W
KCP13
KCP12
KCP11
KCP10
1
1
1
1
K10–K13 input comparison register
FF28H
000SIK20
R R/W
0
∗
3
0
∗
3
0
∗
3
SIK20
–
∗
2
–
∗
2
–
∗
2
0 Enable Disable
Unused
Unused
Unused
K20 interrupt selection register
Unused
Unused
Unused
K20 input comparison register
FF2AH
000KCP20
R R/W
0
∗
3
0
∗
3
0
∗
3
KCP20
–
∗
2
–
∗
2
–
∗
2
1
FFE6H
EIT3 EIT2 EIT1 EIT0
R/W
EIT3
EIT2
EIT1
EIT0
0
0
0
0
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Interrupt mask register (Clock timer 1 Hz)
Interrupt mask register (Clock timer 2 Hz)
Interrupt mask register (Clock timer 8 Hz)
Interrupt mask register (Clock timer 16 Hz)
FFE2H
00EIPT1 EIPT0
R R/W
0
∗
3
0
∗
3
EIPT1
EIPT0
–
∗
2
–
∗
2
0
0
Enable
Enable
Mask
Mask
Unused
Unused
Interrupt mask register (Programmable timer 1)
Interrupt mask register (Programmable timer 0)
FFE7H
000EIAD
R R/W
0
∗
3
0
∗
3
0
∗
3
EIAD
–
∗
2
–
∗
2
–
∗
2
0 Enable Mask
Unused
Unused
Unused
Interrupt mask register (A/D converter)
FFE3H
000EISIF
R R/W
0
∗
3
0
∗
3
0
∗
3
EISIF
–
∗
2
–
∗
2
–
∗
2
0 Enable Mask
Unused
Unused
Unused
Interrupt mask register (Serial I/F)
FFE4H
000EIK0
R R/W
0
∗
3
0
∗
3
0
∗
3
EIK0
–
∗
2
–
∗
2
–
∗
2
0 Enable Mask
Unused
Unused
Unused
Interrupt mask register (K00–K03)
FFE5H
00EIK2 EIK1
R R/W
0
∗
3
0
∗
3
EIK2
EIK1
–
∗
2
–
∗
2
0
0
Enable
Enable
Mask
Mask
Unused
Unused
Interrupt mask register (K20)
Interrupt mask register (K10–K13)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
S1C63158 TECHNICAL MANUAL EPSON 99
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Table 4.14.4.1(b) Control bits of interrupt (2)
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
FFF6H
IT3 IT2 IT1 IT0
R/W
IT3
IT2
IT1
IT0
0
0
0
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Interrupt factor flag (Clock timer 1 Hz)
Interrupt factor flag (Clock timer 2 Hz)
Interrupt factor flag (Clock timer 8 Hz)
Interrupt factor flag (Clock timer 16 Hz)
FFF2H
00IPT1 IPT0
R R/W
0
∗
3
0
∗
3
IPT1
IPT0
–
∗
2
–
∗
2
0
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Unused
Interrupt factor flag (Programmable timer 1)
Interrupt factor flag (Programmable timer 0)
FFF7H
000IAD
R R/W
0
∗
3
0
∗
3
0
∗
3
IAD
–
∗
2
–
∗
2
–
∗
2
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Unused
Unused
Interrupt factor flag (A/D converter)
FFF3H
000ISIF
R R/W
0
∗
3
0
∗
3
0
∗
3
ISIF
–
∗
2
–
∗
2
–
∗
2
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Unused
Unused
Interrupt factor flag (Serial I/F)
FFF4H
000IK0
R R/W
0
∗
3
0
∗
3
0
∗
3
IK0
–
∗
2
–
∗
2
–
∗
2
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Unused
Unused
Interrupt factor flag (K00–K03)
FFF5H
00IK2 IK1
R R/W
0
∗
3
0
∗
3
IK2
IK1
–
∗
2
–
∗
2
0
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Unused
Interrupt factor flag (K20)
Interrupt factor flag (K10–K13)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
EIPT1, EIPT0: Interrupt mask registers (FFE2H•D1, D0)
IPT1, IPT0: Interrupt factor flags (FFF2H•D1, D0)
Refer to Section 4.10, "Programmable Timer".
EISIF: Interrupt mask register (FFE3H•D0)
ISIF: Interrupt factor flag (FFF3H•D0)
Refer to Section 4.11, "Serial Interface".
KCP03–KCP00, KCP13–KCP10, KCP20: Input comparison registers (FF22H, FF26H, FF2AH•D0)
SIK03–SIK00, SIK13–SIK10, SIK20: Interrupt selection registers (FF20H, FF24H, FF28H•D0)
EIK0, EIK1, EIK2: Interrupt mask registers (FFE4H•D0, FFE5H•D0, FFE5H•D1)
IK0, IK1, IK2: Interrupt factor flags (FFF4H•D0, FFF5H•D0, FFF5H•D1)
Refer to Section 4.5, "Input Ports".
EIT3–EIT0: Interrupt mask registers (FFE6H)
IT3–IT0: Interrupt factor flags (FFF6H)
Refer to Section 4.8, "Clock Timer".
EIAD: Interrupt mask register (FFE7H•D0)
IAD: Interrupt factor flag (FFF7H•D0)
Refer to Section 4.9, "A/D Converter".
100 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
4.14.5 Programming notes
(1) The interrupt factor flags are set when the interrupt condition is established, even if the interrupt
mask registers are set to "0".
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(3) After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1
and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine.
Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is
set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one
is set.
S1C63158 TECHNICAL MANUAL EPSON 101
CHAPTER 5: SUMMARY OF NOTES
CHAPTER 5SUMMARY OF NOTES
5.1 Notes for Low Current Consumption
The S1C63158 contains control registers for each of the circuits so that current consumption can be
reduced.
These control registers reduce the current consumption through programs that operate the circuits at the
minimum levels.
The following lists the circuits that can control operation and their control registers. Refer to these when
programming.
Table 5.1.1 Circuits and control registers
Circuit (and item)
CPU
CPU operating frequency
Oscillation system voltage regulator
Voltage booster circuit
SVD circuit
Control register
HALT instruction
CLKCHG, OSCC
VDC
DBON, VDSEL, VADSEL
SVDON
Refer to Chapter 7, "Electrical Characteristics" for current consumption.
Below are the circuit statuses at initial reset.
CPU:Operating status
CPU operating frequency:Low speed side (CLKCHG = "0")
OSC3 oscillation circuit is in OFF status (OSCC = "0")
Oscillation system voltage regulator:Low speed side 1.3 V (VDC = "0")
Supply voltage booster:Voltage regulator is driven with VDD, Normal mode
(DBON = "0", VDSEL = "0", VADSEL = "0")
SVD circuit:OFF status (SVDON = "0")
102 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 5: SUMMARY OF NOTES
5.2 Summary of Notes by Function
Here, the cautionary notes are summed up by function category. Keep these notes well in mind when
programming.
Memory and stack
(1) Memory is not implemented in unused areas within the memory map. Further, some non-implemen-
tation areas and unused (access prohibition) areas exist in the peripheral I/O area. If the program that
accesses these areas is generated, its operation cannot be guaranteed. Refer to the I/O memory maps
shown in Tables 4.1.1 (a)–(f) for the peripheral I/O area.
(2) Part of the RAM area is used as a stack area for subroutine call and register evacuation, so pay
attention not to overlap the data area and stack area.
(3) The S1C63000 core CPU handles the stack using the stack pointer for 4-bit data (SP2) and the stack
pointer for 16-bit data (SP1).
16-bit data are accessed in stack handling by SP1, therefore, this stack area should be allocated to the
area where 4-bit/16-bit access is possible (0100H to 01FFH). The stack pointers SP1 and SP2 change
cyclically within their respective range: the range of SP1 is 0000H to 03FFH and the range of SP2 is
0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more
exceeding the 4-bit/16-bit accessible range in the S1C63158 or it may be set to 00FFH or less. Memory
accesses except for stack operations by SP1 are 4-bit data access.
After initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and
SP2 are set by software. Further, if either SP1 or SP2 is re-set when both are set already, the interrupts
including NMI are masked again until the other is re-set. Therefore, the settings of SP1 and SP2 must
be done as a pair.
Power supply and operating mode
(1) When driving the S1C63158 with a 0.9–1.35 V power supply voltage, software control is necessary. Set
the oscillation system voltage regulator to the VC2 mode. When 1.35 V or more power supply voltage
is used, do not set the oscillation system voltage regulator into the VC2 mode.
(2) When using the A/D converter with a 0.9–1.6 V power supply voltage, software control is necessary.
Set the A/D converter voltage circuit to the VC2 mode. When 1.6 V or more power supply voltage is
used, do not set the A/D converter circuit into the VC2 mode.
(3) If the power supply voltage is out of the specified voltage range for an operating mode, do not switch
to the operating mode. It may cause malfunction or increase current consumption.
(4) When switching from the normal mode to the VC2 mode, the VDSEL and/or VADSEL registers should
be set to "1" after taking a 100 msec or longer interval for the VC2 to stabilize from switching the
DBON register to "1".
(5) When switching from the VC2 mode to the normal mode, use separate instructions to switch the mode
(VDSEL = "0" or VADSEL = "0") and turn the voltage booster OFF (DBON = "0"). Simultaneous
processing with a single instruction may cause malfunction.
(6) The OSC3 oscillation circuit can operate only in the normal mode with a power supply voltage from
2.2 V to 3.6 V.
Watchdog timer
(1) When the watchdog timer is being used, the software must reset it within 3-second cycles.
(2) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled
state (not used) before generating an interrupt (NMI) if it is not used.
Oscillation circuit
(1) When switching the CPU system clock from OSC1 to OSC3, first set VD1. After that maintain 2.5 msec
or more, and then turn the OSC3 oscillation ON.
When switching from OSC3 to OSC1, set VD1 after switching to OSC1 and turning the OSC3 oscilla-
tion OFF. However, when the CR oscillation circuit has been selected as the OSC1 oscillation circuit, it
is not necessary to set VD1.
S1C63158 TECHNICAL MANUAL EPSON 103
CHAPTER 5: SUMMARY OF NOTES
(2) It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabi-
lizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a
minimum of 5 msec have elapsed since the OSC3 oscillation went ON.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics
and conditions of use, so allow ample margin when setting the wait time.
(3) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3
oscillation OFF. An error in the CPU operation can result if this processing is performed at the same
time by the one instruction.
(4) Since the VD1 voltage value is fixed at 2.1 V when CR oscillation is selected for the OSC1 oscillation
circuit by mask option and the OSC3 oscillation circuit (CR or ceramic oscillation) is also used, it is not
necessary to switch VD1 by software. When the OSC3 oscillation circuit is not used, the OSC1 oscilla-
tion circuit can operate with 1.3 V of VD1 even if CR oscillation is selected.
Input port
(1) When input ports are changed from low to high by pull-up resistors, the rise of the waveform is
delayed on account of the time constant of the pull-up resistor and input gate capacitance. Hence,
when fetching input ports, set an appropriate waiting time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-up resistance 300 kΩ
(2) The K13 terminal functions as the clock input terminal for the programmable timer, and the input
signal is shared with the input port and the programmable timer. Therefore, when the K13 terminal is
set to the clock input terminal for the programmable timer, take care of the interrupt setting.
Output port
(1) When using the output port (R02, R03) as the special output port, fix the data register (R02, R03) at "1"
and the high impedance control register (R02HIZ, R03HIZ) at "0" (data output).
Be aware that the output terminal is fixed at a low (VSS) level the same as the DC output if "0" is
written to the R02 and R03 registers when the special output has been selected.
Be aware that the output terminal shifts into high impedance status when "1" is written to the high
impedance control register (R02HIZ, R03HIZ).
(2) A hazard may occur when the FOUT signal and the TOUT signal are turned ON and OFF.
(3) When fOSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation
circuit before output.
Refer to Section 4.4, "Oscillation Circuit", for the control and notes.
I/O port
When in the input mode, I/O ports are changed from low to high by pull-up resistor, the rise of the
waveform is delayed on account of the time constant of the pull-up resistor and input gate capacitance.
Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-up resistance 300 kΩ
104 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 5: SUMMARY OF NOTES
Clock timer
(1) Be sure to read timer data in the order of low-order data (TM0–TM3) then high-order data (TM4–
TM7).
(2) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequen-
cies and times differ from the values described in this section because the oscillation frequency will be
60 kHz (Typ.). Therefore, the clock timer can not be used for the clock function.
A/D converter
(1) When supply voltage is 1.6 V or less, it is necessary to set the A/D converter circuit into the VC2 mode
by writting "1" to VADSEL register befor starting A/D conversion.
(2) The A/D converter can operate by inputting the clock from the clock selector. Therefore, it is neces-
sary to select the clock source and to turn the clock output on before starting A/D conversion. Fur-
thermore, it is also necessary that the OSC3 oscillation circuit is operating when using the OSC3 clock.
(3) When using the OSC3 clock as the A/D conversion clock, do not stop the OSC3 oscillation circuit
during A/D conversion. If the OSC3 oscillation circuit stops, correct A/D conversion result cannot be
obtained.
(4) The input clock and analog input terminals should be set when the A/D converter stops. Changing
these settings in the A/D converter operation may cause errors.
(5) To prevent malfunction, do not start A/D conversion (writing "1" to the ADRUN register) when the
A/D conversion clock is not being output from the clock selector, and do not turn the clock off during
A/D conversion.
(6) If the CHS register selects an input channel which is not included in the analog input terminals set by
the PAD register (the PAD register can select several terminals simultaneously), the A/D conversion
does not result in a correct converted value.
(7) During A/D conversion, do not operate the P4n terminals which are not used for analog inputs of the
A/D converter (for input/output of digital signals). It affects the A/D conversion precision.
(8) Be aware that the maximum A/D clock frequency for the A/D converter is limited to 1 MHz when
OSC3 is used as the clock source.
Programmable timer
(1) When reading counter data, be sure to read the low-order 4 bits (PTD00–PTD03, PTD10–PTD13) first.
Furthermore, the high-order 4 bits (PTD04–PTD07, PTD14–PTD17) should be read within 0.73 msec of
reading the low-order 4 bits (PTD00–PTD03, PTD10–PTD13).
For the 16 bit × 1 mode, be sure to read as following sequence:
(PTD00–PTD03) → (PTD04–PTD07) → (PTD10–PTD13) → (PTD14–PTD17)
The read sequence time should be within 1.46 msec.
(2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge of
the input clock after writing to the PTRUN0/PTRUN1 register. Consequently, when "0" is written to the
PTRUN0/PTRUN1 register, the timer enters STOP status at the point where the counter is decremented
(-1). The PTRUN0/PTRUN1 register maintains "1" for reading until the timer actually stops.
Figure 5.2.1 shows the timing chart for the RUN/STOP control.
PTRUN0/PTRUN1 (WR)
PTD0X/PTD1X 42H 41H 40H 3FH 3EH 3DH
PTRUN0/PTRUN1 (RD)
Input clock
"1" (RUN)
writing "0" (STOP)
writing
Fig. 5.2.1 Timing chart for RUN/STOP control
It is the same even in the event counter mode. Therefore, be aware that the counter does not enter
RUN/STOP status if a clock is not input after setting the RUN/STOP control register (PTRUN0).
S1C63158 TECHNICAL MANUAL EPSON 105
CHAPTER 5: SUMMARY OF NOTES
(3) Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2
cycle is generated when the signal is turned ON and OFF by setting the register.
(4) When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time interval of several msec to several 10 msec from turning the circuit ON until the oscillation
stabilizes. Therefore, allow an adequate interval from turning the OSC3 oscillation circuit ON to
starting the programmable timer. Refer to Section 4.4, "Oscillation Circuit", for the control and notes of
the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the OFF state.
Serial interface
(1) Perform data writing/reading to the data registers SD0–SD7 only while the serial interface is not
running (i.e., the synchronous clock is neither being input or output).
(2) As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be
performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated
through data writing/reading on data registers SD0–SD7.) In addition, be sure to enable the serial
interface with the ESIF register before setting the trigger.
Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from
performing trigger input multiple times, as leads to malfunctioning. Moreover, when the synchronous
clock SCLK is external clock, start to input the external clock after the trigger.
(3) Setting of the input/output permutation (MSB first/LSB first) with the SDP register should be done
before setting data to SD0–SD7.
(4) Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is
used as the clock source of the programmable timer or in the slave mode.
Buzzer output circuit
Since it generates a buzzer signal that is out of synchronization with the BZON register, hazards may at
times be produced when the signal goes ON/OFF due to the setting of the BZON register.
SVD circuit
(1) To obtain a stable detection result, the SVD circuit must be ON for at least l00 µsec. So, to obtain the
SVD detection result, follow the programming sequence below.
1. Set SVDON to "1"
2. Maintain for 100 µsec minimum
3. Set SVDON to "0"
4. Read SVDDT
(2) The SVD circuit should normally be turned OFF because SVD operation increase current consump-
tion.
Interrupt
(1) The interrupt factor flags are set when the interrupt condition is established, even if the interrupt
mask registers are set to "0".
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(3) After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1
and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine.
Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is
set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one
is set.
106 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 5: SUMMARY OF NOTES
5.3 Precautions on Mounting
<Oscillation Circuit>
●Oscillation characteristics change depending on conditions (board pattern, components used, etc.).
In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's
recommended values for constants such as capacitance and resistance.
●Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following
points to prevent this:
(1) Components which are connected to the OSC1, OSC2, OSC3 and
OSC4 terminals, such as oscillators, resistors and capacitors,
should be connected in the shortest line.
(2) As shown in the right hand figure, make a VSS pattern as large as
possible at circumscription of the OSC1, OSC2, OSC3 and OSC4
terminals and the components connected to these terminals.
Furthermore, do not use this VSS pattern for any purpose other
than the oscillation system.
OSC4
OSC3
VSS
Sample VSS pattern (OSC3)
●In order to prevent unstable operation of the oscillation circuit due to current leak between OSC1/
OSC3 and VDD, please keep enough distance between OSC1/OSC3 and VDD or other signals on the
board pattern.
<Reset Circuit>
●The power-on reset signal which is input to the RESET terminal changes depending on conditions
(power rise time, components used, board pattern, etc.).
Decide the time constant of the capacitor and resistor after enough tests have been completed with the
application product.
When the built-in pull-up resistor is added to the RESET terminal by mask option, take into consider-
ation dispersion of the resistance for setting the constant.
●In order to prevent any occurrences of unnecessary resetting caused by noise during operating,
components such as capacitors and resistors should be connected to the RESET terminal in the
shortest line.
<Power Supply Circuit>
●Sudden power supply variation due to noise may cause malfunction. Consider the following points to
prevent this:
(1) The power supply should be connected to the VDD, VSS, AVDD, AVSS and AVREF terminal with
patterns as short and large as possible.
In particular, the power supply for AVDD, AVSS and AVREF affects A/D conversion precision.
(2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals
should be connected as short as possible.
V
DD
V
SS
Bypass capacitor connection example
V
DD
V
SS
(3) Components which are connected to the VD1 and VC2 terminals, such as capacitors, should be
connected in the shortest line.
S1C63158 TECHNICAL MANUAL EPSON 107
CHAPTER 5: SUMMARY OF NOTES
<A/D Converter>
●When the A/D converter is not used, the power supply terminals for the analog system should be
connected as shown below.
AVDD →VDD
AVSS →VSS
AVREF →VSS
<Arrangement of Signal Lines>
●In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do
not arrange a large current signal line near the circuits that are sensitive to noise such as the oscilla-
tion unit and analog input unit.
●When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line,
noise may generated by mutual interference between the signals and it may cause a malfunction.
Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the
oscillation unit and analog input unit.
P40 (AD0)
Large current signal line
High-speed signal line
OSC4
OSC3
V
SS
Large current signal line
High-speed signal line
Prohibited pattern
<Precautions for Visible Radiation (when bare chip is mounted)>
●Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause
this IC to malfunction. When developing products which use this IC, consider the following precau-
tions to prevent malfunctions caused by visible radiations.
(1) Design the product and implement the IC on the board so that it is shielded from visible radiation
in actual use.
(2) The inspection process of the product needs an environment that shields the IC from visible
radiation.
(3) As well as the face of the IC, shield the back and side too.
108 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 6: BASIC EXTERNAL WIRING DIAGRAM
CHAPTER 6BASIC EXTERNAL WIRING DIAGRAM
• When negative polarity is selected for buzzer output (mask option selection)
CA
CB
AVDD
AVREF
TEST
VDD
VD1
OSC1
OSC2
OSC3
OSC4
RESET
VSS
AVSS
C1
C2
CGX
CDC
CRES
CP
0.9 V
|
3.6 V
+
X'tal
CR
*3 *2
RCR2
*1 *2
RCR1
K00–K03
K10–K13
K20
P00–P03
P10 (SIN)
P11 (SOUT)
P12 (SCLK)
P13 (SRDY)
P20–P23
P30–P33
P40 (AD0)
P41 (AD1)
P42 (AD2)
P43 (AD3)
R00
R01
R02 (TOUT)
R03 (FOUT)
R10–R13
R20–R23
∗1: Crystal oscillation
∗2: CR oscillation
∗3: Ceramic oscillation
CGC
BZ
Input
I/O
Output
X'tal
CGX
RCR1
CR
CGC
CDC
RCR2
C1–C3
CP
CRES
Crystal oscillator
Trimmer capacitor
Resistor for OSC1 CR oscillation
Ceramic oscillator
Gate capacitor
Drain capacitor
Resistor for OSC3 CR oscillation
Capacitor
Capacitor
RESET terminal capacitor
32.768 kHz, CI (Max.) = 34 kΩ
5–25 pF
1.5 MΩ (60 kHz)
4 MHz (3.0 V)
100 pF
100 pF
40.2 kΩ (1.8 MHz)
0.2 µF
3.3 µF
0.1 µF
S1C63158
[The potential of the substrate
(back of the chip) is VSS.]
VC2
Note: The above table is simply an example, and is not guaranteed to work.
Piezo
Coil
C3
S1C63158 TECHNICAL MANUAL EPSON 109
CHAPTER 7: ELECTRICAL CHARACTERISTICS
CHAPTER 7ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Rating
Item
Supply voltage
Input voltage (1)
Input voltage (2)
Permissible total output current
∗1
Operating temperature
Storage temperature
Soldering temperature / time
Permissible dissipation ∗2
∗1
∗2
(VSS=0V)
Symbol
VDD
VI
VIOSC
ΣIVDD
Topr
Tstg
Tsol
PD
Rated value
-0.5 to 4.6
-0.5 to VDD + 0.3
-0.5 to VD1 + 0.3
10
-20 to 85
-65 to 150
260°C, 10sec (lead section)
250
Unit
V
V
V
mA
°C
°C
–
mW
The permissible total output current is the sum total of the current (average current) that simultaneously flows from the
output pin (or is drawn in).
In case of plastic package (QFP12-48pin, QFP13-64pin).
7.2 Recommended Operating Conditions
Item
Supply voltage
Oscillation frequency
(Ta=-20 to 70°C)
Symbol
V
DD
AV
DD
AV
REF
f
OSC1
f
OSC3
Unit
V
V
V
V
V
kHz
kHz
kHz
kHz
Max.
1.35
3.6
3.6
3.6
3.6
–
80
4100
Typ.
1.1
3.0
3.0
3.0
3.0
32.768
60
1800
Min.
0.9
1.35
2.2
0.9
0.9
–
40
Condition
V
SS
=0V Booster mode (OSC3 OFF)
Normal mode (OSC3 OFF)
Normal mode (OSC3 ON)
AV
SS
=0V
AV
REF
≤AV
DD
Crystal oscillation
CR oscillation
CR oscillation
Ceramic oscillation
110 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.3 DC Characteristics
Item
High level input voltage (1)
High level input voltage (2)
Low level input voltage (1)
Low level input voltage (2)
High level input current
Low level input current (1)
Low level input current (2)
High level output current (1)
High level output current (2)
Low level output current (1)
Low level output current (2)
Unless otherwise specified:
VDD=1.5V, VSS=0V, fOSC1=32.768kHz, Ta=25°C, VD1/VC2 are internal voltage, C1–C3=0.2µF
Symbol
VIH1
VIH2
VIL1
VIL2
IIH
IIL1
IIL2
IOH1
IOH2
IOL1
IOL2
Unit
V
V
V
V
µA
µA
µA
mA
mA
mA
mA
Max.
VDD
VDD
0.2·VDD
0.1·VDD
0.5
0
-2.5
-0.3
-0.3
Typ.
-5
Min.
0.8·VDD
0.9·VDD
0
0
0
-0.5
-7.5
0.5
0.5
Condition
K00–03, K10–13, K20, P00–03
P10–13, P20–23, P30–33, P40–43
RESET, TEST
K00–03, K10–13, K20, P00–03
P10–13, P20–23, P30–33, P40–43
RESET, TEST
VIH=1.5V K00–03, K10–13, K20, P00–03
P10–13, P20–23, P30–33, P40–43
RESET, TEST
VIL1=VSS K00–03, K10–13, K20, P00–03
No Pull-up P10–13, P20–23, P30–33, P40–43
RESET, TEST
VIL2=VSS K00–03, K10–13, K20, P00–03
With Pull-up P10–13, P20–23, P30–33, P40–43
RESET, TEST
VOH1=0.9·VDD R00–03, R10–13, R20–23, P00–03
P10–13, P20–23, P30–33, P40–43
VOH2=0.9·VDD BZ
VOL1=0.1·VDD R00–03, R10–13, R20–23, P00–03
P10–13, P20–23, P30–33, P40–43
VOL2=0.1·VDD BZ
Item
High level input voltage (1)
High level input voltage (2)
Low level input voltage (1)
Low level input voltage (2)
High level input current
Low level input current (1)
Low level input current (2)
High level output current (1)
High level output current (2)
Low level output current (1)
Low level output current (2)
Unless otherwise specified:
VDD=3.0V, VSS=0V, fOSC1=32.768kHz, Ta=25°C, VD1/VC2 are internal voltage, C1–C3=0.2µF
Symbol
VIH1
VIH2
VIL1
VIL2
IIH
IIL1
IIL2
IOH1
IOH2
IOL1
IOL2
Unit
V
V
V
V
µA
µA
µA
mA
mA
mA
mA
Max.
VDD
VDD
0.2·VDD
0.1·VDD
0.5
0
-5
-1.5
-1.5
Typ.
-10
Min.
0.8·VDD
0.9·VDD
0
0
0
-0.5
-15
3
3
Condition
K00–03, K10–13, K20, P00–03
P10–13, P20–23, P30–33, P40–43
RESET, TEST
K00–03, K10–13, K20, P00–03
P10–13, P20–23, P30–33, P40–43
RESET, TEST
VIH=3.0V K00–03, K10–13, K20, P00–03
P10–13, P20–23, P30–33, P40–43
RESET, TEST
VIL1=VSS K00–03, K10–13, K20, P00–03
No Pull-up P10–13, P20–23, P30–33, P40–43
RESET, TEST
VIL2=VSS K00–03, K10–13, K20, P00–03
With Pull-up P10–13, P20–23, P30–33, P40–43
RESET, TEST
VOH1=0.9·VDD R00–03, R10–13, R20–23, P00–03
P10–13, P20–23, P30–33, P40–43
VOH2=0.9·VDD BZ
VOL1=0.1·VDD R00–03, R10–13, R20–23, P00–03
P10–13, P20–23, P30–33, P40–43
VOL2=0.1·VDD BZ
S1C63158 TECHNICAL MANUAL EPSON 111
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.4 Analog Circuit Characteristics and Power Current Consumption
SVD voltage
SVD circuit response time
Current consumption
∗1
V
SVD
tSVD
I
OP
V
µs
µA
µA
µA
µA
µA
µA
µA
1.15
1.18
1.23
1.28
1.34
1.39
1.50
1.71
2.09
2.14
2.19
2.25
2.35
2.46
2.68
2.78
100
3
5
6
30
800
1200
12
1.05
1.10
1.15
1.20
1.25
1.30
1.40
1.60
1.95
2.00
2.05
2.10
2.20
2.30
2.50
2.60
1
2
3
15
400
900
7
0.95
1.02
1.07
1.12
1.16
1.21
1.30
1.49
1.81
1.86
1.91
1.95
2.05
2.14
2.33
2.42
The SVD circuit and the A/D converter are OFF. AV
REF
is open.
SVDS0–3="0"
SVDS0–3="1"
SVDS0–3="2"
SVDS0–3="3"
SVDS0–3="4"
SVDS0–3="5"
SVDS0–3="6"
SVDS0–3="7"
SVDS0–3="8"
SVDS0–3="9"
SVDS0–3="10"
SVDS0–3="11"
SVDS0–3="12"
SVDS0–3="13"
SVDS0–3="14"
SVDS0–3="15"
During HALT 32.768kHz
Normal mode *1
During HALT 32.768kHz
Booster mode
(V
DD
=1.2V)
∗1
During execution
32.768kHz
(Crystal oscillation)
Normal mode *1 60kHz (CR oscillation)
1.8MHz (CR oscillation)
4MHz
(Ceramic oscillation)
During execution
32.768kHz
(Crystal oscillation)
Booster mode
(V
DD
=1.2V)
∗1
Item Symbol UnitMax.Typ.Min.Condition
Unless otherwise specified:
V
DD
=3.0V, V
SS
=0V, f
OSC1
=32.768kHz, C
G
=25pF, Ta=25°C, V
D1
/V
C2
are internal voltage, C
1
–C
3
=0.2µF
A/D converter characteristic
Item
Resolution
Error
Convertion time
Input voltage
Reference voltage
AVREF resistance
Symbol
tconv
AVREF
Unit
bit
LSB
LSB
LSB
µs
µs
V
V
kΩ
Max.
8
3
3
3
21
641
AVREF
AVDD
Typ.
8
20
Min.
8
-3
-3
-3
AVSS
0.9
15
Condition
2.2V≤VDD≤2.7V Fconv=OSC3/2≤1MHz or OSC1
1.6V≤VDD≤2.2V Fconv=OSC1
0.9V≤VDD≤1.6V Fconv=OSC1, VADSEL=1
Fconv=OSC3/2=1MHz
Fconv=OSC1=32kHz
Unless otherwise specified:
AVDD=VDD=0.9 to 3.6V, AVSS=VSS=0V, Ta=-25 to 85°C
112 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.5 Oscillation Characteristics
The oscillation characteristics change depending on the conditions (components used, board pattern,
etc.). Use the following characteristics as reference values.
OSC1 crystal oscillation circuit
Item
Oscillation start voltage
Oscillation stop voltage
Built-in capacitance (drain)
Frequency/voltage deviation
Frequency/IC deviation
Frequency adjustment range
Harmonic oscillation start voltage
Permitted leak resistance
Symbol
Vsta
Vstp
CD
∂f/∂V
∂f/∂IC
∂f/∂CG
Vhho
Rleak
Unit
V
V
V
pF
ppm
ppm
ppm
ppm
V
MΩ
Max.
10
5
10
Typ.
10
30
Min.
1.1
1.1
0.9
-10
25
3.6
200
Condition
t
sta≤3sec (VDD)
t
stp≤10sec Normal mode
(VDD)Booster mode
Including the parasitic capacitance inside the IC (in chip)
VDD=0.9 to 3.6V with VDC switching
without VDC switching
CG=5 to 25pF
CG=5pF (VDD)
Between OSC1 and VDD, VSS
Unless otherwise specified:
VDD=3.0V, VSS=0V, fOSC1=32.768kHz, CG=25pF, CD=built-in, Ta=25°C
OSC1 CR oscillation circuit
Item
Oscillation frequency dispersion
Oscillation start voltage
Oscillation start time
Oscillation stop voltage
Symbol
fOSC1
Vsta
tsta
Vstp
Unit
%
V
ms
V
Max.
30
3
Typ.
60kHz
Min.
-30
2.2
2.2
Condition
Normal mode (VDD)
VDD=2.2 to 3.6V
Normal mode (VDD)
Unless otherwise specified:
VDD=3.0V, VSS=0V, RCR1=1.5MΩ, Ta=25°C, VDC=1
Item
Oscillation frequency dispersion
Oscillation start voltage
Oscillation start time
Oscillation stop voltage
Symbol
fOSC1
Vsta
tsta
Vstp
Unit
%
V
ms
V
Max.
30
3
Typ.
80kHz
Min.
-30
1.3
1.3
Condition
Normal mode (VDD)
VDD=1.3 to 3.6V
Normal mode (VDD)
Unless otherwise specified:
VDD=3.0V, VSS=0V, RCR1=1MΩ, Ta=25°C, VDC=0
OSC3 ceramic oscillation circuit
Unless otherwise specified:
VDD=3.0V, VSS=0V, Ceramic oscillator: 4MHz, CGC=CDC=100pF, Ta=25°C
Item
Oscillation start voltage
Oscillation start time
Oscillation stop voltage
Symbol
Vsta
tsta
Vstp
Unit
V
ms
V
Max.
5
Typ.Min.
2.2
2.2
Condition
Normal mode (VDD)
VDD=2.2 to 3.6V
Normal mode (VDD)
OSC3 CR oscillation circuit
Unless otherwise specified:
VDD=3.0V, VSS=0V, RCR2=40.2kΩ, Ta=25°C
Item
Oscillation frequency dispersion
Oscillation start voltage
Oscillation start time
Oscillation stop voltage
Symbol
fOSC3
Vsta
tsta
Vstp
Unit
%
V
ms
V
Max.
30
3
Typ.
1.8MHz
Min.
-30
2.2
2.2
Condition
Normal mode (VDD)
VDD=2.2 to 3.6V
Normal mode (VDD)
S1C63158 TECHNICAL MANUAL EPSON 113
CHAPTER 7: ELECTRICAL CHARACTERISTICS
OSC1 CR oscillation frequency-resistance characteristic (VDC = 1)
The oscillation characteristics change depending on the conditions (components used, board pattern,
etc.). Use the following characteristics as reference values and evaluate the characteristics on the actual
product.
Resistance for CR oscillation RCR1 [kΩ]
CR oscillation frequency fOSC1 [kHz]
10
100
1000
10000
10 100 1000 10000
V
DD
= 2.2 to 3.6V
V
D1
= 2.1V (VDC = 1)
V
SS
= 0V
Ta = 25°C
Typ. value
OSC1 CR oscillation frequency-resistance characteristic (VDC = 0)
The oscillation characteristics change depending on the conditions (components used, board pattern,
etc.). Use the following characteristics as reference values and evaluate the characteristics on the actual
product.
Resistance for CR oscillation RCR1 [kΩ]
CR oscillation frequency fOSC1 [kHz]
10
100
1000
10000
10 100 1000 10000
V
DD
= 1.3 to 3.6V
V
D1
= 1.3V (VDC = 0)
V
SS
= 0V
Ta = 25°C
Typ. value
114 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 7: ELECTRICAL CHARACTERISTICS
OSC3 CR oscillation frequency-resistance characteristic
The oscillation characteristics change depending on the conditions (components used, board pattern,
etc.). Use the following characteristics as reference values and evaluate the characteristics on the actual
product.
Resistance for CR oscillation R
CR2
[kΩ]
CR oscillation frequency f
OSC3
[kHz]
10
100
1000
10000
10 100 1000 10000
VDD = 2.2 to 3.6V
VSS = 0V
Ta = 25°C
Typ. value
S1C63158 TECHNICAL MANUAL EPSON 115
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.6 Serial Interface AC Characteristics
Clock synchronous master mode
• During 32 kHz operation
Item
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
Symbol
t
smd
t
sms
t
smh
Unit
µs
µs
µs
Max.
5
Typ.Min.
10
5
Condition: V
DD
=3.0V, V
SS
=0V, Ta=25°C, V
IH1
=0.8V
DD
, V
IL1
=0.2V
DD
, V
OH
=0.8V
DD
, V
OL
=0.2V
DD
• During 1 MHz operation
Item
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
Symbol
tsmd
tsms
tsmh
Unit
ns
ns
ns
Max.
200
Typ.Min.
400
200
Condition: V
DD
=3.0V, V
SS
=0V, Ta=25°C, V
IH1
=0.8V
DD
, V
IL1
=0.2V
DD
, V
OH
=0.8V
DD
, V
OL
=0.2V
DD
Clock synchronous slave mode
• During 32 kHz operation
Item
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
Symbol
t
ssd
t
sss
t
ssh
Unit
µs
µs
µs
Max.
10
Typ.Min.
10
5
Condition: V
DD
=3.0V, V
SS
=0V, Ta=25°C, V
IH1
=0.8V
DD
, V
IL1
=0.2V
DD
, V
OH
=0.8V
DD
, V
OL
=0.2V
DD
• During 1 MHz operation
Item
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
Symbol
tssd
tsss
tssh
Unit
ns
ns
ns
Max.
500
Typ.Min.
400
200
Condition: V
DD
=3.0V, V
SS
=0V, Ta=25°C, V
IH1
=0.8V
DD
, V
IL1
=0.2V
DD
, V
OH
=0.8V
DD
, V
OL
=0.2V
DD
<Master mode>
SCLK OUT
SOUT
SIN
V
OH
V
OH
V
OL
t
sms
t
smh
t
smd
V
IH1
V
IL1
V
OL
<Slave mode>
SCLK IN
SOUT
SIN
V
IH1
V
OH
V
OL
t
sss
t
ssh
t
ssd
V
IH1
V
IL1
V
IL1
116 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.7 Timing Chart
Reset
Supply voltage
OSC1 oscillation clock
RESET terminal
(active-Low)
Internal reset signal
(active-High)
3 sec
Oscillation unstabilized state
6 msec min.
(fOSC1 = 32.768 kHz)
System clock switching
VDC
OSCC
CLKCHG
(Note) When the OSC1 oscillation circuit has been selected as the CR oscillation circuit,
it is not necessary to set the VDC register.
Whether the VDC register value is "1" or "0" does not matter.
∗2.5 msec min.
5 msec min.
∗ 1 instruction execution time or longer
Supply voltage VC2 mode control during heavy load driving
DBON
VDSEL
VADSEL (Note)
Heavy load ON
OFF
(Note) VADSEL is used only when it is required.
∗
∗100 msec min.
100 msec min.
1 msec min. 2 sec min.
∗ 1 instruction execution time or longer
S1C63158 TECHNICAL MANUAL EPSON 117
CHAPTER 8: PACKAGE
CHAPTER 8PACKAGE
8.1 Plastic Package
QFP12-48pin
(Unit: mm)
The dimensions are subject to change without notice.
7
±0.1
9
±0.4
2536
7
±0.1
9
±0.4
13
24
INDEX
0.18
121
48
37
1.4
±0.1
0.1
1.7
max
1
0.5
±0.2
0°
10°
0.125
±0.05
0.5
+0.1
–0.05
118 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 8: PACKAGE
QFP13-64pin
(Unit: mm)
The dimensions are subject to change without notice.
10
±0.1
12
±0.4
3348
10
±0.1
12
±0.4
17
32
INDEX
0.18
161
64
49
1.4
±0.1
0.1
1.7
max
1
0.5
±0.2
0°
10°
0.125
+0.1
–0.05
+0.05
–0.025
0.5
S1C63158 TECHNICAL MANUAL EPSON 119
CHAPTER 8: PACKAGE
8.2 Ceramic Package for Test Samples
QFP13-64pin
(Unit: mm)
10
±0.1
12.4
±0.3
10
±0.1
12.4
±0.3
0.5 0.2
0.2
2.81
max
0.5
±0.2
0.15
3348
17
32
161
64
49
INDEX
120 EPSON S1C63158 TECHNICAL MANUAL
CHAPTER 9: PAD LAYOUT
CHAPTER 9PAD LAYOUT
9.1 Diagram of Pad Layout
X
Y
(0, 0)
3.30 mm
3.23 mm
151015
20
25
30
35 40
45
50
55
57
Die No.
Chip thickness: 400 µm
Pad opening: 98 µm
9.2 Pad Coordinates
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Pad name
P43
P42
P41
P40
P33
P32
P31
P30
P23
P22
P21
P20
P13
P12
P11
P10
P03
P02
P01
X
946
815
684
553
421
290
159
28
-104
-235
-366
-498
-629
-760
-891
-1023
-1521
-1521
-1521
Y
1486
1486
1486
1486
1486
1486
1486
1486
1486
1486
1486
1486
1486
1486
1486
1486
1039
907
776
No.
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Pad name
P00
R23
R22
R21
R20
R13
R12
R11
R10
R03
R02
R01
R00
BZ
K00
K01
K02
K03
K10
X
-1521
-1521
-1521
-1521
-1521
-1521
-1521
-1521
-1521
-1521
-1521
-392
-260
-128
2
133
265
396
527
Y
645
514
382
251
120
-11
-143
-274
-405
-536
-668
-1486
-1486
-1486
-1486
-1486
-1486
-1486
-1486
No.
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
Pad name
K11
K12
K13
K20
VSS
OSC1
OSC2
VD1
OSC3
OSC4
VDD
RESET
TEST
AVDD
AVSS
AV
REF
CB
CA
VC2
X
658
790
921
1052
1521
1521
1521
1521
1521
1521
1521
1521
1521
1521
1521
1521
1521
1521
1521
Y
-1486
-1486
-1486
-1486
-831
-700
-569
-438
-306
-175
-44
88
219
350
481
613
744
875
1006
Unit: µm
S1C63158 TECHNICAL MANUAL EPSON 121
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63158/358/P366)
APPENDIX S5U1C63000P MANUAL
(P
ERIPHERAL
C
IRCUIT
B
OARD
FOR
S1C63158/358/P366)
This manual describes how to use the Peripheral Circuit Board for the S1C63158/358/P366
(S5U1C63000P), which provides emulation functions when mounted on the debugging tool for the S1C63
Family of 4-bit single-chip microcomputers, the ICE (S5U1C63000H1/S5U1C63000H2).
This description of the S1C63 Family Peripheral Circuit Board (S5U1C63000P) provided in this document
assumes that circuit data for the S1C63158/358/P366 has already been downloaded to the board. For
information on downloading various circuit data and on common board specifications, please see the
S5U1C63000P Manual (S1C63 Family Peripheral Circuit Board) included with the product. Please refer to
the user’s manual provided with your ICE for detailed information on its functions and method of use.
A.1 Names and Functions of Each Part
The following explains the names and functions of each part of the board (S5U1C63000P).
VSVD
VC5
PRG
CLK
RESET
IOSEL2
XC4062XLA
DE
13
VLCD
CN3 connector (Unused) CN2 connector CN1 connector
(3)
(4)
(9)
(1) (2)
(11)
(10)
(9)
(8)
(7)
(6)
(5)
(1) VLCD
You can turn this control to adjust the LCD drive power supply voltage. However, in the actual IC,
LCD drive power supply voltage cannot be adjusted.
(2) VSVD
This control allows you to vary the power supply voltage artificially in order to verify the operation of
the power supply voltage detect function (SVD). Keep in mind that a single control position indicates
two voltage values.
SVD levels 0 1 2 3 4 5 6 7
89101112 13 14 15
(For example, SVD levels 0 and 8 are at the same control position.)
(3) Register monitor LEDs
These LEDs correspond one-to-one to the registers listed below. The LED lights when the data is logic
"1" and goes out when the data is logic "0".
VDC, OSCC, CLKCHG, DBON, HLON, VDSEL, VADSEL, SVDS0–3, SVDON, LPWR, VCCHG
122 EPSON S1C63158 TECHNICAL MANUAL
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63158/358/P366)
(4) Register monitor pins
These pins correspond one-to-one to the registers listed below. The pin outputs a high for logic "1"
and a low for logic "0".
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Monitor
∗1 DONE: The monitor pin outputs a high while the LED lights when
initialization of this board completes without problems.
∗2 DBON: Used for the S1C63158 and S1C6P366.
Name
DONE *1
VDC
OSCC
CLKCHG
DBON *2
–
VDSEL
VADSEL
SVDS0
SVDS1
SVDS2
SVDS3
SVDON
LPWR
VCCHG
–
LED No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LEDName
DONE *1
VDC
OSCC
CLKCHG
DBON *2
–
VDSEL
VADSEL
SVDS0
SVDS1
SVDS2
SVDS3
SVDON
LPWR
VCCHG
–Monitor pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
LED
(5) CR oscillation frequency adjusting control
When OSC1 and OSC3 respectively are set for a CR oscillation circuit and a CR/ceramic oscillation
circuit by a mask option, this control allows you to adjust the oscillation frequency. The oscillation
frequency can be adjusted in the range of approx. 20 kHz to 500 kHz for OSC1 and approx. 100 kHz to
8 MHz for OSC3. Note that the actual IC does not operate with all of these frequencies; consult the
technical manual for the S1C63158/358/P366 to select the appropriate operating frequency.
OSC1 rough adjustment
OSC1 fine adjustment
OSC3 rough adjustment
OSC3 fine adjustment
(6) CR oscillation frequency monitor pins
These pins allow you to monitor the clock waveform from the CR oscillation circuit with an oscillo-
scope. Note that these pins always output a signal waveform whether or not the oscillation circuit is
operating.
OSC3 monitor pin (red)
OSC1 monitor pin (red)
GND pin (black)
RESET
S1C63158 TECHNICAL MANUAL EPSON 123
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63158/358/P366)
(7) RESET switch
This switch initializes the internal circuits of this board and feeds a reset signal to the ICE.
(8) Monitor pins and external part connecting socket
These parts are currently unused.
(9) CLK and PRG switch
If power to the ICE is shut down before circuit data downloading is complete, the circuit configura-
tion in this board will remain incomplete, and the debugger may not be able to start when you power
on the ICE once again. In this case, temporarily power off the ICE and set CLK to the 32K position and
the PRG switch to the Prog position, then switch on power for the ICE once again. This should allow
the debugger to start up, allowing you to download circuit data. After downloading the circuit data,
temporarily power off the ICE and reset CLK and PRG to the LCLK and the Norm position, respec-
tively. Then power on the ICE once again.
(10) IOSEL2
When downloading circuit data, set IOSEL2 to the "E" position. Otherwise, set to the "D" position.
(11) VC5
Unused.
124 EPSON S1C63158 TECHNICAL MANUAL
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63158/358/P366)
A.2 Connecting to the Target System
To connect this board (S5U1C63000P) to the target system, use the I/O connecting cables supplied with
the board (80-pin/40-pin × 2, 100-pin/50-pin × 2, flat type). Take care when handling the connectors,
since they conduct electrical power (VDD = +3.3 V).
CN1-1
(40-pin)
CN1-2
(40-pin)
I/O connection cable
To target board
mark
CN2-2
(50-pin)
CN2-1
(50-pin)
Fig. A.2.1 Connecting the S5U1C63000P to the target system
S1C63158 TECHNICAL MANUAL EPSON 125
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63158/358/P366)
Table A.2.1 I/O connector pin assignment
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
40-pin CN1-1 connector
Pin name
V
DD
(=3.3 V)
V
DD
(=3.3 V)
K00
K01
K02
K03
K10
K11
K12
K13
V
SS
V
SS
P00
P01
P02
P03
P10
P11
P12
P13
V
DD
(=3.3 V)
V
DD
(=3.3 V)
P20
P21
P22
P23
P30
P31
P32
P33
V
SS
V
SS
P40
P41
P42
P43
V
REF
K20
V
SS
V
SS
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
40-pin CN1-2 connector
Pin name
V
DD
(=3.3 V)
V
DD
(=3.3 V)
R00
R01
R02
R03
R10
R11
R12
R13
V
SS
V
SS
R20
R21
R22
R23
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
V
DD
(=3.3 V)
V
DD
(=3.3 V)
BZ
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
V
SS
V
SS
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
RESET
V
SS
V
SS
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
50-pin CN2-1 connector
Pin name
V
DD
(=3.3 V)
V
DD
(=3.3 V)
SEG0 (DC)
SEG1 (DC)
SEG2 (DC)
SEG3 (DC)
SEG4 (DC)
SEG5 (DC)
SEG6 (DC)
SEG7 (DC)
V
SS
V
SS
SEG8 (DC)
SEG9 (DC)
SEG10 (DC)
SEG11 (DC)
SEG12 (DC)
SEG13 (DC)
SEG14 (DC)
SEG15 (DC)
V
DD
(=3.3 V)
V
DD
(=3.3 V)
SEG16 (DC)
SEG17 (DC)
SEG18 (DC)
SEG19 (DC)
SEG20 (DC)
SEG21 (DC)
SEG22 (DC)
SEG23 (DC)
V
SS
V
SS
SEG24 (DC)
SEG25 (DC)
SEG26 (DC)
SEG27 (DC)
SEG28 (DC)
SEG29 (DC)
SEG30 (DC)
SEG31 (DC)
V
DD
(=3.3 V)
V
DD
(=3.3 V)
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
50-pin CN2-2 connector
Pin name
V
DD
(=3.3 V)
V
DD
(=3.3 V)
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
V
SS
V
SS
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
V
DD
(=3.3 V)
V
DD
(=3.3 V)
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
V
SS
V
SS
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
V
DD
(=3.3 V)
V
DD
(=3.3 V)
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
Cannot be connected
∗ Connectors CN2-1 and CN2-2 are used when the SEG pins are set for DC output with a mask option.
126 EPSON S1C63158 TECHNICAL MANUAL
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63158/358/P366)
A.3 Usage Precautions
To ensure correct use of this board (S5U1C63000P), please observe the following precautions.
A.3.1 Operational precautions
(1) Before inserting or removing cables, turn off power to all pieces of connected equipment.
(2) Do not turn on power or load mask option data if all of the input ports (K00–K03) are held low. Doing
so may activate the multiple key entry reset function.
(3) Before debugging, always be sure to load mask option data.
A.3.2 Differences with the actual IC
(1) Differences in I/O
<Interface power supply>
This board and target system interface voltage is set to +3.3 V. To obtain the same interface voltage as
in the actual IC, attach a level shifter circuit, etc. on the target system side to accommodate the
required interface voltage.
<Each output port’s drive capability>
The drive capability of each output port on this board is higher than that of the actual IC. When
designing application system and software, refer to the technical manual for the S1C63158/358/P366
to confirm each output port’s drive capability.
<Each port’s protective diode>
All I/O ports incorporate a protective diode for VDD and VSS, and the interface signals between this
board and the target system are set to +3.3 V. Therefore, this board and the target system cannot be
interfaced with voltages exceeding VDD by setting the output ports for open-drain mode.
<Pull-up resistance value>
The pull-up resistance values on this board are set to 220 kΩ which differ from those for the actual IC.
For the resistance values on the actual IC, refer to the technical manual for the S1C63158/358/P366.
Note that when using pull-up resistors to pull the input pins high, the input pins may require a
certain period to reach a valid high level. Exercise caution if a key matrix circuit is configured using a
combination of output and input ports, since rise delay times on these input ports differ from those of
the actual IC.
(2) Differences in current consumption
The amount of current consumed by this board differs significantly from that of the actual IC. Inspect-
ing the LEDs on this board may help you keep track of approximate current consumption. The
following factors/components greatly affect device current consumption:
<Those which can be verified by LEDs and monitor pins>
a) Run and Halt execution ratio (verified by LEDs and monitor pins on the ICE)
b) CPU operating voltage select circuit (VDC)
c) OSC3 oscillation on/off circuit (OSCC)
d) CPU clock change circuit (CLKCHG)
e) ×2 boost on/off circuit (DBON)
f) Power supply select circuit for oscillator-system voltage-regulating circuit (VDSEL)
g) Power supply select circuit for A/D converter circuit (VADSEL)
h) SVD circuit on/off circuit (SVDON)
i) LCD power supply on/off circuit (LPWR)
j) LCD constant-voltage change circuit (VCCHG)
<Those that can only be counteracted by system or software>
k) Current consumed by the internal pull-up resistors
l) Input ports in a floating state
S1C63158 TECHNICAL MANUAL EPSON 127
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63158/358/P366)
(3) Functional precautions
<LCD power supply circuit>
There is a finite delay time from the point at which the LCD power supply circuit (LPWR) turns on
until an LCD drive waveform is output. On this board, this delay is set to approx. 125 msec, which
differs from that of the actual IC. Refer to the technical manual for the S1C63158/358/P366.
<Differences in LCD drive waveform>
If the LCD is set for static output (STCD register = "1"), the LCD drive waveform on this board and
that of the actual IC will differ in the following respects (for 1/3 bias only).
VC3
VC2
VC1
VSS
VC3
VC2
VC1
VSS
VC3
VC2
VC1
VSS
VC3
VC2
VC1
VSS
<Actual IC>
<S5U1C63000P + LCD board>
SEG
terminal
COM
terminal
SEG
terminal
COM
terminal
Register 10
<SVD circuit>
-Although the S1C63158/358/P366 has a function for detecting externally sourced voltages, this
board is unable to detect externally sourced voltages. The SVD function is realized by artificially
varying the power supply voltage using the VSVD control on this board.
-There is a finite delay time from when the power to the SVD circuit turns on until actual detection of
the voltage. On this board, this delay is set to 61–92 µsec, which differs from that of the actual IC.
Refer to the technical manual for the S1C63158/358/P366 when setting the appropriate wait time for
the actual IC.
<Oscillation circuit>
-A wait time is required before oscillation stabilizes after the OSC3 oscillation control circuit (OSCC)
is turned on. On this board, even when OSC3 oscillation is changed (CLKCHG) without a wait time,
OSC3 will function normally. Refer to the technical manual for the S1C63158/358/P366 when setting
the appropriate wait time for the actual IC.
-Use separate instructions to switch the clock from OSC3 to OSC1 and to turn off the OSC3 oscillation
circuit. If executed simultaneously with a single instruction, these operations, although good with
this board, may not function properly well with the actual IC.
-Because the logic level of the oscillation circuit is high, the timing at which the oscillation starts on
this board differs from that of the actual IC.
-This board contains oscillation circuits for OSC1 and OSC3. Keep in mind that even though the
actual IC may not have a resonator connected to its OSC3, its emulator can operate with the OSC3
circuit.
-Do not turn on the OSC3 oscillation circuit when the voltage-regulating circuit for high-speed
operation remains idle.
128 EPSON S1C63158 TECHNICAL MANUAL
APPENDIX S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63158/358/P366)
<Access to undefined address space>
If any undefined space in the S1C63158/358/P366's internal ROM/RAM or I/O is accessed for data
read or write operations, the read/written value is indeterminate. Additionally, it is important to
remain aware that indeterminate state differs between this board and the actual IC. Note that the ICE
(S5U1C63000H1/S5U1C63000H2) incorporates the program break function caused by accessing to an
undefined address space.
<Reset circuit>
Keep in mind that the operation sequence from when the ICE and this board are powered on until the
time at which the program starts running differs from the sequence from when the actual IC is
powered on till the program starts running. This is because this board becomes capable of operating
as a debugging system after the user program and optional data are downloaded. When operating the
ICE after placing it in free-running mode, always apply a system reset. A system reset can be per-
formed by pressing the reset switch on this board, by a reset pin input, or by holding the input ports
low simultaneously.
<Internal power supply circuit>
-Although this board contains VDC, DBON, HLON, VDSEL, and VADSEL registers, it does not
actually exercise power supply control by these registers. Be sure to refer to the technical manual for
the S1C63158/358/P366 when setting the correct voltage. Also, when switching the control voltages,
consult the technical manual to determine the appropriate wait time to be inserted.
-Although this board has a control (VLCD) for adjusting the LCD drive voltage, the actual IC does
not have this capability. Note that the LCD drive voltage on this board may not be identical to that
on the actual IC.
-Since the usable operating frequency range depends on the device's internal operating voltage,
consult the technical manual for the S1C63158/358/P366 to ensure that the device will not be
operated with an inappropriate combination of the operating frequency and the internal power
supply.
<Differences in I/O registers>
Although the register bit D1 (address FF01H) is always set to 0 when read out, it operates as a read/
write register on this board. Take care to avoid writing a 1 to this bit.
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Technical Manual
S1C63158
EPSON Electronic Devices Website
ELECTRONIC DEVICES MARKETING DIVISION
First issue April, 1998
Printed October, 2001 in Japan A
L
M
