Hi gh Per for m an ce 128K 128 K x8 C M OS S R A M A S 7C1024 A S 7C31024 (R) 1288K x8 CMOS S R A M 12 Features * Organization: 131,072 words x 8 bits * High speed - 10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time * Low power consumption - Active: 660 mW max (15 ns cycle) - Standby: 55 mW max, CMOS I/O - Very low DC component in active power * 2.0V data retention * Equal access and cycle times * Easy memory expansion with CE1, CE2, OE inputs * TTL/LVTTL-compatible, three-state I/O * 32-pin JEDEC standard packages - 300 mil PDIP and SOJ Socket compatible with 7C512 (64Kx8) - 400 mil PDIP and SOJ - 8x20 TSOP * ESD protection 2000 volts * Latch-up current 200 mA * 3.3V and 5.0V versions available * Industrial and commercial temperature available Logic block diagram Pin arrangement TSOP 8x20 DIP, SOJ Vcc Input buffer 512x256x8 Array (1,048,576) Sense amp I/O7 Row decoder A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O0 Control circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AS7C1024 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE NC A10 CE1 A16 I/O7 A14 I/O6 A12 A7 I/O4 I/O5 A6 I/O3 A5 GND A4 I/O2 A3 I/O1 A2 I/O0 A1 A0 A0 A1 I/O0 A2 I/O1 A3 I/O2 GND WE OE CE1 CE2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 A9 A10 A11 A12 A13 A14 A15 A16 Column decoder A11 A9 A8 A13 WE CE2 A15 Vcc NC A16 A14 A12 A7 A6 A5 A4 AS7C1024 GND Selection guide Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current AS7C1024 AS7C31024 7C1024-10 - 10 3 175 - 10.0 7C1024-12 7C31024-12 12 3 160 100 10.0 7C1024-15 7C31024-15 15 4 120 70 10.0 7C1024-20 7C31024-20 20 5 110 65 10.0 Unit ns ns mA mA mA Shaded areas contain advance information. ALLIANCE SEMICONDUCTOR DID 11-20000-*A. 5/29/97 1 Copyright (c)1997 Alliance Semiconductor. All rights reserved. AS7C1024 AS7C31024 (R) Functional description The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memories (SRAM) organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank memory systems. When CE1 is HIGH or CE2 is LOW the device enters standby mode. The standard AS7C1024 is guaranteed not to exceed 55 mW power consumption in standby mode. Both devices offer 2.0V data retention. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) HIGH. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL/LVTTL-compatible, and operation is from a single 5V supply (AS7C1024) or 3.3V supply (AS7C31024). The AS7C1024 and AS7C31024 are packaged in common industry standard packages. Absolute maximum ratings Parameter Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Temperature under bias DC output current Symbol Vt PD Tstg Tbias Iout Min -0.5 - -55 -10 - Max +7.0 1.0 +150 +85 20 Unit V W o C o C mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE1 H X L L L CE2 X L H H H WE X X H H L OE X X H L X Data High Z High Z High Z Dout Din Mode Standby (ISB, ISB1) Standby (ISB, ISB1) Output disable Read Write Key: X = Don't Care, L = LOW, H = HIGH Recommended operating conditions Parameter Supply voltage AS7C1024 AS7C31024 Input voltage AS7C1024 AS7C31024 Symbol VCC VCC GND VIH VIH VIL Min 4.5 3.0 0.0 2.2 2.0 -0.5 Nominal 5.0 3.3 0.0 - - - Max 5.5 3.6 0.0 VCC + 0.5 VCC + 0.5 0.8 Unit V V V V V V VIL min = -3.0V for pulse width less than tRC/2. 2 DID F11-20000-*A. 5/29/97 Copyright (c)1997 Alliance Semiconductor. All rights reserved. AS7C1024 AS7C31024 (R) DC operating characteristics 1 | ILI | VCC = Max, Vin = GND to VCC - 1 - 1 - 1 - 1 A Output leakage current | ILO | CE1 = VIH or CE2 = VIL, VCC = Max, Vout = GND to VCC - 1 - 1 - 1 - 1 A Operating power supply current ICC CE1 = VIL, CE2 = VIH, f = fmax, Iout = 0 mA - - 175 - - - 160 100 - - 120 70 - - 110 65 mA mA ISB CE1 = VIH or CE2 = VIL, f = fmax - 55 - 50 - 40 - 40 mA Standby power supply current Output voltage Symbol -10 -12 -15 -20 Min Max Min Max Min Max Min Max Parameter Input leakage current Test conditions AS7C1024 AS7C31024 Unit CE1 VCC-0.2V or CE2 0.2V, ISB1 Vin 0.2V or Vin VCC-0.2V, - 10 - 10 - 10 - 10 mA VOL VOH f=0 IOL = 8 mA, VCC = Min IOH = -4 mA, V CC = Min - 2.4 0.4 - - 2.4 0.4 - - 2.4 0.4 - - 2.4 0.4 - V V Shaded areas contain advance information. Capacitance 2 (f = 1 MHz, Ta = Room temperature, VCC = 5V) Parameter Input capacitance Symbol CIN I/O capacitance CI/O Signals Test conditions V A, CE1, CE2, WE, OE in = 0V I/O Vin = Vout = 0V Max 5 Unit pF 7 pF Read cycle 3,9,12 OE LOW to output in Low Z Symbol tRC tAA tACE1 tACE2 tOE tOH tCLZ1 tCLZ2 tCHZ1 tCHZ2 tOLZ Min 10 - - - - 2 3 3 - - 0 OE HIGH to output in High Z Power up time Power down time tOHZ tPU tPD - 0 - Parameter Read cycle time Address access time Chip enable (CE1) access time Chip enable (CE2) access time Output enable (OE) access time Output hold from address change CE1 LOW to output in Low Z CE2 HIGH to output in Low Z CE1 HIGH to output in High Z CE2 LOW to output in High Z -10 Max - 10 10 10 3 - - - 3 3 - 3 - 10 -12 -15 -20 Min 12 - - - - 3 3 3 - - 0 Max - 12 12 12 3 - - - 3 3 - Min 15 - - - - 3 3 3 - - 0 Max - 15 15 15 4 - - - 4 4 - Min 20 - - - - 3 3 3 - - 0 Max - 20 20 20 5 - - - 5 5 - Unit ns ns ns ns ns ns ns ns ns ns ns 5 4, 5, 12 4, 5, 12 4, 5, 12 4, 5, 12 4, 5 - 0 - 3 - 12 - 0 - 4 - 15 - 0 - 5 - 20 ns ns ns 4, 5 4, 5, 12 4, 5, 12 Notes 3 3, 12 3, 12 3 DID F11-20000-*A. 5/29/97 Copyright (c)1997 Alliance Semiconductor. All rights reserved. AS7C1024 AS7C31024 (R) Key to switching waveforms Rising input Falling input Undefined output/don't care Read waveform 1 3,6,7,9,12 Address controlled tRC Address tAA tOH Dout Data valid Read waveform 2 3,6,8,9,12 CE1 and CE2 controlled tRC1 CE1 CE2 tOE OE tOLZ tOHZ tACE1, tACE2 tCHZ1, tCHZ2 Dout Data valid tCLZ1, tCLZ2 Current supply tPU tPD 50% ICC ISB 50% Write cycle 11, 12 Parameter Write cycle time Chip enable (CE1) to write end Chip enable (CE2) to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in High Z Output active from write end Symbol tWC tCW1 tCW2 tAW tAS tWP tAH tDW tDH tWZ tOW -10 Min Max 10 - 9 - 9 - 9 - 0 - 7 - 0 - 6 - 0 - - 5 3 - -12 Min Max 12 - 10 - 10 - 10 - 0 - 8 - 0 - 6 - 0 - - 5 3 - -15 Min Max 15 - 12 - 12 - 12 - 0 - 9 - 0 - 9 - 0 - - 5 3 - -20 Min Max 20 - 12 - 12 - 12 - 0 - 12 - 0 - 10 - 0 - - 5 3 - Unit ns ns ns ns ns ns ns ns ns ns ns Notes 12 12 12 4, 5 4, 5 4, 5 Shaded areas contain advance information. 4 DID F11-20000-*A. 5/29/97 Copyright (c)1997 Alliance Semiconductor. All rights reserved. AS7C1024 AS7C31024 (R) Write waveform 1 10,11,12 WE controlled tWC tAW tAH Address tWP WE tAS tDW Din tDH Data valid tWZ tOW D out Write waveform 2 10,11,12 CE1 and CE2 controlled tWC tAW tAH Address tAS tCW1, tCW2 CE1 CE2 tWP WE tWZ Din tDW tDH Data valid Dout Data retention characteristics 14 Parameter VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Symbol VDR ICCDR tCDR tR Input leakage current | ILI | Test conditions VCC = 2.0V CE1 VCC-0.2V or CE2 0.2V Vin VCC-0.2V or Vin 0.2V Min 2.0 - 0 tRC Max - 500 - - Unit V A ns ns - 1 A Data retention waveform Data retention mode VCC VDR 2.0V 4.5V 4.5V tCDR CE VIH tR VDR VIH 5 DID F11-20000-*A. 5/29/97 Copyright (c)1997 Alliance Semiconductor. All rights reserved. AS7C1024 AS7C31024 (R) AC test conditions - 5V output load: see Figure B, except as noted see Figure C. - 3.3V output load: see Figure D, except as noted see Figure E. - Input pulse level: GND to 3.0V. See Figure A. - Input rise and fall times: 5 ns. See Figure A. - Input and output timing reference levels: 1.5V. Thevenin equivalent: 168 Dout +1.728V +5V +5V 480 +3.0V GND 480 Dout 90% 10% 90% 255 10% Figure A: Input waveform Dout 255 30 pF* GND Figure B: Output load +3.3V 320 350 320 Dout 30 pF* GND Figure D: Output load *including scope and jig capacitance GND Figure C: Output load for tCLZ, tCHZ, tOLZ, tOHZ, tOW +3.3V Dout 5 pF* 350 5 pF* *including scope and jig capacitance GND Figure C: Output load for tCLZ, tCHZ, tOLZ, tOHZ, tOW Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification. This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, C. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed but not tested. WE is HIGH for read cycle. CE1 and OE are LOW and CE2 is HIGH for read cycle. Address valid prior to or coincident with CE transition LOW. All read cycle timings are referenced from the last valid address to the first transitioning address. CE1 or WE must be HIGH or CE2 LOW during address transitions. All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. This data applicable to the AS7C1024. The AS7C31024 functions similarly. 2V data retention applies to commercial tempoerature operating range only. 6 DID F11-20000-*A. 5/29/97 Copyright (c)1997 Alliance Semiconductor. All rights reserved. AS7C1024 AS7C31024 (R) Typical DC and AC characteristics 1.4 1.0 0.8 0.6 ISB 0.4 0.2 1.5 4.5 5.0 5.5 Supply voltage (V) Normalized access time tAA vs. supply voltage VCC 1.5 Output source current (mA) Normalized access time 0.9 4.5 5.0 5.5 Supply voltage (V) Output source current IOH vs. output voltage VOH 120 100 VCC = 5.0V Ta = 25C 80 60 40 20 0 0.0 1.25 2.5 3.75 Output voltage (V) 5.0 0.2 -10 35 80 125 Ambient temperature (C) Normalized supply current ICC vs. cycle frequency 1/tRC, 1/tWC 1.2 VCC = 5.0V 0.9 VCC = 5.0V Ta = 25C 1.0 0.8 0.6 0.4 0.2 0.0 -10 35 80 125 Ambient temperature (C) 0 25 50 75 Cycle frequency (MHz) 100 Typical access time change tAA vs. output capacitive loading Output sink current IOL vs. output voltage VOL 35 120 30 VCC = 5.0V Ta = 25C 80 60 40 20 0 0.0 1 1.4 1.0 100 5 -55 Normalized access time tAA vs. ambient temperature Ta 1.1 140 VCC = 5.0V 25 -10 35 80 125 Ambient temperature (C) 1.2 0.8 -55 6.0 Output sink current (mA) Normalized access time 1.0 1.3 625 0.04 1.4 Ta = 25C 1.1 140 ISB 0.4 0.0 -55 6.0 1.2 0.8 4.0 0.6 0.2 1.4 1.3 0.8 Normalized ICC 0.0 4.0 ICC 1.0 Normalized supply current ISB1 vs. ambient temperature Ta Normalized ISB1 (log scale) 1.2 ICC Normalized ICC, ISB Normalized ICC, ISB 1.2 Normalized supply current ICC, ISB vs. ambient temperature Ta Change in tAA (ns) 1.4 Normalized supply current ICC, ISB vs. supply voltage VCC VCC = 4.5V 25 20 15 10 5 0 1.25 2.5 3.75 Output voltage (V) 5.0 0 250 500 750 Capacitance (pF) 1000 7 DID F11-20000-*A. 5/29/97 Copyright (c)1997 Alliance Semiconductor. All rights reserved. AS7C1024 AS7C31024 (R) AS7C1024 ordering codes Package \ Access time 10 ns 12 ns AS7C1024-12TPC AS7C31024-12TPC AS7C1024-12PC AS7C31024-12PC AS7C1024-12TJC AS7C31024-12TJC Plastic DIP, 300 mil Plastic DIP, 400 mil AS7C1024-10TJC Plastic SOJ, 300 mil AS7C1024-10JC AS7C1024-12JC AS7C31024-12JC Plastic SOJ, 400 mil AS7C1024-12TC AS7C31024-12TC TSOP 8x20 15 ns AS7C1024-15TPC AS7C31024-15TPC AS7C1024-15PC AS7C31024-15PC AS7C1024-15TJC AS7C31024-15TJC AS7C31024-15TJI AS7C1024-15JC AS7C1024-15JI AS7C31024-15JC AS7C31024-15JI 20 ns AS7C1024-20TPC AS7C31024-20TPC AS7C1024-20PC AS7C31024-20PC AS7C1024-20TJC AS7C31024-20TJC AS7C31024-20TJI AS7C1024-20JC AS7C1024-20JI AS7C31024-20JC AS7C31024-20JI AS7C1024-15TC AS7C31024-15TC AS7C1024-20TC AS7C31024-20TC Shaded areas contain advance information. AS7C1024 part numbering system AS7C SRAM prefix X 1024 Blank 3 = 5V CMOS Device = 3.3V CMOS number -XX X Access time Package: TP =PDIP 300 mil P = TJ = SOJ 300 mil J = T = TSOP 8x20 PDIP 400 mil SOJ 400 mil X C = Commercial temperature range, 0C to 70 C I = Industrial temperature range, -40C to 85C 8 DID F11-20000-*A. 5/29/97 Copyright (c)1997 Alliance Semiconductor. All rights reserved. AS7C1024 AS7C31024 (R) Representatives and sales offices DOMESTIC REPS INDIANA ALABAMA CC Electro Sales Concord Component Reps Madison, AL (205) 772-8883 Indianapolis, IN (317) 921-5000 Phoenix, AZ (602) 944-9542 Raytown, MO (816) 358-8100 KENTUCKY ARKANSAS CC Electro Sales Southern States Marketing Richardson, TX (214) 238-7500 Indianapolis, IN (317) 921-5000 North: Brooks Technical Group Southern States Marketing Centaur North Inc. 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The company cannot assume responsibility for circuits shown or represent that they are free from patent infringement. Alliance products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Alliance. ProMotion(R) and the Alliance logo are registered trademarks of Alliance Semiconductor Corporation. All other trademarks are property of their respective holders. ALLIANCE SEMICONDUCTOR 3099 North First Street Printed in U.S.A. San Jose, CA 95134 Tel (408) 383-4900 Fax (408) 383-4999 Copyright (c) 1997 All rights reserved. BBS: (408) 383-4994 www.alsc.com May 1997