ALLIANCE SEMICONDUCTOR
1
HHiiggh h PPeerrffoorrmmaannccee
128128KK××88
CCMMOOS S SSRRAAMM
AASS77CC10241024
AASS77CC3102431024
®
121288KK××8 8 CCMMOOS S SSRRAAMM
DID 11 - 20000-*A. 5/29/97 Copyright ©1997 Alliance Se mico nducto r. All rights reserved.
Features
• Organization: 131,072 words × 8 bits
• High speed
- 10/12/15/20 ns address access time
- 3/3/4/5 ns output enable access time
• Low power consumption
- Active: 660 mW max (15 ns cycle)
- Standby:55 mW max, CMOS I/O
- Very low DC component in active power
• 2.0V data retention
• Equal access and cycle times
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
-300 mil PDIP and SOJ
Socket compatible with 7C512 (64K×8)
-400 mil PDIP and SOJ
- 8×20 TSOP
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• 3.3V and 5.0V versions available
• Industrial and commercial temperature available
Logic block diagram
512×256×8
Array
(1,048,576)
Sense amp
I nput buffer
A10
A11
A12
A13
A14
A15
A16
I/O0
I/O7
OE
CE1
WE
Column decoder
Row deco der
Control
circuit
A9
A0
A1
A2
A3
A4
A5
A6
A7
Vcc
GND
A8
CE2
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
AS7C1024
DIP, SOJ
Vcc
A15
CE2
WE
A13
A8
A9
A11 OE
A10
CE1
I/O7
I/O6
I/O5
NC
A16
A14
A12
A7
A6
A5
A4 A3
A2
A1
A0
I/O0
I/O1
TSO P 8×2 0
I/O2
GND
I/O4
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
AS7C1024
20
19
15
16 18
17
Selection guide
Shaded areas contain advance information.
7C1024-10
–
7C1024-12
7C31024-12
7C1024-15
7C31024-15
7C1024-20
7C31024-20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 3345ns
Maximum operating current AS7C1024 175 160 120 110 mA
AS7C31024 – 100 70 65 mA
Maximum CMOS standby current 10.0 10.0 10.0 10.0 mA
AS7C1024
AS7C31024
2
®®
DID F11-20 00 0-*A. 5/2 9/ 9 7 Copyright ©1997 Alliance Semiconductor. All r ights r e ser ved .
Functional description
The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memories (SRAM) organized as 131,072
words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for
high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank memory
systems.
When CE1 is HIGH or CE2 is LOW the device enters standby mode. The standard AS7C1024 is guaranteed not to exceed 55 mW power
consumption in standby mode. Both devices offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written
on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) HIGH. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL/LVTTL-compatible, and operation is from a single 5V supply (AS7C1024) or 3.3V supply (AS7C31024).
The AS7C1024 and AS7C31024 are packaged in common industry standard packages.
Absolute maximum ratings
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don’t Care, L = LOW, H = HIGH
Recommended operating conditions
†VIL min = –3.0V for pulse width less than tRC/2.
Parameter Symbol Min Max Unit
Voltage on any pin relative to GND Vt–0.5 +7.0 V
Power dissipation PD–1.0W
Storage temperature (plastic) Tstg –55 +150 oC
Temperature under bias Tbias –10 +85 oC
DC output current Iout –20mA
CE1 CE2 WE OE Data Mode
HXXXHigh Z Standby (I
SB, ISB1)
XLXXHigh Z Standby (I
SB, ISB1)
L H H H High Z Output disable
LHHLD
out Read
LHLXD
in Write
Parameter Symbol Min Nominal Max Unit
Supply voltage
AS7C1024 VCC 4.5 5.0 5.5 V
AS7C31024 VCC 3.0 3.3 3.6 V
GND 0.0 0.0 0.0 V
Input voltage
AS7C1024 VIH 2.2 – VCC + 0.5 V
AS7C31024 VIH 2.0 – VCC + 0.5 V
VIL –0.5 – 0.8 V
AS7C1024
AS7C31024
3
®®
DID F11-20000-*A. 5/29/97 Copyright ©1997 Alliance Semiconductor. All rights reserve d.
DC operating characteristics 1
Shaded areas contain advance information.
Capacitance 2(f = 1 MHz, Ta = Room temperature, VCC = 5V)
Read cycle 3,9,12
Parameter Symbol Test conditions
-10 -12 -15 -20
UnitMin Max Min Max Min Max Min Max
Input leakage
current | ILI | VCC = Max,
Vin = GND to VCC –1–1–1–1µ
A
Output leakage
current | ILO | CE1 = VIH or CE2 = VIL,
VCC = Max,
Vout = GND to VCC
–1–1–1–1µ
A
Operating power
supply current ICC CE1 = VIL, CE2 = VIH,
f = fmax, Iout = 0 mA
AS7C1024 – 175 – 160 – 120 – 110 mA
AS7C31024 – – – 100 – 70 – 65 mA
Standby
power supply
current
ISB CE1 = VIH or CE2 = VIL,
f = fmax
–55 – 50 – 40 – 40 mA
ISB1
CE1 ≥ VCC–0.2V or CE2 ≤0.2V,
V in ≤ 0.2V or Vin ≥ VCC–0.2V,
f = 0
–10 – 10 – 10 – 10 mA
Output voltage VOL IOL = 8 mA, VCC = Min – 0.4–0.4–0.4–0.4 V
V
OH IOH = –4 mA, VCC = Min 2.4 –2.4–2.4–2.4– V
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CE1, CE2, WE, OE Vin = 0V 5 pF
I/O capacitance CI/O I/O Vin = Vout = 0V 7 pF
Parameter Symbol
-10-12-15-20
Unit Notes
Min Max Min Max Min Max Min Max
Read cycle time tRC 10 –12–15–20– ns
Address access time tAA –10 – 12 – 15 – 20 ns 3
Chip enable (CE1) access time tACE1 –10 – 12 – 15 – 20 ns 3, 12
Chip enable (CE2) access time tACE2 –10 – 12 – 15 – 20 ns 3, 12
Output enable (OE) access time tOE –3–3–4–5 ns
Output hold from address change tOH 2–3–3–3– ns 5
CE1 LOW to output in Low Z tCLZ1 3–3–3–3– ns4, 5, 12
CE2 HIGH to output in Low Z tCLZ2 3–3–3–3– ns4, 5, 12
CE1 HIGH to output in High Z tCHZ1 –3–3–4–5 ns4, 5, 12
CE2 LOW to output in High Z tCHZ2 –3–3–4–5 ns4, 5, 12
OE LOW to output in Low Z tOLZ 0–0–0–0– ns 4, 5
OE HIGH to output in High Z tOHZ –3–3–4–5 ns 4, 5
Power up time tPU 0–0–0–0– ns4, 5, 12
Power down time tPD –10 – 12 – 15 – 20 ns 4, 5, 12
AS7C1024
AS7C31024
4
®®
DID F11-20 00 0-*A. 5/2 9/ 9 7 Copyright ©1997 Alliance Semiconductor. All r ights r e ser ved .
Key to switching waveforms
Read waveform 1 3,6,7,9,12 Address controlled
Read waveform 2 3,6,8,9,12 CE1 and CE2 controlled
Write cycle 11 , 12
Shaded areas contain advance information.
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Write cycle time tWC 10 –12–15–20– ns
Chip enable (CE1) to write end tCW1 9–10–12–12– ns 12
Chip enable (CE2) to write end tCW2 9–10–12–12– ns 12
Address setup to write end tAW 9–10–12–12– ns
Address setup time tAS 0–0–0–0– ns 12
Write pulse width tWP 7–8–9–12– ns
Address hold from end of write tAH 0–0–0–0– ns
Data valid to write end tDW 6–6–9–10– ns
Data hold time tDH 0–0–0–0– ns 4, 5
Write enable to output in High Z tWZ –5–5–5–5 ns 4, 5
Output active from write end tOW 3–3–3–3– ns 4, 5
Undefined output/don’t careFalling inputRising input
Address
Dout Data valid
tOH
tAA
tRC
supply
Current
CE2
OE
Dout
tOE
tOLZ
tACE1, tACE2 tCHZ1, tCHZ2
tCLZ1, tCLZ2
tPU
tPD ICC
ISB
50% 50%
tOHZ
Data valid
tRC1
CE1
AS7C1024
AS7C31024
5
®®
DID F11-20000-*A. 5/29/97 Copyright ©1997 Alliance Semiconductor. All rights reserve d.
Write waveform 1 10,11,12 WE controlled
Write waveform 2 10,11,12 CE1 and CE2 controlled
Data retention characteristics 14
Data retention waveform
Parameter Symbol Test conditions Min Max Unit
VCC for data retention VDR VCC = 2.0V
CE1 ≥ VCC–0.2V or
CE2 ≤ 0.2V
Vin ≥ VCC–0.2V or
Vin ≤ 0.2V
2.0 – V
Data retention current ICCDR –500µA
Chip deselect to data retention time tCDR 0–ns
Operation recovery time tRtRC –ns
Input leakage current | ILI | –1µA
t
AW tAH
tWC
Address
WE
Dout
tDH
tOW
tDW
tWZ
tWP
tAS
Data valid
Din
tAW
Address
CE1
WE
Dout
tCW1, tCW2
tWP
tDW tDH
tAH
tWZ
tWC
tAS
CE2
Data validDin
VCC
CE
tR
tCDR
Data retention mode
4.5V 4.5V
VDR ≥ 2.0V
VIH VIH
VDR
AS7C1024
AS7C31024
6
®®
DID F11-20 00 0-*A. 5/2 9/ 9 7 Copyright ©1997 Alliance Semiconductor. All r ights r e ser ved .
AC test conditions
Notes
1During V
CC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.
2 This parameter is sampled and not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, C.
4t
CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed but not tested.
6WE
is HIGH for read cycle.
7CE1
and OE are LOW and CE2 is HIGH for read cycle.
8 Address valid prior to or coincident with CE transition LOW.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE1 or WE must be HIGH or CE2 LOW during address transitions.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 This data applicable to the AS7C1024. The AS7C31024 functions similarly.
14 2V data retention applies to commercial tempoerature operating range only.
255Ω
– 5V output load: see Figure B,
except as noted see Figure C.
– 3.3V output load: see Figure D,
except as noted see Figure E.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 5 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
5 pF*
480Ω
Dout
GND
+5V
168Ω
Thevenin equivalent:
Dout +1.728V
Figure C: Ou tp u t lo ad for tCLZ, tCHZ, tOLZ, tOHZ, tOW
255Ω30 pF*
480Ω
Dout
GND
+5V
Fi gure B: Output lo ad
*including sc ope
10%
90%
10%
90%
GND
+3.0V
Figure A: Input waveform
and jig capacitance
350Ω5 pF*
320Ω
Dout
GND
+3.3V
350Ω30 pF*
320Ω
Dout
GND
+3.3V
Figure D: Outp ut load
*including sc ope
and jig capacitance
Figure C: Ou tp u t lo ad for tCLZ, tCHZ, tOLZ, tOHZ, tOW
AS7C1024
AS7C31024
7
®®
DID F11-20000-*A. 5/29/97 Copyright ©1997 Alliance Semiconductor. All rights reserve d.
Typical DC and AC characteristics
Supply voltage (V)
4.0 5.5 6.0
5.04.5
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized ICC, ISB
Normalized supply current ICC, ISB
Ambient temperature (°C)
–55 80 125
35–10
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized ICC, ISB
Normalized supply current ICC, ISB
vs. ambient temperature Ta
vs. supply voltage VCC
ICC
ISB
ICC
ISB
Ambient temperature (°C)
-55 80 125
35-10
0.2
1
0.04
5
25
625
Normalized ISB1 (log scale)
Normalized supply current ISB1
vs. ambient temperature Ta
VCC = 5.0V
Supply voltage (V)
4.0 5.5 6.0
5.04.5
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time tAA
Ambient temperature (°C)
–55 80 125
35–10
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time tAA
Cycle frequency (MHz)
075
100
5025
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized ICC
Normalized supply current ICC
vs. ambient temperature Tavs. cycle frequency 1/tRC, 1/tWC
vs. supply voltage VCC
VCC = 5.0V
Ta = 25°C
VCC = 5.0VTa = 25°C
Output voltage (V)
0.0 3.75 5.0
2.51.25
0
20
60
80
40
100
120
140
Output source current (mA)
Output source current IOH
Output voltage (V)
0.0 3.75 5.0
2.51.25
Output sink current (mA)
Output sink current IOL
vs. output voltage VOL
vs. output voltage VOH
0
20
60
80
40
100
120
140
VCC = 5.0V
Ta = 25°C
VCC = 5.0V
Ta = 25°C
Capacitance (pF)
0750
1000
500250
0
5
15
20
10
25
30
35
Change in tAA (ns)
Typical access time change ∆tAA
vs. output capacitive loading
VCC = 4.5V
AS7C1024
AS7C31024
8
®®
DID F11-20 00 0-*A. 5/2 9/ 9 7 Copyright ©1997 Alliance Semiconductor. All r ights r e ser ved .
AS7C1024 ordering codes
Shaded areas contain advance information.
AS7C1024 part numbering system
Package \ Access time 10 ns 12 ns 15 ns 20 ns
Plastic DIP, 300 mil AS7C1024-12TPC
AS7C31024-12TPC
AS7C1024-15TPC
AS7C31024-15TPC
AS7C1024-20TPC
AS7C31024-20TPC
Plastic DIP, 400 mil AS7C1024-12PC
AS7C31024-12PC
AS7C1024-15PC
AS7C31024-15PC
AS7C1024-20PC
AS7C31024-20PC
Plastic SOJ, 300 mil
AS7C1024-10TJC AS7C1024-12TJC AS7C1024-15TJC
AS7C31024-15TJC
AS7C31024-15TJI
AS7C1024-20TJC
AS7C31024-20TJC
AS7C31024-20TJI
AS7C31024-12TJC
Plastic SOJ, 400 mil
AS7C1024-10JC AS7C1024-12JC AS7C1024-15JC
AS7C1024-15JI
AS7C31024-15JC
AS7C31024-15JI
AS7C1024-20JC
AS7C1024-20JI
AS7C31024-20JC
AS7C31024-20JI
AS7C31024-12JC
TSOP 8×20 AS7C1024-12TC AS7C1024-15TC
AS7C31024-15TC
AS7C1024-20TC
AS7C31024-20TC
AS7C31024-12TC
AS7C X 1024 –XX X X
SRAM
prefix
Blank = 5V CMOS
3 = 3.3V CMOS
Device
number
Access
time
Package: TP =PDIP 300 mil P = PDIP 400 mil
TJ = SOJ 300 mil J = SOJ 400 mil
T = TSOP 8×20
C = Commercial temperature
range, 0°C to 70 °C
I = Industrial temperature range,
-40°C to 85°C
AS7C1024
AS7C31024
Alliance Semiconductor reserves the right to make changes in this data sheet at any time to improve design and supply the best product possible. Publication of advance information does not constitute a
committment to produce or supply the product described. The company cannot assume responsibility for circuits shown or represent that they are free from patent infringement. Alliance products are not
authorized for use as critical components in life support devices or systems without the express written approval of the president of Alliance. ProMotion® and the Alliance logo are registered trademarks of
Alliance Semiconductor Corporation. All other trademarks are property of their respective holders.
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Printed in U.S.A. Copyright © 1997 All rights reserved. May 1997
®®
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+44-1932 346256
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+49-894488496
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+33-1-69387678
DataTech
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+49-89-89470030
interACTIVE
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+44-1332-668665
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Eastele Technology, Ltd.
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Excelpoint
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(408) 954-1866
Satcom Sales and Services
Hyderabad
+91-40-761-4675
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Eldis Technologies
Herzlia
+9729-9-562-666
JAPAN
Bussan Micro Electronics Corp.
Shinagawa-ku, Tokyo
+81-3-5421-1730
Rohm Corporation
Kyoto
+81-75-315-4152
KOREA
FM Korea
Seoul
+822-596-3880
fm@ktnet.co.kr
Woo Young Tech Co., Ltd.
Seoul
+822-369-7099
MALAYSIA
Excelpoint
+60-4-6413218
Exertec Pte Ltd.
Gelugor, Penang
+60-4-657-9592
SINGAPORE
Excelpoint
+65-741-8966
Exertec Pte Ltd.
+65-749-1349
TAI WAN
ASTL
Taipei, Tai wan R .O.C.
+886-2-521-2363
Golden Way
Taipei-Hsien Taiwan R.O.C.
+886-2-698-1868 x505
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Taipei, Tai wan R .O.C.
+886-2-729-0373
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