1. General description
The 74HC595; 74HCT595 ar e hig h-sp eed Si-g ate CMOS d evices and ar e pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard No. 7A.
The 74HC595; 74HCT595 are 8-stage serial shift registers with a storage register and
3-state outputs. The registers have separate clocks.
Data is shifted on the positive-going transitions of the shift register clock input (SHCP).
The data in each register is transferred to the storage register on a positive-going
transition of the storage register clo ck input (STCP). If both clocks are connected together,
the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.
It is also provided with asynchronou s reset (acti ve LOW) for all 8 shif t register st ages. The
storage register has 8 parallel 3-state bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW.
2. Features and benefits
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceed s 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Serial-to-parallel data conversion
Remote control holding register
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Rev. 6 — 12 December 2011 Product data sheet
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 2 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperatu re range Name Description Version
74HC595N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT595N
74HC595D 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74HCT595D
74HC595DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74HCT595DB
74HC595PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74HCT595PW
74HC595BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
74HCT595BQ
Fig 1. Functional di agram
mna554
3-STATE OUTPUTS
8-BIT STORAGE REGISTER
8-STAGE SHIFT REGISTER
Q0Q1Q2Q3Q4Q5Q6Q7
Q7S
14
151234567
9
DS
SHCP
STCP
OE
11
10
12
13
MR
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 3 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Fig 2. Logic symbol Fig 3. IEC logic symbol
OEMR
9
15
1
2
3
4
5
6
7
1310
14
11 12
mna552
Q1
Q0
Q2
Q3
Q4
Q5
Q6
Q7
Q7S
DS
STCP
SHCP
mna553
15
9
1
2
3
4
5
6
7
1D 2D
C1/
10
11
14
C2
12
13 EN3
SRG8
R
3
Fig 4. Logic diag ram
STAGE 0 STAGES 1 TO 6 STAGE 7
FF0
D
CP
Q
R
LATCH
D
CP
Q
FF7
D
CP
Q
R
LATCH
D
CP
Q
mna555
DQ
Q1Q2Q3Q4Q5Q6Q7
Q7S
Q0
DS
STCP
SHCP
OE
MR
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 4 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
6. Pinning information
6.1 Pinning
Fig 5. Pin configuration DIP16, SO16 Fig 6. Pin configuration SSOP16, TSSOP16
74HC595
74HCT595
Q1 VCC
Q2 Q0
Q3 DS
Q4 OE
Q5 STCP
Q6 SHCP
Q7 MR
GND Q7S
001aao241
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
74HC595
74HCT595
Q1 VCC
Q2 Q0
Q3 DS
Q4 OE
Q5 STCP
Q6 SHCP
Q7 MR
GND Q7S
001aao242
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 7. Pin configuration for DHVQFN16
001aao243
74HC595
74HCT595
Q7 MR
Q6 SHCP
Q5 STCP
Q4 OE
Q3 DS
Q2 Q0
GND
Q7S
Q1
VCC
Transparent top view
710
611
512
413
314
215
8
9
1
16
terminal 1
index area
GND(1)
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 5 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
6.2 Pin description
7. Functional description
[1] H = HIGH voltage state;
L = LOW voltage state;
= LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
Table 2. Pin description
Symbol Pin Description
Q1 1 parallel data output 1
Q2 2 parallel data output 2
Q3 3 parallel data output 3
Q4 4 parallel data output 4
Q5 5 parallel data output 5
Q6 6 parallel data output 6
Q7 7 parallel data output 7
GND 8 ground (0 V)
Q7S 9 serial data output
MR 10 master reset (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input
OE 13 output enable input (active LOW)
DS 14 serial data input
Q0 15 parallel data output 0
VCC 16 supply voltage
Table 3. Function table[1]
Control Input Output Function
SHCP STCP OE MR DS Q7S Qn
X X L L X L NC a LOW-level on MR only affects the shift registers
XL L X L L empty shift register loaded into storage register
X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state
X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
XL H X NC QnS contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
L H X Q6S QnS contents of shift register sh ifted through ; pre vi o us contents of the
shift register is transferred to the storage register and the parallel
output stages
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 6 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
8. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[3] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
[4] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
Fig 8. Timing diagram
SHCP
DS
STCP
MR
OE
Q0
Q1
Q6
Q7
Q7S
Z-state
Z-state
Z-state
Z-state
mna556
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC + 0.5 V - 20 mA
IOK output clamping current VO<0.5 V or VO > VCC + 0.5 V - 20 mA
IOoutput current VO=0.5 V to (VCC +0.5V)
pin Q7S - 25 mA
pins Qn - 35 mA
ICC supply current - 70 mA
IGND ground current 70 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation
DIP16 package [1] - 750 mW
SO16 package [2] - 500 mW
SSOP16 package [3] - 500 mW
TSSOP16 package [3] - 500 mW
DHVQFN16 package [4] - 500 mW
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 7 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
9. Recommended operating conditions
10. Static characteristics
Table 5. Recommended operating con ditions
Symbol Parameter Conditions 74HC595 74HCT595 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
t/V input transition rise and
fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max
74HC595
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
all outputs
IO=20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - V
IO=20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - V
IO=20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - V
Q7S output
IO=4mA; V
CC = 4.5 V 3.84 4.32 - 3.7 - V
IO=5.2 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V
Qn bus driver outputs
IO=6mA; V
CC = 4.5 V 3.84 4.32 - 3.7 - V
IO=7.8 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 8 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
VOL LOW-level
output voltage VI=V
IH or VIL
all outputs
IO=20A; VCC = 2.0 V - 0 0.1 - 0.1 V
IO=20A; VCC = 4.5 V - 0 0.1 - 0.1 V
IO=20A; VCC = 6.0 V - 0 0.1 - 0.1 V
Q7S output
IO=4mA; V
CC = 4.5 V - 0.15 0.33 - 0.4 V
IO=5.2mA; V
CC = 6.0 V - 0.16 0.33 - 0.4 V
Qn bus driver outputs
IO=6mA; V
CC = 4.5 V - 0.15 0.33 - 0.4 V
IO=7.8mA; V
CC = 6.0 V - 0.16 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND; VCC =6.0V - - 1.0 - 1.0 A
IOZ OFF-state
output current VI=V
IH or VIL; VCC =6.0V;
VO=V
CC or GND --5.0 - 10 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V - - 80 - 160 A
CIinput
capacitance -3.5- - -pF
74HCT595
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL; VCC =4.5V
all outputs
IO=20 A 4.4 4.5 - 4.4 - V
Q7S output
IO=4 mA 3.84 4.32 - 3.7 - V
Qn bus driver outputs
IO=6 mA 3.7 4.32 - 3.7 - V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC =4.5V
all outputs
IO=20A - 0 0.1 - 0.1 V
Q7S output
IO= 4.0 mA - 0.15 0.33 - 0.4 V
Qn bus driver outputs
IO= 6.0 mA - 0.16 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND; VCC =5.5V - - 1.0 - 1.0 A
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 9 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
IOZ OFF-state
output current VI=V
IH or VIL; VCC =5.5 V;
VO=V
CC or GND --5.0 - 10 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V - - 80 - 160 A
ICC additional
supply current per input pin; IO=0A; V
I=V
CC
2.1 V; other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
pins MR, SHCP, STCP, OE - 150 675 - 735 A
pin DS - 25 113 - 123 A
CIinput
capacitance -3.5- - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 10 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
74HC595
tpd propagation
delay SHCP to Q7S; see Figure 9 [2]
VCC = 2 V - 52 160 - 200 - 240 ns
VCC = 4.5 V - 19 32 - 40 - 48 ns
VCC = 6 V - 15 27 - 34 - 41 ns
STCP to Qn; see Figure 10 [2]
VCC = 2 V - 55 175 - 220 - 265 ns
VCC = 4.5 V - 20 35 - 44 - 53 ns
VCC = 6 V - 16 30 - 37 - 45 ns
MR to Q7S; see Figure 12 [3]
VCC = 2 V - 47 175 - 220 - 265 ns
VCC = 4.5 V - 17 35 - 44 - 53 ns
VCC = 6 V - 14 30 - 37 - 45 ns
ten enable time OE to Qn; see Figure 13 [4]
VCC = 2 V - 47 150 - 190 - 225 ns
VCC = 4.5 V - 17 30 - 38 - 45 ns
VCC = 6 V - 14 26 - 33 - 38 ns
tdis disable time OE to Qn; see Figure 13 [5]
VCC = 2 V - 41 150 - 190 - 225 ns
VCC = 4.5 V - 15 30 - 38 - 45 ns
VCC = 6 V - 12 27 - 33 - 38 ns
tWpulse width SHCP HIGH or LOW;
see Figure 9
VCC = 2 V 75 17 - 95 - 110 - ns
VCC = 4.5 V 15 6 - 19 - 22 - ns
VCC = 6 V 13 5 - 16 - 19 - ns
STCP HIGH or LOW;
see Figure 10
VCC = 2 V 75 11 - 9 5 - 110 - ns
VCC = 4.5 V 15 4 - 19 - 22 - ns
VCC = 6 V 13 3 - 16 - 19 - ns
MR LOW; see Figure 12
VCC = 2 V 75 17 - 95 - 110 - ns
VCC = 4.5 V 15 6 - 19 - 22 - ns
VCC = 6 V 13 5 - 16 - 19 - ns
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 11 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
tsu set-up time DS to SHCP; see Figure 10
VCC = 2 V 50 11 - 6 5 - 75 - ns
VCC = 4.5 V 10 4 - 13 - 15 - ns
VCC = 6 V 9 3 - 11 - 13 - ns
SHCP to STCP;
see Figure 11
VCC = 2 V 75 22 - 95 - 110 - ns
VCC = 4.5 V 15 8 - 19 - 22 - ns
VCC = 6 V 13 7 - 16 - 19 - ns
thhold time DS to SHCP; see Figure 11
VCC = 2 V 3 6- 3 - 3 - ns
VCC = 4.5 V 3 2- 3 - 3 - ns
VCC = 6 V 3 2- 3 - 3 - ns
trec recovery
time MR to SHCP; see Figure 12
VCC = 2 V 50 19 - 65 - 75 - ns
VCC = 4.5 V 10 7- 13 - 15 - ns
VCC = 6 V 9 6- 11 - 13 - ns
fmax maximum
frequency SHCP or STCP;
see Figure 9 and 10
VCC = 2 V 9 30 - 4.8 - 4 - MHz
VCC = 4.5 V 30 91 - 24 - 20 - MHz
VCC = 6 V 35 108 - 2 8 - 24 - MHz
CPD power
dissipation
capacitance
fi = 1 MHz; VI=GNDtoV
CC [6][7] -115- - - - - pF
74HCT595; VCC = 4.5 V to 5.5 V
tpd propagation
delay SHCP to Q7S; see Figure 9 [2] -2542- 53 - 63ns
STCP to Qn; see Figure 10 [2] -2440- 50 - 60ns
MR to Q7S; see Figure 12 [3] -2340- 50 - 60ns
ten enable time OE to Qn; see Figure 13 [4] -2135- 44 - 53ns
tdis disable time OE to Qn; see Figure 13 [5] -1830- 38 - 45ns
tWpulse width SHCP HIGH or LOW;
see Figure 9 16 6 - 20 - 24 - ns
STCP HIGH or LOW;
see Figure 10 16 5 - 20 - 24 - ns
MR LOW; see Figure 12 20 8 - 25 - 30 - ns
tsu set-up time DS to SHCP; see Figure 10 16 5 - 20 - 24 - ns
SHCP to STCP;
see Figure 11 16 8 - 20 - 24 - ns
thhold time DS to SHCP; see Figure 11 32- 3 - 3 - ns
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 12 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
[1] Typical values are measured at nominal supply voltage.
[2] tpd is the same as tPHL and tPLH.
[3] tpd is the same as tPHL only.
[4] ten is the same as tPZL and tPZH.
[5] tdis is the same as tPLZ and tPHZ.
[6] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fi+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
(CLVCC2fo) = sum of outputs;
CL= output load capacitance in pF;
VCC = supply voltage in V.
[7] All 9 outputs switching.
12. Waveforms
trec recovery
time MR to SHCP; see Figure 12 10 7- 13 - 15 - ns
fmax maximum
frequency SHCP and STCP;
see Figure 9 and 10 30 52 - 24 - 20 - MHz
CPD power
dissipation
capacitance
fi = 1 MHz; VI=GNDtoV
CC [6]
[7] - 130 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9. Shift clock pulse, maximum frequency and input to output propagation delays
mna557
SHCP input
Q7S output
tPLH tPHL
tW
1/fmax
VM
VOH
VI
GND
VOL
VM
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 13 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. Storage clock to output propagation delays
mna558
STCP input
Qn output
tPLH tPHL
tW
tsu 1/fmax
VM
VOH
VI
GND
VOL
VM
SHCP input
VI
GND
VM
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. Data s et-u p an d hold times
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 14 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. Master reset to output prop agation delays
mna561
MR input
SHCP input
Q7S output
t
PHL
t
W
t
rec
V
M
V
OH
V
OL
V
I
GND
V
I
GND
V
M
V
M
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 13. Enable and disa ble times
msa697
tPLZ
tPHZ
outputs
disabled outputs
enabled
90 %
10 %
outputs
enabled
OE input VM
tPZL
tPZH
VM
VM
Qn output
LOW-to-OFF
OFF-to-LOW
Qn output
HIGH-to-OFF
OFF-to-HIGH
trtf
90 %
10 %
Table 8. Measurement points
Type Input Output
VMVM
74HC595 0.5VCC 0.5VCC
74HCT595 1.3 V 1.3 V
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 15 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Test data is given in Table 9.
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
S1 = test selection switch.
Fig 14. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
VIVO
RT
RLS1
CL
open
G
Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC595 VCC 6 ns 50 pF 1 kopen GND VCC
74HCT595 3 V 6 ns 50 pF 1 kopen GND VCC
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Product data sheet Rev. 6 — 12 December 2011 16 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
13. Package outline
Fig 15. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT38-4 95-01-14
03-02-13
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT A
max. 12 b1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 0.764.2 0.51 3.2
inches 0.068
0.051 0.021
0.015 0.014
0.009
1.25
0.85
0.049
0.033 0.77
0.73 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.030.17 0.02 0.13
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 17 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Fig 16. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 18 of 24
NXP Semiconductors 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Fig 17. Package outline SOT338-1 (SSOP16)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25
7.9
7.6 1.03
0.63 0.9
0.7 1.00
0.55 8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
A
max.
2