PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to h elp you evaluate t his product. AMD reserves t he right to cha nge or discontinue work o n this proposed
product without notice.
Publication# 20002 Re v: BAmendment/0
Issue Date: February 1997
Am186TMES/ESLV and Am188TM ES/ESLV
High Performance, 80C186-/80C188-Compatible and
80L186-/80L188-Compatib le, 16-Bit Embedded Microcontrollers
DISTINCTIVE CHARACTERISTICS
nE86 family 80C186-/188- and 80L186-/188-
compatible microcontrollers with enhanced bus
interface
— Lower system cost with higher performance
— 3.3-V ±0.3-V operation (Am186ESLV and
Am188ESLV microcontrollers)
nHigh performance
— 20-, 25-, 33-, and 40-MHz operating frequencies
— Supports zero-wait-state operation at 25 MHz
with 100-ns static memory (Am186ESLV and
Am188ESLV microcontrollers) and 40 MHz with
70-ns static memory (Am186ES and Am188ES
microcontrollers)
— 1-Mbyte memory address space
— 64-Kbyte I/O space
nEnhanced features provide improved memory
access and remove the requirement for a 2x clock
input
— Nonmultiplexed address bus
— Processor operates at the clock input frequency
— On the Am186ES/ESLV microc ontroller, 8-bit or
16-bit memory and I/O static bus option
nEnhanced integrated peripherals provide
increased functionality, while reducing system
cost
— Thirty-two programmable I/O (PIO) pins
— Two full-featured asynchronous serial ports allow
full-duplex, 7-bit, 8-bit, or 9-bit data transfers
— Serial port hardware handshaking with CTS,
RTS, ENRX, and RTR selectab le for each port
— Multidrop 9-bit serial port protocol
— Independent serial port baud rate generators
— DMA to and from the serial ports
— Watchdog timer can generate NMI or reset
— A pulse-width demodulation option
— A data strobe, true asynchronous bus interface
option included for DEN
— Pseudo static RAM (PSRAM) controller includes
auto refresh capability
— Reset configuration register
nFamiliar 80C186/80L186 peripherals
— Two independent DMA channels
— Programmable interrupt controller with up to
eight external and eight internal interrupts
— Three programmable 16-bit timers
— Programmable memory and peripheral
chip-select logic
— Programmable wait state generator
— Power - sa ve cloc k div id e r
nSoftware-compatible with the 80C186/80L186
and 80C188/80L188 microcontrollers with widely
available native development tools,
applications, and system software
nA compatible evolution of the Am186EM and
Am188EM microcontrollers
nAvailable in the following packages:
— 100-pin, thin quad flat pack (TQFP)
— 100-pin, plastic quad flat pack (PQFP)
GENERAL DESCRIPTION
The Am186ES/ESLV and Am188ES/ESLV
microcontrollers are an ideal upgrade for 80C186/188 and
80L186/188 microcontroller designs requiring 80C186/188
and 80L1 86/188 compatibility, increased p erformance,
serial communications, and a direct bus interface.
The Am186ES/ESLV and Am188ES/ESLV microcontrollers
are part of the AMD E86 family of embedded
microcon trollers a nd micropr ocessors bas ed on the x8 6
ar chi tecture . The E86 fa mil y inc lud es th e 16- and 32-bit
microcontrollers and microprocessors described on page 8.
The Am186ES/ESLV and Am188ES/ESLV
microcon trollers have been des igned to m eet the mos t
common requirements of embedded products
developed for the office automation, mass storage, and
commu nications markets. Spec ific applic ations incl ude
disk drives, hand-held and desktop terminals, set-top
controllers, fax machines, printers, photocopiers,
feature phones, cellular phones, PBXs, multiplexers,
modems, and industrial controls.
2 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Am186ES MICROCONTROLLER BLOCK DIAGRAM
Notes:
*All PIO s ignals are shar ed with other phy sica l pins. See the pin desc ript ions begi nning o n pag e 27 and Tabl e 2 on pa ge 34 for
information on shared functions.
** PWD, INT5, INT 6, RTS1/RTR1, and CTS 1/ENRX1 are multi plexed wit h INT2/INTA 0, DRQ0, DRQ1, PCS3, and PC S2 respec-
tively. See the pin descriptions beginning on page 27.
S2–S0
Interrupt
Control Unit
Timer Control
Unit DMA
Unit
Bus
Interface
Unit
Execution
Unit Chip-Select
Unit
Clock and
Power
Management
Unit
Control
Registers
16-Bit Count
Registers
Max Count A
Registers 16-Bit Count
Registers
20-Bit Destination
Pointers
20-Bit Source
Pointers
Control
Registers
Control
Registers
Control
Registers
01 2 0 1
Max Count B
Registers
Refresh
Control
Unit
Control
Registers Control
Registers Control
Registers
CLKOUTB
CLKOUTA INT6–INT4**
INT3/INTA1/IRQ
INT2/INTA0**
INT1/SELECT
INT0 TMROUT0 TMROUT1
DRQ0** DRQ1**
VCC
GND
TMRIN0 TMRIN1
ARDY
SRDY
DT/R
DEN/DS
HOLD
HLDA
Asynchronous
Serial Port 0
TXD0
RXD0
NMI
A19–A0
AD15–AD0
ALE
BHE/ADEN
WR
WLB
WHB
RD
RES
LCS/ONCE0
MCS2–MCS0
PCS6/A2
PCS3–PCS0**
PCS5/A1
UCS/ONCE1
X2
X1
PSRAM
Control
Unit
MCS3/RFSH
PIO
Unit PIO31–
PIO0*
Control
Registers
S6/LOCK/
UZI
CLKDIV2
TXD1
RXD1
CTS0/ENRX0
CTS1/ENRX1**
RTS0/RTR0
RTS1/RTR1**
Watchdog
Timer (WDT)
Pulse
Width
Demod-
ulator
(PWD)
PWD**
Asynchronous
Serial Port 1
Am186/188ES and Am186/188ESLV Microcontrollers 3
PRELIMINARY
Am188ES MICROCONTROLLER BLOCK DIAGRAM
Notes:
*All PIO s ignals are shar ed with other phy sica l pins. See the pin desc ript ions begi nning o n pag e 27 and Tabl e 2 on pa ge 34 for
information on shared functions.
** PWD, INT5, INT 6, RTS1/RTR1, and CTS 1/ENRX1 are multi plexed wit h INT2/INTA 0, DRQ0, DRQ1, PCS3, and PC S2 respec-
tively. See the pin descriptions beginning on page 27.
Interrupt
Control Unit
Timer Control
Unit DMA
Unit
Bus
Interface
Unit
Execution
Unit Chip-Select
Unit
Clock and
Power
Management
Unit
Control
Registers
16-Bit Count
Registers
Max Count A
Registers 16-Bit Count
Registers
20-Bit Destination
Pointers
20-Bit Source
Pointers
Control
Registers
Control
Registers
Control
Registers
01 2 0 1
Max Count B
Registers
Refresh
Control
Unit
Control
Registers Control
Registers Control
Registers
CLKOUTB
CLKOUTA INT6–INT4**
INT3/INTA1/IRQ
INT2/INTA0**
INT1/SELECT
INT0 TMROUT0 TMROUT1
DRQ0** DRQ1**TMRIN0 TMRIN1
Asynchronous
Serial Port 0
TXD0
RXD0
NMI
A19–A0
AD7–AD0
ALE
RFSH2/ADEN
WR
WB
RD
LCS/ONCE0
MCS2–MCS0
PCS6/A2
PCS3–PCS0**
PCS5/A1
UCS/ONCE1
X2
X1
PSRAM
Control
Unit
MCS3/RFSH
PIO
Unit PIO31–
PIO0*
Control
Registers
TXD1
RXD1
CTS0/ENRX0
CTS1/ENRX1**
RTS0/RTR0
RTS1/RTR1**
Watchdog
Timer (WDT)
Pulse
Width
Demod-
ulator
(PWD)
PWD**
Asynchronous
Serial Port 1
S2–S0
VCC
GND
ARDY
SRDY
DT/R
DEN/DS
HOLD
HLDA
RES
S6/LOCK/
UZI
CLKDIV2
AO15–AO8
4 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a
combination of the elements below.
-40Am186ES
–20 = 20 MHz
–25 = 25 MHz
–33 = 33 MHz
–40 = 40 MHz
C
TEMPERATURE RANGE
C=ES Commercial (TC=0°C to +100°C)
SPEED OPTION
DEVICE NUMBER/DESCRIPTION
\W
LEAD FORMING
\W=Trimmed and Formed
Valid combinations list configurations planned to
be suppo rted in volu me for this device. Consult the
local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
Note: The ind us tria l v ers io n of the Am 186 ES an d
Am188ES microcontrollers, as well as the
Am186ESLV and Am188ESLV, are available in 20
and 25 MHz operating frequencies only.
The Am186ES, Am188ES, Am186ESLV, and
Am188ESLV microcontrollers are all functionally
the same except for their DC characteristics and
available frequencies.
Valid Combinations
PACKAGE TYPE
V=100-Pin Thin Quad Flat Pack (TQFP)
K=100-Pin Plastic Quad Flat Pack (PQFP)
V
where: TC = case temperature
Am186ESLV–25
Valid Combinations
Am188ESLV–25
Am188ESLV–20
Am186ESLV–20
VC\W or
KC\W
Am186ES–25
Am186ES–33
Am186ES–40
Am188ES–25
Am188ES–33
Am188ES–40
VC\W or
KC\W
Am188ES–20
Am186ES–20
KI\W
Am186ES–25
Am188ES–25 KI\W
Am188ES–20
Am186ES–20
VC\W or
KC\W
VC\W or
KC\W
TA = ambi ent temperature
C=ESLV Commercial (TA=0°C to +70°C)
I=ES Industrial (TA=–40°C to +85°C)
Am186ES High-Performance, 80C 1 86-Co mp atib le,
16-Bit Embedded Microcontroller
Am188ES High-Performance, 80C 1 88-Co mp atib le,
16-Bit Embedded Microcontroller
Am186ESLV High-Performance, 80L186-Compatible,
Low-Voltage, 16-Bit Embedded Microcontroller
Am188ESLV High-Performance, 80L188-Compatible,
Low-Voltage, 16-Bit Embedded Microcontroller
Am186/188ES and Am186/188ESLV Microcontrollers 5
PRELIMINARY
TABLE OF CONTENTS
Distinctive Characteristics ............................................................................................................ 1
General Description ..................................................................................................................... 1
Am186ES Microcontroller Block Diagram..................................................................................... 2
Am188ES Microcontroller Block Diagram..................................................................................... 3
Ordering Information .................................................................................................................... 4
Related AMD Products ................................................................................................................ 8
Key Features and Benefits ........................................................................................................ 10
Comparing the ES to the 80C186 .............................................................................................. 11
Comparing the ES to the EM ..................................................................................................... 11
TQFP Connection Diagra ms and Pinouts .............. ............................................. .. ......... .. .......... 13
PQFP Connection Diagrams and Pinouts ........................ ......... .. .................. .. .................. .. ...... 19
Logic Symbol—Am186ES Microcontroller ................................................................................. 25
Logic Symbol—Am188ES Microcontroller ................................................................................. 26
Pin Descriptions ......................................................................................................................... 27
Pins That Are Used by Emulators .................................................................................. 27
Pin Terminology ............................................................................................................. 27
A19–A0 .......................................................................................................................... 27
AD15–AD8 (Am186ES Microcontroller).......................................................................... 27
AO15–AO8 (Am188ES Microcontroller) .... ........... ......... .. ......... ........... ......... .. ............... 27
AD7–AD0 ....................................................................................................................... 27
ALE ................................................................................................................................ 27
ARDY ............................................................................................................................. 27
BHE/ADEN (Am186ES Microcontroller Only) ................................................................ 28
CLKOUTA ...................................................................................................................... 28
CLKOUTB ...................................................................................................................... 28
CTS0/ENRX0/PIO 21 ............. ................ .................... ............... ................ .................... .. 28
DEN/DS/PIO5 ................................................................................................................ 29
DRQ0/INT5/PIO12 ......................................................................................................... 29
DRQ1/INT6/PIO13 ......................................................................................................... 29
DT/R/PIO4 ..................................................................................................................... 29
GND ............................................................................................................................... 29
HLDA ............................................................................................................................. 29
HOLD ............................................................................................................................. 29
INT0 ............................................................................................................................... 30
INT1/SELECT ................................................................................................................ 30
INT2/INTA0/PWD/PIO31 ............................................................................................... 30
INT3/INTA1/IRQ ... ......... ........ ....... ......... ......... ......... ...... ......... ......... ......... ...... ......... ....... 30
INT4/PIO30 .................................................................................................................... 31
LCS/ONCE0 .... ......... ....... ......... ......... ........ ....... ......... ......... ......... ...... ......... ......... ...... ..... 31
MCS0 (MCS0/PIO14) .................................................................................................... 31
MCS2–MCS1 (MCS2/PIO24, MCS1/PIO15) ................................................................. 31
MCS3/RFSH/PIO25 ....................................................................................................... 31
NMI ................................................................................................................................ 32
PCS1–PCS0 (PCS1/PIO17, PCS0/PIO1 6) ...... ....... ........ ......... ....... ......... ......... ........ ..... 32
PCS2/CTS1/ENRX1/PIO18 ........................................................................................... 32
PCS3/RTS1/RTR1/PIO19 .............................................................................................. 32
PCS5/A1/PIO3 ............................................................................................................... 33
PCS6/A2/PIO2 ............................................................................................................... 33
PIO31–PIO0 (Shared) .......................... .. .. .. .............. .. .. .. .. ............ .. .. .. .. .............. .. .. .. .. .... 33
RD .................................................................................................................................. 35
RES .... ......... ......... ......... ...... ......... ......... ......... ...... ......... ......... ....... ......... ........ ......... ....... 35
RFSH2/ADEN (Am188ES Microcontroller Only) ............................................................ 35
6 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
RTS0/RTR0/PIO20 ........................................................................................................ 35
RXD0/PIO23 .................................................................................................................. 35
RXD1/PIO28 .................................................................................................................. 35
S2–S0 ............................................................................................................................ 35
S6/LOCK/CLKDIV2/PIO 29 ............. ................ ............... .................... ................ ............. 36
SRDY/PIO6 .................................................................................................................... 36
TMRIN0/PIO11 .............................................................................................................. 36
TMRIN1/PIO0 ................................................................................................................ 36
TMROUT0/PIO10 .......................................................................................................... 36
TMROUT1/PIO1 ............................................................................................................ 36
TXD0 /PIO22 .. ....... ......... ........ ......... ....... ......... ......... ...... ......... ......... ......... ...... ......... ....... 36
TXD1 /PIO27 .. ....... ......... ........ ......... ....... ......... ......... ...... ......... ......... ......... ...... ......... ....... 36
UCS/ONCE1 .................................................................................................................. 36
UZI/PIO26 ...................................................................................................................... 37
VCC ................................................................................................................................ 37
WHB (Am 186 E S Mic rocon troll e r On ly ) . .. .. ....... ........... ....... ...... ........... ....... ....... ........... .. 37
WLB (Am186ES Microcontroller Only) ........................................................................... 37
WB (Am188ES Microcontroller Only) ............................................................................. 37
WR ................................................................................................................................. 37
X1 . ...... ....... ...... ..... ...... ....... .... ....... ....... ...... ..... ...... ....... ....... .... ....... ...... ..... ...... ....... ....... .. 37
X2 . ...... ....... ...... ..... ...... ....... .... ....... ....... ...... ..... ...... ....... ....... .... ....... ...... ..... ...... ....... ....... .. 37
Functional Descriptio n.. ........... ......... .. .................. .. .................. .. .................. .. .................. .. ........ 38
Bus Ope ra t io n ..... .. ...... ....... ........... ....... ...... ........... ....... ....... ........... ...... ....... ........... ....... ........... .. 39
Bus Interf ac e Un it . ........... ...... ....... ........... ....... ...... ........... ....... ....... ........... ...... ....... ........... ....... .. 41
Peripheral Control Block (PCB) .................. ............ .. .. .. .. .. .............. .. .. .. ............ .. .. .. .. .. .............. . 42
Clock and Power Management ............... ......... .. .................. .. .................. .. ......... .. .................. .. . 44
Chip-Select Unit ......................................................................................................................... 46
Refresh Control Unit .................................................................................................................. 47
Interrupt Control Unit ................................................................................................................. 48
Timer Control Unit ...................................................................................................................... 48
Direct Memory Access (DMA) ................................................................................................... 49
Pulse Width Demodulation ..................... .. .. ............ .. .. .. .. .. .............. .. .. .. ............ .. .. .. .. .. .............. . 51
Asynchronous Serial Ports ..... ........................... .. .................. .. .................. .. .................. .. .......... 51
Programmable I/O (PIO) Pins .................................................................................................... 52
Absolute Maximum Ratings ....................................................................................................... 53
Operating Ranges .............................. .................. .. .................. .. .................. .. .................. .. ........ 53
DC Characteristics Over Comme rci al Operating Ranges ............... .. .. .. .............. .. .. .. .. ............ .. . 53
Commercial Swit ching Characteristics and Waveforms .............. ........................... .. ................. 61
TQFP Physical Dimensions........................................................................................................ 98
PQFP Physical Dimensions...................................................................................................... 100
Am186/188ES and Am186/188ESLV Microcontrollers 7
PRELIMINARY
LIST OF FIGURES
Figure 1 Am186ES Microcontroller Example System Design .............................................. 10
Figure 2 80C186 Microcontroller Example System Design ................................................. 11
Figure 3 Two-Component Address ...................................................................................... 38
Figure 4 Am186ES Microcontroller Address Bus — Normal Operation................................ 39
Figure 5 Am186ES Microcontroller—Address Bus Disable In Effect ................................... 40
Figure 6 Am188ES Microcontroller Address Bus — Normal Operation ............................... 40
Figure 7 Am188ES Microcontroller— Address Bus Disable In Effect................................... 41
Figure 8 Am186ES and Am188ES Microcontroll ers Oscillator Confi gurations .............. .. .... 44
Figure 9 Clock Organization ................................................................................................ 45
Figure 10 DMA Unit Block Diagram ....................................................................................... 50
Figure 11 Typical Icc Versus Frequency for the Am186ESLV and Am188ESLV ................... 54
Figure 12 Typical Icc Versus Frequency for the Am186ES and Am188ES............................. 54
Figure 13 Thermal Resistance(°C/Watt) ................................................................................ 55
Figure 14 Ther m al Ch a ra c te r istics E q uat io n s ...... .. ........... ...... ............ ...... ....... ........... ...... ..... 55
Figure 15 Typical Ambient Temperatures for PQFP with a 2-Layer Board ............. ........... .... 57
Figure 16 Typical Ambient Temperatures for TQFP with a 2-Layer Boar d ............................ 58
Figure 17 Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board .......... 59
Figure 18 Typical Ambient Temperatures for TQFP with a 4-Layer t o 6-Layer Board ........... 60
LIST OF TABLES
Table 1 Data Byte Encoding ............................................................................................... 28
Table 2 Numeric PIO Pin Designations ............... ............... .............. ............... ....... ............ 34
Table 3 Alphabetic PIO Pin Designations ........................................................................... 34
Table 4 Bus Cycle Encoding ............................................................................................... 35
Table 5 Segment Register Selection Rules ........................................................................ 38
Table 6 Programming Am186ES Microcontroller Bus Width .............................................. 42
Table 7 Peripheral Control Block Register Map .............. .. ......... .. .................. .. .................. . 43
Table 8 Am186ES Microcontroller Maximum DMA Transfer Rates .................................... 49
Table 9 Typical Power Consumption for the Am186ESLV and Am188ESLV....... ......... .. .... 54
Table 10 Thermal Characteristics (°C/Watt) ......................................................................... 55
Table 11 Typical Power Consumption Calculation ............................................................... 56
Table 12 Junction Temperature Calculation ......................................................................... 56
Table 13 Typical Ambient Temperatures for PQFP with a 2-Layer Board ............. ........... .... 57
Table 14 Typical Ambient Temperatures for TQFP with a 2-Layer Boar d ............................ 58
Table 15 Typical Ambient Temperatures for PQFP with a 4-Layer to 6- Layer Board .... ...... 59
Table 16 Typical Ambient Temperatures for TQFP with a 4-Layer t o 6-Layer Board ........... 60
8 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
RELATED AMD PRODUCTS
E86 Family Devices
Device Description
80C186 16-bit microcontroller
80C188 16-bit microcontroller with 8-bit external data bus
80L186 Low-voltage, 16-bit microcontroller
80L188 Low-voltage, 16-bit microcontroller with 8-bit external data bus
Am186EM High-performance, 80C186-compatible, 16-bit embedded microcontroller
Am188EM High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus
Am186EMLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller
Am188EMLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit
external data bus
Am186ES High-performance, 80C186-compatible, 16-bit embedded microcontroller
Am188ES High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus
Am186ESLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller
Am188ESLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit
external data bus
Am186ER High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller with 32 Kbyte
of internal RAM
Am188ER High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit
external data bus and 32 Kbyte of internal RAM
Élan™SC300 High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller
ÉlanSC310 High-performance, single-chip, 32-bit embedded PC/AT microcontroller
ÉlanSC400 Single-chip, low-power, PC/AT-compatible microcontroller
Am386®DX High-performance, 32-bit embedded microprocessor with 32-bit external data bus
Am386®SX High-performance, 32-bit embedded microprocessor with 16-bit external data bus
Am486®DX High-performance, 32-bit embedded microprocessor with 32-bit external data bus
AT Perip her al
Microcontrollers
186 Peripheral
Microcontrollers ÉlanSC400
Microcontroller
80C186 and 80C188
Microcontrollers
Microprocessors
ÉlanSC300
Microcontroller
Am386SX/DX
Microprocessors
Am486DX
Microprocessor
AMD-K5™
Microprocessor
Time
The E86 Family of Embedded Microprocessors and Microcontrollers
Am186ES and
Am188ES
Microcontrollers
Am186EM and
Am188EM
Microcontrollers
Am186 and
Am188 Future
ÉlanSC310
Microcontroller
80L186 and 80L188
Microcontrollers
Am186EMLV &
Am188EMLV
Microcontrollers
Am186ESLV &
Am188ESLV
Microcontrollers
32-bit Future
Am186ER and
Am188ER
Microcontrollers
Future
K86™
Am486
Future
Am186/188ES and Am186/188ESLV Microcontrollers 9
PRELIMINARY
Related Documents
The following documents provide additional
information regarding the Am186ES and Am188ES
microcontrollers:
nThe Am186ES and Am188ES Microcontrollers
User’s Manual, order# 21096
nThe FusionE86SM Catalog, order# 19255
Third-Party Development
Support Products
The FusionE86SM Program of Partnerships for
Application Solutions provides the customer with an
array of products designed to meet critical time-to-
market needs. Products and solutions available from
the AMD FusionE86 partners include emulators,
hardware and software debuggers, board-level
products, and software development tools, among
others.
In addition, mature development tools and applications
for the x86 platform are widely available in the general
marketplace.
Customer Service
The AMD customer service network includes U.S. of-
fices, international offices, and a customer training cen-
ter. Expert technical assistance is available from the
AMD worldwide staff of field application engineers and
factory support staff who can answer E86 family hard-
ware and software development questions.
Hotline and World Wide Web Support
For answers to technical questions, AMD provides a
toll-free n umber for di rect access to our corpor ate ap-
plications hotline. Also available is the AMD World
Wide Web home page and FTP site, which provides
the latest E86 family product information, including
technical information and data on upcoming product re-
leases.
For technical support questions on all E86 products,
send E-mail to lpd.support@amd.com.
Corporate Applications Hotline
(800) 222-9323 Toll-free for U.S. and Canada
44-(0) 1276-803-299 U.K. and Europe hotline
World Wide Web Home Page and FTP Site
To access the AMD home page go to http://
www.amd.com.
To download documents and software, ftp to
ftp.amd.com and log on as anonymous using your
E-mail address as a password. Or via your web
browser, go to ftp://ftp.amd.com.
Questions, requests, and input concerning AMD’s
WWW pages can be sent via E-mail to
webmaster@amd.com.
Documentation and Literature
Free E86 family information such as data books, user’s
manuals, data sheets, application notes, the
FusionE86 Partner Solutions Catalog, and other litera-
ture is available with a simple phone call. Internation-
ally, contact your local AMD sales office for complete
E86 family literature.
Literature Ordering
(800) 222-9323 Toll-free for U.S. and Canada
(512) 602-5651 Direct dial worldwide
(800) 222-9323 AMD Facts-On-Demand™
fax information service,
toll-free for U.S. and Canada
10 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
KEY FEATURES AND BENEFITS
The Am186 ES a nd Am 188ES mic rocontr ollers extend
the AMD family of microcontrollers based on the
industry-standard x86 architecture. The Am186ES and
Am188ES microcontrollers are higher-performance,
more integrated versions of the 80C186/188
microp roce ssors , offer ing an att ractive m igrat ion path.
In addition, the Am186ES and Am188ES
microc ontroll ers o ffer ap plicati on-s pecif ic fea tures tha t
can enhance the system functionality of the Am186EM
and Am188EM microcontrollers. Upgrading to the
Am186ES and Am188ES microcontrollers is an
attractive solution for several reasons:
nMinimized total system cost—New peripherals
and on-chip system interface logic on the Am186ES
and Am188ES microcontrollers reduce the cost of
existing 80C186/188 designs.
nx86 software compatibility—80C186/188-com-
patible and upward-compatible with the other mem-
bers of the AMD E86 family. The x86 architecture is
the most widely used and supported computer ar-
chitecture in the world.
nEnhanced performance—The Am186ES and
Am188ES microcontrollers increase the perfor-
mance of 80C186/188 systems, and the nonmulti-
plexed address bus offers faster, unbuffered access
to memory.
nEnhanced functionality—The new and enhanced
on-chip peripherals of the Am186ES and Am188ES
microcontrollers include two asynchronous serial
ports, 32 PIOs, a watchdog timer, additional inter-
rupt pins, a pulse width demodulation option, DMA
directly to and from the serial ports, 8-bit and 16-bit
static bus sizing, a PSRAM controller, a 16-bit reset
configuration register, and enhanced chip-select
functionality.
Application Considerations
The integration enhancements of the Am186ES and
Am188ES microcontrollers provide a high-
performance, low-system-cost solution for 16-bit
embedded microcontroller designs. The
nonmultiplexed address bus eliminates the need for
system-support logic to interface memory devices,
while the multiplexed address/data bus maintains the
value of previously engineered, customer-specific
peripherals and circuits within the upgraded design.
Figure 1 illustrates an example system design that
uses the integrated peripheral set to achieve high
performance with reduced system cost.
Clock Generati on
The integrated clock generation circuitry of the
Am186ES and Am188ES microcontrollers allows the
use of a times-one crystal frequency. The design
shown in Figure 1 achieves 40-MHz CPU operation,
while using a 40-MHz crystal.
Memory Interface
The integrated memory controller logic of the
Am186ES and Am188ES microcontrollers provides a
direct address bus interface to memory devices. It is
not necessary to use an external address latch
controlled by the address latch enable (ALE) signal.
Individual byte-write-enable signals eliminate the need
for external high/low byte-write-enable circuitry. The
maximum bank size that is programmable for the
memory chip-select signals has been increased to
facilitate the use of high-density memory devices.
The improved memory timing specifications for the
Am186ES and Am188ES microcontrollers allow no-
wait-state operation with 70-ns memory access times
at a 40-MHz CPU clock speed. This reduces overall
system cost significantly by allowing the use of a more
commonly available memory speed and technology.
Figure 1 also shows an implementation of an RS-23 2
console or modem communications port. The RS-232-
to-CMOS voltage-level converter is required for the
electrical interface with the external device.
Figure 1. Am186ES Microcontroller Example
System Design
Direct Memory Interface Example
Figure 1 illustrates the Am186ES microcontroller’s
direct memory interface. The processor A19–A0 bus
connects to the memory address inputs, the AD bus
X2
X1
RS-232
Level
Converter
Serial Port 0
LCS
UCS
WHB
WLB
WE
Address
Data
OE
CS
WE
RD
WE
Address
Data
OE
CS
WE
AD15–AD0
A19–A0
Flash PROM
Static RAM
Am186ES
Microcontroller
40-MHz
Crystal
Serial Port 1
PW
PWD Input
Am186/188ES and Am186/188ESLV Microcontrollers 11
PRELIMINARY
connects to the data inputs and outputs, and the chip
selects connect to the memory chip-select inputs.
The RD output connects to the SRAM Output Enable
(OE) pin fo r read o perat ions. Wr ite o peration s use the
byte-write enables connected to the SRAM Write
Enable (WE) pins.
The example design uses 2-Mbit memory technology
(256 Kbytes) to fully populate the available address
space. Two flash PROM devices provide 512 Kbytes of
nonvolatile program storage, and two static RAM
devices provide 512 Kbytes of data storage area.
COMPARING THE ES TO THE 80C186
Figure 1 shows an example system using a 40-MHz
Am186ES microcontroller. Figure 2 shows a
comparable system implementation with an 80C186.
Because of its superior integration, the Am186ES
microcontroller system does not require the support
devices that are required on the 80C186 example
system. In addition, the Am186ES microcontroller
provides significantly better performance with its 40-
MHz clock rate.
Figure 2. 80 C186 Microcontroller Example System Design
COMPARING THE ES TO THE EMTABLE1
Compared to the Am186EM and Am188EM
microcontrollers, the Am186ES and Am188ES
microcontrollers have the following additional features:
nTwo full-featured asynchronous serial ports
nThe ability to use DMA to and from the serial ports
nTwo additional external interrupt signals
nEnhancements to the watchdog timer to improve its
security and functionality
nA pulse width demodulation option
nA da ta strobe bus interface option for DEN
nARDY functi onality is ch anged to allow both edges
of ARDY to be asynchronous to the clock
nAn option to have all MC S space ass erted throug h
MCS0
nOn the Am186ES m icrocontrol ler, stati c bus siz ing
allows UCS space to use a 16-bit data bus, while
LCS space can be either 8-bit or 16-bit. All non-
UCS and non-LCS memory and I/O accesses can
be 8-bit or 16-bit. This capability is available only on
the Am186ES microcontroller; the Am188ES micro-
controller has a uniform 8-bit access width.
nThe synchronous serial interface is removed
nOn the ES, row addresses are not driven on DRAM
refreshes
Two Asynchronous Serial Ports
The Am186ES and Am188ES microcontrollers have
two identical asynchronous serial ports. Each serial
UCS
WR WE
OE
CS
AD15–AD0
ALE
40-MHz
Crystal
Address
Data
Timer 0–2
INT3
DMA 0–1
CLKOUT 20 MHz
X2
X1
SRAM
WE
WE
Address
Data
OE
CS
RD
LCS
BHE
A0
PAL
LATCH
PCS0
LATCH
Serial
Port RS-232
Level
Converter
INT2–INT0
PIOs
Am29F200
Flash
12 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
port operates independently and has the following
features:
nFull-duplex operation
n7-bit, 8-bit, or 9-bit operation
nEven, odd, or no parity
nOne stop bit
nLong or short break character recognition
nParity error, framing error, overrun error, and break
character detection
nConfigurable hardware handshaking with CTS,
RTS, ENRX, and RTR
nDMA to and from the serial ports
nSeparate maskable interrupts for each port
nMultiprocessor 9-bit protocol
nIndependent baud rates for each port
nMaximum baud rate of 1/16th of the CPU clock rate
nDouble-buffered transmit and receive
nProgrammable interrupt generation for transmit, re-
ceive, and/or error detection
DMA and the Serial Por ts
The Am186ES and Am188ES microcontrollers can
DMA directly to and from the serial ports. DMA and
serial port transfer is accomplished by programming
the DMA controller to perform transfers between a data
source in memory or I/O space and a serial port
transmit or receive register. The two DMA channels
can s upport one s erial port in full-dupl ex mode or two
serial ports in half-duplex mode.
Two Additional External Interrupts
Two new interrupts, INT5 and INT6, are multiplexed
with the DMA request signals, DRQ0 and DRQ1. If a
DMA channel is not enabled, or if it is not using external
synchronization, then the associated pin can be used
as an external interrupt. INT5 and INT6 can also be
used in conjunction with the DMA terminal count
interrupts.
Enhanced Watchdog Timer
The Am186ES and Am188ES microcontrollers provide
a true watchdog timer that can be configured to
generate either an NMI interrupt or a system reset
upon timeout. The watchdog timer supports up to a
1.67-second timeout period in a 40-MHz system.
After reset, the watchdog timer defaults to enabled and
can be modif ied or disabl ed onl y one ti me. If t he t imer
is not disabled, the application program must
periodically reset the timer by writing a specific key
sequen ce to t he watchd og ti mer contr ol reg is ter. If the
timer is not r eset before i t coun ts dow n, eith er an NMI
or a system reset is issued, depending on the
configuration of the timer.
Pulse Width Demodulation Option
The Am186ES and Am188ES microcontrollers provide
pulse width demodulation by adding a Schmitt trigger
buffer to the INT2 pin. If pulse width demodulation
mode is enabled, timer 0 and timer 1 are used to
determine the pulse width of the signal period.
Separate maskable interrupts are generated on the
rising and falling edge of the pulse input.
In pulse width demodulation mode, the external pins
INT4, TIMERIN0, and TIMERIN1 are available as
PIOs, but not as their normal functionality.
Data Strobe Bus Interface Option
The Am186ES and Am188ES microcontrollers provide
a truly asyn chro nous b us in terface that al lows t he use
of 68K-type peripherals. This implementation
combines a new DS data strobe signal (multiplexed
with DEN) with a truly asynchronous ARDY ready input.
When DS is asserted, the data and address signals are
valid.
A chip-select signal, ARDY, DS, and other control
signals (RD /WR) can control the interface of 68K-type
external peripherals to the AD bus.
MCS0 Asserted fo r All MCS Option
When the MCS0-only mode is enabled in the
Am186ES and Am188ES microcontrollers, the entire
middle chip-select range is selected through MCS0.
The remaining MCS pins are available as PIOs or
alternate functions.
ARDY Functionality Change
In the Am186ES and Am188ES microcontrollers, the
ARDY signal i s c han ged to al lo w b oth ed ges o f A RDY
to be asynchronous to the clock.
On the Am186EM and Am188EM microcontrollers,
proper operation was not guaranteed if ARDY did not
meet the specification relative to the clock for all edges
except the falling edge of a normally-ready system
(relative to the rising edge of CLKOUTA).
To guarantee the number of wait states inserted,
ARDY or SRDY must be synchronized to CLKOUTA. If
the falling edge of ARDY is not synchronized to
CLKOUTA as specified, an additional clock period can
be added.
8-Bit and 16-Bit Bus Sizing Option
The Am186ES microcontroller allows switchable 8-bit
and 16-bit bus sizing based on chip selects for three
chip-select regions. The Am188ES microcontroller
supports only 8-bit data widths.
On the Am186ES microcontroller, the upper chip select
(UCS) region is always 16 bits, so memory used for
boot code at power-on reset must be 16-bit memory.
However, the LCS memo ry regio n, memory that is not
UCS or LCS (including memory mapped to MCS and
PCS), and I/O s pa ce ca n be in dependentl y co nfi gur ed
as 8-bit or 16-bit.
Am186/188ES and Am186/188ESLV Microcontrollers 13
PRELIMINARY
TQFP CONNECTION DIAGRAMS AND PINOUTS
Am186ES Microcontr o ller
Top Side View—100-Pin Thin Quad Flat Pack (TQFP)
Note:
Pin 1 is marked for orienta tion.
GND
6/A2
5/A1
3
2
AD0 1
AD8 2
AD1 3
AD9 4
AD2 5
AD10 6
AD3 7
AD11 8
AD4 9
AD12 10
AD5 11
12
AD13 13
AD6 14
15
AD14 16
AD7 17
AD15 18
19
20
TXD1 21
RXD1 22
23
RXD0 24
TXD0 25
VCC
75 INT4
74
73
72
71
70 NMI
69 SRDY
68 HOLD
67 HLDA
66
65
64
63 A0
62 A1
61
60 A2
59 A3
58 A4
57 A5
56 A6
55 A7
54 A8
53 A9
52 A10
51 A11
VCC
100 DRQ0/INT5
99 DRQ1/INT6
98 TMRIN0
97 TMROUT0
96 TMROUT1
95 TMRIN1/PIO0
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79 INT0
78 INT1/
77 INT2/
76 INT3/
VCC
VCC
1
0
0
1/IRQ
RTS0/RTR0 26
27
28
29
ALE 30
ARDY 31
32
33
34
35
X1 36
37
38
CLKOUTA 39
40
41
A19 42
A18 43
44
A17 45
A16 46
A15 47
A14 48
A13 49
A12 50
X2
VCC
CLKOUTB
VCC /0
/1
2/PIO24
3/
GND
GND GND
GND
GND
WHB
WLB
DT/R
DEN/DS
MCS0
MCS1
BHE/ADEN
WR
RD
S2
S1
S0
INTA
INTA
SELECT
UCS ONCE
ONCE
PCS
PCS
PCS
PCS
PCS
PCS
MCS
MCS RFSH
RES
LCS
S
6/LOCK/CLKDIV2
UZI
CTS0/ENRX0
/PWD
/RTS1/RTR1
/CTS1/ENRX1
Am186 ES Mi crocontroll er
14 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
TQFP PIN ASSIGNMENTS—Am186ES Microcontroller
(Sorted by Pin Number)
Pin No. Name Pin No. Name Pin No. Name Pin No. Name
1AD0 26
RTS0/RTR0/
PIO20 51 A11 76 INT3/INTA1/IRQ
2 AD8 27 BHE/ADEN 52 A10 77 INT2/INTA0/PWD/
PIO31
3AD1 28WR 53 A9 78 INT1/SELECT
4 AD9 29 RD 54 A8 79 INT0
5 AD2 30 ALE 55 A7 80 UCS/ONCE1
6 AD10 31 ARDY 56 A6 81 LCS/ONCE0
7AD3 32S
2 57A5 82PCS6/A2/PIO2
8AD11 33S
1 58A4 83PCS5/A1/PIO3
9AD4 34S0 59A3 84V
CC
10 AD12 35 GND 60 A2 85 PCS3/RTS1/
RTR1/
PIO19
11AD5 36X1 61V
CC 86 PCS2/CTS1/
ENRX1/PIO18
12GND 37X2 62A1 87GND
13 AD13 38 VCC 63 A0 88 PCS1/PIO17
14 AD6 39 CLKOUTA 64 GND 89 PCS0/PIO16
15 VCC 40 CLKOUTB 65 WHB 90 VCC
16 AD14 41 GND 66 WLB 91 MCS2/PIO24
17 AD7 42 A19/PIO9 67 HLDA 92 MCS3/RFSH/
PIO25
18 AD15 43 A18/PIO8 68 HOLD 93 GND
19 S6/LOCK/CLKDIV2/
PIO29 44 VCC 69 SRDY/PIO6 94 RES
20 UZI/PIO26 45 A17/PIO7 70 NMI 95 TMRIN1/PIO0
21 TXD1/PIO27 46 A16 71 DT/R/PIO4 96 TMROUT1/PIO1
22 RXD1/PIO28 47 A15 72 DEN/DS/PIO5 97 TMROUT0/PIO10
23 CTS0/ENRX0/PIO21 48 A14 73 MCS0/PIO14 98 TMRIN0/PIO11
24 RXD0/PIO23 49 A13 74 MCS1/PIO15 99 DRQ1/INT6/PIO13
25 TXD0/PIO22 50 A12 75 INT4/PIO30 100 DRQ0/INT5/PIO12
Am186/188ES and Am186/188ESLV Microcontrollers 15
PRELIMINARY
TQFP PIN DESIGNATIONS—Am186ES Microcontroller
(Sorted by Pin Name)
Pin Name No. Pin Name No. Pin Name No. Pin Name No.
A0 63 AD5 11 GND 87 RXD1 22
A1 62 AD6 14 GND 93 S034
A2 60 AD7 17 HLDA 67 S133
A3 59 AD8 2 HOLD 68 S232
A4 58 AD9 4 INT0 79 S6/LOCK/
CLKDIV2/PIO29 19
A5 57 AD10 6 INT1/SELECT 78 SRDY/PIO6 69
A6 56 AD11 8 INT2/INTA0/
PWD/PIO31 77 TMRIN0/PIO11 98
A7 55 AD12 10 INT3/INTA1/IRQ 76 TMRIN1/PIO0 95
A8 54 AD13 13 INT4/PIO30 75 TMROUT0/
PIO10 97
A9 53 AD14 16 LCS/ONCE0 81 TMROUT1/PIO1 96
A10 52 AD15 18 MCS0/PIO14 73 TXD0/PIO22 25
A11 51 ALE 30 MCS1/PIO15 74 TXD1 21
A12 50 ARDY 31 MCS2/PIO24 91 UCS/ONCE180
A13 49 BHE/ADEN 27 MCS3/RFSH/PIO25 92 UZI/PIO26 20
A14 48 CLKOUTA 39 NMI 70 VCC 15
A15 47 CLKOUTB 40 PCS0/PIO16 89 VCC 38
A16 46 CTS0/ENRX0/
PIO21 23 PCS1/PIO17 88 VCC 44
A17/PIO7 45 DEN/DS/PIO5 72 PCS2/CTS1/
ENRX1/PIO18 86 VCC 61
A18/PIO8 43 DRQ0/INT5/PIO12 100 PCS3/RTS1/RTR1/
PIO19 85 VCC 84
A19/PIO9 42 DRQ1/INT6/PIO13 99 PCS5/A1/PIO3 83 VCC 90
AD0 1 DT/R/PIO4 71 PCS6/A2/PIO2 82 WHB 65
AD1 3 GND 12 RD 29 WLB 66
AD2 5 GND 35 RES 94 WR 28
AD3 7 GND 41 RTS0/RTR0/PIO20 26 X1 36
AD4 9 GND 64 RXD0/PIO23 24 X2 37
16 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
CONNECTION DIAGRAM
Am188ES Microcontr o ller
Top Side View—100-Pin Thin Quad Flat Pack (TQFP)
Note:
Pin 1 is marked for orienta tion.
GND
6/A2
5/A1
3
2
AD0 1
AO8 2
AD1 3
AO9 4
AD2 5
AO10 6
AD3 7
AO11 8
AD4 9
AO12 10
AD5 11
12
AO13 13
AD6 14
15
AO14 16
AD7 17
AO15 18
19
20
TXD1 21
RXD1 22
23
RXD0 24
TXD0 25
VCC
75 INT4
74
73
72
71
70 NMI
69 SRDY
68 HOLD
67 HLDA
66
65
64
63 A0
62 A1
61
60 A2
59 A3
58 A4
57 A5
56 A6
55 A7
54 A8
53 A9
52 A10
51 A11
VCC
100 DRQ0/INT5
99 DRQ1/INT6
98 TMRIN0
97 TMROUT0
96 TMROUT1
95 TMRIN1
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79 INT0
78 INT1/
77 INT2/
76 INT3/
VCC
VCC
1
0
0
1/IRQ
RTS0/RTR0 26
27
28
29
ALE 30
ARDY 31
32
33
34
35
X1 36
37
38
CLKOUTA 39
40
41
A19 42
A18 43
44
A17 45
A16 46
A15 47
A14 48
A13 49
A12 50
X2
VCC
CLKOUTB
VCC /0
/1
2
3/
GND
GND GND
GND
GND
GND
WB
DT/R
DEN/DS
MCS0
MCS1
RFSH2/ADEN
WR
RD
S2
S1
S0
INTA
INTA
SELECT
UCS ONCE
ONCE
PCS
PCS
PCS
PCS
PCS
PCS
MCS
MCS RFSH
RES
LCS
S6/LOCK/CLKDIV2
UZI
CTS0/ENRX0
/PWD
/RTS1/RTR1
/CTS1/ENRX1
Am188ES Microcontroller
Am186/188ES and Am186/188ESLV Microcontrollers 17
PRELIMINARY
TQFP PIN DESIGNATIONS—Am188ES Microcontroller
(Sorted by Pin Number)
Pin No. Name Pin No. Name Pin No. Name Pin No. Name
1AD0 26
RTS0/RTR0/
PIO20 51 A11 76 INT3/INTA1/IRQ
2AO8 27RFSH2/ADEN 52 A10 77 INT2/INTA0/
PWD/PIO31
3AD1 28WR 53 A9 78 INT1/SELECT
4AO9 29RD 54 A8 79 INT0
5 AD2 30 ALE 55 A7 80 UCS/ONCE1
6AO10 31ARDY 56A6 81LCS/ONCE0
7AD3 32S
257A5 82PCS6/A2/PIO2
8AO11 33S
158A4 83PCS5/A1/PIO3
9AD4 34S059A3 84V
CC
10 AO12 35 GND 60 A2 85 PCS3/RTS1/RTR1/
PIO19
11 AD5 36 X1 61 VCC 86 PCS2/CTS1/ENRX1/
PIO18
12 GND 37 X2 62 A1 87 GND
13 AO13 38 VCC 63 A0 88 PCS1/PIO17
14 AD6 39 CLKOUTA 64 GND 89 PCS0/PIO16
15 VCC 40 CLKOUTB 65 GND 90 VCC
16 AO14 41 GND 66 WB 91 MCS2/PIO24
17 AD7 42 A19/PIO9 67 HLDA 92 MCS3/RFSH/PIO25
18 AO15 43 A18/PIO8 68 HOLD 93 GND
19 S6/LOCK/
CLKDIV2/PIO29 44 VCC 69 SRDY/PIO6 94 RES
20 UZI/PIO26 45 A17/PIO7 70 NMI 95 TMRIN1/PIO0
21 TXD1/PIO27 46 A16 71 DT/R/PIO4 96 TMROUT1/PIO1
22 RXD1/PIO28 47 A15 72 DEN/DS/PIO5 97 TMROUT0/PIO10
23 CTS0/ENRX0/
PIO21 48 A14 73 MCS0/PIO14 98 TMRIN0/PIO11
24 RXD0/PIO23 49 A13 74 MCS1/PIO15 99 DRQ1/INT6/PIO13
25 TXD0/PIO22 50 A12 75 INT4/PIO30 100 DRQ0/INT5/PIO12
18 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
TQFP PIN DESIGNATIONS—Am188ES Microcontroller
(Sorted by Pin Name)
Pin Name No. Pin Name No. Pin Name No. Pin Name No.
A0 63 AD5 11 GND 87 RXD0/PIO23 24
A1 62 AD6 14 GND 93 RXD1/PIO28 22
A2 60 AD7 17 HLDA 67 S034
A3 59 ALE 30 HOLD 68 S133
A4 58 AO8 2 INT0 79 S232
A5 57 AO9 4 INT1/SELECT 78 S6/LOCK/
CLKDIV2/PIO29 19
A6 56 AO10 6 INT2/INTA0/
PWD/PIO31 77 SRDY/PIO6 69
A7 55 AO11 8 INT3/INTA1/IRQ 76 TMRIN0/PIO11 98
A8 54 AO12 10 INT4/PIO30 75 TMRIN1/PIO0 95
A9 53 AO13 13 LCS/ONCE0 81 TMROUT0/PIO10 97
A10 52AO14 16MCS
0/PIO14 73 TMROUT1/PIO1 96
A11 51AO15 18MCS1/PIO15 74 TXD0/PIO22 25
A12 50 ARDY 31 MCS2/PIO24 91 TXD1/PIO27 21
A13 49 CLKOUTA 39 MCS3/RFSH/
PIO25 92 UCS/ONCE180
A14 48 CLKOUTB 40 NMI 70 UZI/PIO26 20
A15 47 CTS0/ENRX0/
PIO21 23 PCS0/PIO16 89 VCC 15
A16 46 DEN/DS/PIO5 72 PCS1/PIO17 88 VCC 38
A17/PIO7 45 DRQ0/INT5/
PIO12 100 PCS2/CTS1/
ENRX1/PIO18 86 VCC 44
A18/PIO8 43 DRQ1/INT6/
PIO13 99 PCS3/RTS1/
RTR1/
PIO19 85 VCC 61
A19/PIO9 42 DT/R/PIO4 71 PCS5/A1/PIO3 83 VCC 84
AD0 1 GND 12 PCS6/A2/PIO2 82 VCC 90
AD1 3 GND 35 RD 29 WB 66
AD2 5 GND 41 RES 94 WR 28
AD3 7 GND 64 RFSH2/ADEN 27 X1 36
AD4 9 GND 65 RTS0/RTR0/
PIO20 26 X2 37
Am186/188ES and Am186/188ESLV Microcontrollers 19
PRELIMINARY
PQFP CONNECTION DIAGRAMS AND PINOUTS
Am186ES Microcontr o ller
Top Side View—100-Pin Plastic Quad Flat Pack (PQFP)
Note:
Pin 1 is marked for orienta tion.
AD0
AD8
AD1
AD9
AD2
AD10
AD3
AD11
AD4
AD12
AD5
AD13
AD6
AD14
AD7
AD15
TXD1
RXD1
CTS0/ENRX0
RXD0
TXD0
GND
GND
ALE
ARDY
X1
CLKOUTA
A19
A18
A17
A16
A15
A14
A12
A13
X2
VCC
CLKOUTB
VCC
GND
INT4
DT/R
NMI
SRDY
HOLD
HLDA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
VCC
GND
TMRIN0
TMROUT0
TMROUT1
TMRIN1
INT0
GND
GND
VCC
S6/LOCK/CLKDIV2
VCC
VCC
Am186ES Microcontroller
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
BHE/ADEN
UZI
WHB
WLB
DEN/DS
MCS0
WR
RD
S2
S1
S0
MCS1
INT3/INTA1/IRQ
INT2/INTA0/PWD
INT1/SELECT
UCS/ONCE1
LCS/ONCE0
PCS6/A2
PCS5/A1
PCS3/RTS1/RTR1
PCS2/CTS1/ENRX1
PCS1
PCS0
MCS2
MCS3/RFSH
RES
RTS0/RTR0
DRQ1/INT6
DRQ0/INT5
20 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
PQFP PIN DESIGNATIONS—Am186ES Microcontroller
(Sorted by Pin Number)
Pin No. Name Pin No. Name Pin No. Name Pin No. Name
1 RXD0/PIO23 26 A13 51 MCS1/PIO15 76 DRQ1/INT6/PIO13
2 TXD0/PIO22 27 A12 52 INT4/PIO30 77 DRQ0/INT5/PIO12
3RTS0/RTR0/
PIO20 28 A11 53 INT3/INTA1/IRQ 78 AD0
4BHE
/ADEN 29 A10 54 INT2/INTA0/
PWD/PIO31 79 AD8
5WR 30 A9 55 INT1/SELECT 80 AD1
6RD 31 A8 56 INT0 81 AD9
7 ALE 32 A7 57 UCS/ONCE182AD2
8 ARDY 33A6 58LCS
/ONCE083AD10
9S2 34A5 59PCS6/A2/PIO2 84 AD3
10 S1 35A4 60PCS5/A1/PIO3 85 AD11
11 S0 36A3 61V
CC 86 AD4
12 GND 37 A2 62 PCS3/RTS1/RTR1/
PIO19 87 AD12
13 X1 38 VCC 63 PCS2/CTS1/
ENRX1/PIO18 88 AD5
14 X2 39 A1 64 GND 89 GND
15 VCC 40 A0 65 PCS1/PIO17 90 AD13
16 CLKOUTA 41 GND 66 PCS0/PIO16 91 AD6
17 CLKOUTB 42 WHB 67 VCC 92 VCC
18 GND 43 WLB 68 MCS2/PIO24 93 AD14
19 A19/PIO9 44 HLDA 69 MCS3/RFSH/PIO25 94 AD7
20 A18/PIO8 45 HOLD 70 GND 95 AD15
21 VCC 46 SRDY/PIO6 71 RES 96 S6/LOCK/
CLKDIV2/PIO29
22 A17/PIO7 47 NMI 72 TMRIN1/PIO0 97 UZI/PIO26
23 A16 48 DT/R/PIO4 73 TMROUT1/PIO1 98 TXD1/PIO27
24 A15 49 DEN/DS/PIO5 74 TMROUT0/PIO10 99 RXD1/PIO28
25 A14 50 MCS0/PIO14 75 TMRIN0/PIO11 100 CTS0/ENRX0/PIO21
Am186/188ES and Am186/188ESLV Microcontrollers 21
PRELIMINARY
PQFP PIN DESIGNATIONS—Am186ES Microcontroller
(Sorted by Pin Name)
Pin Name No. Pin Name No. Pin Name No. Pin Name No.
A0 40 AD5 88 GND 70 RXD1/PIO28 99
A1 39 AD6 91 GND 89 S011
A2 37 AD7 94 HLDA 44 S110
A3 36 AD8 79 HOLD 45 S29
A4 35 AD9 81 INT0 56 S6/LOCK/
CLKDIV2/PIO29 96
A5 34 AD10 83 INT1/SELECT 55 SRDY/PIO6 46
A6 33 AD11 85 INT2/INTA0/
PWD/PIO31 54 TMRIN0/PIO11 75
A7 32 AD12 87 INT3/INTA1/IRQ 53 TMRIN1/PIO0 72
A8 31 AD13 90 INT4/PIO30 52 TMROUT0/
PIO10 74
A9 30 AD14 93 LCS/ONCE0 58 TMROUT1/PIO1 73
A10 29 AD15 95 MCS0/PIO14 50 TXD0/PIO22 2
A11 28 ALE 7 MCS1/PIO15 51 TXD1/PIO27 98
A12 27 ARDY 8 MCS2/PIO24 68 UCS/ONCE157
A13 26 BHE/ADEN 4MCS3/RFSH/PIO25 69 UZI/PIO26 97
A14 25 CLKOUTA 16 NMI 47 VCC 15
A15 24 CLKOUTB 17 PCS0/PIO16 66 VCC 21
A16 23 CTS0/ENRX0/
PIO21 100 PCS1/PIO17 65 VCC 38
A17/PIO7 22 DEN/DS/PIO5 49 PCS2/CTS1/ENRX1/
PIO18 63 VCC 61
A18/PIO8 20 DRQ0/INT5/PIO12 77 PCS3/RTS1/RTR1/
PIO19 62 VCC 67
A19/PIO9 19 DRQ1/INT6/PIO13 76 PCS5/A1/PIO3 60 VCC 92
AD0 78 DT/R/PIO4 48 PCS6/A2/PIO2 59 WHB 42
AD1 80 GND 12 RD 6WLB 43
AD2 82 GND 18 RES 71 WR 5
AD3 84 GND 41 RTS0/RTR0/PIO20 3 X1 13
AD4 86 GND 64 RXD0/PIO23 1 X2 14
22 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
CONNECTION DIAGRAM
Am188ES Microcontr o ller
Top Side View—100-Pin Plastic Quad Flat Pack (PQFP)
Note:
Pin 1 is marked for orienta tion.
AD0
AO8
AD1
AO9
AD2
AO10
AD3
AO11
AD4
AO12
AD5
AO13
AD6
AO14
AD7
AO15
TXD1
RXD1
CTS0/ENRX0
RXD0
TXD0
GND
GND
ALE
ARDY
X1
CLKOUTA
A19
A18
A17
A16
A15
A14
A12
A13
X2
VCC
CLKOUTB
VCC
GND
INT4
DT/R
NMI
SRDY
HOLD
HLDA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
VCC
GND
TMRIN0
TMROUT0
TMROUT1
TMRIN1
INT0
GND
GND
VCC
S6/LOCK/CLKDIV2
DRQ1/INT6
DRQ0/INT5
VCC
VCC
Am188ES Microcontroller
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
R
FSH2/ADEN
UZI
GND
WB
DEN/DS
MCS0
WR
RD
S2
S1
S0
MCS1
INT3/INTA1/IRQ
INT2/INTA0/PWD
INT1/SELECT
UCS/ONCE1
LCS/ONCE0
PCS6/A2
PCS5/A1
PCS3/RTS1/RTR1
PCS2/CTS1/ENRX
1
PCS1
PCS0
MCS2
MCS3/RFSH
RES
RTS0/RTR0
Am186/188ES and Am186/188ESLV Microcontrollers 23
PRELIMINARY
PQFP PIN DESIGNATIONS—Am188ES Microcontroller
(Sorted by Pin Number)
Pin No. Name Pin No. Name Pin No. Name Pin No. Name
1 RXD0/PIO23 26 A13 51 MCS1/PIO15 76 DRQ1/INT6/PIO13
2 TXD0/PIO22 27 A12 52 INT4/PIO30 77 DRQ0/INT5/PIO12
3RTS0/RTR0/
PIO20 28 A11 53 INT3/INTA1/IRQ 78 AD0
4RFSH
2/ADEN 29 A10 54 INT2/INTA0/
PWD/PIO31 79 AO8
5WR 30 A9 55 INT1/SELECT 80 AD1
6RD 31 A8 56 INT0 81 AO9
7 ALE 32 A7 57 UCS/ONCE182AD2
8 ARDY 33A6 58LCS
/ONCE083AO10
9S2 34A5 59PCS6/A2/PIO2 84 AD3
10 S1 35A4 60PCS5/A1/PIO3 85 AO11
11 S0 36A3 61V
CC 86 AD4
12 GND 37 A2 62 PCS3/RTS1/RTR1/
PIO19 87 AO12
13 X1 38 VCC 63 PCS2/CTS1/ENRX1/
PIO18 88 AD5
14 X2 39 A1 64 GND 89 GND
15 VCC 40 A0 65 PCS1/PIO17 90 AO13
16 CLKOUTA 41 GND 66 PCS0/PIO16 91 AD6
17 CLKOUTB 42 GND 67 VCC 92 VCC
18 GND 43 WB 68 MCS2/PIO24 93 AO14
19 A19/PIO9 44 HLDA 69 MCS3/RFSH/PIO25 94 AD7
20 A18/PIO8 45 HOLD 70 GND 95 AO15
21 VCC 46 SRDY/PIO6 71 RES 96 S6/LOCK/
CLKDIV2/PIO29
22 A17/PIO7 47 NMI 72 TMRIN1/PIO0 97 UZI/PIO26
23 A16 48 DT/R/PIO4 73 TMROUT1/PIO1 98 TXD1/PIO27
24 A15 49 DEN/DS/PIO5 74 TMROUT0/PIO10 99 RXD1/PIO28
25 A14 50 MCS0/PIO14 75 TMRIN0/PIO11 100 CTS0/ENRX0/PIO21
24 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
PQFP PIN DESIGNATIONS—Am188ES Microcontroller
(Sorted by Pin Name)
Pin Name No. Pin Name No. Pin Name No. Pin Name No.
A0 40 AD5 88 GND 70 RXD0/PIO23 1
A1 39 AD6 91 GND 89 RXD1/PIO28 99
A2 37 AD7 94 HLDA 44 S011
A3 36 ALE 7 HOLD 45 S110
A4 35 AO8 79 INT0 56 S29
A5 34 AO9 81 INT1/SELECT 55 S6/LOCK/
CLKDIV2/PIO29 96
A6 33 AO10 83 INT2/INTA0/
PWD/PIO31 54 SRDY/PIO6 46
A7 32 AO11 85 INT3/INTA1/IRQ 53 TMRIN0/PIO11 75
A8 31 AO12 87 INT4/PIO30 52 TMRIN1/PIO0 72
A9 30 AO13 90 LCS/ONCE058
TMROUT0/
PIO10 74
A10 29 AO14 93 MCS0/PIO14 50 TMROUT1/PIO1 73
A11 28 AO15 95 MCS1/PIO15 51 TXD0/PIO22 2
A12 27 ARDY 8 MCS2/PIO24 68 TXD1/PIO27 98
A13 26 CLKOUTA 16 MCS3/RFSH/PIO25 69 UCS/ONCE157
A14 25CLKOUTB 17NMI 47UZI
/PIO26 97
A15 24 CTS0/ENRX0/
PIO21 100 PCS0/PIO16 66 VCC 15
A16 23 DEN/DS/PIO5 49 PCS1/PIO17 65 VCC 21
A17/PIO7 22 DRQ0/INT5/PIO12 77 PCS2/CTS1/ENRX1/
PIO18 63 VCC 38
A18/PIO8 20 DRQ1/INT6/PIO13 76 PCS3/RTS1/RTR1/
PIO19 62 VCC 61
A19/PIO9 19 DT/R/PIO4 48 PCS5/A1/PIO3 60 VCC 67
AD0 78 GND 12 PCS6/A2/PIO2 59 VCC 92
AD1 80 GND 18 RD 6WB 43
AD2 82 GND 41 RES 71 WR 5
AD3 84 GND 42 RFSH2/ADEN 4X1 13
AD4 86 GND 64 RTS0/RTR0/PIO20 3 X2 14
Am186/188ES and Am186/188ESLV Microcontrollers 25
PRELIMINARY
LOGIC SYMBOL—Am186ES MICROCONTROLLER
Notes:
* These signals are the normal function of a pin that can be used as a PIO. See Pin Descriptions beginni ng on page 27 and
Table 2 on page 34 for information on shared function.
** All PIO signals are shared with other physical pins.
X1
X2
CLKOUTA
CLKOUTB
A19–A0
AD15–AD0
ALE
WHB
WLB
RD
WR
S2–S0
HOLD
HLDA
DT/R
DEN/DS
ARDY
SRDY
TMRIN0
TMROUT0
20
16
Clocks
Address and
Address/ Data Buses
Bus Control
Timer Control
RES
INT4
INT3/INTA1/IRQ
INT2/INTA0/PWD
INT1/SELECT
INT0
NMI
PCS6/A2
PCS5/A1
PCS1–PCS0
LCS/ONCE0
MCS2–MCS0
UCS/ONCE1
DRQ0/INT5
PIO32–PIO0
2
32
shared
Reset Cont rol and
Interrupt Service
Memory and
Peripheral Control
DMA Control
Asynchronous
Serial Port Control
Programmable
I/O Control
3
TMRIN1
TMROUT1
3
MCS3/RFSH
S6/LOCK/CLKDIV2
BHE/ADEN
UZI
**
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
DRQ1/INT6
DRQ0/INT5
DRQ1/INT6
*
TXD0
RXD0
*
*
CTS0/ENRX0
RTS0/RTR0 *
*
TXD1
RXD1
*
*
PCS2/CTS1/ENRX1
PCS3/RTS1/RTR1
PCS3/RTS1/RTR1
*
PCS2/CTS1/ENRX1
*
*
*
26 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
LOGIC SYMBOL—Am188ES MICROCONTROLLER
Notes:
* These signals are the normal function of a pin that can be used as a PIO. See Pin Descriptions beginni ng on page 27 and
Table 2 on page 34 for information on shared function.
** All PIO signals are shared with other physical pins.
X1
X2
CLKOUTA
CLKOUTB
A19–A0
AD7–AD0
ALE
WB
RD
WR
S2–S0
HOLD
HLDA
DT/R
DEN/DS
ARDY
SRDY
TMRIN0
TMROUT0
20
8
Clocks
Address and
Address/Data Buses
Bus Control
Timer Control
RES
INT4
INT3/INTA1/IRQ
INT2/INTA0/PWD
INT1/SELECT
INT0
NMI
PCS6/A2
PCS5/A1
PCS1–PCS0
LCS/ONCE0
MCS2–MCS0
UCS/ONCE1
DRQ0/INT5
PIO32–PIO0
2
32
shared
Reset Control and
Interrupt Service
Memory and
Peripheral Control
DMA Control
Asynchronous
Serial Port Control
Programmable
I/O Control
3
TMRIN1
TMROUT1
3
MCS3/RFSH
S6/LOCK/CLKDIV2
RFSH2/ADEN
UZI
**
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
DRQ1/INT6
DRQ0/INT5
DRQ1/INT6
*
TXD0
RXD0
*
*
CTS0/ENRX0
RTS0/RTR0 *
*
TXD1
RXD1
*
*
PCS2/CTS1/ENRX1
PCS3/RTS1/RTR1
PCS3/RTS1/RTR1
*
PCS2/CTS1/ENRX1
*
AO15–AO8
8
*
*
Am186/188ES and Am186/188ESLV Microcontrollers 27
PRELIMINARY
PIN DESCRIPTIONS
Pins That Are Used by Emulators
The following pins are used by emulators: A19–A0,
AO15– AO8, AD7 –AD0, AL E, BHE/ADEN (on the 186),
CLKOUTA, RFSH2/ADEN (on the 188), RD, S2–S0,
S6/LOCK/CLKDIV2, and UZI.
Emulators require S6/LOCK/CLKDIV2 and UZI to be
configur ed in their no rmal fun ction ality as S6 a nd UZI ,
not as PIOs. If BHE/ADEN (on the 186) or RFSH2/
ADEN (on the 188 ) is held Low durin g the risi ng edge
of RES, S6 and UZI are configured in their normal
functionality.
Pin Terminology
The following terms are used to describe the pins:
Input—An input-only pin.
Output—An output-only pin.
Input/Output—A pin that can be either input or output.
Synchronous—Synch ronous i nputs mu st meet s etup
and hold times in relation to CLKOUTA. Synchronous
outputs are synchronous to CLKOUTA.
Asynchronous—Inputs or outputs that are
asynchronous to CLKOUTA.
A19–A0
(A19/PIO9, A18/PIO8, A17/PIO7)
Address Bus (output, thr ee-state, synchronous)
These pins supply nonmultiplexed memory or I/O
addresses to the system one half of a CLKOUTA
period earlier than the multiplexed address and data
bus (AD15–A D0 on the 186 or AO15–AO8 and AD7–
AD0 on the 188 ). Dur ing a bus hold or res et c on diti on ,
the address bus is in a high-impedance state.
AD15–AD8 (Am186ES Microcontroller)
AO15–AO8 (Am188ES Microcontroller)
Address and Data Bus (input/output, three-state,
synchronous, level-sensitive)
Address-Only Bus (output, three-state,
synchronous, level-sensitive)
AD15–AD8—On t he Am186ES microcontroller, these
time-multiplexed pins supply memory or I/O addresses
and data to the system. This bus can supply an
address to the system during the first period of a bus
cycle (t1). It supplies data to the system during the
remaining periods of that cycle (t2, t3, and t4).
The address phase of these pins can be disabled. See
the ADEN description with the BHE/ADEN pin. When
WHB is deasserted, these pins are three-stated during
t2, t3, and t4.
During a bus hold or reset condition, the address and
data bus is in a high-impedance state.
During a power-on reset, the address and data bus
pins (AD15–AD0 for the 186, AO15–AO8 and AD7–
AD0 for the 188) can also be used to load system
configuration information into the internal reset
configuration register.
AO15–AO8—When the address bus is enabled on the
Am188ES mic rocontrol ler, via th e AD b it in the UMCS
and LMCS registers, the address-only bus (AO15–
AO8) contains valid high-order address bits from bus
cycles t1–t4. These outputs are floated during a bus
hold or reset.
On the Am188ES microcontroller, AO15–AO8
combine with AD7–AD0 to form a complete multiplexed
address bus while AD7–AD0 is the 8-bit data bus.
AD7–AD0
Address and Data Bus (input/output, three-state,
synchronous, level-sensitive)
These time-multiplexed pins supply partial memory or
I/O addresses, as well as data, to the system. This bus
supplies the low-order 8 bits of an address to the
system durin g the fi r st per iod of a bu s cyc l e (t 1), and it
supplies data to the system during the remaining
periods of that cycle (t2, t3, and t4). In 8-bit mode on the
Am188ES microcontroller, AD7–AD0 supplies the
data.
The address phase of these pins can be disabled. See
the ADEN description with the BHE/ADEN pin. When
WLB is dea ss erted, thes e pi ns ar e thr ee -stat ed d ur in g
t2, t3, and t4.
During a bus hold or reset condition, the address and
data bus is in a high-impedance state.
During a power-on reset, the address and data bus
pins (AD15–AD0 for the 186, AO15–AO8 and AD7–
AD0 for the 188) can also be used to load system
configuration information into the internal reset
configuration register.
ALE
Address Latch Enable (output, synchronous)
This pin indicates to the system that an address ap-
pears on the address and data bus (AD15–AD0 for the
186 or AO15–AO8 and AD7–AD0 for the 188). The ad-
dress is guaranteed to be valid on the trailin g edge of
ALE. This pin is three-stated during ONCE mode. This
pin is not three-stated during a bus hold or reset.
ARDY
Asynchronous Ready (input, asynchronous,
level-sensitive)
This pin i s a tru e as ync hr ono us re ady tha t in dic ate s t o
the microcontroller th at the addressed memory space
or I/O devi ce wi ll com plete a data tra nsfer. Th e ARDY
28 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
pin is asynchronous to CLKOUTA and is active High.
To guarantee the number of wait states inserted,
ARDY or SRDY must be synchronized to CLKOUTA. If
the falling edge of ARDY is not synchronized to
CLKOUTA as specified, an additional clock period can
be added.
To always assert the ready condition to the
microcont ro ll er, ti e A RDY High . If t he s y ste m d oes not
use ARDY, tie the pin Low to yield control to SRDY.
BHE/ADEN
(Am186ES Microcontroller Only)
Bus High Enable (three-state, output,
synchronous)
Address Enable (input, internal pullup)
BHE—During a memory access, this pin and the least-
significant address bit (AD0 or A0) indicate to the
system which bytes of the data bus (upper, lower, or
both) participate in a bus cycle. The BHE/ADEN and
AD0 pins are encoded as shown in Table 1.
Table 1. Data Byte Encoding
BHE is asserted during t1 and remains asserted
through t3 and tW. BHE does not need to be latched.
BHE floats during bus hold and reset.
On the Am186ES microcontroller, WLB and WHB
implement the functionality of BHE and AD0 for high
and low byte-write enables.
BHE/ADEN also signals DRAM refresh cycles when
using the multiplexed address and data (AD) bus. A
refresh cycle is indicated when both BHE/ADEN and
AD0 are High. During refresh cycles, the A bus and the
AD bus are not guaranteed to provide the same
address during the address phase of the AD bus cycle.
For this r eas on , the A 0 sig nal c an not be us ed in pla ce
of the AD0 signal to determine refresh cycles. PSRAM
refreshes al so pr ov ide a n additio nal RFS H s ign al (see
the MCS3/RFSH pin description on page 31).
ADEN—If BHE/ADEN is held High or left floating
during power-on reset, the address portion of the AD
bus (AD15 –AD0 for th e 186 or A O15–AO8 an d AD7–
AD0 for the 188) is enabled or disabled during LCS and
UCS bus c ycles ba sed on the DA bi t in th e LM CS and
UMCS registers. In this case, the memory address is
accessed on the A19–A0 pins. There is a weak internal
pullup resistor on BHE/ADEN so no external p ullup is
required. This mode of operation reduces power
consumption.
If BHE/ADEN is held Low on power-on reset, the AD
bus drives both addresse s and data , regar dles s of the
DA bit setting. The pin is sampled on the rising edge of
RES. (S6 and UZI also assume their normal
functionality in this instance. See Table 2 on page 34.)
Note:
On the Am188ES microcontroller, AO15–AO8
are drive n during t he
t
2–
t
4
bus cycle , regardl ess of th e
setting of the DA bit in the UMCS and LMCS registers.
CLKOUTA
Clock Output A (output, synchronous)
This pin supplies the internal clock to the system.
Depending on the value of the system configuration
register (SYSCON), CLKOUTA operates at either the
PLL frequ ency, the p ower-sa ve freque ncy, o r is thre e-
stated. CLKOUTA remains active during reset and bus
hold conditions.
All AC timing specs that use a clock relate to
CLKOUTA.
CLKOUTB
Clock Output B (output, synchronous)
This pin supplies an additional clock with a delayed
output compared to CLKOUTA. Depending upon the
value o f the sys tem configurat ion register (SYSCON),
CLKOUTB operates at either the PLL frequency, the
power-save frequency, or is three-stated. CLKOUTB
remains active during reset and bus hold conditions.
CLKOUTB is not used for AC timing specs.
CTS0/ENRX0/PIO21
Clear-to-Send 0 (input, asynchronous)
Enable-Receiver-Request 0 (input, asynchronous)
CTS0—This pin provides the Clear to Send signal for
asynch ronou s se rial port 0 wh en the ENRX 0 bit in the
AUXCON register is 0 and hardware flow control is
enabled fo r the port (FC b it in the seri al port 0 contr ol
register is set). The CTS0 signal gates the
transmission of data from the associated serial port
transmit register. When CTS0 is asserted, the
transmitter begins transmission of a frame of data, if
any is available. If CTS0 is deasserted, the transmitter
holds the data in the serial port transmit register. The
valu e of CTS 0 is check ed only at the begin ning of th e
transmission of the frame.
ENRX0—This pin provides the Enable Receiver
Request for asynchronous serial port 0 when the
ENRX0 bit i n the A UXCON r egister is 1 and hardwa re
flow c ontr ol is enab led f or th e por t (FC bit i n the ser ial
port 0 control register is set). The ENRX0 signal
enables the receiver for the associated serial port.
BHE AD0 Type of Bus Cycle
0 0 Word Transfer
01High Byte Transfer (Bits 15–8)
1 0 Low Byte Transfer (Bits 7–0)
11Refresh
Am186/188ES and Am186/188ESLV Microcontrollers 29
PRELIMINARY
DEN/DS/PIO5
Data Enable (output, three-state, synchronous)
Data Strobe (output, three-state, synchronous)
DEN—This pin supplies an output enable to an
external data -bus transceiv er. DEN is asserted during
memory, I/O, and interrupt acknowledge cycles. DEN
is deasserted when DT/R changes state. DEN floats
during a bus hold or reset condition.
DS—The data strobe provides a signal where the write
cycle t imi ng is ide nti ca l to the r e ad c ycl e ti min g. W hen
used with other control signals, DS provides an
interfac e for 68K- type p eripheral s withou t the need for
additional system interface logic.
When DS is asserted, addresses are valid. When DS is
asserte d on wr ite s, d ata i s va lid . W hen D S is asserted
on reads, data can be asserted on the AD bus.
Note: This pin resets to DEN.
DRQ0/INT5/PIO12
DMA Request 0 (input, synchronous,
level-sensitive)
Maskable Interrupt Request 5 (input,
asynchronous, edge-triggered)
DRQ0—This pin indicates to the microcontroller that an
externa l device is rea dy for DM A channel 0 t o perfor m a
transfer. DRQ0 is level-triggered and internally synchronized.
DRQ0 is not latched and must remain active until
serviced.
INT5—If DMA 0 is not enabled or DMA 0 is no t being
used with external s ynchroniza tion, INT5 c an be used
as an additional external interrupt request. INT5 shares
the DMA 0 interrupt type (0Ah) and register control bits.
INT5 is edge -trigge red only and mus t be hel d until the
interru pt is acknowledged.
DRQ1/INT6/PIO13
DMA Request 1 (input, synchronous,
level-sensitive)
Maskable Interrupt Request 6 (input,
asynchronous, edge-triggered)
DRQ1—This pin indicates to the microcontroller that an
external de vi ce is r eady fo r DM A c ha nne l 1 to perform
a transfer. DRQ1 is level-triggered and internally
synchronized.
DRQ1 is not latched and must remain active until
serviced.
INT6—If DMA 1 is not enabled or DMA 1 is no t being
used with external s ynchroniza tion, INT6 c an be used
as an additional external interrupt request. INT6 shares
the DMA 1 interrupt type (0Bh) and register control bits.
INT6 is edge -trigge red only and mus t be hel d until the
interru pt is acknowledged.
DT/R/PIO4
Data Transmit or Receive (output, three-state,
synchronous)
This pin indicates in which direction data should flow
through an exte rnal data-bu s tran sceiver. When DT/R
is asserted High, the microcontroller transmits data.
When this pin is deasserted Low, the microcontroller
receives data. DT/R floats during a bus hold or reset
condition.
GND
Ground
Ground pins connect the microcontroller to the system
ground.
HLDA
Bus Hold Acknowledge (output, synchronous)
This pin is asserted High to indicate to an external bus
master that the mi crocon troll er has relea sed cont rol of
the local bus. When an external bus master requests
control of the local bus (by asserting HOLD), the
microc ontroll er co mplete s the bu s cycl e in pro gres s. It
then relinquishes control of the bus to the external bus
master by asserting HLDA and floating DEN, RD, WR,
S2–S0, AD15–AD0, S6, A19–A0, BHE, WHB, WLB,
and DT/R, and then driving the chip selects UCS, LCS,
MCS3–MCS0, PCS6–PCS5, and PCS3–PCS0 High.
When the external bus master has finished using the
local bus, it indicates this to the microcontroller by
deasserting HOLD. The microcontroller responds by
deasserting HLDA.
If the microcontroller requires access to the bus (for
example, to refresh), it will deassert HLDA before the
external bus master deasserts HOLD. The external bus
master must be ab le to deasse rt HOLD a nd allow th e
microcontroller access to the bus. See the timing
diagrams for bus hold on page 97.
HOLD
Bus Hold Request (input, synchronous,
level-sensitive)
This pin indicates to the microcontroller that an external
bus master needs control of the local bus.
The Am186 ES and Am18 8ES microc ontro llers’ H OLD
latency time is a function of the activity occurring in the
processor when the HOLD request is received. A
DRAM request will delay a HOLD request when both
requests are made at the same time. In addition, if
locked transfers are performed, the HOLD latency time
is increased by the length of the locked transfer.
For more information, see the HLDA pin description on
page 29.
30 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
INT0
Maskable Interrupt Request 0 (input,
asynchronous)
This pin indicates to the microcontroller that an
interrupt request has occurred. If the INT0 pin is not
masked, the microcontroller transfers program
execution to the location specified by the INT0 vector in
the microcontroller interrupt vector table.
Interrupt r eques ts are s ynchro nized in terna lly and c an
be edge-triggered or level-triggered. To guarantee
interrupt recognition, the requesting device must
continue asserting INT0 until the request is
acknowledged.
INT1/SELECT
Maskable Interrupt Request 1 (input,
asynchronous)
Slave Select (input, asynchronous)
INT1—This pin in dicate s to the m icroc ontrolle r that an
interrupt r equest has occ urred. If INT1 is n ot masked,
the microco ntroller transfe rs program execu tion to the
location specified by the INT1 vector in the
microcontroller interrupt vector table.
Interrupt r eques ts are s ynchro nized in terna lly and c an
be edge-triggered or level-triggered. To guarantee
interrupt recognition, the requesting device must
continue asserting INT1 until the request is
acknowledged.
SELECT—When the microcontroller interrupt control
unit is operating as a slave to an external interrupt
controller, this pin indicate s to the microcontroller that
an interrupt type appears on the address and data bus.
The INT0 pin m ust indicate to the microcontroller that
an interrupt has occurred before the SELECT pin
indicates to the microcontroller that the interrupt type
appears on the bus.
INT2/INTA0/PWD/PIO31
Maskable Interrupt Request 2 (input,
asynchronous)
Interrupt Acknowledge 0 (output, synchronous)
Pulse Width Demodulator (input, Schmitt trigger)
INT2—This pin in dicate s to the m icroc ontrolle r that an
interrupt request has occurred. If the INT2 pin is not
masked, the microcontroller transfers program
execution to the location specified by the INT2 vector in
the microcontroller interrupt vector table.
Interrupt r eques ts are s ynchro nized in terna lly and c an
be edge-triggered or level-triggered. To guarantee
interrupt recognition, the requesting device must
continue asserting INT2 until the request is
acknowledged. INT2 becomes INTA0 when INT0 is
configured in cascade mode.
INTA0—When the microcontroller interrupt control unit
is oper ating in c asc ade m ode, th is p in in dicat es to the
system that the microcontroller needs an interrupt type
to process the interrupt request on INT0. The
peripheral issuing the interrupt request must provide
the microcontroller with the corresponding interrupt
type.
PWD—If pulse width demodulation is enabled, PWD
processes a signal through the Schmitt trigger. PWD is
used internally to drive TIMERIN0 and INT2, and PWD
is inverted internally to drive TIMERIN1 and INT4. If
INT2 and INT4 are enabled and timer 0 and timer 1 are
properly configured, the pulse width of the alternating
PWD signal can be calculated by comparing the values
in timer 0 and timer 1.
In PWD mode, the signals TIMERIN0/PIO11,
TIMERIN1/PIO0, and INT4/PIO30 can be used as
PIOs. If they are not used as PIOs they are ignored
internally. The level of INT2/INTA0/PWD/PIO31 is
reflected in the PIO data register for PIO 31 as if it was
a PIO.
INT3/INTA1/IRQ
Maskable Interrupt Request 3
(input, asynchronous)
Interrupt Acknowledge 1 (output, synchronous)
Slave Interrupt Request (output, synchronous)
INT3—This pi n indic ates t o the microc ontrol ler that a n
interrupt request has occurred. If the INT3 pin is not
masked, the microcontroller then transfers program
execution to the location specified by the INT3 vector in
the microcontroller interrupt vector table.
Interrupt requests are synchronized internally, and can
be edge-triggered or level-triggered. To guarantee
interrupt recognition, the requesting device must
continue asserting INT3 until the request is
acknowledged. INT3 becomes INTA1 when INT1 is
configured in cascade mode.
INTA1—When the microcontroller interrupt control unit
is oper ating in c asc ade m ode, th is p in in dicat es to the
system that the microcontroller needs an interrupt type
to process the interrupt request on INT1. The
peripheral issuing the interrupt request must provide
the microcontroller with the corresponding interrupt
type.
IRQ—When the microcontroller interrupt control unit is
operating as a slave to an external master interrupt
controller, this pin lets the microcontroller issue an
interrupt request to the external master interrupt
controller.
Am186/188ES and Am186/188ESLV Microcontrollers 31
PRELIMINARY
INT4/PIO30
Maskable Interrupt Request 4 (input,
asynchronous)
This pin indicates to the microcontroller that an
interrupt request has occurred. If the INT4 pin is not
masked, the microcontroller then transfers program
execution to the location specified by the INT4 vector in
the microcontroller interrupt vector table.
Interrupt requests are synchronized internally, and can
be edge-triggered or level-triggered. To guarantee
interrupt recognition, the requesting device must
continue asserting INT4 until the request is
acknowledged.
When pul se width d emodulati on mode is e nabled, the
INT4 signal is used internally to indicate a High-to-Low
transition on the PWD signal. When pulse width
demodulation mode is enabled, INT4/PIO30 can be
used as a PIO.
LCS/ONCE0
Lower Memory Chip Select (output, synchronous,
internal pullup)
ONCE Mode Request 0 (input)
LCS—This pi n indicates to th e system that a me mory
access is in progr ess to the low er memory block. The
base addr ess and si ze of th e lower memo ry block a re
programmable up to 512 Kbytes. On the Am186ES
microcontroller, LCS is configured for 8-bit or 16-bit bus
size by the auxiliary configuration register. LCS is he ld
High during a bus hold condition.
ONCE0—During reset, this pin and ONCE1 indicate to
the microcontroller the mode in which it should operate.
ONCE0 and ONCE1 are sampled on the rising edge of
RES. If both pins are asserted Low, the microcontroller
enters ONCE mode; otherwise, it operates normally.
In ONCE mode, all pins assume a high-impedance
state a nd rem ain in t hat stat e until a subs equent rese t
occurs. To guarantee that the microcontroller does not
inadvertently enter ONCE mode, ONCE0 has a weak
internal pullup resistor that is active only during reset.
This pin is not three-stated during a bus hold condition.
MCS0
(MCS0/PIO14)
Midrange Memory Chip Select 0 (output,
synchronous, internal pullup)
This pin indicates to the system that a memory access
is in progress to the corresponding region of the
midrange memory block. The base address and size of
the midrange memory block are programmable. On the
Am186ES microcontroller, MCS0 is configured for 8-bit
or 16-bit bus size by the auxiliary configuration register.
MCS0 is held High during a bus hold condition. In
addition, it has weak internal pullup resistors that are
active during reset.
This signal functions like the corresponding signal in
the Am186EM and Am188EM microcontrollers except
that MCS0 can be programmed as the chip select for
the entire middle chip select address range.
MCS2–MCS1
(MCS2/PIO24, MC S 1/PIO15)
Midrange Memory Chip Selects (output,
synchronous, internal pullup)
These pins indicate to the system that a memory
access is in progress to the corresponding region of the
midrange memory block. The base ad dress an d size of
the midrange memory block are pro grammable. On the
Am186ES microcontroller, MCS2–MCS1 are
configured for 8-bit or 16-bit bus size by the auxiliary
configuration register. MCS2–MCS1 are held High
during a bus hold condition. In addition, they have weak
internal pullup resistors that are active during reset.
These signals function like the signals in the Am186EM
and Am188EM microcontrollers except that if MCS0 is
programmed to be active for the entire middle chip-
select range, then these signals are available as PIOs.
If they are not programmed as PIOs and if MCS0 is
programmed for the whole middle chip-select range,
then these signals operate normally.
MCS3/RFSH/PIO25
Midrange Memory Chip Select 3
(output, synchronous, internal pullup)
Automatic Refresh (output, synchronous)
MCS3—This pin indicates to the system that a memory
access is in progress to the fourth region of the
midrange memory block. The base address and size of
the midrange memory block are programmable. On the
Am186ES microcontroller, MCS3 is configured for 8-bit
or 16-bit bus size by the auxiliary configuration register.
MCS3 is held High during a bus hold condition. In
addition, this pin has a weak internal pullup resistor that
is active during reset.
This signal functions like the corresponding signal in
the Am186EM and Am188EM microcontrollers except
that if MCS0 is programmed for the entire middle chip-
select range, then this signal is available as a PIO. If
MCS3 is not programmed as a PIO and if MCS0 is
programmed for the entire middle chip-select range,
then this signal operates normally. Depending on the
chip configuration, this signal can serve as a memory
RFSH.
RFSH—This pin provides a signal timed for auto
refresh to PSRAM or DRAM devices. It is only enabled
to function as a refresh pulse when the PSRAM or
DRAM mode bit is set. An active Low pulse is
32 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
generated for 1.5 clock cycles with an adequate
deassertion period to ensure that overall auto refresh
cycle time is met.
This signal functions like the RFSH signal in the
Am186EM and Am188EM microcontrollers except that
the DRAM row address is not driven on DRAM
refreshes. This pin is not three-stated during a bus hold
condition.
NMI
Nonmaskable Interrupt (input, synchronous,
edge-sensitive)
This pin indicates to the microcontroller that an
interrupt request has occurred. The NMI signal is the
highest priority hardware interrupt and, unlike the
INT6–INT0 pins, cannot be masked. The
microc ontroller a lways transf ers program execution to
the location specified by the nonmaskable interrupt
vector in the microcontroller interrupt vector table when
NMI is asserted.
Although NMI is the hi ghest prio rity in terr upt so urce , it
does not participate in the priority resolution process of
the maskable interrupts. There is no bit associated with
NMI in the interrupt in-service or interrupt request
registers. This means that a new NMI request can
interrupt an executing NMI interrupt service routine. As
with all hardware interrupts, the IF (interrupt flag) is
cleared when the processor takes the interrupt,
disabling the maskable interrupt sources. However, if
maskable int errupts are re-enabled by software in the
NMI inte rrup t se rvi ce ro uti ne, via t he ST I ins tru ctio n fo r
example, the fact that an NMI is currently in service
does not have any effect on the priority resolution of
maskable interrupt requests. For this reason, it is
strongly advised that the interrupt service routine for
NMI should not enable the maskable interrupts.
An NMI transition from Low to High is latched and
synchron ized internally, and it init iates the interrupt at
the next instruction boundary. To guarantee that the
interrupt is recognized, the NMI pin must be asserted
for at least one CLKOUTA period.
PCS1–PCS0
(PCS1/PIO17, PCS0/PIO16)
Peripheral Chip Selects (output, synchronous)
These pins indicate to the system that a memory
access is in progress to the corr esponding region of the
peripheral memory block (either I/O or memory
address space). The base address of the peripheral
memory block is programmable. PCS3–PCS0 are held
High during a bus hold condition. They are also held
High during reset.
Unlike the UCS and LCS chip sel ects, t he PCS outputs
assert with the mu lti pl exe d AD add re ss bus. Note al so
that each peripheral chip select asserts over a 256-
byte address range, which is twice the address rang e
cove red by peripher al chip s elects in the 80C186 and
80C188 micr oc ont ro ll ers.
PCS2/CTS1/ENRX1/PIO18
Peripheral Chip Select 2 (output, synchronous)
Clear-to-Send 1 (input, asynchronous)
Enable-Receiver-Request 1 (input, asynchronous)
PCS2— This pin prov ides the Peri phera l Chip Selec t 2
signal to the system when hardware flow control is not
enabled for asynchronous serial port 1. The PCS2
signal indicates to the system that a memory access is
in progress to the corresponding region of the
peripheral memory block (either I/O or memory
address space). The base address of the peripheral
memory block is programmable. PCS2 is held High
during a bus hold or reset condition.
Unlike the UCS and LCS chip sel ects, t he PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a 256-
byte address range, which is twice the address rang e
cove red by peripher al chip s elects in the 80C186 and
80C188 micr oc ont ro ll ers.
CTS1—This pin provides the Clear to Send signal for
asynch ronou s se rial port 1 wh en the ENRX1 bit in th e
AUXCON register is 0 and hardware flow control is
enabled fo r the port (FC b it in the seri al port 1 contr ol
register is set). The CTS1 signal gates the
transmission of data from the associated serial port
transmit register. When CTS1 is asserted, the
transmitter begins transmission of a frame of data, if
any is available. If CTS1 is deasserted, the transmitter
holds the data in the serial port transmit register. The
valu e of CTS 1 is check ed only at the begin ning of th e
transmission of the frame.
ENRX1—This pin provides the Enable Receiver
Request for asynchronous serial port 1 when the
ENRX1 bit i n the A UXCON r egister is 1 and hardwa re
flow c ontr ol is enab led f or th e por t (FC bit i n the ser ial
port 1 control register is set). The ENRX1 signal
enables the receiver for the associated serial port.
PCS3/RTS1/RTR1/PIO19
Peripheral Chip Select 3 (output, synchronous)
Ready-to-Send 1 (output, asynchronous)
Ready-to-Receive 1 (output, asynchronous)
PCS3— This pin prov ides the Peri phera l Chip Selec t 3
signal to the system when hardware flow control is not
enabled for asynchronous serial port 1. The PCS3
signal indicates to the system that a memory access is
in progress to the corresponding region of the
peripheral memory block (either I/O or memory
address space). The base address of the peripheral
memory block is programmable. PCS3 is held High
during a bus hold or reset condition.
Am186/188ES and Am186/188ESLV Microcontrollers 33
PRELIMINARY
Unlike the UCS and LCS chip sel ects, t he PCS outputs
assert with the mu lti pl exe d AD add re ss bus. Note al so
that each peripheral chip select asserts over a 256-
byte address range, which is twice the address range
covered by periphe ral chip selects in the 80C1 86 and
80C188 micr oc ontro ll er s.
RTS1—This pin provides the Ready to Send signal for
asynchronous serial port 1 when the RTS1 bit in the
AUXCON register is 1 and hardware flow control is
enabled fo r the port (FC b it in the seri al port 1 co ntrol
regi ster is se t). The RT S1 signa l is a sser ted wh en the
associated serial port transmit register contains data
which has not been transmitted.
RTR1—This pin p ro vides t he Ready t o Re cei v e sig nal
for asynchronous serial port 1 when the RTS1 bit in the
AUXCON register is 0 and hardware flow control is
enabled fo r the port (FC b it in the seri al port 1 co ntrol
regi ster i s se t). Th e RT R1 signal is asserted when the
associated serial port receive register does not contain
valid, unread data.
PCS5/A1/PIO3
Peripheral Chip Select 5 (output, synchronous)
Latched Address Bit 1 (output, synchronous)
PCS5—This pin indicates to the system that a memory
access is in progress to the sixth region of the
peripheral memory block (either I/O or memory
address space). The base address of the peripheral
memory block is programmable. PCS5 is held High
during a bus hold c onditi on. It is al so he ld Hig h d uring
reset.
Unlike the UCS and LCS chip sel ects, t he PCS outputs
assert with the mu lti pl exe d AD add re ss bus. Note al so
that each peripheral chip select asserts over a 256-
byte address range, which is twice the address range
covered by periphe ral chip selects in the 80C1 86 and
80C188 micr oc ontro ll er s.
A1—When the EX bit in the MCS and PCS auxiliary
register is 0, this pin supplies an internally latched
address bit 1 to the system. During a bus hold
condition, A1 retains its previously latched value.
PCS6/A2/PIO2
Peripheral Chip Select 6 (output, synchronous)
Latched Address Bit 2 (output, synchronous)
PCS6—This pin indicates to the system that a memory
access is in progress to the seventh region of the
peripheral memory block (either I/O or memory
address space). The base address of the peripheral
memory block is programmable. PCS6 is held High
during a bus hold condition or reset.
Unlike the UCS and LCS chip sel ects, t he PCS outputs
assert with the mu lti pl exe d AD add re ss bus. Note al so
that each peripheral chip select asserts over a 256-
byte address range, which is twice the address range
cove red by peripher al chip s elects in the 80C186 and
80C188 micr oc ont ro ll ers.
A2—When the EX bit in the MCS and PCS auxiliary
register is 0, this pin supplies an internally latched
address bit 2 to the system. During a bus hold
condition, A2 retains its previously latched value.
PIO31–PIO0 (Shared)
Programmable I/O Pins (input/output,
asynchronous, open-drain)
The Am186ES and Am188ES microcontrollers provide
32 individually programmable I/O pins. Each PIO can
be programmed with the following attributes: PIO
function (enabled/disabled), direction (input/output),
and weak pullup or pulldown. The pins that are
multiple xed wit h PIO31 –PI O0 are li sted in Table 2 an d
Table 3.
After power-on reset, the PIO pins default to various
configurations. The column titled
Power-On Reset
Status
in Table 2 and Table 3 lists the defaults for the
PIOs. Most of the PIO pins are configured as PIO
inputs with pullup after power-on reset. The system
initialization code must reconfigure any PIO pins as
required.
The A19–A17 address pins default to normal operation
on power-on res et, allowing the processo r t o correctly
begin fetching instructions at the boot address
FFFF0h. The DT/R, D EN, and SRDY pins al so def aul t
to normal operation on power-on reset.
34 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Table 2. Numeric PIO Pin Designations Table 3. Alphabetic PIO Pin Designations
Notes:
The following notes apply to both tables.
1. Thes e pi ns are us ed by emu la tors. (Em ulator s also us e S2–S0, RES, NMI, CLKOUTA, BHE, AL E, A D15–AD0,
and A16–A0.)
2. Thes e pins reve rt to normal operati on if BHE
/
ADEN (186) or RFSH 2/ADEN (188 ) is he ld Low du ring powe r-on
reset.
3. When used as a PIO, input with pullup option available.
4. When used as a PIO, input with pulldown option available.
PIO No Associated Pin Power-On Reset Status
0 TMRIN1 Input with pullup
1 TMROUT1 Input wi th pul ldo wn
2PCS
6/A2 Input with pullup
3PCS
5/A1 Input with pullup
4 DT/R Normal operation(3)
5DEN/DS Normal operation(3)
6 SRDY Normal operation(4)
7(1) A17 Normal operation(3)
8(1) A18 Normal operation(3)
9(1) A19 Normal operation(3)
10 TMROUT0 Input wi th pul ldo w n
11 TMRIN0 Input with pullup
12 DRQ0/INT5 Input with pullup
13 DRQ1/INT6 Input with pullup
14 MCS0 Input with pullup
15 MCS1 Input with pullup
16 PCS0 Input with pul lup
17 PCS1 Input with pul lup
18 PCS2/CTS1/ENRX1 Input with pullup
19 PCS3/RTS1/RTR1 Input with pul lup
20 RTS0/RTR0 Input with pul lup
21 CTS0/ENRX0 Input with pul lup
22 TXD0 Input with pullup
23 RXD0 Input with pul lup
24 MCS2 Input with pullup
25 MCS3/RFSH Inp ut wi th pul lup
26(1,2) UZI Input wi th pul lup
27 TXD1 Input with pullup
28 RXD1 Input with pul lup
29(1,2) S6/LOCK/CLKDIV2 Input with pullup
30 INT4 Input with pullup
31 INT2/INTA0/ PW D Input with pul lup
Associat ed Pin PIO No Power-On Reset Status
A17(1) 7 Normal operation(3)
A18(1) 8 Normal operation(3)
A19(1) 9 Normal operation(3)
CTS0/ENRX0 21 Input with pullup
DEN/DS 5 Normal operation(3)
DRQ0/INT5 12 Inp ut with pul lup
DRQ1/INT6 13 Inp ut with pul lup
DT/R 4 Normal operation(3)
INT2/INTA0/PWD 31 Input with pullup
INT4 3 0 Input with pullup
MCS0 14 Input with pullup
MCS1 15 Input with pullup
MCS2 24 Input with pullup
MCS3/RFSH 25 Input with pul lup
PCS0 16 Input with pul lup
PCS1 17 Input with pul lup
PCS2/CTS1/ENRX1 18 Input with pullup
PCS3/RTS1/RTR1 19 Input with pullup
PCS5/A1 3 Input with pullup
PCS6/A2 2 Input with pullup
RTS0/RTR0 20 Input with pullup
RXD0 2 3 Input with pullup
RXD1 2 8 Input with pullup
S6/LOCK/CLKDIV2(1,2) 29 Input with pullup
SRDY 6 Normal operation(4)
TMRIN0 11 Input with pullup
TMRIN1 0 Input with pul lup
TMROUT0 1 0 Input with pulldown
TMROUT1 1 Input with pulldown
TXD0 22 Input with pullup
TXD1 27 Input with pullup
UZI(1,2) 26 Input with pullup
Am186/188ES and Am186/188ESLV Microcontrollers 35
PRELIMINARY
RD
Read Strobe (output, synchronous, three-state)
RD—This pin indicates to the system that the
microcontroller is performing a memory or I/O read
cycle. RD is guaranteed t o not be asser ted befor e the
address and data bus is floated during the address-to-
data transition. RD floats during a bus hold condition.
RES
Reset (input, asynchronous, level-sensitive)
This pin requires the microcontroller to perform a reset.
When RES is asserted, the microcontroller
immediately terminates its present activity, clears its
internal logic, and transfers CPU control to the reset
address, FFFF0h.
RES must be held Low for at least 1 ms.
RES can be asserted asynchronously to CLKOUTA
because RES is synchronized internally. For proper
initialization, VCC must be within specifications, and
CLKOUTA must be stable for more than four
CLKOUTA periods during which RES is assert ed.
The microcontroller begins fetching instructions
approximately 6.5 CLKOUTA periods after RES is
deasserted. This input is provided with a Schmitt
trigger to facilitate power-on RES generation via an RC
network.
RFSH2/ADEN
(Am188ES Microcontroller Only)
Refresh 2 (three-state, output, synchronous)
Address Enable (input, internal pullup)
RFSH2—Asser ted Lo w to si gni fy a DRAM r efres h b us
cycle. The use of RFSH2/ADEN to signal a refresh is
not vali d when P SR AM mo de is sele cted. I nst ead, the
MCS3/RFSH signal is provided to the PSRAM.
ADEN—If RFSH2/ADEN is held High or left floating on
power-on reset, the AD bus (AO15–AO8 and AD7–
AD0) is enabled or disabled during the address portion
of LCS and UCS bus cycles based on the DA bit in the
LMCS and UMCS registers. If the DA bit is set, the
memory address is accessed on the A19–A0 pins. This
mode of operation reduces power consumption. For
more information, see the “Bus Operation” section on
page 39. There is a weak internal pullup resistor on
RFSH2/ADEN so no external pullup is required.
If RFSH2/ADEN is held Low on power-on reset, the AD
bus drives both ad dresse s and data , regar dles s of the
DA bit setting. The pin is sampled one crystal clock
cycle after the rising edge of RES. RFSH2/ADEN is
three-stated during bus holds and ONCE mode.
RTS0/RTR0/PIO20
Ready-to-Send 0 (output, asynchronous)
Ready-to-Receive 0 (output, asynchronous)
RTS0—This pin provides the Ready to Send signal for
asynchronous serial port 0 when the RTS0 bit in the
AUXCON register is 1 and hardware flow control is
enabled fo r the port (FC b it in the seri al port 0 contr ol
registe r is set) . The RTS 0 signa l is asser ted w hen the
associated serial port transmit register contains data
that has not been transmitted.
RTR0—This pi n provi de s t he Read y t o Re ce iv e s ig nal
for asynchronous serial port 0 when the RTS0 bit in the
AUXCON register is 0 and hardware flow control is
enabled fo r the port (FC b it in the seri al port 0 contr ol
registe r is se t). The RTR 0 signal is asserted when th e
associated serial port receive register does not contain
valid, unread data.
RXD0/PIO23
Receive Data 0 (input, asynchronous)
This pin supplies asynchronous serial receive data
from the system to asynchronous serial port 0.
RXD1/PIO28
Receive Data 1 (input, asynchronous)
This pin supplies asynchronous serial receive data
from the system to asynchronous serial port 1.
S2–S0
Bus Cycle Status (output, three-state,
synchronous)
These pins indicate to the system the type of bus cycle
in p rogres s. S2 can be used as a logical me mory or I/
O indi cator, and S1 c an be used as a data transm it or
receive indicator. S2–S0 float during bus hold and hold
acknowledge conditions. The S2–S0 pins are encoded
as shown in Table 4.
Table 4. Bus Cycle Encoding
S2S1S0 Bus Cycle
0 0 0 Interrupt acknowledge
0 0 1 Read data from I/O
0 1 0 Write data to I/O
011Halt
1 0 0 Instruction fetch
1 0 1 Read data from memory
1 1 0 Write data to memory
111None (passive)
36 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
S6/LOCK/CLKDIV2/PIO29
Bus Cycle Status Bit 6 (output, synchronous)
Bus Lock (output, synchronous)
Clock Divide by 2 (input, internal pullup)
S6—During the second and remaining periods of a
cycle (t2, t3, and t4), this pin is asserted High to indicate
a DMA-initiated bus cycle. During a bus hold or reset
condition, S6 floats.
LOCK—Thi s sig nal i s as serted Low t o in dicate to o ther
system bus masters that they are not to gain control of
the system bus. This signal is only available during t1.
LOCK on the Am186ES and Am188ES
microcont rollers does not conform to the timing of the
LOCK signal on the 80C186/188 microcontrollers. This
signal is primarily intended for use by emulators.
CLKDIV2—If S6/CLKDIV2/PIO29 is held Low during
power-on reset, the chip enters clock divided by 2
mode where the processor clock is derived by dividing
the external clock input b y 2. If this mode is selected,
the PLL is disabled. The pin is sampled on the rising
edge of RES.
If S6 is t o be us ed a s PIO 29 in input mode, the de vi ce
driving PIO29 must not drive the pin Low during power-
on reset. S6/CLKDIV2/PIO29 defaults to a PIO input
with pullup, so the pin does not need to be driven High
externally.
SRDY/PIO6
Synchronous Ready (input, synchronous,
level-sensitive)
This pin indicates to the microcontroller that the
addressed memory space or I/O device will complete a
data transfer. The SRDY pin accepts an active High
input synchronized to CLKOUTA .
Using SRDY instead of ARDY allows a relaxed system
timing be ca use of the el imina tion of the one-hal f cloc k
period required to internally synchronize ARDY. To
always assert the ready condition to the
microcont ro ll er, ti e S RDY High . If t he s y ste m d oes not
use SRDY, tie the pin Low to yield control to ARDY.
TMRIN0/PIO11
Timer Input 0 (input, synchronous, edge-sensitive)
This pin supplies a clock or control signal to the internal
microcontroller timer 0. After internally synchronizing a
Low-to-High tr a nsi ti on on TM RIN0, th e mi croc on tro ller
increm ents t he timer . TMRIN0 must be ti ed Hi gh if no t
being used. When PIO11 is enabled, TMRIN0 is pulled
High internally.
TMRIN 0 is driven in ternall y by INT2/I NTA0/PWD when
pulse width demodulation mode is enabled. The
TMRIN0/PIO1 1 pin can b e used as a P IO when pulse
width demodulation mode is enabled.
TMRIN1/PIO0
Timer Input 1 (input, synchronous, edge-sensitive)
This pin supplies a clock or control signal to the internal
microcontroller timer 1. After internally synchronizing a
Low-to-H igh t ra nsiti on on TM RIN1, th e mi cr oc on troll er
increm ents the ti mer. TMRIN1 m ust be ti ed Hi gh if no t
being us ed. When PIO0 i s enabled, TMRIN1 is pulled
High internally.
TMRIN1 is driven internally by INT2/INTA0/PWD when
pulse width demodulation mode is enabled. The
TMRIN1/PIO0 pin can be used as a PIO when pulse
width demodulation mode is enabled.
TMROUT0/PIO10
Timer Output 0 (output, synchronous)
This pin sup plies the sy stem w ith eith er a sin gle puls e
or a continuous waveform with a programmable duty
cycle. TMROUT0 is floated during a bus hold or reset.
TMROUT1/PIO1
Timer Output 1 (output, synchronous)
This pin sup plies the sy stem w ith eith er a sin gle puls e
or a continuous waveform with a programmable duty
cycle. TMROUT1 floats during a bus hold or reset.
TXD0/PIO22
Transmit Data 0 (output, asynchronous)
This pin sup plies a synchr onous seri al trans mit data t o
the system from serial port 0.
TXD1/PIO27
Transmit Data 1 (output, asynchronous)
This pin sup plies a synchr onous seri al trans mit data t o
the system from serial port 1.
UCS/ONCE1
Upper Memory Chip Select (output, synchronous)
ONCE Mode Request 1 (input, internal pullup)
UCS—This pin i ndicates to the system th at a memory
access is i n pr ogress to th e uppe r memor y bloc k. Th e
base addre ss and size of the upp er memo ry block are
programmable up to 512 Kbytes. UCS is held High
during a bus hold condition.
After reset, UCS is active for the 64 Kbyte memory
range from F0000h to FFFFFh, including the reset
address of FFFF0h.
ONCE1—During reset, this pin and LCS /ONCE0 indi-
cate to the micr ocontr oller the mod e in which it should
operate. ONCE0 and ONCE1 are sampled on the ris-
ing edge of RES. If b ot h pi ns ar e as se rted Lo w, th e mi -
crocontroller enters ONCE mode. Otherwise, it
operates normally. In ONCE mode, all pins a ssume a
high-impedance state and remain in that state until a
subsequent reset occurs. To guarantee that the micro-
Am186/188ES and Am186/188ESLV Microcontrollers 37
PRELIMINARY
controller does not inadvertently enter ONCE mode,
ONCE1 has a weak internal pullup resist or that is ac-
tive only during a reset. This pin is not three-stated dur-
ing a bus hold condition.
UZI/PIO26
Upper Zero Indicate (output, synchronous)
This pin lets the designer determine if an access to the
interrupt vector table is in progress by ORing it with bits
15–10 of the address and data bus (AD15–AD10 on
the 186 and AO15–AO10 on the 188). UZI is the l ogical
OR of the in verted A19–A 16 bits. It assert s in the first
period of a bus cycle and is held throughout the cycle.
This pin should be allowed to float or it should be pulled
High at reset. This pin has an internal pullup. If this pin
is Low at the negation of reset, the Am186ES and
Am188ES microcontrollers will en ter a reserved clock
test mode.
VCC
Power Supply (input)
These pins supply power (+5 V) to the microcontroller.
WHB (Am186ES Microcontroller Only)
Write High Byte (output, three-state, synchronous)
This pin and WLB indicate to the system which bytes of
the data bus (upper, lower, or both) participate in a
write cycle. In 80C186 microcontroller designs, this
information is provided by BHE, AD0, and WR.
However, by using WHB and WLB, the standard
system interface logic and external address latch that
were required are eliminated.
WHB is asserted with AD15–AD8. WHB is the logical
OR of BHE and WR. This pin floats during reset.
WLB (Am186ES Microcontroll er Only)
WB (Am188ES Microcontroll er Only)
Write Low Byte (output, three-state, synchronous)
Write Byte (output, three-state, synchronous)
WLB—This pin and WHB indica te to th e sys tem whic h
bytes of the data bus (upper, lower, or both) participate
in a write cycle. In 80C186 microcontroller designs, this
information is provided by BHE, AD0, and WR.
However, by using WHB and WLB, the standard
system interface logic and external address latch that
were required are eliminated.
WLB is asserted with AD7–AD0. WLB is the logical OR
of AD0 and WR. This pin floats during reset.
WB—On the Am188ES microcontroller, this pin
indicates a write to the bus. WB uses the same early
timing as the nonmultiplexed address bus. WB is
associated with AD7–AD0. This pin floats during reset.
WR
Write Strobe (output, synchronous)
WR—This pin i ndi ca tes t o t he sy s tem tha t t he data o n
the bus is to be written to a memory or I/O device. WR
floats during a bus hold or reset condition.
X1
Crystal Input (input)
This pin and the X2 pin provide connections for a
fundamenta l mode o r thi rd-overto ne, paral lel- resonan t
crystal used by the internal oscillator circuit. To provide
the microcontroller with an external clock source,
conne ct the sou rce t o the X1 pin and le ave the X2 pi n
unconnected.
X2
Crystal Output (output)
This pin and the X1 pin provide connections for a
fundamenta l mode o r thi rd-overto ne, paral lel- resonan t
crystal used by the internal oscillator circuit. To provide
the microcontroller with an external clock source, leave
the X2 pin unconnected and connect the source to the
X1 pin.
38 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
FUNCTIONAL DESCRIPTION
The Am186ES and Am188ES microcontrollers are
based on the architecture of the original Am186 and
Am188 microcontrollers—the 80C186 and 80C188 mi-
crocontrollers. The Am186ES and Am188ES micro-
controllers function in the enhanced mode of earlier
generations of Am186 and Am188 microcontrollers.
Enhanced mode includes system features such as
power-save control.
Each of the 8086, 8088, 80 186, and 80188 m icrocon-
trollers contains the same basic set of registers, in-
structions, and addressing modes. The Am186ES and
Am188ES microcontrollers are backward compatible
with the 80C186 and 80C188 microcontrollers.
A full description of all the Am186ES and Am188ES mi-
crocontroller registers and instructions is included in
the
Am186ES and Am188ES Microcontrollers User’s
Manual
, order# 21096.
Memory Organization
Memory is organized in sets of segments. Each seg-
ment is a linear contiguous sequence of 64K (216) 8-bit
bytes. Memory is addressed using a two-component
address that consis ts of a 16-bi t segment val ue and a
16-bit of fse t. The 16 -b it seg men t v al ues are co ntai ned
in one o f f our inte rnal segment regi sters (CS, DS, S S,
or ES). The physical address is calculated by shifting
the segment value left by 4 bits and adding the 16-bit
offset value to yield a 20-bit physical address (see Fig-
ure 3). This allows for a 1-Mbyte physical address size.
All instructions that address operands in memory must
specify the segment v alue and the 16- bit offset val ue.
For speed a nd compac t instruc tion en codin g, the se g-
ment register used for physical address generation is
implied by the addressing mode used (see Table 5).
Figure 3. Two-Component Address
I/O Space
The I/O space consists of 64K 8-bit or 32K 16-bit ports.
Separate instructions (IN, INS and OUT, OUTS) ad-
dress the I/O space with either an 8-bit port address
specified in the instruction, or a 16-bit port address in
the DX register. Eight-bit port addresses are zero-ex-
tended s uc h that A 15– A8 ar e Lo w. I/O p ort addresses
00F8h through 00FFh are reserved.
Table 5. Segment Register Selection Rules
1 2 A 4 0
0 0 0 2 2
1 2 A 6 2
1 2 A 4
0 0 2 2
Segment
Base Logical
Address
Shift
Left
4 Bits
Physical Address
To Memo ry
15 0
19 0
19 0
15 0
15 0
Offset
Memory Reference
Needed Segment Register Used Implicit Segment Selection Rule
Instructions Code (CS) Instructions (including immediate data)
Local Data Data (DS) All data references
Stack Stack (SS) All stack pushes and pops;
any memory references that use BP Register
External Data ( Global) Extra (ES) All string instru ction references t hat use the DI Re gister as an index
Am186/188ES and Am186/188ESLV Microcontrollers 39
PRELIMINARY
BUS OPERATION
The indus tr y-s tan dar d 80 C186 a nd 80C 188 mic roco n-
trollers use a multiplexed add ress and data (AD) bus.
The addres s is prese nt on the A D bus only during the
t1 clock phase. The Am186ES and Am188ES micro-
control lers conti nu e to pr ov id e th e m ulti pl exed AD b us
and, in ad dit ion , pr ovi de a nonmultiple xe d addres s (A)
bus. The A b us p rovide s an a ddres s to t he system for
the complete bus cycle (t1–t4).
For systems where power consumption is a concern, it
is possible to disable the address from being driven on
the AD bus on the Am186ES microcontroller and on the
AD and AO buses on the Am188ES microcontroller
during the normal address portion of the b us cycle for
accesses to UCS and/or LCS address spaces. In this
mode, the affecte d bus is placed in a high-imp edance
state duri ng the address porti on of the bus cycle . This
feature is enabled through the DA bits in the UMCS and
LMCS registers. When address disable is in effect, the
number of signals that assert on the bus during all nor-
mal bus c ycles to th e assoc iated addr ess space is re-
duced, decreasing power consumption and reducing
processor switching noise. On the Am188ES micro-
controller, the address is driven on A015–A08 during
the data portio n of the bu s cy c le regar d less of the s et-
ting of the DA bits.
If the ADEN p in is pulled Low during processo r reset,
the value of the DA bits in the UMCS and LMCS regis-
ters is ignored and the address is driven on the AD bus
for all acc ess es , t hus pr es ervi ng the industry-st anda r d
80C186 an d 80C188 microc ontrollers ’ multiple xed ad-
dress bus and providing support for existing emulation
tools.
The following diagrams show the Am186ES and
AM188ES microcontroller bus cycles when the ad-
dress bus disable feature is in effect:
nFigure 4 shows the affected signals during a normal
read or wr ite oper ation for an Am186ES microco n-
troller. The address and data are multiplexed onto
the AD bus.
nFigure 5 shows an Am186ES microcontroller bus
cycle when address bus disable is in effect. This re-
sults in the AD bus operating in a nonmultiplexed
address/data mode. The A bus has the address
during a read or write operation.
nFigure 6 shows the affected signals during a normal
read or wr ite oper ation for an Am188ES microco n-
troller. The mul tip le xe d a ddres s /dat a m ode i s co m-
patible with the 80C186 and 80C188
microc ontrollers an d might be used to take adva n-
tage of existing logic or peripherals.
nFigure 7 shows an Am188ES microcontroller bus
cycle when address bus disable is in effect. The ad-
dress and data is not multiplexed. The AD7–AD0
signals have only data on the bus, while the AO bus
has the address during a read or write operation.
Figure 4. Am186ES Microcontroller Address Bus—Normal Read and Write Operation
CLKOUTA
t1t2t3t4
AD15–AD0
(Read) Data
AD15–AD0
(Write)
LCS or UCS
Address
DataAddress
Address
Phase Data
Phase
A19–A0 Address
MCSx, PCSx
40 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Figure 5. Am186ES Microcontroller—Read and Write with Address Bus Disable In Effect
Figure 6. Am188ES Microcontroller Address Bus—Normal Read and Write Operation
CLKOUTA
t1t2t3t4
AD15–AD0
(Write) Data
LCS, UCS
AD15–AD0
(Read)
Address
Phase
Data
Data
Phase
A19–A0 Address
MCSx, PCSx
CLKOUTA
t1t2t3t4
AD7–AD0
(Read) Data
AO15–AO8
(Rea d or Write)
AD7–AD0
(Write)
Address
Address
DataAddress
Address
Phase Data
Phase
A19–A0 Address
LCS or UCS
MCSx, PCSx
Am186/188ES and Am186/188ESLV Microcontrollers 41
PRELIMINARY
Figure 7. Am188ES Microcontroller—Read and Write with Address Bus Disable In Effect
BUS INTERFACE UNIT
The bus interface unit controls all accesses to external
peripherals and memory devices. External accesses
include those to memory devices, as well as those to
memory- mappe d and I/O- mappe d peri pherals and the
peripheral control block. The Am186ES and Am188ES
microcontrollers provide an enhanced bus interface
unit with the following features:
nA nonmultiplexed address bus
nOn the Am186ES microcontroller, a static bus-siz-
ing option for 8-bit and 16-bit memory and I/O
nSeparate b yte w rite enabl es f or h igh and l ow by tes
in the Am186ES microcontroller only
nPseudo Static RAM (PSRAM) support
The standa rd 80C186/188 microcontrol ler multiplex ed
address and data bus requires system interface logic
and an external address latch. On the Am186ES and
Am188ES microcontrollers, new byte write enables,
PSRAM control logic, and a new nonmultiplexed ad-
dress b us can reduce d esign cost s by elimin ating this
external logic.
Nonmultiplexed Address Bus
The nonmultiplexed address bus (A19–A0) is valid one-
half CLKOUTA cycle in advance of the address on the
AD bus. When used in conjunction with the modified
UCS and LCS outputs and the byte-write enable sig-
nals, the A19–A0 bus provides a seamless interface to
SRAM, PSRAM, and Flash EPROM memory systems.
Static Bus Sizing
The 80C186 microcontroller provided a 16-bit wide
data bus over its entire address range, memory, and
I/O, but did not allow accesses to an 8-bit wide bus.
The 80C188 microcontroller provided a lower-cost in-
terface by r educing the data bus width to 8 bit s, again
over the entire address range. The Am188ES micro-
controller follows the 80C188 microcontroller in provid-
ing an 8-bit data bus to all memory and peripherals.
However, the Am186ES microcontroller differs from
the 80C186 microcontroller in allowing programmabil-
ity for data bus widths through fields in the auxiliary
configuration (AUXCON) register, as shown in Table 6.
The width of the data access should not be modified
whil e th e proc essor is f etchi ng in struc tions from the as-
sociated address space.
CLKOUTA
t1t2t3t4
AD7–AD0
(Read) Data
Address
AO15–AO8
LCS, UCS
AD7–AD0
(Write) Data
Address
Phase Data
Phase
A19–A0 Address
MCSx, PCSx
42 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Table 6. Programming Am186ES Microcontroller
Bus Width
Byte-Write Enables
The Am186ES microcontroller provides the WHB
(Write High Byte) and WLB (Write Low Byte) signals,
which act as byte-write enables.
WHB is the logical OR of BHE and WR. WHB is Low
when BHE and WR are both Low. WLB is the logical
OR o f A0 an d WR . WLB is Low when A0 and WR are
both Low. WB is Low whenever a byte is written on the
Am188ES microcontroller.
On the Am188ES microcontroller, the WB (Write Byte)
pin indicates a write to the bus. WB uses the same
early timing as the nonmulitplexed address bus. WB is
associated with AD7–-AD0. This pin floats during reset.
The byte-write enables are driven in conjunction with
the nonmultiplexed address bus as required for the
write timing requirements of common SRAMs.
Pseudo Static RAM (PSRAM) Support
The Am186ES and Am188ES microcontrollers support
the use of PSRAM device s in low mem ory ch ip-selec t
(LCS) space only. When PSRAM mode is enabled, the
timing for the LCS signal is modified by the chip-select
control unit to provide a CS precharge period during
PSRAM accesses. The 40-MHz timing of the
Am186 ES a nd Am 188ES mic rocontr olle rs is approp ri-
ate to allow 70-ns PSRAM to run with one wait state.
PSRAM mode is enabled through a bit in the Low Mem-
ory Chip-Select (LMCS) register. The PSRAM feature
is disabled on CPU reset.
In addition to the LCS timing changes for PSRAM pre-
charge, the PSRAM devices also require periodic re-
fresh of a ll internal row a ddresses to r etain their data .
Although refresh of PSRAM can be accomplished sev-
eral wa ys, the A m186ES and Am 188ES m icrocontro l-
lers implement auto refresh only.
The Am186E S and Am1 88ES microc ontrollers ge ner-
ate a refresh signal, RFSH, to the PSRAM devices
when PSRAM mode and the refresh control unit are
enabled. No refresh address is required by the PSRAM
when using the auto refresh mechanism. The RFSH
signal is multiplexed with the MCS3 signal pin. When
PSRAM mode is enabled, MCS3 is not available for
use as a chip-select signal.
The refresh control unit must be programmed before
access ing PSRAM in LCS s pace . The r efre sh coun ter
in the clock prescaler (CDRAM) register must be con-
figured with the required refresh interval value. The
ending a ddr es s of LCS s pa ce an d the ready and wai t-
state generation in the LMCS register must also be pro-
grammed. The refresh counter reload value in the
CDRAM register should not be set to less than 18 (12h)
in order to prov ide time for proce ssor cycles within re-
fresh. The refresh address counter must be set to
000000h to prevent another chip select from asserting.
LCS is held High during a refr esh cycle. Th e A bus is
not used during refresh cycles. The LMCS register
must be configured to external ready ignored (R2=1)
with one wait state (R1–R0=01b), and the PSRAM
mode enable bit (PSE) must be set to 1.
PERIPHERAL CONTROL BLOCK (PCB)
The integrated peripherals of the Am186ES and
Am188ES microcontrollers are controlled by 16-bit
read/write registers. The peripheral registers are con-
tained within an internal 256-byte control block. The
registers are physically located in the peripheral de-
vices they control, b ut they are ad dressed as a single
256-byte block. Table 7 shows a map of these regis-
ters.
Reading and Writing the PCB
Code that is i nte nde d to e xe cut e o n the Am 188 ES m i-
crocon troller s hould perfo rm all writes t o the P CB reg-
isters as byte writes. These writes transfer 16 bits of
data to the PCB register even if an 8-bit register is
named in the instruction. For example, out dx, al results
in the value of ax being written to the port address in dx.
Reads to the PCB should be done as word reads. Code
written i n this manner runs correctly on th e Am188ES
microcontroller and on the Am186ES microcontroller.
Unaligned reads and writes to the PCB result in unpre-
dictable behavior on both the Am186ES and Am188ES
microcontrollers.
For a complete description of all the registers in the
PCB, see the
Am186ES and Am188ES Microcontrol-
lers User’s Manual
, order# 21096.
Space AUXCON
Field Value Bus
Width Comments
UCS – – 16 bits not
configurable
LCS LSIZ 0 16 bits default
1 8 bits
I/O IOSIZ 0 16 bits default
1 8 bits
Other MSIZ 0 16 bits default
1 8 bits
Am186/188ES and Am186/188ESLV Microcontrollers 43
PRELIMINARY
Table 7. Peripheral Control Block Register Map
Notes:
1. The register has been changed from the Am186EM
and Am188EM microcontrollers.
2. The register is new.
Note: All unus ed addresses are re served and s hould
not be accessed.
Register Na me Offset
Processor Control Registers:
Peripheral control block relocation register FEh
Reset configu rati on re gister F6h
Pro cessor release level register 1F4h
Auxiliary configuration register 2F2h
System configuration register 1F0h
Watchdog timer control register 2E6h
Enable RCU register 1E4h
Clock prescaler register E2h
Memory partition register E0h
DMA Registers:
DMA 1 control register 1DAh
DMA 1 transfer count register D8h
DMA 1 destination address high register D6h
DMA 1 destination address low regi ster D4h
DMA 1 source address high regi ster D2h
DMA 1 source address low register D0h
DMA 0 control register 1CAh
DMA 0 transfer count register C8h
DMA 0 destination address high register C6h
DMA 0 destination address low regi ster C4h
DMA 0 source address high regi ster C2h
DMA 0 source address low register C0h
Chip-Select Registers:
PCS and MCS auxiliary register A8h
Midrange memory chip-select register A6h
Peripheral chip-select register A4h
Low memory chip-sel ect regist er 1A2h
Upper memory chip-select register A0h
Serial Port 0 Registers:
Serial port 0 baud rate divisor register 188h
Serial port 0 receive register 186h
Serial port 0 transmit register 184h
Serial port 0 status register 182h
Serial port 0 control register 180h
PIO Registers:
PIO data 1 register 7Ah
PIO direction 1 register 78h
PIO mode 1 register 76h
PIO data 0 register 74h
PIO direction 0 register 72h
PIO mode 0 register 70h
Timer Registers:
Timer 2 mode/control register 66h
Timer 2 max count compare A register 62h
Timer 2 count register 60h
Timer 1 mode/control register 5Eh
Timer 1 max count compare B register 5Ch
Timer 1 max count compare A register 5Ah
Timer 1 count register 58h
Timer 0 mode/control register 56h
Timer 0 max count compare B register 54h
Timer 0 max count compare A register 52h
Timer 0 count register 50h
Interrupt Registers:
Serial port 0 interrupt control register 144h
Serial port 1 interrupt control register 242h
INT4 interrupt control register 40h
INT3 control register 3Eh
INT2 control register 3Ch
INT1 control register 3Ah
INT0 control register 38h
DMA1/INT6 interrupt control register 136h
DMA0/INT5 interrupt control register 134h
Timer interrupt control register 32h
Interrupt status register 30h
Interrupt request register 12Eh
Interrupt in-service register 12Ch
Interrupt priority mask register 2Ah
Interrupt mask register 128h
Interrupt poll status register 26h
Interrupt poll register 24 h
End-of-interrupt register 22h
Interrupt vector register 20h
Serial Port 1 Registers:
Serial port 1 baud rate divisor register 218h
Serial port 1 receiv e regis ter 216h
Serial port 1 transmit register 214h
Serial port 1 status regi ster 212h
Serial port 1 control regist er 210h
Register Name Offset
44 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
CLOCK AND POWER MANAGEMENT
The clock and power management unit of the
Am186ES and Am188ES microcontrollers includes a
phase -locke d loop (PLL ) and a s econd prog ramma ble
system clock output (CLKOUTB).
Phase-Locked Loop (PLL)
In a traditional 80C186/188 microcontroller design, the
crystal frequency is twice that of the desired internal
clock. Because of the internal PLL on the Am186ES
and Am188ES microcontrollers, the internal clock gen-
erated by the Am186ES and Am188ES microcontrol-
lers (CLKO UTA) is the same frequenc y as the crystal.
The PLL takes the crystal inputs (X1 and X2) and gen-
erates a 45–5 5% (worst case) duty cycle intermedi ate
system clock of the same frequency. This removes the
need for an external 2x oscillator, reducing system
cost. The PLL is reset during power-on reset by an on-
chip power-on reset (POR) circuit.
Crystal-Drive n Clock Source
The internal oscillator circuit of the Am186ES and
Am188ES microcontrollers is designed to function with
a parallel resonant fundamental or third overtone crys-
tal. Because of the PLL, the crystal frequency should
be equal to the pro cessor freq uency . Do not replac e a
crystal with an LC or RC equivalent.
The signals X1 and X2 are connected to an internal in-
verting amplifier (oscillator) that provides, along with
the external feedback loading, the necessary phase
shift (F igur e 8) . I n su ch a positiv e f eedback c irc ui t, the
inverting amplifier has an output signal (X2) 180 de-
grees out of phase of the input signal (X1).
The external feedb ack network provides an additional
180-degree phase shift. In an ideal system, the input to
X1 will have 360 or zero degrees of phase shift. The ex-
ternal feedback network is designed to be as close to
ideal as possible. If the feedback network is not provid-
ing necessary phase shift, negative feedback dampens
the output of the amplifier and negatively affects the op-
eration of the clock generator. Values for the loading on
X1 and X2 must be chosen to provide the necessary
phase shift and crystal operation.
Selecting a Crystal
When se le cting a c rystal , the load c apac itanc e sho uld
always be specified (CL). This value can cause vari-
ance in the oscillation frequency from the desired spec-
ified valu e (resonance) . The load capacit ance and the
loading o f the fee dbac k net wor k hav e th e fol lo win g r e-
lationship:
wher e CS is the stray capacitance of the circuit. Placing
the crysta l an d CL i n s er ie s a cros s the i nv er tin g am pl i-
fier and tuning these values (C1, C2) allows the crystal
to oscillate at resonance. This relationship is true for
both fundamental and third-overtone operation. Finally,
ther e is a relat ions hip bet ween C1 and C2. To enhance
the oscillation of the inverting amplifier, these values
need to be offset with the larger load on the output (X2).
Equal values of these loads tend to balance the poles
of the inverting amplifier.
The characteristics of the inverting amplifier set limits
on the following parameters for crystals:
ESR (Equivalent Series Resistance) ......40 Ω max
Drive Level..............................................1 mW max
The rec ommended range of values for C 1 and C2 are
as follows:
C1..................................................................15 pF ± 20%
C2..................................................................22 pF ± 20%
The speci fic v alu es for C1 an d C2 mu st be determi ne d
by the designer and are dependent on the characteris-
tics of the chosen crystal and board design.
Figure 8. Am186ES and Am188ES Microcontrollers Oscillator Configurations
(C1 ⋅ C2)
(C1 + C2)
CL = + CS
Crystal
Am186ES
200 pF
Note 1
Note 1: Use for Third Overtone Mode
XTAL Frequency L1 Value (Max)
20 MHz 12
µ
H ±20%
25 MHz 8.2
µ
H ±20%
33 MHz 4.7
µ
H ±20%
40 MHz 3.0
µ
H ±20%
X1
X2
b. Crystal Configuration
a. Inverting Amplif ier Configurati on
C1C2
Crystal
C1
C2Microcontroller
Am186/188ES and Am186/188ESLV Microcontrollers 45
PRELIMINARY
External Source Clock
Alternately, the internal oscillator can be driven from an
external clock source. This source should be con-
nected to the inp ut of the inverting ampl ifier (X1), with
the output (X2) not connected.
Syst em Clocks
The base sy stem clock of A MD’s origin al 80C186 and
80C188 microcontrollers is renamed CLKOUTA and
the additional output is called CLKOUTB. CLKOUTA
and CLKOUTB operate at either the processor fre-
quency or the PLL frequency. The output drivers for
both cloc ks are ind ividual ly program mable for disable .
Figure 9 shows the organization of the clocks.
The second clock output (CLKOUTB) allows one clock
to run at the P LL frequenc y and the othe r clock to run
at the power-save frequency. Individual drive enable
bits allow selective enabling of just one or both of these
clock outp uts .
Power-Save Operation
The power-save mode of the Am186ES and Am188ES
microcontrollers reduces power consumption and heat
dissipation, thereby extending battery life in portable
systems. In power-save mode, operation of the CPU
and internal peripherals continues at a slower clock fre-
quency. W hen an interrupt oc curs, the microcon troller
automatically returns to its normal operating frequency
on the internal clock’s next rising edge of t3.
Note: Power-save operation requires that clock-de-
pendent devices be reprogrammed for clock frequency
changes . S oft war e driv er s must b e awar e o f c l ock fr e-
quency.
Initialization and Processor Reset
Processor initialization or startup is accomplished by
drivin g t he RES inpu t pi n Low. RE S must be held Low
for 1 ms during po wer-up to ensure proper device ini-
tialization. RES forces the Am186ES and Am188ES
microcontrollers to terminate all execution and local
bus activity. No instruction or bus activity occurs as long
as RES is active. After RES b ecomes inactive and a n
internal processing interval elapses, the microcontrol-
ler begin s executi on with the instructio n at phys ical lo-
cation FFFF0h, with UCS asserted with three wait
states. RES also sets some registers to predefined val-
ues and resets the watchdog timer.
The Reset Configuration Register
When the RES input is asserted Low, the contents of
the addr ess/d ata bu s (AD1 5–AD0) are w ritten into the
reset configuration register. The system can place con-
figuration information on the address/data bus using
weak external pullup or pulldown resistors, or using an
external driver that is enabled during reset. The pro-
cessor does n ot drive t he add ress/data bus dur ing re-
set.
For examp le, the reset configu ration registe r could be
used to provide the software with the position of a con-
figuration switch in the system. Using weak external
pullup and pulldown resistors on the address and data
bus, the syste m can pr ovide the mi croco ntroller with a
value c orrespon ding to th e position of the ju mper dur-
ing a reset.
Figure 9. Clock Organization
PLL Power-Save
Divisor
(/2 to /128 )
Mux
CLKOUTA
CLKOUTB
Drive
Enable
Drive
Enable
X1, X2
Processor Internal Clock
Time
Delay
6 ± 2.5ns
Mux
46 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
CHIP-SELECT UNIT
The Am186ES and Am188ES microcontrollers contain
logic that provides programmable chip-select genera-
tion for bo th memories and peripherals. The l ogic can
be programmed to provide ready and wait-state gener-
ation and latched address bits A1 and A2. The chip-se-
lect lines are active for all memory and I/O cycles in
their programmed areas, whether they are generated
by the CPU or by the integrated DMA unit.
The Am186ES and Am188ES microcontrollers provide
six chip-select outputs for use with memory devices
and six more for use with peripherals in either memory
space or I/O space. The six memory chip selects can
be used to address three memory ranges. Each periph-
eral c hip s el ec t a ddr ess es a 256 - byt e block th at is o ff-
set from a programmable base address. A write to a
chip sel ect registe r will enable the c orrespondin g chip
select lo gic even if the ac tual pin has another funct ion
(e.g., PIO).
Chip-Select Timing
The timing for the UCS and LCS outputs is modified
from the original 80C186 microcontroller. These out-
puts now assert in conjunction with the nonmultiplexed
address bus for normal memory timing. To allow these
outputs to be available earlier in the bus cycle, the num-
ber of programmable memory size selections has been
reduced.
Ready and Wait-State Programming
The Am186ES and Am 188ES micr ocontroll ers can be
programmed to sense a ready signal for each of the
peripheral or me mory ch ip-s elect lines . The read y sig-
nal can be either the ARDY or SRDY signal. Each chip-
select control register (UMCS, LMCS, MMCS, PACS,
and MPCS) contains a single-bit field that determines
whether the external ready signal is required or
ignored.
The number of wait stat es to be inserted for each ac-
cess to a perip heral or me mory regio n is pro gramma-
ble. The chip-select control registers for UCS, LCS,
MCS3–MCS0, PCS6, and PCS5 contain a two-bit field
that determines the number of wait states from zero to
three to be inserted. PCS3–PCS0 use three bits to pro-
vide additional values of 5, 7, 9, and 15 wait states.
When external ready is required, internally pro-
grammed wait states will always complete before exter-
nal ready can terminate or extend a bus cycle. For
example, if the internal wait states are set to insert two
wait stat es, the proc essor sampl es the exter nal ready
pin during the first wait cycle. If external ready is as-
serted a t that time, the a ccess completes after six cy-
cles (four cycles plus two wait states). If external ready
is not asserted during the first wait cycle, the access is
extended until ready is asserted, and one more wait
state occurs followed by t4.
The ARDY si gn al o n th e A m18 6ES an d A m18 8E S m i-
crocontrollers is a true asynchronous ready signal. The
ARDY pin accep ts a rising edge that is asynch ronous
to CLKOUTA and is active High. If the falling edge of
ARDY is not synchronized to CLKOUTA as specified,
an additional clock period may be added.
Chip-Select Ove rlap
Although progr ammin g the var ious chip select s on the
Am186ES microcontroller so that multiple chip select
signals are asserted for the same p hysical address is
not recommended, it may be unavoidable in some sys-
tems. In such systems, the chip selects whose asser-
tions overlap must have the same configuration for
ready (external ready required or not required) and the
number of wait states to be inserted into the cycle by
the processor.
The peripheral control block (PCB) is accessed using
internal signals. These internal signals function as chip
selects configured with zero wait states and no external
ready. The refore, the PCB can be progr ammed to ad-
dresses that overlap external chip-select signals only if
those external chip selects are programmed to zero
wait states with no external ready required.
When over lapping an addi tional chip sel ect with either
the LCS or UCS chip sel ects, it must be note d that set-
ting the Disable Address (DA) bit in the LMCS or UMCS
registe r disables the addre ss from be ing drive n on the
AD bus for all access es for which the associate d chip
select is asserted, including any accesses for which
multiple chip selects assert.
The MCS and PCS c hip -sel ec t pi ns can b e c onfi gured
as either chip selects (normal function) or as PIO inputs
or outputs. It should be noted; however, that the ready
and wait state generation logic for these chip selects is
in effect regardless of their configurations as chip se-
lects or PIOs. This means that if these chip selects are
enabled (by a write to the MMCS and MPCS for the
MCS chip selects, or by a write to the PACS and MPCS
registers for the PCS chip selects ), th e r e ady a nd wai t
state programming for these signals must agree with
the programming for any other chip selects with which
their assertion would overlap if they were configured as
chip selects.
Although the PCS4 si gn al i s n ot av ai la ble on a n ex ter -
nal pin, the ready and wait state logic for this signal still
exists internal to the part. For this reason, the PCS4 ad-
dress spac e must follo w the r ules for o verlapp ing c hip
selects. The ready and wait-state logic for PCS6–
PCS5 is disabled when these signals are configured as
address bits A2–A1.
Failure to configure overlapping chip selects with the
same ready and wait state requirements may cause
the processor to hang with the appearance of waiting
Am186/188ES and Am186/188ESLV Microcontrollers 47
PRELIMINARY
for a ready signal . This behavior may occur even in a
system in which ready is always asserted (ARDY or
SRDY tied High).
Configuring PCS in I/O space with LCS or any other
chip select configured for memory address 0 is not con-
sidered overlapping of the chip selects. Overlapping
chip selects refers to configurations where more than
one chip select asserts for the same physical address.
Upper Memory Chip Select
The Am186ES and Am188ES microcontrollers provide
a UCS chip selec t for the to p of memory . On reset the
Am186ES and Am188ES microcontrollers begin fetch-
ing and executing instructions at memory location
FFFF0h. Therefore, upper memory is usually used as
instruction memory. To facilitate this usage, UCS de-
faults to active on reset, with a default memory range of
64 Kbytes from F0000h to FFFFFh, with external ready
required and three wait states automatically inserted.
The UCS memo ry rang e a lways ends at FFFFFh. The
UCS lower boundary is programmable.
Low Memory Chip Select
The Am186ES and Am188ES microcontrollers provide
an LCS chip select for lower memory. The AUXCON
register can be used to configure LCS for 8-bit or 16-bit
access es. S inc e t he i nte rrup t v ect or tab le i s loc at ed a t
the bottom of mem ory starti ng at 000 00h, the LCS pin
is us ual ly use d to co ntro l dat a memo ry . The LC S pin is
not active on reset.
Midrange Memory Chip Se lects
The Am186ES and Am188ES microcontrollers provide
four chip selects, MCS3–MCS0, for use in a user-lo cat-
able memory block. With some exceptions, the base
address of the memory block can be located anywhere
within the 1-Mbyte memory address space of the
Am186ES and Am188ES microcontrollers. The areas
associated with the UCS and LCS chip sele cts are ex-
cluded. If they are mapped to memory, the address
range of the peripheral chip selects, PCS6, PCS5, and
PCS3–PCS0, are also excluded. The MCS address
range can overlap the PCS a ddress range if the PCS
chip selects are mapped to I/O space.
MCS0 ca n be confi gured to be asserted fo r the entire
MCS range. When configured in this mode, the MCS3–
MCS1 pins can be used as PIOs.
The AUXC ON register can b e used to conf igure MCS
for 8-bit or 16-bit ac cess es. The bus width of the MCS
range is de termi ned by the widt h of the n on- UCS /no n-
LCS memory range.
Unlike the UCS and LCS chip selects, the MCS outputs
assert with the s ame ti mi ng as th e m ul tip lexed AD a d-
dress bus.
Peripheral Chi p Selec ts
The Am186ES and Am188ES microcontrollers provide
six chip selects, PCS6–PCS5 and PCS3–PCS0, for
use within a user-configured memory or I/O block.
PCS4 is not available on the Am186ES and Am188ES
microcontrollers. The base address of the memory
block can be located anywhere within the 1-Mbyte
memory address space, exclusive of the areas associ-
ated with the UCS, LCS, and MCS chip s elects, or the y
can be configured to access the 64-Kbyte I/O space.
The PCS pins are not active on reset. PCS6–PCS5 can
be programmed for zero to three wait states. PCS3–
PCS0 can be programmed for four additional wait-state
values: 5, 7, 9, and 15.
The AUXCON register can be used to configure PCS
for 8-bit or 16-bit access es. The bus wid th of the PCS
range is de termi ned by the wid th of the non- UCS /no n-
LCS memory range or by the width of the I/O area.
Unlike the UCS and LCS chip sel ects, t he PCS outputs
assert with the multiplexed AD address bus. Each
peripheral chip select asserts over a 256-byte address
range, which is twice the address range covered by
peripheral chip selects in the 80C186/188 microcon-
trollers.
REFRESH CONTROL UNIT
The Refresh Control Unit (RCU) automatically gener-
ates refresh bus cycles. After a programmable period
of time, the RCU generate s a memory read request to
the bus interface unit. The RCU is fixed to three wait
states for the PSRAM auto refresh mode.
In the Am186ES and Am188ES microcontrollers, re-
fresh is enabl ed when the ENA bit is se t in the enable
RCU register, offset E4h. This is different from the
Am186EM and Am188EM microcontrollers where the
PSRAM e nable bi t in the low memor y chip-se lect reg-
ister, of fset A2 h, enabl es refresh . The refres h func tion
is the same as on the Am186EM and Am188EM micro-
controllers, except that the DRAM address is not driven
on DRAM refreshes.
If the HLDA pin is active when a refresh request is gen-
erated ( in dic at ing a b us hol d c on di tion), the Am 186 ES
and Am188ES microcontrollers deactivate the HLDA
pin in order to perform a refresh cycle. The external bus
master must remo ve the HOLD si gnal for at least one
clock in order to allow the refresh cycle to execute.
48 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
INTERRUPT CONTROL UNIT
The Am186ES and A m18 8ES mi cr ocon tro ller s can r e-
ceive interrupt requests from a variety of sources, both
internal and external. The internal interrupt controller
arranges these requests by priority and presents them
one at a time to the CPU.
There are up to eight exte rn al inte rrupt sour ce s o n the
Am186ES and Am188ES microcontrollers—seven
maskable interrupt pins and one nonmaskable interrupt
(NMI) pin. In addi tion, t here a re eight inter nal i nterrup t
sources (three timers, two DMA channels, the two
asynchronous serial ports, and the Watchdog Timer
NMI) that are not connected to external pins. INT5 and
INT6 are multiplexed with DRQ0 and DRQ1. These two
interrupts are availabl e if the associated DMA is not en-
abled or is being used with internal synchronization.
The Am186ES and Am188ES microcontrollers provide
up to six interrupt sou rces no t present on the 80 C186
and 80C188 microcontrollers. There are up to three ad-
ditional exter na l int er rupt pin s— INT4, INT5, and INT6 .
These pins ope rate mu ch li ke the INT3 –INT0 interr upt
pins on the 80C186 and 80C188 microcontrollers.
There are also two internal interrupts from the serial
ports and the watchdog timer can generate interrupts.
The seven maskable interrupt request pins can be
used as direct interrupt requests. INT4–INT0 can be ei-
ther edge triggered or level triggered. INT6 and INT5
are edge triggered only. In addition, INT0 and INT1 can
be configured in cascade mode for use with an external
82C59A-com patible interrupt controller. Wh en INT0 is
configured in cascade mode, the INT2 pin is automati-
cally configured in its INTA0 function. When INT1 is
configured in cascade mode, the INT3 pin is automati-
cally configured in its INTA1 function. An external inter-
rupt controller can be used as the system master by
programming the internal interrupt controller to operate
in slave mode. INT6–INT4 are not available in slave
mode.
Interrupts are automatically disabled when an interrupt
is taken. Interrupt-service routines (ISRs) may
re-enable interrupts by setting the IF flag. This allows
interrupts of greater or equal priority to interrupt the
currently executing ISR. Interrupts from the same
source are disabled as long as the corresponding bit in
the interrupt in-service register is set. INT1 and INT0
provide a special bit to enable special fully nested
mode. When configured in special fully nested mode,
the interrupt source may generate a new interrupt
regardless of the setting of the in-service bit.
TIM E R CONTROL UNIT
There are three 16-bit programmable timers and a
watchdog timer on the Am186ES and Am188ES micro-
controllers.
Timer 0 and timer 1 are connected to four external pins
(each one has an input and an output). These two tim-
ers can be used to count or time external events, or to
generate nonrepetitive or variable-duty-cycle wave-
forms. When pulse width demodulation is enabled,
timer 0 and timer 1 are used to measure the width of
the High and Low pulses on the PWD pin. (See the
Pulse Width Demodulation section on page 51.)
Timer 2 is not connected to any external pins. It can be
used for real-time coding and time-delay applications.
It can also be used as a pres c al er to ti me rs 0 a nd 1 or
to synchronize DMA transfers.
The programmable timers are controlled by eleven 16-
bit registers in the peripheral control block. A timer’s
timer-count register contains the current value of that
timer. The timer-count register can be read or written
with a value at any time, whether the timer is running or
not. The microcontroller increments the value of the
timer-count register each time a timer event occurs.
Each timer also has a maximum-count register that de-
fines the maximum value the timer can reach. When
the timer reaches the maximum value, it resets to 0
during the same clock cycle. The value in the maxi-
mum-count register is never stored in the timer-count
registe r. Also, ti mers 0 and 1 have a secondar y maxi-
mum-count register. Using both the primary and sec-
ondary maximum-count registers lets the timer
alternate between two maximum values.
If the timer is programmed to use only the primary max-
imum-count register, the timer output pin switches Low
for one clock cycle after the maximum value is
reached . If the tim er is progr ammed to us e both of its
maximum-count registers, the output pin indicates
which maximum-count register is currently in control,
thereby creating a waveform. The duty cycle of the
waveform depends on the values in the maximum-
count regis te rs .
Each timer is serviced every fourth clock cycle, so a
timer can operate at a speed of up to one-quarter of the
internal clock frequency. A timer can be clocked exter-
nally at this same frequency; however, because of in-
ternal synchronization and pipelining of the timer
circuitry, the timer output can take up to six clock cycles
to respond to the clock or gate input.
Am186/188ES and Am186/188ESLV Microcontrollers 49
PRELIMINARY
Watchdog Timer
The Am186ES and Am188ES microcontrollers provide
a true watchdog timer function. The Watchdog Timer
(WDT) can be used to regain control of the system
when software fails to respond as expected. The WDT
is active after reset. It can only be modified a single
time by a keyed sequence of writes to the watchdog
timer control register (WDTCON) following reset. This
single write can either disable the timer or modify the
timeout period and the action taken upon timeout. A
keyed sequence is also required to reset the current
WDT count. This behavior ensures that randomly exe-
cuting code will not prevent a WDT event from occur-
ring.
The WDT supports up to a 1.67-second timeout period
in a 40-MHz system. After reset, the WDT is enabled
and the timeout period is set to its maximum value.
The WDT can be configured to cause either an NMI in-
terrupt or a system reset upon timeout. If the WDT is
configured for NMI, the NMIFLAG in the WDTCON reg-
ister is se t when t he NMI is g enera ted. The NMI inter -
rupt service routine (ISR) should examine this flag to
determine if the interrupt was generated by the WDT or
by an external source. If the NMIFL AG is set, the ISR
should clear the flag by writing the correct keyed se-
quence to the WDTCON register. If the NMIFLAG is set
when a second WDT timeout occurs, a WDT system
reset is generated rather than a second NMI event.
When the proc essor takes a WD T reset, ei ther due to
a single WDT event with the WDT configured to gener-
ate resets or due to a WDT event with the NMIFLAG
set, the RSTFLAG in the WDTCON register is set. This
allows system initialization code to differentiate be-
tween a hardware reset and a WDT reset and take ap-
propriate action. The RSTFLAG is cleared when the
WDTCON register is read or written. The processor
does not resample external pins during a WDT reset.
This means that the clocking, the reset configuration
register, and any other features that are user-select-
able dur ing reset do not c hange when a W DT system
reset occurs. All other activities are identical to those of
a normal system reset.
Note: The Watchdog Timer (WDT) is active after re-
set.
DIRECT MEMORY ACCESS (DMA)
Direct memory access (DMA) permits transfer of data
between memory and peripherals without CPU involve-
ment. The DMA unit in the Am186ES and Am188ES
microcontrollers, shown in Figure 10, provides two
high-speed DMA channels. Data transfers can occur
between memory and I/O spaces (e.g., memory to I/O)
or within the sa me space (e .g., memor y to memor y or
I/O to I/O). The DMA channels can be directly con-
nected to the asynchronous serial ports.
Either bytes or words can be transferred to or from
even or odd addresses on the Am186ES microcon-
troller. However, the Am186ES microcontroller does
not support word DMA transfers to or from memory
configured for 8-bit accesses. The Am188ES micro-
controller does not support word transfers. Only two
bus cycles (a mi nimum of eight clocks) ar e necess ary
for each data transfer.
Each channel accepts a DMA request from one of four
sources: the channel request pin (DRQ1–DRQ0),
Timer 2, a serial port, or the system software. The
channels can be programmed with different priorities in
the event of a simultan eous DMA request or if there is
a need to interrupt transfers on the other channel.
DMA Operation
Each channel has six registers in the peripheral control
block that define specific channel operations. The DMA
registers consist of a 20-bit source address (two regis-
ters), a 20-bit destination address (two registers), a 16-
bit transfer count register, and a 16-bit control register.
The DMA transfer count register (DTC) specifies the
number of DMA transfers to be performed. Up to 64K
of byte or word transfers can be performed with auto-
matic termination. The DMA control registers define the
chann el oper ation. A l l r e gi st e rs ca n be mo d if i ed dur-
ing any DMA activity. Any changes made to the DMA
registers are reflected immediately in DMA operation.
Table 8. Am186ES Microcontroller Maximum
DMA Transfer Rates
Type of Synchronization
Selected
Maximum DMA
Transfer Rate (Mbytes)
40
MHz 33
MHz 25
MHz 20
MHz
Unsynchronized 10 8.25 6.25 5
Source Synch 10 8.25 6.25 5
Destination Synch
(CPU needs bus) 6.6 5.5 4.16 3.3
Destination Synch
(CPU does not need bus) 8 6.6 5 4
50 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Figure 10. DMA Unit Block Diagram
DMA Channel Control Registers
Each DMA control register determines the mode of op-
eration for the particul ar DMA channel. The DMA con-
trol registers specify the following:
nThe mode of synchronization
nWhether bytes or words are transferred
nWhether an interrupt is generated after the last
transfer
nWhether the DRQ pins are configured as INT pins
nWhether DMA activity ceases after a programmed
number of DMA cycles
nThe relative priority of the DMA channel with re-
spect to the other DMA channel
nWhether the source address is incremented, decre-
mented, or maintained constant after each transfer
nWhether the source address addresses memory or
I/O space
nWhether the destination address is incremented,
decremented, or maintained constant after trans-
fers
nWhether the destination address addresses mem-
ory or I/O space
DMA Priority
The DMA channels can be programmed so that one
chann el is alw ays given prior ity over the other, or t hey
can be programmed to alternate cycles when both
have DMA requests pending. DMA cycles always have
priority over internal CPU cycles except between
locked memory accesses or word accesses to odd
memory locations. However, an external bus hold
takes priority over an internal DMA cycle.
Because an interrupt request cannot suspend a DMA
operatio n and the CP U ca nnot a ccess memory dur ing
a DMA cycle, interrupt latency time suffers during se-
quences of continuous DMA cycles. An NMI request,
howeve r, causes all in ternal DMA acti vity to halt. This
allows the CPU to respond quickly to the NMI request.
Source Address Ch. 1
Source Address Ch. 0
20-bit Adder/Subtractor
DMA
Control
Logic
Request
Selection
Logic
Adder Control
Logic
20
20
Channel Control Register 1
Channel Control Register 0
16
DRQ1/Serial Port
DRQ0/Serial Port
Internal Address/Data Bus
Timer Request
Interrupt
Request
Transfer Coun ter Ch. 1
Destination Address Ch. 1
Destination Address Ch. 0
Transfer Coun ter Ch. 0
Am186/188ES and Am186/188ESLV Microcontrollers 51
PRELIMINARY
PULSE WIDTH DEMODULATION
For many applicati ons, such as bar-code readin g, it is
necessar y to measure th e width of a signa l in both its
High and Low phases. The Am186ES and Am188ES
microcontrollers provide a pulse-width demodulation
(PWD) option to fulfill this need. The PWD bit in the
system configuration register (SYSCON) enables the
PWD option. Please note that the Am186ES and
Am188ES microcontrollers do not support analog-to-
digital conversion.
In PWD mod e, TM RIN0, TMRIN1 , INT2, and INT4 a re
configured internal to the microcontroller to support the
detection of risin g and falli ng edg es on th e PWD i nput
pin (INT2/INTA0/PWD) and to enable either timer 0
when the signal is High or timer 1 when the signal is
Low. The INT4, TMRIN0, and TMRIN1 pins are not
used in PWD mode and so are available for use as
PIOs.
The following diagram shows the behavior of a system
for a typical waveform.
The interrupt service routine (ISR) for the INT2 and
INT4 interrupts should examine the current count of the
associated timer, timer 1 for INT2 and timer 0 for INT4,
in order to deter mine the pulse width. The IS R should
then reset the timer count register in preparation for the
next pulse.
Since the tim ers coun t at one quarter of the process or
clock rate, this determines the maximum resolution that
can be obtained. Further, in applications where the
pulse width may be short, it may be necessary to poll
the INT2 and INT4 request bits in the interrupt request
registe r in order to avoi d the overhea d involve d in tak-
ing and returning from an interrupt. Overflow condi-
tions, where the pulse width is greater than the
maximum count of the tim er , ca n be dete cte d by mo n-
itoring the Maximum Count (MC) b it in the associated
timer or by s etting the INT bit to enable time r interrupt
requests.
ASYNCHRONOUS SERIAL PORTS
The Am186ES and Am188ES microcontrollers provide
two independent asynchronous serial ports. These
ports provide full-duplex, bidirectional data transfer
using several industry-standard communications pro-
tocols. The serial ports can be used as sources or des-
tinations of DMA transfers.
The asynchronous serial ports support the following
features:
nFull-duplex operation
n7-bit, 8-bit, or 9-bit data transfers
nOdd, even, or no parity
nOne stop bit
nTwo lengths of break characters
nError detection
— Parity e rrors
— Framing errors
— Overrun errors
nHardware handshaking with the following select-
able control signals:
— Clear-to-send (CTS)
— Enable-r ece iv er- request (ENRX)
— Ready-to-send (RTS)
— Ready-to-receive (RTR)
nDMA to and from the serial ports
nSeparate maskable interrupts for each port
nMultidrop protocol (9-bit) support
nIndependent baud rate generators
nMaximum baud rate of 1/16th of the CPU clock
nDouble-buffered transmit and receive
DMA Transfers through the Serial Port
The Am186ES and Am188ES microcontrollers support
DMA transfe rs both to and from the serial port. Either
or both DMA channels and either or both serial ports
can be used for DMA transmits or receives. See the
DMA Control register descriptions in the
Am186ES and
Am188 ES M icro co ntr ol le rs User’ s Manual
for more in-
formation.
INT2 INT4 INT2 Ints generated
TMR1 enabled
TMR0 enabled
52 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
PROGRAMMABLE I/O (PIO) PINS
There are 32 pins on the Am186ES and Am188ES mi-
crocontrollers that are available as user-programmable
I/O signals. Table 2 on page 34 and Table 3 on
page 34 list the PIO pins. Each of these pins can be
used as a user-pr ogrammab le input or output s ignal if
the normal shared function is not needed.
If a pin is enable d to function as a PIO signal , the pre-
assigned signal function is disabled and does not affect
the level on the pi n. A P IO s ign al ca n b e c onf igu red to
operate as an input or output with or without a weak
pullup or pulldown, or as an open-drain output.
After power-on reset, the PIO pins default to various
configurations. The column titled
Power-On Reset Sta-
tus
in Table 2 on page 34 and Table 3 on page 34 lists
the defaults for the PIOs. The system initialization code
must reconfigure the PIOs as required.
The A19–A17 address pins default to normal operation
on power-on res et, allowing the processo r t o correctly
begin fetching instructions at the boot address
FFFF0h. The DT/R, DEN, and SRDY pi ns also default
to normal operation on power-on reset.
Note that emula tors use A19, A18, A17, S6, an d U ZI.
In environments where an emulator is needed, these
pins must be configured for normal function—not as
PIOs.
If the AD15–AD0 bus overri de is enable d on powe r-on
reset, then S6/CLKDIV2 and UZI revert to normal oper-
ation instead of PIO input with pullup. If BHE/ADEN
(186) or RFSH2/ADEN (188) is held Low during power-
on reset, the AD15–AD0 bus override is enabled.
Am186/188ES and Am186/188ESLV Microcontrollers 53
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage temperature
Am186ES/Am188ES.......................–65°C to +125°C
Am186ESLV/Am188ESLV..............–65°C to +125°C
Voltage on any pin with respect to ground
Am186/188ES............................–0.5 V to Vcc +0.5 V
Am186/188ESLV .......................–0.5 V to Vcc +0.5 V
Note: Stresses above those listed under Absolute
Maximum Ratings may cause permanent device fail-
ure. Functionality at or above these limits is not implied.
Exposure to absolute maximum ratings for extended
periods may affect device reliability.
OPERATING RANGES
Operating Ranges define those limits between which
the functionality of the device is guaranteed.
Am186ES/Am1 88E S Micr ocontroller s
Commercial (TC).................................0°C to +100°C
Industrial* (TA) ..................................–40°C to +85°C
VCC up to 33 MHz......................................5 V ± 10%
VCC greater than 33 MHz ............................5 V ± 5%
Am186ESLV/Am188ESLV Microcontrollers
Commercial (TA) ...................................0°C to +70°C
VCC up to 25 MHz................................. 3.3 V ± 0.3 V
Where: TC = case temperature
TA = ambient temperature
*Industrial versions of Am186ES and Am188ES
microcontrollers are available in 20 and 25 MHz operating
frequencies only.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Notes:
a The LCS/ONCE0, MCS3–MCS0, UCS/ONCE1, and RD pins have weak internal pullup resistors. Loading the LCS/ONCE0
and UCS/ONCE1 pins in exc es s of I
OH
= – 200
µ
A during reset can cause the device to go into ONCE mode.
b Current is measured wi th the device in RESET with X1 a nd X2 driven and all othe r non-power pin s open but held High or Low.
c Testing is performed with the pins floating, either during HOLD or by invoking the ONCE mode.
d Power supply current for the Am186ESLV and Am188ESLV microcontrollers, which are available in 20 and 25 MHz operating
frequencies only.
Symbol Parameter Description Test Conditions
Preliminary
UnitMin Max
V
IL
Input Low Voltage (Except X1) –0.5 0.8 V
V
IL
1Clock Input Low Voltage (X1) –0.5 0.8 V
V
IH
Input High Voltage (Except RES and X1) 2.0 VCC +0.5 V
V
IH
1Input High Voltage (RES)2.4V
CC +0.5 V
V
IH
2Clock Input High Voltage (X1) VCC –0.8 VCC +0.5 V
VOL
Output Low Voltage
Am186ES and Am188ES IOL= 2 .5 mA (S2–S0)
IOL= 2.0 mA (others) 0.45 V
Am186ESLV and Am188ESLV IOL= 1.5 m A (S2–S0)
IOL= 1.0 mA (others) 0.45 V
VOH
Output High Voltage(a)
Am186ES and Am188ES IOH= –2.4 mA @ 2.4 V 2.4 VCC +0.5 V
IOH= –200 µA @
V
CC
–0.5 VCC –0.5 VCC V
Am186ESLV and Am188ESLV IOH= –200 µA @
V
CC
–0.5 VCC –0.5 VCC V
ICC
Power Supply Current @ 0°C
Am186ES and Am188ES VCC = 5.5 V (b) 5.9 mA/MHz
Am186ESLV and Am188ESLV VCC = 3.6 V (b) 2.75 mA/MHz
ILI Input Leakage Current @ 0.5 MHz 0.45 V≤VIN≤
V
CC
±10 µA
ILO Output Leakage Current @ 0.5 MHz 0.45 V≤VOUT≤
V
CC
(c) ±10 µA
VCLO Cloc k Out put Low ICLO= 4.0 mA 0. 4 5 V
VCHO Clock Output High ICHO= –500 µAV
CC –0.5 V
54 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Capacitance
Note:
Capacitance limits are guaranteed by characterization.
Power Supply Current
For the fol lo win g ty pi ca l s y st em s pe ci fi cat ion s hown in
Figure 11, ICC has been meas ured at 4.0 mA p er MHz
of system clock. For the following typical system
specification shown in Figure 12, ICC has been
measured at 5.9 mA per MHz of system clock. The
typical system is measured while the system is
executing code in a typical application with maximum
voltage and maximum case temperature. Actual power
supply current is dependent on system design and may
be greater or less than the typical ICC figure presented
here.
Typical current in Figure 11 is given by:
ICC = 4.0 mA ⋅ freq(MHz)
Typical current in Figure 12 is given by:
ICC = 5.9 mA ⋅ freq(MHz)
Please note that dynamic ICC measurements are de-
pendent upon chip activity, operating frequency, output
buffer logic, and capacitive/resistive loading of the out-
puts. For these ICC measurements, the devices were
set to the following modes:
nNo DC loads on the output buffers
nOutput capacitive load set to 35 pF
nAD bus set to data only
nPIOs are disabled
nTimer, serial port, refresh, and DMA are enabled
Table 9 shows the variables that are used to calculate
the typical power consumption value for each version
of the Am186ESLV and Am188ESLV microcontrollers.
Table 9. Typical Power Consumption Calculation
for the Am186ESLV and Am188ESLV
Figure 11. Typical ICC Versus Frequency for the
Am186ESLV and Am188ESLV
Figure 12. Typical Icc Versus Frequency for Am186ES and Am188ES
Preliminary
Symbol Parameter Description Test Conditions Min Max Unit
CIN Input Capacitance @ 1 MHz 10 pF
CIO Output or I/O Capacitance @ 1 MHz 20 pF
MHz ⋅ ICC ⋅ Volts / 1 000 = P Typical Power
in Watts
MHz Typical ICC Volts
20 4.0 3.6 0.288
25 4.0 3.6 0.360
Clock Frequency (MHz)
ICC (mA)
25 MHz
20 MHz
0
20
40
60
80
100
120
140
10 20 30
Clock Frequency (MHz)
ICC (mA)
25 MHz
33 MHz
20 MHz
40 MHz
0
40
80
120
160
200
240
280
10 20 30 40 50
Am186/188ES and Am186/188ESLV Microcontrollers 55
PRELIMINARY
THERMAL CHARACTERISTICS
TQFP Package
The Am186ES and Am188ES microcontrollers are
specified for operation with case temperature ranges
from 0°C to +100°C for a commercial device. Case
temperature is measured at the top center of the
package as shown in Figure 13. The various
temperatures and thermal resistances can be
determined using the equations in Figure 14 with
information given in Table 10.
θJA is the total thermal resistance. θJA is the sum of θJC,
the internal thermal resistance of the assembly, and
θCA, the case to ambient thermal resistance.
The variable
P
is power in watts. Typical power supply
current (ICC) is TBD mA per MHz of clock frequency.
Figure 13. Thermal Resistance(°C/Watt)
Figure 14. Thermal Characteristics Equations
Table 10. Thermal Characteristics (°C/Watt)
θJA θCA
θJC
θJA = θJC + θCA
TC
Package/Board
Airflow
(Linear Feet
per Minute) θJA θJC θCA
PQFP/2-Layer 0 fpm 4 5 7 38
200 fpm 39 7 32
400 fpm 35 7 28
600 fpm 33 7 26
TQFP/2-Layer 0 fp m 56 10 46
200 fpm 461036
400 fpm 401030
600 fpm 381028
PQFP/4-Layer
to 6-Layer 0 fpm 23518
200 fpm 21 5 16
400 fpm 19 5 14
600 fpm 17 5 12
TQFP/4-Layer
to 6-Layer 0 fpm 30624
200 fpm 28 6 22
400 fpm 26 6 20
600 fpm 24 6 18
θJA = θJC + θCA
P=ICC ⋅ freq (MHz) ⋅
V
CC
TJ=TC+( P ⋅θJC )
TJ=TA+ ( P⋅θJA )
TC=TJ–( P⋅θJC )
TC=TA+( P ⋅θCA )
TA=TJ–( P⋅θJA )
TA=TC–( P⋅θCA )
56 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Typical Ambient Temperatures
The typical ambient temperature specifications are
based on the following assumptions and calculations:
The commer cia l o perati ng ra nge of the Am 186E S and
Am188ES microcontrollers is a case temperature TC of
0 to 100 degree s Centigrade. TC is measured at the top
center of the package. An increase in the ambient
temperature causes a proportional increase in TC.
The 40-MHz microcontroll er is specified as 5.0 V plus
or minus 5%. Th erefore, 5.25 V is use d for cal culating
typical power consumption on the 40-MHz
microcontroller.
Microcontrollers up to 33 MHz are specified as 5.0 V
plus or minus 10%. Therefore, 5.5 V is used for
calculating typical power consumption up to 33 MHz.
Typical power supply current (ICC) in normal usage is
estimated at 5.9 mA per MHz of microcontroller clock
rate.
Typical power consumption (watts) = (5.9 mA/MHz)
times microcontroller clock rate times voltage divided
by 1000.
Table 11 shows the variables that are used to calculate
the typical power consumption value for each version
of the Am186ES and Am188ES microcontrollers.
Table 11. Typical Power Consumption
Calculation
Thermal resistance is a measure of the ability of a
package to remove heat from a semiconductor device.
A safe operating range for the device can be calculated
using the f or mul as fr om Fi gure 1 4 an d the variab les in
Table 10.
By using the maximum case rating TC, the typical
power consumption value from Table 11, and θJC from
Table 10, the junction temperature TJ can be
calculated by using the following formula from Figure
14.
TJ = TC + (P ⋅ θJC)
Table 12 shows TJ values for the various versions of
the Am186ES and Am188ES microcontrollers. The
column titled
Speed/Pkg/Board
in Table 12 indicates
the clock speed in MHz, the type of package (P for
PQFP and T for TQFP), and the type of board (2 for 2-
layer and 4-6 for 4-layer to 6-layer).
Table 12. Junction Temperature Calculation
By using TJ from Table 12, the typical power
consumption value from Table 11, and a θJA value from
Table 10, the typical ambient temperature TA can be
calculated using the following formula from Figure 14:
TA = TJ – (P ⋅ θJA)
For exampl e, TA for a 40-MHz PQFP des ign with a 2-
layer board and 0 fpm airflow is calculated as follows:
TA = 108.673 – (1.239 ⋅ 45)
TA = 52.918
In this calculation, TJ comes from Table 12, P comes
from Table 11, and θJA comes from Table 10. See Tab le
13.
TA for a 33-MHz TQFP design with a 4-layer to 6-layer
board and 200 fpm airflow is calculated as follows:
TA = 106.4251 – (1.07085 ⋅ 28)
TA = 76.4413
See Table 16 for the result of this calculation.
Table 13 through Table 16 and Figure 15 through
Figure 18 show TA based on the preceding
assumptions and calculations for a range of θJA values
with air flow from 0 line ar feet per m inute to 600 line ar
feet per minute.
P = MHz ⋅ ICC ⋅ Volts / 1000
Typical
Power (P) in
Watts
MHz Typical ICC Volts
40 5.9 5.25 1.239
33 5.9 5.5 1.07085
25 5.9 5.5 0.81125
20 5.9 5.5 0.649
Speed/
Pkg/
Board TJ
TJ = TC + (P ⋅ θJC)
TC P θJC
40/P2 108.673 100 1.239 7
40/T2 112.39 100 1.239 10
40/P4-6 106.195 100 1.239 5
40/T4-6 107.434 100 1.239 6
33/P2 107.49595 100 1.07085 7
33/T2 110.7085 100 1.07085 10
33/P4-6 105.35425 100 1.07085 5
33/T4-6 106.4251 100 1.07085 6
25/P2 105.67875 100 0.81125 7
25/T2 108.1125 100 0.81125 10
25/P4-6 104.05625 100 0.81125 5
25/T4-6 104.8675 100 0.81125 6
20/P2 104.543 100 0.649 7
20/T2 106.49 100 0.649 10
20/P4-6 103.245 100 0.649 5
20/T4-6 103.894 100 0.649 6
Am186/188ES and Am186/188ESLV Microcontrollers 57
PRELIMINARY
Table 13 s hows typi cal m aximu m ambient tem perature s in degr ees Centigrad e for a PQFP pac kage used on a 2-
layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature.
Figure 15 graphically illustrates the typical temperatures in Table 13.
Table 13. Typical Ambient Temperatures for PQFP with a 2-Layer Board
Figure 15. Typical Ambient Temperatures for PQFP with a 2-Layer Board
Microcontroller
Speed Typical Power
(Watts)
Linear Feet per Minute Airflow
0 fpm 200 fpm 400 fpm 600 fpm
40 MHz 1.239 52.918 60.352 65.308 67.786
33 MHz 1.07085 59.3077 65.7328 70.0162 72.1579
25 MHz 0.81125 69.1725 74.04 77.285 78.9075
20 MHz 0.649 75.338 79.232 81.828 83.126
Airflow (Linear Feet Per Minute)
0 fpm 200 fpm 400 fpm 600 fpm
Typical Ambient Temperature (Degrees C)
●40 MHz
■20 MHz
◆25 Mhz
✵33 MHz
Legend:
40
50
60
70
80
90
●
●
●●
✶
✶
✶✶
◆
◆
◆◆
■
■■■
58 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Table 14 s hows typi cal max imum ambien t temp eratures in degrees Centig rade for a TQ FP pac kage used on a 2-
layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature.
Figure 16 graphically illustrates the typical temperatures in Table 14.
Table 14. Typical Ambient Temperatures for TQFP with a 2-Layer Board
Figure 16. Typical Ambient Temperatures for TQFP with a 2-Layer Board
Microcontroll er
Speed Typical Power
(Watts)
Linear Feet per Minute Airflow
0 fpm 200 fpm 400 fpm 600 fpm
40 MHz 1.239 43.006 55.396 62.83 65.308
33 MHz 1.07085 50.7409 61.4494 67.8745 70.0162
25 MHz 0.81125 62.6825 70.795 75.6625 77.285
20 MHz 0.649 70.146 76.636 80.53 81.828
Airflow (Linear Feet Per Minute)
●
●
●
●
✶
✶
✶✶
◆
◆
◆◆
■
■
■■
0 fpm 200 fpm 400 fpm 600 fpm
●40 MHz
■20 MHz
◆25 Mhz
✵33 MHz
Legend:
40
50
60
70
80
90
Typical Ambient Temperature (D egrees C)
Am186/188ES and Am186/188ESLV Microcontrollers 59
PRELIMINARY
Table 15 s hows typi cal m aximu m ambient tem perature s in degr ees Centigrad e for a PQFP pac kage used on a 4-
layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case
temperature. Figure 17 graphically illustrates the typical temperatures in Table 15.
Table 15. Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board
Figure 17. Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board
Microcontroller
Speed Typical Power
(Watts)
Linear Feet per Minute Airflow
0 fpm 200 fpm 400 fpm 600 fpm
40 MHz 1.239 77.698 80.176 82.654 85.132
33 MHz 1.07085 80.7247 82.8664 85.0081 87.1498
25 MHz 0.81125 85.3975 87.02 88.6425 90.265
20 MHz 0.649 88.318 89.616 90.914 92.212
0 fpm 200 fpm 400 fpm 600 fpm
Typical Ambient Temperature (Degrees C)
●40 MHz
■20 MH z
◆25 Mhz
✵33 MHz
Legend:
70
75
80
85
90
95
Airflow (Linea r Feet Per Minute)
●
●
●
●
✶
✶
✶
✶
◆
◆
◆
◆
■■
■■
60 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Table 16 s hows typi cal max imum ambien t temp eratures in degrees Centig rade for a TQ FP pac kage used on a 4-
layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case
temperature. Figure 18 graphically illustrates the typical temperatures in Table 16.
Table 16. Typical Ambient Temperatures for TQFP with a 4-Layer to 6-Layer Board
Figure 18. Typical Ambient Temperatures for TQFP with a 4-Layer to 6-Layer Board
Microcontroll er
Speed Typical Power
(Watts)
Linear Feet per Minute Airflow
0 fpm 200 fpm 400 fpm 600 fpm
40 MHz 1.239 70.264 72.742 75.22 77.698
33 MHz 1.07085 74.2996 76.4413 78.583 80.7247
25 MHz 0.81125 80.53 82.1525 83.775 85.3975
20 MHz 0.649 84.424 85.722 87.02 88.318
0 fpm 200 fpm 400 fpm 600 fpm
Typical Ambient Temperature ( Degrees C)
70
75
80
85
90
95
●40 MHz
■20 MHz
◆25 Mhz
✵33 MHz
Legend:
Airflow (Linear Feet Per Minute)
●
●
●
●
✶
✶
✶
✶
◆
◆
◆
◆
■■■
■
Am186/188ES and Am186/188ESLV Microcontrollers 61
PRELIMINARY
COMMERCIAL SWITCHING CHARACTERISTICS AND WAVEFORMS
In the switching waveforms that follow, several
abbrevi ations are use d to indicate the specific periods
of a bus cycle. These periods are referred to as time
states. A typical bus cycle is composed of four
consecutive time states: t1, t2, t3, and t4. Wait states,
which represent multiple t3 states, are referred to as tw
states. W hen no bu s cy cle is pe ndi ng, an id le (t i) state
occurs.
In the switching parameter descriptions, the
multiplexed
address is referred to as the AD address
bus; the
demultiplexed
address is referred to as the A
address bus.
Key to Switching Waveforms
Must be
Steady
May
Change
from H to L
May
Change
from L to H
Does Not
Apply
Don’t Care,
Any Change
Permitted
Will be
Steady
Will be
Changing
from H to L
Will be
Changing
from L to H
Changing,
State
Unknown
Center
Line is High-
Impedance
Off
State
WAVEFORM INPUT OUTPUT
Invalid Invalid
62 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Alphabetical Key to Switching Parameter Symbols
Parameter Symbol No. Description
tARYCH 49 ARDY Resolution Transition Setup Time
tARYCHL 51 ARDY Inactive Holding Time
tARYHDSH 95 ARDY High to DS High
tARYHDV 89 ARDY Assert to Data Valid
tARYLCL 52 ARDY Setup Time
tARYLDSH 96 ARDY Low to DS High
tAVBL 87 A Address Valid to WHB, WLB Low
tAVCH 14 AD Address Valid to Clock High
tAVLL 12 AD Address Valid to ALE Low
tAVRL 66 A Address Valid to RD Low
tAVWL 65 A Address Valid to WR Low
tAZRL 24 AD Address Float to RD Active
tCH1CH2 45 CL KOUTA Rise Time
tCHAV 68 CLKOUTA High to A Address Valid
tCHCK 38 X1 High Time
tCHCL 44 CLKOUTA High Time
tCHCSV 67 CLKOUTA High to LCS/UCS Valid
tCHCSX 18 MCS/PCS Inactive Delay
tCHCTV 22 Co ntro l Active D elay 2
tCHCV 64 Comman d Lines Valid Delay (after Float)
tCHCZ 63 Comman d Lines Float Delay
tCHDX 8Status Hold Time
tCHLH 9ALE Active Delay
tCHLL 11 ALE Inactive Delay
tCHRFD 79 CLKOUTA High to RFSH Valid
tCHSV 3Status Active Delay
tCICOA 69 X1 to CLKOUTA Skew
tCICOB 70 X1 to CLKOUTB Skew
tCKHL 39 X1 Fall Time
tCKIN 36 X1 Period
tCKLH 40 X1 Rise Time
tCL2CL1 46 CL KOUTA Fall Time
tCLARX 50 ARDY Active Hold Time
tCLAV 5AD Address Valid Delay
tCLAX 6Address Hold
tCLAZ 15 AD Address Float Dela y
tCLCH 43 CLKOUTA Low Time
tCLCK 37 X1 Low Time
tCLCL 42 CLKOUTA Period
tCLCLX 80 LCS Inactive Delay
tCLCSL 81 LCS Active Delay
Am186/188ES and Am186/188ESLV Microcontrollers 63
PRELIMINARY
Alphabetical Key to Switching Parameter Symbols (continued)
Parameter Symbol No. Description
tCLCSV 16 MCS/PCS Active Delay
tCLDOX 30 Data Hold Time
tCLDV 7Data Valid Delay
tCLDX 2Data in Hold
tCLHAV 62 HLDA Valid Delay
tCLRF 82 CLKOUTA High to RFSH Invalid
tCLRH 27 RD Inactive Delay
tCLRL 25 RD Active Delay
tCLSH 4Status Inactive Delay
tCLSRY 48 SRDY Transition Hold Time
tCLTMV 55 Timer Output Delay
tCOAOB 83 CLKOUTA to CLKOUTB Skew
tCSHARYL 88 Chip Select to ARDY Low
tCVCTV 20 Co ntro l Active D elay 1
tCVCTX 31 Co ntro l Inactive Delay
tCVDEX 21 DEN Inactive Delay
tCXCSX 17 MCS/PCS Hold from Command Inactive
tDSHDIR 92 DS High to Data Invalid—Read
tDSHDIW 98 DS High to Data Invalid—Write
tDSHDX 93 DS High to Data Bus Turn-off Time
tDSHLH 41 DS Inactive to ALE Inactive
tDSLDD 90 DS Low to Data Driven
tDSLDV 91 DS Low to Data Valid
tDVCL 1Data in Setup
tDVDSL 97 Data Valid to DS Low
tDXDL 19 DEN Inactive to DT/R Low
tHVCL 58 HOLD Setup
tINVCH 53 Peripheral Setup Time
tINVCL 54 DRQ Setup Time
tLCRF 86 LCS Inactive to RFSH Active Delay
tLHAV 23 ALE High to Address Valid
tLHLL 10 ALE Width
tLLAX 13 AD Address Hold from ALE Inactive
tLOCK 61 Maximum P LL Loc k Tim e
tLRLL 84 LCS Precharge Pulse Width
tRESIN 57 RES Setup Time
tRFCY 85 RFSH Cycle Time
tRHAV 29 RD Inactive to AD Address Active
tRHDX 59 RD High to Data Hold on AD Bus
tRHDZ 94 RD High to Data Bus Turn-off Time
tRHLH 28 RD Inactive to ALE High
64 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Alphabetical Key to Switching Parameter Symbols (continued)
Note:
The following parameters are not defined or used as this ti me: 56, 60, 71–78.
Parameter Symbol No. Description
tRLRH 26 RD Pulse Width
tSRYCL 47 SRDY Transition Setup Time
tWHDEX 35 WR Inactive to DEN Inactive
tWHDX 34 Data Hold after WR
tWHLH 33 WR Inactive to ALE High
tWLWH 32 WR Pulse Width
Am186/188ES and Am186/188ESLV Microcontrollers 65
PRELIMINARY
Numerical Key to Switching Parameter Symbols
No. Parameter Symbol Description
1 tDVCL Data in Setup
2 tCLDX Data in Hold
3 tCHSV Status Active Delay
4 tCLSH Status Inactive Delay
5 tCLAV AD Address Valid Delay
6 tCLAX Address Hold
7 tCLDV Data Valid Delay
8 tCHDX Status Hold Time
9 tCHLH ALE Active Delay
10 tLHLL ALE Width
11 tCHLL ALE Inactive Delay
12 tAVLL AD Address Valid to ALE Low
13 tLLAX AD Address Hold from ALE Inactive
14 tAVCH AD Address Valid to Clock High
15 tCLAZ AD Addre s s Float Delay
16 tCLCSV MCS/PCS Active Delay
17 tCXCSX MCS/PCS Hold from Command Inactive
18 tCHCSX MCS/PCS Inactive Delay
19 tDXDL DEN Inactive to DT/R Low
20 tCVCTV Contro l Active D elay 1
21 tCVDEX DEN Inactive Delay
22 tCHCTV Contro l Active D elay 2
23 tLHAV ALE High to Address Valid
24 tAZRL AD Address Float to RD Active
25 tCLRL RD Active Delay
26 tRLRH RD Pulse Width
27 tCLRH RD Inactive Dela y
28 tRHLH RD Inactive to ALE High
29 tRHAV RD Inactive to AD Address Active
30 tCLDOX Data Hold Time
31 tCVCTX Contro l Inactive Delay
32 tWLWH WR Pulse Width
33 tWHLH WR Inactive to ALE High
34 tWHDX Data Hold after WR
35 tWHDEX WR Inactive to DEN Inactive
36 tCKIN X1 Period
37 tCLCK X1 Low Time
38 tCHCK X1 High Time
39 tCKHL X1 Fall Time
40 tCKLH X1 Rise Time
41 tDSHLH DS Inactive to ALE Inactive
42 tCLCL CLKOUTA Period
66 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Numerical Key to Switching Parameter Symbols (continued)
No. Parameter Symbol Description
43 tCLCH CLKOUTA Low Time
44 tCHCL CLKOUTA High Time
45 tCH1CH2 CLKOUTA Rise Time
46 tCL2CL1 CL KOUTA Fall Time
47 tSRYCL SRDY Transition Setup Time
48 tCLSRY SRDY Transition Hold Time
49 tARYCH ARDY Resolution Transition Setup Time
50 tCLARX ARDY Active Hold Time
51 tARYCHL ARDY Inactive Holding Time
52 tARYLCL ARDY Setup Time
53 tINVCH Peripheral Setup Time
54 tINVCL DRQ Setup Time
55 tCLTMV Timer Output Delay
57 tRESIN RES Setup Time
58 tHVCL HOLD Setup
59 tRHDX RD High to Data Hold on AD Bus
61 tLOCK Maximum P LL Loc k Tim e
62 tCLHAV HLDA Valid Delay
63 tCHCZ Co mmand Lines Float Delay
64 tCHCV Co mmand Lines Valid Delay ( afte r Float)
65 tAVWL A Address Valid to WR Low
66 tAVRL A Address Valid to RD Low
67 tCHCSV CLKOUTA High to LCS/UCS Valid
68 tCHAV CLKOUTA High to A Address Valid
69 tCICOA X1 to CLKOUTA Skew
70 tCICOB X1 to CLKOUTB Skew
79 tCHRFD CLKOUTA High to RFSH Valid
80 tCLCLX LCS Inactive Delay
81 tCLCSL LCS Active Delay
82 tCLRF CLKOUTA High to RFSH Invalid
83 tCOAOB CLKOUTA to CLKOUTB Skew
84 tLRLL LCS Precharge Pulse Width
85 tRFCY RFSH Cycle Time
86 tLCRF LCS Inactive to RFSH Active Delay
87 tAVBL A Address Valid to WHB, WLB Low
88 tCSHARYL Chip Select to ARDY Low
89 tARYHDV ARDY Assert to Data Valid
90 tDSLDD DS Low to Data Driven
91 tDSLDV DS Low to Data Valid
92 tDSHDIR DS High to Data Invalid—Read
93 tDSHDX DS High to Data Bus Turn-off Time
Am186/188ES and Am186/188ESLV Microcontrollers 67
PRELIMINARY
Numerical Key to Switching Parameter Symbols (continued)
Note:
The following parameters are not defined or used as this ti me: 56, 60, 71–78.
No. Parameter Symbol Description
94 tRHDZ RD High to Data Bus Turn-off Time
95 tARYHDSH ARDY High to DS High
96 tARYLDSH ARDY Low to DS High
97 tDVDSL Data Valid to DS Low
98 tDSHDIW DS High to Data Invalid—Write
68 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over Commercial ope rating ranges
Read Cycle (20 MHz and 25 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0.5 V.
a Equal loading on referenced pins.
b This parameter applies to the DEN, DS
,
INTA1–INTA0, WR
,
WHB
,
and WLB signals.
c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Parameter Preliminary
Unit
20 MHz 25 MHz
No. Symbol Description Min Max Min Max
General Timing Requirements
1t
DVCL Data in Setup 10 10 ns
2t
CLDX Data in Hold(c) 33ns
General Timing Responses
3t
CHSV Status Active Delay 0 25 0 20 ns
4t
CLSH Status Inactive Delay 0 25 0 20 ns
5t
CLAV AD Address Valid Delay and BHE 0 25 0 20 n s
6t
CLAX Address Hold 025020ns
8t
CHDX Status Hold Time 0 0 ns
9t
CHLH ALE Active Delay 25 20 ns
10 tLHLL ALE Width tCLCL–10=
40 tCLCL–10=
30 ns
11 tCHLL ALE Inactive Delay 25 20 ns
12 tAVLL AD Address Valid to ALE Low(a) tCLCHL–2 tCLCH–2 ns
13 tLLAX AD Address Hold from ALE
Inactive(a) tCHCL–2 tCHCL–2 ns
14 tAVCH AD Address Valid to Clock High 0 0 ns
15 tCLAZ AD Address Float Delay tCLAX=0 25 tCLAX=0 20 ns
16 tCLCSV MCS/PCS Active Delay 0 25 0 20 ns
17 tCXCSX MCS/PCS Hold from Command
Inactive(a) tCLCH–2 tCLCH–2 ns
18 tCHCSX MCS/PCS Inactive Delay 0 25 0 20 ns
19 tDXDL DEN Inactive to DT/R Low(a) 00ns
20 tCVCTV Contro l Active Delay 1(b) 025020ns
21 tCVDEX DEN Inactive Delay 0 12 0 12 ns
22 tCHCTV Control Active Delay 2(b) 025020ns
23 tLHAV ALE High to Address Valid 20 15 ns
99 tPLAL PCS Low to ALE Low 15 28 15 24 n s
Read Cycle Timing Responses
24 tAZRL AD Address Float to RD Active 0 0 ns
25 tCLRL RD Active Delay 0 25 0 20 ns
26 tRLRH RD Pulse Width 2tCLCL–15=
85 2tCLCL–15=
65 ns
27 tCLRH RD Inactive Delay 0 25 0 20 ns
28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–3 ns
29 tRHAV RD Inactive to AD Address
Active(a) tCLCL–10=
40 tCLCL–10=
30 ns
41 tDSHLH DS Inactive to ALE High tCLCH–2=
21 tCLCH–2=
16
59 tRHDX RD High to Data Hold on AD Bus(c) 00ns
66 tAVRL A Address Valid to RD Low(a) tCLCL+
tCHCL–3 tCLCL+
tCHCL–3 ns
67 tCHCSV CLKOUTA High to LCS/UCS Valid025020ns
68 tCHAV CLKOUTA High to A Address
Valid 025020ns
Am186/188ES and Am186/188ESLV Microcontrollers 69
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
Read Cycle (33 MHz and 40 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0.5 V.
a Equal loading on referenced pins.
b This parameter applies to the DEN, DS, INTA1–INTA0, WR
,
WHB
,
and WLB signals.
c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Parameter Preliminary
Unit
33 MHz 40 MHz
No. Symbol Description Min Max Min Max
General Timing Requirements
1t
DVCL Data in Setup 8 5 ns
2t
CLDX Data in Hold(c) 32ns
General Timing Responses
3t
CHSV Status Active Delay 0 15 0 12 ns
4t
CLSH Status Inactive Delay 0 15 0 12 ns
5t
CLAV AD Address Valid Delay and BHE 0 15 0 12 ns
6t
CLAX Address Hold 015012ns
8t
CHDX Status Hold Time 0 0 ns
9t
CHLH ALE Active Delay 15 12 ns
10 tLHLL ALE Width tCLCL–10=20 tCLCL–5=20 ns
11 tCHLL ALE Inactive Delay 15 12 ns
12 tAVLL AD Address Valid to ALE Low(a) tCLCH–2 tCLCH–2 ns
13 tLLAX AD Address Hold from ALE
Inactive(a) tCHCL–2 tCHCL–2 ns
14 tAVCH AD Address Valid to Clock High 0 0 ns
15 tCLAZ AD Address Float Delay tCLAX=0 15 tCLAX=0 12 ns
16 tCLCSV MCS/PCS Active Delay 0 15 0 12 ns
17 tCXCSX MCS/PCS Hold from Command
Inactive(a) tCLCH–2 tCLCH–2 ns
18 tCHCSX MCS/PCS Inactive Delay 0 15 0 12 ns
19 tDXDL DEN Inactive to DT/R Low(a) 00ns
20 tCVCTV Contro l Active Delay 1(b) 015012ns
21 tCVDEX DEN Inactive Delay 0 12 0 12 ns
22 tCHCTV Control Active Delay 2(b) 015012ns
23 tLHAV ALE High to Address Valid 10 7.5 ns
99 tPLAL PCS Low to ALE Low 12 20 10 18 ns
Read Cycle Timing Responses
24 tAZRL AD Address Float to RD Active 0 0 ns
25 tCLRL RD Active Delay 0 15 0 10 ns
26 tRLRH RD Pulse Width 2tCLCL–15=45 2tCLCL–10=40 ns
27 tCLRH RD Inactive Delay 0 15 0 12 ns
28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–2 ns
29 tRHAV RD Inactive to AD Address
Active(a) tCLCL–10=20 tCLCL–5=20 ns
41 tDSHLH DS Inactive to ALE Inactive tCLCH–2=11.5 tCLCH–2=9.25
59 tRHDX RD High to Data Hold on AD Bus(c) 00ns
66 tAVRL A Address Valid to RD Low(a) tCLCL+ tCHCL–3 tCLCL+ tCHCL–
1.125 ns
67 tCHCSV CLKOUTA High to LCS/UCS Valid015010ns
68 tCHAV CLKOUTA High to A Address
Valid 015010ns
70 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Read Cycle W av eforms
CLKOUTA
t1t2t3t4
tW
S2–S0
LCS, UCS
RD
MCS1–MCS0,
PCS6–PCS5,
PCS3–PCS0
A19–A0
DEN, DS
DT/R
S6/LOCK S6
BHE*
ALE
1
2
3
4
5
6
8
911
12
13
14
15
16 17
18
19
20 21
2222
24
25
26 27
29
68
66
67
28
10
UZI
AO15–AO8**
Notes:
*
Am186ES microcontroller only
**
Am188ES microcontroller only
*** Changes in t phase preceding next bus cycle if followed by read, INTA, or halt.
59
LOCK
23
AD15–AD0*,
AD7–AD0** Data
Address
S6
Status
Address
Address
BHE
*** ***
41
99
Am186/188ES and Am186/188ESLV Microcontrollers 71
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
Write Cycle (20 MHz and 25 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH =
2.4 V, except at X1 where V
IH
=V
CC
– 0.5 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals.
Parameter Preliminary
Unit
20 MHz 25 MHz
No. Symbol Description Min Max Min Max
General Timing Responses
3t
CHSV Status Active Delay 0 25 0 20 ns
4t
CLSH Status Inactive Delay 0 25 0 20 ns
5t
CLAV AD Address Valid Delay and BHE 0 25 0 20 ns
6t
CLAX Address Hold 025020ns
7t
CLDV Data Valid Delay 0 15 0 20 ns
8t
CHDX Status Hold Time 0 0 ns
9t
CHLH ALE Active Delay 25 20 ns
10 tLHLL ALE Width tCLCL–10=40 tCLCL–10=30 ns
11 tCHLL ALE Inactive Delay 25 20 ns
12 tAVLL AD Address Valid to ALE Low(a) tCLCH –2 tCLCH–2 ns
13 tLLAX AD Address Hold from ALE
Inactive(a) tCHCL–2 tCHCL–2 ns
14 tAVCH AD Address Valid to Clock High 0 0 ns
16 tCLCSV MCS/PCS Active Delay 0 25 0 20 ns
17 tCXCSX MCS/PCS Hold from Command
Inactive(a) tCLCH–2 tCLCH–2 ns
18 tCHCSX MCS/PCS Inactive Delay 0 25 0 20 ns
19 tDXDL DEN Inactive to DT/R Low(a) 00ns
20 tCVCTV Contro l Active Delay 1(b) 015020ns
21 tCVDEX DS Inactive Delay 0 25 0 20 ns
22 tCHCTV Control Active Delay 2 0 25 0 20 n s
23 tLHAV ALE High to Address Valid 20 1 5 ns
Write Cycle Timing Responses
30 tCLDOX Data Hold Time 0 0 ns
31 tCVCTX Contro l Inactive Delay(b) 025020ns
32 tWLWH WR Pulse Width 2tCLCL–10=90 2tCLCL–10=70 ns
33 tWHLH WR Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns
34 tWHDX Data Hold after WR(a) tCLCL–10=40 tCLCL–10=30 ns
35 tWHDEX WR Inactive to DEN Inactive(a) tCLCH–3 tCLCH–3 ns
41 tDSHLH DS Inactive to ALE High tCLCH–2=
21 tCLCH–2=
16
65 tAVWL A Address Valid to WR Low tCLCL+tCHCL–3 tCLCL+tCHCL–3 ns
67 tCHCSV CLKOUTA High to LCS/UCS Valid025020ns
68 tCHAV CLKOUTA High to A Address
Valid 025020ns
87 tAVBL A Address Vali d to WHB, WLB
Low tCHCL–3 25 tCHCL–3 20 ns
98 tDSHDIW DS High to Data Invalid—Write 35 0 30 ns
72 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
Write Cycle (33 MHz and 40 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0.5 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB si gna ls .
Parameter Preliminary
Unit
33 MHz 40 MHz
No. Symbol Description Min Max Min Max
General Timing Responses
3t
CHSV Status Active Delay 0 15 0 12 ns
4t
CLSH Status Inactive Delay 0 15 0 12 ns
5t
CLAV AD Address Valid Delay and BHE 0 15 0 12 ns
6t
CLAX Address Hold 025020ns
7t
CLDV Data Valid Delay 0 15 0 12 ns
8t
CHDX Status Hold Time 0 0 ns
9t
CHLH ALE Active Delay 15 12 ns
10 tLHLL ALE Width tCLCL–10=20 tCLCL–5=20 ns
11 tCHLL ALE Inactive Delay 15 12 ns
12 tAVLL AD Address Valid to ALE Low(a) tCLCH–2 tCLCH–2 ns
13 tLLAX AD Address Hold from ALE
Inactive(a) tCHCL–2 tCHCL–2 ns
14 tAVCH AD Address Valid to Clock High 0 0 ns
16 tCLCSV MCS/PCS Active Delay 0 15 0 12 ns
17 tCXCSX MCS/PCS Hold from Command
Inactive(a) tCLCH–2 tCLCH–2 ns
18 tCHCSX MCS/PCS Inactive Delay 0 15 0 12 ns
19 tDXDL DEN Inactive to DT/R Low(a) 00ns
20 tCVCTV Contro l Active Delay 1(b) 015012ns
21 tCVDEX DS Inactive Delay 0 15 0 12 ns
22 tCHCTV Control Active Delay 2 0 15 0 12 n s
23 tLHAV ALE High to Address Valid 10 7.5 ns
Write Cycle Timing Responses
30 tCLDOX Data Hold Time 0 0 ns
31 tCVCTX Contro l Inactive Delay(b) 015012ns
32 tWLWH WR Pulse Width 2tCLCL–10=50 2tCLCL–10=40 ns
33 tWHLH WR Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns
34 tWHDX Data Hold after WR(a) tCLCL–10=20 tCLCL–10=15 ns
35 tWHDEX WR Inactive to DEN Inactive(a) tCLCH–5 tCLCH ns
65 tAVWL A Address Valid to WR Low tCLCL+tCHCL–3 tCLCL+tCHCL–
1.25 ns
67 tCHCSV CLKOUTA High to LCS/UCS Valid015010ns
68 tCHAV CLKOUTA High to A Address
Valid 015010ns
87 tAVBL A Address Vali d to WHB, WLB
Low tCHCL–3 15 tCHCL–1.25 12 ns
98 tDSHDIW DS High to Data Invalid—Write 0 20 0 15 ns
Am186/188ES and Am186/188ESLV Microcontrollers 73
PRELIMINARY
Write Cycle Waveforms
CLKOUTA
t1t2t3t4
tW
S2–S0 Status
LCS, UCS
Address Data
AD15–AD0*,
AD7–AD0**
WR
MCS3–MCS0,
PCS6–PCS5,
PCS3–PCS0
A19–A0
DEN
DT/R
S6/LOCK S6
ALE
WHB*, WLB*
WB**
BHE*
34
5
7
8
9
10
11
12
13
14
16
17
18
19
67
68
65
35
31
20
30
34
32
31
33
UZI
S6
20 31
87
AO15–AO8**
Notes:
*
Am186ES microcontroller only
**
Am188ES microcontroller only
*** Changes in t phase preceding next bus cycle if followed by read, INTA, or halt.
LOCK
23
DS
21
20
Address
Address
6
BHE
41
20
98
22
22 ***
***
99
74 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
PSRAM Read Cycl e (20 MHz and 25 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
–0.5 V.
a Testing is performed with equal loading on referenced pins.
b If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Parameter Preliminary
Unit
20 MHz 25 MHz
No. Symbol Description Min Max Min Max
General Timing Requirements
1t
DVCL Data in Setup 10 10 ns
2t
CLDX Data in Hold(b) 33ns
General Timing Responses
5t
CLAV AD Address Valid Delay and BHE 0 25 0 20 ns
7t
CLDV Data Valid Delay 0 25 0 20 ns
8t
CHDX Status Hold Time 0 0 ns
9t
CHLH ALE Active Delay 25 20 ns
10 tLHLL ALE Width tCLCL–10=40 tCLCL–10=30 ns
11 tCHLL ALE Inactive Delay 25 20 ns
23 tLHAV ALE High to Address Valid 20 1 5 ns
80 tCLCLX LCS Inactive Delay 0 25 0 20 ns
81 tCLCSL LCS Active Delay 0 25 0 20 ns
84 tLRLL LCS Precharge Pulse Width tCLCL+ tCLCH–3 tCLCL + tCLCH –3 ns
Read Cycle Timing Responses
24 tAZRL AD Address Float to RD Active 0 0 ns
25 tCLRL RD Active Delay 0 25 0 20 ns
26 tRLRH RD Pulse Width 2tCLCL–15=85 2tCLCL–15=65 ns
27 tCLRH RD Inactive Delay 0 25 0 20 ns
28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–3 ns
59 tRHDX RD High to Data Hold on AD
Bus(b) 00ns
66 tAVRL A Address Valid to RD Low tCLCL+ tCHCL–3 tCLCL+ tCHCL–3 ns
68 tCHAV CLKOUTA High to A Address
Valid 025020ns
Am186/188ES and Am186/188ESLV Microcontrollers 75
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
PSRAM Read Cycl e (33 MHz and 40 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
–0.5 V.
a Testing is performed with equal loading on referenced pins.
b If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Parameter Preliminary
Unit
33 MHz 40 MHz
No. Symbol Description Min Max Min Max
General Timing Requirements
1t
DVCL Data in Setup 8 5 ns
2t
CLDX Data in Hold(b) 32ns
General Timing Responses
5t
CLAV AD Address Valid Delay and BHE 0 15 0 12 ns
7t
CLDV Data Valid Delay 0 15 0 12 ns
8t
CHDX Status Hold Time 0 0 ns
9t
CHLH ALE Active Delay 15 12 ns
10 tLHLL ALE Width tCLCL–10=20 tCLCL–5=20 ns
11 tCHLL ALE Inactive Delay 15 12 ns
23 tLHAV ALE High to Address Valid 10 7.5 ns
80 tCLCLX LCS Inactive Delay 0 15 0 12 ns
81 tCLCSL LCS Active Delay 0 15 0 12 ns
84 tLRLL LCS Precharge Pulse Width tCLCL + tCLCH –3 tCLCL + tCLCH –
1.25 ns
Read Cycle Timing Responses
24 tAZRL AD Address Float to RD Active 0 0 ns
25 tCLRL RD Active Delay 0 15 0 10 ns
26 tRLRH RD Pulse Width 2tCLCL–15=45 2tCLCL–10=40 ns
27 tCLRH RD Inactive Delay 0 15 0 12 ns
28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–1.25 ns
59 tRHDX RD High to Data Hold on AD
Bus(b) 00ns
66 tAVRL A Address Valid to RD Low tCLCL+ tCHCL–3 tCLCL+ tCHCL–
1.25 ns
68 tCHAV CLKOUTA High to A Address
Valid 015010ns
76 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
PSRAM Read Cycle Wave forms
Data
CLKOUTA
t1t2t3
tW
LCS
Address
AD15–AD0*,
AD7–AD0**
RD
A19–A0
S6/LOCK
ALE
1
2
5
7
8
911
24
25
26
27
68
66
28
10
t4
81
84
t1
Address
80
80
27
AO15–AO8**
Notes:
*
Am186ES microcontro ller only
**
Am188ES microcontro ller only
59
23
LOCK S6
Address
Address
S6
Am186/188ES and Am186/188ESLV Microcontrollers 77
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
PSRAM Wri te Cycle (20 MHz and 25 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0 . 5 V .
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN, W R, WHB, and WLB signals.
Parameter Preliminary
Unit
20 MHz 25 MHz
No. Symbol Description Min Max Min Max
General Timing Responses
5t
CLAV AD Address Vali d Del ay an d BHE 0 25 0 20 ns
7t
CLDV Data Valid Delay 0 25 0 20 ns
8t
CHDX Status Hold Time 0 0 ns
9t
CHLH ALE Active Delay 25 20 ns
10 tLHLL ALE Width tCLCL–10=40 tCLCL–10=30 ns
11 tCHLL ALE Inactive Delay 25 20 ns
20 tCVCTV Contro l Active Delay 1(b) 0 25 0 20 ns
23 tLHAV ALE High to Address Valid 20 15 ns
80 tCLCLX LCS Inactive Delay 0 25 0 20 ns
81 tCLCSL LCS Active Delay 0 25 0 20 ns
84 tLRLL LCS Precharge Pulse Width tCLCL + tCLCH –3 tCLCL + tCLCH –3
Write Cycle Timing Responses
30 tCLDOX Data Hold Time 0 0 ns
31 tCVCTX Contro l Inactive Delay(b) 0 25 0 20 ns
32 tWLWH WR Pulse Width 2tCLCL–10=90 2tCLCL–10=70 ns
33 tWHLH WR Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns
34 tWHDX Data Hold after WR(a) tCLCL–10=40 tCLCL–10=30 ns
65 tAVWL A Address Valid to WR Lo w tCLCL+tCHCL
–3 tCLCL+tCHCL
–3 ns
68 tCHAV CLKOUTA High to A
Address Valid 0 25 0 20 ns
87 tAVBL A Address Vali d to WHB, WLB
Low tCHCL–3 25 tCHCL–3 20 ns
78 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
PSRAM Wri te Cycle (33 MHz and 40 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0 . 5 V .
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN, W R, WHB, and WLB signals.
Parameter Preliminary
Unit
33 MHz 40 MHz
No. Symbol Description Min Max Min Max
General Timing Responses
5t
CLAV AD Address Valid Delay and BHE 0 15 0 12 ns
7t
CLDV Data Valid Delay 0 15 0 12 n s
8t
CHDX Status Hold Time 0 0 ns
9t
CHLH ALE Active Delay 15 12 ns
10 tLHLL ALE Width tCLCL–10=20 tCLCL–5=20 ns
11 tCHLL ALE Inactive Delay 15 12 ns
20 tCVCTV Contro l Active Delay 1(b) 015012ns
23 tLHAV ALE High to Address Valid 10 7.5 ns
80 tCLCLX LCS Inactive Delay 0 15 0 12 ns
81 tCLCSL LCS Active Delay 0 15 0 12 ns
84 tLRLL LCS Precharge Pulse Width tCLCL + tCLCH –
3tCLCL + tCLCH –
1.25
Write Cycle Timing Responses
30 tCLDOX Data Hold Time 0 0 ns
31 tCVCTX Contro l Inactive Delay(b) 015012ns
32 tWLWH WR Pulse Width 2tCLCL–10=50 2tCLCL–10=40 ns
33 tWHLH WR Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns
34 tWHDX Data Hold after WR(a) tCLCL–10=20 tCLCL–10=15 ns
65 tAVWL A Address Valid to WR Low tCLCL+tCHCL
–3 tCLCL+tCHCL
–1.25 ns
68 tCHAV CLKOUTA High to A
Address Valid 015010ns
87 tAVBL A Address Valid to WHB, WLB
Low tCHCL–3 15 tCHCL–1.25 12 ns
Am186/188ES and Am186/188ESLV Microcontrollers 79
PRELIMINARY
PSRAM Write Cycle Waveforms
CLKOUTA
t1t2t3t4
tW
LCS
Data
AD15–AD0*,
AD7–AD0**
WR
Address
A19–A0
S6/LOCK S6
ALE
WHB*, WLB*
WB**
5
7
8
9
10
11
68
65
20
30
34
32 33
t1
31
20
80
84 81
87
80
31
AO15–AO8**
Notes:
*
Am186ES microcontroller only
**
Am188ES microcontroller only
23
LOCK
Address
S6
Address
80 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
PSRAM Refresh Cycle (20 MHz and 25 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0.5 V.
a Testing is performed with equal loading on referenced pins.
Parameter Preliminary
Unit
20 MHz 25 MHz
No. Symbol Description Min Max Min Max
General Timing Responses
9t
CHLH ALE Active Delay 25 20 ns
10 tLHLL ALE Width tCLCL–10=40 tCLCL–10=30 ns
11 tCHLL ALE Inactive Delay 25 20 ns
Read/Write Cycle Timing Responses
25 tCLRL RD Active Delay 0 25 0 20 ns
26 tRLRH RD Pulse Width 2tCLCL–15=85 2tCLCL–15=65 ns
27 tCLRH RD Inactive Delay 0 25 0 20 ns
28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–3 ns
80 tCLCLX LCS Inactive Delay 0 25 0 20 ns
81 tCLCSL LCS Active Delay 0 25 0 20 ns
Refresh Timing Cycle Parameters
79 tCLRFD CLKOUTA Low to RFSH Valid 025020ns
82 tCLRF CLKOUTA High to RFSH Invalid025020ns
85 tRFCY RFSH Cycle Time 6 • tCLCL 6 • tCLCL ns
86 tLCRF LCS Inactive to RFSH Active
Delay 2tCLCL–3 2tCLCL–3
Am186/188ES and Am186/188ESLV Microcontrollers 81
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
PSRAM Refresh Cycle (33 MHz and 40 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0.5 V.
a Testing is performed with equal loading on referenced pins.
Parameter Preliminary
Unit
33 MHz 40 MHz
No. Symbol Description Min Max Min Max
General Timing Responses
9t
CHLH ALE Active Delay 15 12 ns
10 tLHLL ALE Width tCLCL–10=20 tCLCL–5=20 ns
11 tCHLL ALE Inactive Delay 15 12 ns
Read/Write Cycle Timing Responses
25 tCLRL RD Active Delay 0 15 0 10 ns
26 tRLRH RD Pulse Width 2tCLCL–15=45 2tCLCL–10=40 ns
27 tCLRH RD Inactive Delay 0 15 0 12 ns
28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–2 ns
80 tCLCLX LCS Inactive Delay 0 15 0 12 ns
81 tCLCSL LCS Active Delay 0 15 0 12 ns
Refresh Timing Cycle Parameters
79 tCLRFD CLKOUTA Low to RFSH Valid 015012ns
82 tCLRF CLKOUTA High to RFSH Invalid015012ns
85 tRFCY RFSH Cycle Time 6 • tCLCL 6 • tCLCL ns
86 tLCRF LCS Inactive to RFSH Active
Delay 2tCLCL –3 2tCLCL –1.25
82 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
PSRAM Re f res h Cycl e Wav efo rms
CLKOUTA
t1t2t3t4
tW *
LCS
RD
Address
A19–A0
ALE
9
25
26
27
28
10
RFSH
11
t1
79
85
82
80 81
86
*
The period t
w
is fixed at 3 wait states for PSRAM auto refresh only.
27
Notes:
Am186/188ES and Am186/188ESLV Microcontrollers 83
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
Interrupt Acknowledge Cycle (20 MHz and 25 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0.5 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the INTA1–INTA0 signals.
c This parameter applies to the DEN and DT/R signals.
Parameter Preliminary
Unit
20 MHz 25 MHz
No. Symbol Description Min Max Min Max
General Timing Requirements
1t
DVCL Data in Setup 1 0 10 ns
2t
CLDX Data in Hold 3 3 ns
General Timing Responses
3t
CHSV Status Active Delay 0 25 0 20 ns
4t
CLSH Status Inactive Delay 0 25 0 20 ns
7t
CLDV Data Valid Delay 0 25 0 20 ns
8t
CHDX Status Hold Time 0 0 ns
9t
CHLH ALE Active Delay 25 20 ns
10 tLHLL ALE Width tCLCL–10=40 tCLCL–10=30 ns
11 tCHLL ALE Inactive Delay 25 20 ns
12 tAVLL AD Address Invalid to ALE
Low(a) tCLCH tCLCH ns
15 tCLAZ AD Address Float Delay tCLAX=0 25 tCLAX=0 20 ns
19 tDXDL DEN Inactive to DT/R Low(a) 00ns
20 tCVCTV Contro l Active Delay 1(b) 025020ns
21 tCVDEX DEN Inactive Delay 0 25 0 20 ns
22 tCHCTV Control Active Delay 2(c) 025020ns
23 tLHAV ALE High to Address Valid 20 15 ns
31 tCVCTX Contro l Inactive Delay(b) 025020ns
68 tCHAV CLKOUTA High to A
Address Valid 025020ns
84 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
Interrupt Acknowledge Cycle (33 MHz and 40 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0 . 5 V .
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the INTA1–INTA0 signals.
c This parameter applies to the DEN and DT/R signals.
Parameter Preliminary
Unit
33 MHz 40 MHz
No. Symbol Description Min Max Min Max
General Timing Requirements
1t
DVCL Data in Setup 8 5 ns
2t
CLDX Data in Hold 3 2 ns
General Timing Responses
3t
CHSV Status Active Delay 0 15 0 12 ns
4t
CLSH Status Inactive Delay 0 15 0 12 ns
7t
CLDV Data Valid Delay 0 15 0 12 ns
8t
CHDX Status Hold Time 0 0 ns
9t
CHLH ALE Active Delay 15 12 ns
10 tLHLL ALE Width tCLCL–10=20 tCLCL–5=20 ns
11 tCHLL ALE Inactive Delay 15 12 ns
12 tAVLL AD Address Invalid to ALE
Low(a) tCLCH tCLCH ns
15 tCLAZ AD Address Float Delay tCLAX=0 15 tCLAX=0 12 ns
19 tDXDL DEN Inactive to DT/R Low(a) 00ns
20 tCVCTV Contro l Active Delay 1(b) 015012ns
21 tCVDEX DEN Inactive Delay 0 15 0 12 ns
22 tCHCTV Control Active Delay 2(c) 015012ns
23 tLHAV ALE High to Address Valid 10 7.5 ns
31 tCVCTX Contro l Inactive Delay(b) 015012ns
68 tCHAV CLKOUTA High to A
Address Valid 015010ns
Am186/188ES and Am186/188ESLV Microcontrollers 85
PRELIMINARY
Interrupt Acknowledge Cycle Waveforms
CLKOUTA
t1t2t3t4
tW
S2–S0 Status
ALE
AD15–AD0*,
AD7–AD0**
INTA1–INTA0
DEN
DT/R
Ptr
A19–A0
S6/LOCK
BHE* BHE
8
12
3 4
7
9
10 11
12
15
19
20
22
22
22
68
31
(a)
(b)
(c)
(d)
S6
21
Notes:
*
Am186ES mi crocontroller only
**
Am188ES mi crocontroller only
a The status bits become inactive in the state preceding t
4
.
b The data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge
transition occurs prior to t
CLDX
(min).
c This parameter applies for an interrupt acknowledge cycle that follows a write cycle.
d If followed by a write cycle, this change occurs in the state preceding that write cycle.
AO15–AO8**
4
LOCK
23
Address
Address
S6
86 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
Software Halt Cycle (20 MHz and 25 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0 . 5 V .
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN
signal.
Parameter Preliminary
Unit
20 MHz 25 MHz
No. Symbol Description Min Max Min Max
General Timing Responses
3t
CHSV Status Active Delay 0 25 0 20 ns
4t
CLSH Status Inactive Delay 0 25 0 20 ns
5t
CLAV AD Address Invalid Delay and BHE 0 25 0 20 ns
9t
CHLH ALE Active Delay 25 20 ns
10 tLHLL ALE Width tCLCL–10=40 tCLCL–10=30 ns
11 tCHLL ALE Inactive Delay 25 20 ns
19 tDXDL DEN Inactive to DT/R Low(a) 00ns
22 tCHCTV Contro l Active Delay 2(b) 025020ns
68 tCHAV CLKOUTA High to A Address
Invalid 025020ns
Am186/188ES and Am186/188ESLV Microcontrollers 87
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
Software Halt Cycle (33 MHz and 40 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0.5 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN
signal.
Parameter Preliminary
Unit
33 MHz 40 MH z
No. Symbol Description Min Max Min Max
Genera l Tim ing R espons es
3t
CHSV Status Active Delay 0 15 0 12 ns
4t
CLSH Status Inactive Delay 0 15 0 12 ns
5t
CLAV AD Addre ss In va lid D e lay an d BH E 0 15 0 12 ns
9t
CHLH ALE Active Delay 15 12 ns
10 tLHLL ALE Width tCLCL–10=20 tCLCL–5=20 ns
11 tCHLL ALE Inactive Delay 15 12 ns
19 tDXDL DEN Inactive to DT/R Low(a) 00ns
22 tCHCTV Contro l Active Delay 2(b) 015012ns
68 tCHAV CLKOUTA High to A Address
Invalid 015010ns
88 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Software Halt Cycle Waveforms
CLKOUTA
t1t2titi
S2–S0 Status
ALE
Invalid Address
S6, AD15–AD0*,
AD7–AD0**,
AO15–AO8**
DEN
DT/R
Invalid Address
A19–A0
3
4
5
9
10
11
19
22
68
Notes:
*
Am186ES microcontro ller only
**
Am188ES microcontro ller only
Am186/188ES and Am186/188ESLV Microcontrollers 89
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
Clock (20 MHz and 25 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0 . 5 V .
a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes.
The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2
mode should be used.
Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should
be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.
Parameter Preliminary
Unit
20 MHz 25 MHz
No. Symbol Description Min Max Min Max
CLKIN Requirements
36 tCKIN X1 Period(a) 50 60 40 60 ns
37 tCLCK X1 Low Time (1.5 V)(a) 15 15 ns
38 tCHCK X1 High Time (1 .5 V)(a) 15 15 ns
39 tCKHL X1 Fall Time (3.5 to 1.0 V)(a) 55ns
40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 55ns
CLKOUT Timing
42 tCLCL CLKOUTA Period 50 40 ns
43 tCLCH CLKOUTA Low Time (CL=50
pF) 0.5tCLCL–2=23 0.5tCLCL–2=18 ns
44 tCHCL CLKOUTA High Time (CL=50
pF) 0.5tCLCL–2=23 0.5tCLCL–2=18 ns
45 tCH1CH2 CLKOUTA Rise Time
(1.0 to 3.5 V) 33ns
46 tCL2CL1 CLKOUTA Fall Time
(3.5 to 1.0 V) 33ns
61 tLOCK Maximu m PLL Loc k Tim e 1 1 ms
69 tCICOA X1 to CLKOUTA Skew 15 15 ns
70 tCICOB X1 to CLKOUTB Skew 25 25 ns
90 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
Clock (33 MHz and 40 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0 . 5 V .
a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes.
The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2
mode should be used.
Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should
be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.
Parameter Preliminary
Unit
33 MHz 40 MHz
No. Symbol Description Min Max Min Max
CLKIN Requirements
36 tCKIN X1 Period(a) 30 60 25 60 ns
37 tCLCK X1 Low Time (1.5 V)(a) 10 7.5 ns
38 tCHCK X1 High Time (1 .5 V)(a) 10 7.5 ns
39 tCKHL X1 Fall Time (3.5 to 1.0 V)(a) 55ns
40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 55ns
CLKOUT Timing
42 tCLCL CLKOUTA Period 30 25 ns
43 tCLCH CLKOUTA Low Time
(CL=50 pF) 0.5tCLCL–1.5
=13.5 0.5tCLCL–1.25
=11.25 ns
44 tCHCL CLKOUTA High Time
(CL=50 pF) 0.5tCLCL–1.5
=13.5 0.5tCLCL–1.25
=11.25 ns
45 tCH1CH2 CLKOUTA Rise Time
(1.0 to 3.5 V) 33ns
46 tCL2CL1 CLKOUTA Fall Time
(3.5 to 1.0 V) 33ns
61 tLOCK Maximu m PLL Loc k Tim e 1 1 ms
69 tCICOA X1 to C L KOUTA Skew 15 15 ns
70 tCICOB X1 to C L KOUTB Skew 25 25 ns
Am186/188ES and Am186/188ESLV Microcontrollers 91
PRELIMINARY
Clock Waveforms—Active Mode
Clock Waveforms—Power-Save Mode
X1
X2
CLKOUTB
CLKOUTA
(Active, F=000 )
36 37
39 40
42 43
46
69
70
38
44
45
X1
CLKOUTA
(Power-Save, F=010)
X2
CLKOUTB
(Like CLKOUTA, CBF=0)
CLKOUTB
(Like X1, CBF=1)
92 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
Ready and Peripheral (20 MHz and 25 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0 . 5 V .
a This timing must be met to guarantee proper operation.
b This timing must be met to guarantee recognition at the clock edge.
Parameter Preliminary Preliminary
Unit
20 MHz 25 MHz
No. Symbol Description Min Max Min Max
Ready and Peripheral Timing Requirements
47 tSRYCL SRDY Transition Se tup Time(a) 10 10 ns
48 tCLSRY SRDY Transition Hold Time(a) 33ns
49 tARYCH ARDY Resolution Transition
Setup Time(b) 10 10 ns
50 tCLARX ARDY Active Hold Time(a) 44ns
51 tARYCHL ARDY Inactive Holding Time 6 6 ns
52 tARYLCL ARDY Setup Time(a) 15 15 ns
53 tINVCH Peripheral Setup Time(b) 10 10 ns
54 tINVCL DRQ Setup Time(b) 10 10 ns
Peripheral Timing Responses
55 tCLTMV Timer Output Delay 25 20 ns
Am186/188ES and Am186/188ESLV Microcontrollers 93
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
Ready and Peripheral (33 MHz and 40 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0 . 5 V .
a This timing must be met to guarantee proper operation.
b This timing must be met to guarantee recognition at the clock edge.
Synchronous Ready Waveforms
Parameter Preliminary
Unit
33 MHz 40 MHz
No. Symbol Description Min Max Min Max
Ready and Peripheral Timing Requirements
47 tSRYCL SRDY Transition Se tup Time(a) 85ns
48 tCLSRY SRDY Transition Hold Time(a) 32ns
49 tARYCH ARDY Resolution Transition
Setup Time(b) 85ns
50 tCLARX ARDY Active Hold Time(a) 43ns
51 tARYCHL ARDY Inactive Holding Time 6 5 ns
52 tARYLCL ARDY Setup Time(a) 10 5 ns
53 tINVCH Peripheral Setup Time(b) 85ns
54 tINVCL DRQ Setup Time(b) 85ns
Peripheral Timing Responses
55 tCLTMV Timer Output Delay 15 12 ns
CLKOUTA
tWtWtWt4
SRDY
t3tWtWt4
t2t3tWt4
t1t2t3t4
Case 2
Case 3
Case 4
47
48
Case 1
94 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Asynchronous Ready Waveforms
Peripheral Wa ve form s
CLKOUTA
tWtWtWt4
ARDY (Normally Not-
Ready System)
t3tWtWt4
t2t3tWt4
t1t2t3t4
Case 2
Case 3
Case 4
ARDY (Normally
Ready System)
49 50
49
51 50
52
Case 1
CLKOUTA
TMROUT1–
TMROUT0
DRQ1–DRQ0
INT4–INT0, NMI,
TMRIN1–TMRIN0
53
54
55
Am186/188ES and Am186/188ESLV Microcontrollers 95
PRELIMINARY
SWITCHING CHARACTERISTICS o v er C O M ME R C IA L op e r a ti n g ra n g e s
Reset and Bus Hold (20 MHz and 25 MHz)
Reset and Bus Hold (33 MHz and 40 MHz)
Notes:
All timin g paramete rs are measu red at 1.5 V with 50 pF loadin g on CLKOUTA, unless oth erwise noted . All outpu t test condi tions
are with C
L
=50 pF. For switching tests, V
IL
=0.45 V and V
IH
=2.4 V, except at X1 where V
IH
=V
CC
– 0 . 5 V .
a This timing must be met to guarantee recognition at the next clock.
Parameter Preliminary
Unit
20 MHz 25 MHz
No. Symbol Description Min Max Min Max
Reset and Bus Hold Timing Requirements
5t
CLAV AD Address Valid Delay and BHE 0 25 0 20 ns
15 tCLAZ AD Address Float Delay 0 25 0 20 ns
57 tRESIN RES Setup Time 10 10 ns
58 tHVCL HOLD Setup(a) 10 10 ns
Reset and Bus Hold Timing Responses
62 tCLHAV HLDA Valid Delay 0 25 0 20 ns
63 tCHCZ Co mmand Lines Float Delay 25 2 0 ns
64 tCHCV Co mmand Lines Valid Delay
(after Float) 25 20 ns
Parameter Preliminary
Unit
33 MHz 40 MHz
No. Symbol Description Min Max Min Max
Reset and Bus Hold Timing Requirements
5t
CLAV AD Address Valid Delay and BHE 0 15 0 12 ns
15 tCLAZ AD Address Float Delay 0 15 0 12 ns
57 tRESIN RES Setup Time 8 5 ns
58 tHVCL HOLD Setup(a) 85ns
Reset and Bus Hold Timing Responses
62 tCLHAV HLDA Valid Delay 0 15 0 12 ns
63 tCHCZ Co mmand Lines Float Delay 15 1 2 ns
64 tCHCV Co mmand Lines Valid Delay
(after Float) 15 12 ns
96 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
Reset Waveforms
Signals Related to Reset Waveforms
X1
RES
CLKOUTA
57 57
RES
CLKOUTA
BHE/ADEN,
RFSH2/ADEN,
S6/CLKDIV2, and
UZI
AD15–AD0 (186)
AO15–AO8,
AD7–AD0 (188)
three-state
three-state
Am186/188ES and Am186/188ESLV Microcontrollers 97
PRELIMINARY
Bus Hold Waveforms—Entering
Bus Hold Waveforms—Leaving
CLKOUTA
tititi
AD15–AD0, DEN
HLDA
A19–A0, S6, RD,
WR, BHE,
DT/R, S2–S0
WHB, WLB
HOLD
t4titi
Case 2
58
62
15
63
Case 1
CLKOUTA
titit1
AD15–AD0, DEN
HLDA
A19–A0, S6, RD,
WR, BHE,
DT/R, S2–S0
WHB, WLB
HOLD
tit4t1
Case 2
ti
ti
58
62
64
5
Case 1
98 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
TQFP PHYSICAL DIMENSIONS
PQL 100, Trimmed and Formed
Thin Quad Flat Pack
Pin 100
Pin 25
Pin 1 ID
12.00
Ref
Notes:
1. All mea sureme nts ar e in m illim eters, unles s othe rwise noted .
2. Not to scale; for reference only.
pql100
4-15-94
–B–
–A–
–D–
Pin 75
12.00
Ref
13.80
14.20
15.80
16.20
Pin 50
13.80
14.20 15.80
16.20
–A–
–C–
S
S1.60
Max
0.50 Basi c
1.00 Ref
1.35
1.45
See Detail X
Seating Plane
Top View
Side View
Am186/188ES and Am186/188ESLV Microcontrollers 99
PRELIMINARY
PQL 100 (continued)
0.17
0.27
0.05
0.15
Seating Plane
Detail X
0.17
0.27
0°–7°
Gage
Plane
0.20
0.45
0.75
0.13
0.20
0° Min
0.25
0.14
0.18
Section S-S
1.60
Max
Notes:
1. All meas urements are in millimeters, unless otherwise noted.
2. Not to scale; for reference only.
pql100
4-15-94
Max 0.08 Lead Coplanarity
R
100 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
PQFP PHYSICAL DIMENSIONS
PQR 100, Trimmed and Formed
Plastic Quad Flat Pack
Notes:
1. All measurements are in millimeters, unless otherwise noted.
2. Not to scale; for reference only.
17.00
17.40
13.90
14.10
12.35
REF Pin 80
Pin 100
Pin 30
Pin 50
Pin 1 I.D.
19.90
20.10
See Detail X
Seating
Plane
0.65
BASIC
0.25
Min
2.70
2.90 3.35
Max
S
S
–A–
–D–
–B–
–A–
–C–
Top View
Side View
18.85
REF
23.00
23.40
pqr100
4-15-94
Am186/188ES and Am186/188ESLV Microcontrollers 101
PRELIMINARY
PQFP PQR 100 (continued)
0.20 Min. Flat Shoulder
7° Typ.
0° Min.
0.30±0.05 R
Gage
Plane 0.25
0.73
1.03
0°-7°
7° Typ.
Detail X 0.22
0.38
0.15
0.23
3.35
Max
Section S-S
0.15
0.23
0.22
0.38
Note:
Not to scale; for reference only.
pqr100
4-15-94
Trademarks
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am386 and Am486 are registered trademarks of Advanced Micro Devices, Inc.
Am186, Am188, E86, K86, Élan, and AMD Facts-on-Demand are trademarks of Advanced Micro Devices, Inc.
FusionE86 is a service mark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
102 Am186/188ES and Am186/188ESLV Microcontrollers
PRELIMINARY
