BUK127-50GT,115 - NXP Semiconductors / Philips Semiconductors

Philips Semiconductors Product specification

PowerMOS transistor BUK127-50GT

Logic level TOPFET

DESCRIPTION QUICK REFERENCE DATA

Monolithic temperature and SYMBOL PARAMETER MAX. UNIT

overload protected logic level power

MOSFET in TOPFET2 technology VDS Continuous drain source voltage 50 V

assembled in a 3 pin surface mount

plastic package. IDContinuous drain current 2.1 A

APPLICATIONS PDTotal power dissipation 1.8 W

General purpose switch for driving TjContinuous junction temperature 150 ˚C

lamps

motors RDS(ON) Drain-source on-state resistance 200 mΩ

solenoids

heaters

in automotive systems and other

applications.

FEATURES FUNCTIONAL BLOCK DIAGRAM

TrenchMOS output stage

Current trip protection

Overload protection

Overtemperature protection

Protection latched reset by input

5 V logic compatible input level

Control of output stage

and supply of overload

protection circuits

derived from input

Low operating input current

permits direct drive by

micro-controller

ESD protection on all pins

Overvoltage clamping for turn

off of inductive loads

Fig.1. Elements of the TOPFET.

PINNING - SOT223 PIN CONFIGURATION SYMBOL

PIN DESCRIPTION

1 input

2 drain

3 source

4 drain (tab)

DRAIN

SOURCE

INPUT RIG

LOGIC AND

PROTECTION

O / V

CLAMP POWER

MOSFET

123

TOPFET

December 2001 1 Rev 2.000

Philips Semiconductors Product specification

PowerMOS transistor BUK127-50GT

Logic level TOPFET

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDS Continuous drain source voltage1- - 50 V

IDDrain current2- - current trip A

IDContinuous drain current Ta = 25˚C - 2.1 A

IIContinuous input current clamping - 3 mA

IIRM Non-repetitive peak input current tp ≤ 1 ms - 10 mA

PDTotal power dissipation Ta = 25 ˚C - 1.8 W

Tstg Storage temperature - -55 150 ˚C

TjContinuous junction temperature normal operation3- 150 ˚C

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VCElectrostatic discharge capacitor Human body model; - 2 kV

voltage C = 250 pF; R = 1.5 kΩ

OVERVOLTAGE CLAMPING LIMITING VALUES

At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

EDSM Non-repetitive clamping energy Ta ≤ 25 ˚C; IDM ≤ ID(TO); - 100 mJ

inductive load

EDRM Repetitive clamping energy Tsp ≤ 125 ˚C; IDM = 1 A; - 5 mJ

f = 250 Hz

OVERLOAD PROTECTION LIMITING VALUES

With the protection supply provided via the input pin, TOPFET can protect itself from short circuit loads.

Overload protection operates by means of drain current trip or by activating the overtemperature protection.

SYMBOL PARAMETER REQUIRED CONDITION MIN. MAX. UNIT

VDDP Protected drain source supply voltage VIS ≥ 4 V - 35 V

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Thermal resistance

Rth j-sp Junction to solder point - 12 18 K/W

Rth j-b Junction to board4Mounted on any PCB - 40 - K/W

Rth j-a Junction to ambient Mounted on PCB of fig. 4 - - 70 K/W

1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.

2 Refer to OVERLOAD PROTECTION CHARACTERISTICS.

3 Not in an overload condition with drain current limiting.

4 Temperature measured 1.3 mm from tab.

December 2001 2 Rev 2.000

Philips Semiconductors Product specification

PowerMOS transistor BUK127-50GT

Logic level TOPFET

OUTPUT CHARACTERISTICS

Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25 ˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Off-state VIS = 0 V

V(CL)DSS Drain-source clamping voltage ID = 10 mA 50 - - V

ID = 200 mA; tp ≤ 300 µs; δ ≤ 0.01 50 60 70 V

IDSS Drain source leakage current VDS = 40 V - - 100 µA

Tmb = 25 ˚C - 0.1 10 µA

On-state VIS ≥ 4 V; tp ≤ 300 µs; δ ≤ 0.01

RDS(ON) Drain-source resistance ID = 100 mA - - 380 mΩ

Tmb = 25 ˚C - 150 200 mΩ

INPUT CHARACTERISTICS

The supply for the logic and overload protection is taken from the input.

Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VIS(TO) Input threshold voltage VDS = 5 V; ID = 1 mA 0.6 - 2.4 V

Tmb = 25˚C 1.1 1.6 2.1 V

IIS Input supply current normal operation; VIS = 5 V 100 220 400 µA

VIS = 4 V 80 195 330 µA

IISL Input supply current protection latched; VIS = 5 V 1.4 2 2.5 mA

VIS = 3 V 0.7 1.1 1.5 mA

VISR Protection reset voltage1reset time tr ≥ 100 µs 1.5 2 2.5 V

tlr Latch reset time VIS1 = 5 V, VIS2 < 1 V 10 40 100 µs

V(CL)IS Input clamping voltage II = 1.5 mA 5.5 - 8.5 V

RIG Input series resistance2Tmb = 25˚C - 2.5 - kΩ

to gate of power MOSFET

OVERLOAD PROTECTION CHARACTERISTICS

TOPFET switches off to protect itself when one of the overload thresholds is exceeded. It remains latched off until

reset by the input.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Overload protection VIS = 4 V to 5.5 V

ID(TO) Drain current trip threshold Tj = 25˚C 4 - 8 A

-40˚C ≤ Tj ≤ 150˚C 3 - 9 A

Overtemperature protection

Tj(TO) Threshold junction temperature VIS = 4 V to 5.5 V 150 170 - ˚C

1 The input voltage below which the overload protection circuits will be reset.

2 Not directly measureable from device terminals.

December 2001 3 Rev 2.000

Philips Semiconductors Product specification

PowerMOS transistor BUK127-50GT

Logic level TOPFET

SWITCHING CHARACTERISTICS

Ta = 25 ˚C; resistive load RL = 50 Ω; adjust VDD to obtain ID = 250 mA; refer to test circuit and waveforms

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

td on Turn-on delay time VIS = 0 V to VIS = 5 V - 0.5 0.9 µs

trRise time - 0.7 1.5 µs

td off Turn-off delay time VIS = 5 V to VIS = 0 V - 3.2 6.5 µs

tfFall time - 1.6 3.5 µs

REVERSE DIODE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

ISContinuous forward current Tmb ≤ 25 ˚C; VIS = 0 V - 2 A

REVERSE DIODE CHARACTERISTICS

Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VSDO Forward voltage IS = 2 A; VIS = 0 V; tp = 300 µs - 0.83 1.1 V

trr Reverse recovery time not applicable1----

1 The reverse diode of this type is not intended for applications requiring fast reverse recovery.

December 2001 4 Rev 2.000

Philips Semiconductors Product specification

PowerMOS transistor BUK127-50GT

Logic level TOPFET

MECHANICAL DATA

Fig.2. SOT223 surface mounting package1.

UNIT A1bpcDEe1HELpQywv

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 0.10

0.01

1.8

1.5 0.80

0.60

3.1

2.9 0.32

0.22 6.7

6.3 3.7

3.3 2.3

4.6 7.3

6.7 1.1

0.7 0.95

0.85 0.1 0.10.2

DIMENSIONS (mm are the original dimensions)

SOT223 SC-73 97-02-28

99-09-13

detail X

vMA

0 2 4 mm

scale

132

Plastic surface mounted package; collector pad for good heat transfer; 4 leads SOT223

1 For further information, refer to surface mounting instructions for SOT223 envelope. Epoxy meets UL94 V0 at 1/8". Net Mass: 0.11 g

December 2001 5 Rev 2.000

Philips Semiconductors Product specification

PowerMOS transistor BUK127-50GT

Logic level TOPFET

MOUNTING INSTRUCTIONS

Dimensions in mm.

Fig.3. Soldering pattern for surface mounting.

PRINTED CIRCUIT BOARD

Dimensions in mm.

Fig.4. PCB for thermal resistance and power rating.

PCB: FR4 epoxy glass (1.6 mm thick),

copper laminate (35 µm thick).

4.6

4.5

3.8

min

6.3

2.3

4.6

1.5

min

1.5

min

1.5

min

(3x)

December 2001 6 Rev 2.000

Philips Semiconductors Product specification

PowerMOS transistor BUK127-50GT

Logic level TOPFET

DEFINITIONS

DATA SHEET STATUS

DATA SHEET PRODUCT DEFINITIONS

STATUS1STATUS2

Objective data Development This data sheet contains data from the objective specification for

product development. Philips Semiconductors reserves the right to

change the specification in any manner without notice

Preliminary data Qualification This data sheet contains data from the preliminary specification.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the specification without

notice, in order to improve the design and supply the best possible

product

Product data Production This data sheet contains data from the product specification. Philips

Semiconductors reserves the right to make changes at any time in

order to improve the design, manufacturing and supply. Changes will

be communicated according to the Customer Product/Process

Change Notification (CPCN) procedure SNW-SQ-650A

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 2001

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

1 Please consult the most recently issued datasheet before initiating or completing a design.

2 The product status of the device(s) described in this datasheet may have changed since this datasheet was published. The latest information is

available on the Internet at URL http://www.semiconductors.philips.com.

December 2001 7 Rev 2.000