HMC798ALC4 Data Sheet
Rev. 0 | Page 24 of 26
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
Figure 80 shows the typical application circuit for the
HMC798ALC4. The integrated LO amplifier is single bias at 5 V
with a typical 4 dBm input. Place capacitors as close as possible
to the pin to decouple the power supply. The LO and RF pins
are internally ac-coupled. The IF pin is internally dc-coupled.
When IF operation to dc is not required, use of an external
series capacitor is recommended, of a value chosen to pass the
necessary IF frequency range. When IF operation to dc is
required, do not exceed the IF source or sink current rating
specified in the Absolute Maximum Ratings section.
16785-072
LO
GND
NIC
NIC
GND
IF
GND GND
GND
LO
GND
NIC
GND
GND
RF
GND
NIC
VCC
GND GND
NIC
NIC
NIC
NIC
GND
13
14
15
16
17
18
6
5
4
3
2
1
19
20
21
22
23
24
12
11
10
9
8
7
HMC798ALC4
VCC
TERMINAL_SWAGE
TERMINAL_SWAGE
K_SRI-NS
IF
SMA_JC_062PCB
RF
K_SRI-NS
C1
100pF C2
10nF C3
4.7µF
+
Figure 80. Typical Application Circuit
EVALUATION PCB INFORMATION
Use RF circuit design techniques for the circuit board used in
the application. Ensure that signal lines have 50 Ω impedance,
and connect the package ground leads and the exposed pad
directly to the ground plane (see Figure 81). Use a sufficient
number of via holes to connect the top and bottom ground
planes. The evaluation circuit board shown in Figure 81 is
available from Analog Devices, Inc., upon request.
Table 5. List of Materials for Evaluation PCB
EV1HMC798ALC4
Item Description
J1 Johnson Surface-Mount Type A (SMA) connector
J2, J3 SRI 2.92 mm connector
U1 HMC798ALC4
PCB1 126598-1 evaluation board
C1 C0G, 0402, 100 pF capacitor
C2 X7R, 0603, 10000 pF capacitor
C3 SMD, 3216, 4.7 µF capacitor
1 126598-1 is the raw bare PCB identifier. Reference EV1HMC798ALC4 when
ordering the complete evaluation PCB.
SOLDERING INFORMATION AND RECOMMENDED
LAND PATTERN
Figure 81 shows the recommended land pattern for the
HMC798ALC4. The HMC798ALC4 is contained in a 3.90 mm
× 3.90 mm, 24-terminal, ceramic LCC package with an exposed
ground pad (EPAD). This exposed pad is internally connected
to the ground of the chip. To minimize thermal impedance and
ensure electrical performance, solder the exposed pad to the
low impedance ground plane on the PCB. It is recommended
that the ground planes on all layers under the exposed pad be
stitched together with vias to further reduce thermal
impedance. The land pattern on the HMC798ALC4 evaluation
board provides a simulated thermal resistance (θJC) of 119° C / W.