Back MC74HC4051A, MC74HC4052A, MC74HC4053A Analog Multiplexers / Demultiplexers High-Performance Silicon-Gate CMOS The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The HC4051A, HC4052A and HC4053A are identical in pinout to the metal-gate MC14051AB, MC14052AB and MC14053AB. The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel-Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal-gate CMOS analog switches. For a multiplexer/demultiplexer with injection current protection, see HC4851A and HC4852A. * Fast Switching and Propagation Speeds * Low Crosstalk Between Switches * Diode Protection on All Inputs/Outputs * Analog Power Supply Range (VCC - VEE) = 2.0 to 12.0 V * Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V * Improved Linearity and Lower ON Resistance Than Metal-Gate Counterparts * Low Noise * In Compliance With the Requirements of JEDEC Standard No. 7A * Chip Complexity: HC4051A -- 184 FETs or 46 Equivalent Gates HC4052A -- 168 FETs or 42 Equivalent Gates HC4053A -- 156 FETs or 39 Equivalent Gates http://onsemi.com MARKING DIAGRAMS 16 PDIP-16 N SUFFIX CASE 648 16 1 MC74HC405xAN AWLYYWW 1 16 SO-16 D SUFFIX CASE 751B 16 1 HC405xA AWLYYWW 1 16 SO-16 WIDE DW SUFFIX CASE 751G 16 HC405xA AWLYWW 1 1 16 HC40 5xA ALYW TSSOP-16 DT SUFFIX CASE 948F 16 1 1 16 SOEIAJ-16 F SUFFIX CASE 966 16 1 74HC405xA ALYW 1 A tion WL YY WW = Assembly Loca= Wafer Lot = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. Semiconductor Components Industries, LLC, 2001 May, 2001 - Rev. 2 1 Publication Order Number: MC74HC4051A/D MC74HC4051A, MC74HC4052A, MC74HC4053A FUNCTION TABLE - MC74HC4051A LOGIC DIAGRAM MC74HC4051A Single-Pole, 8-Position Plus Common Off Control Inputs Enable C L L L L L L L L H L L L L H H H H X 13 X0 14 X1 15 X2 ANALOG 12 MULTIPLEXER/ INPUTS/ X3 DEMULTIPLEXER OUTPUTS X4 1 5 X5 2 X6 4 X7 11 A CHANNEL 10 B SELECT 9 INPUTS C 6 ENABLE PIN 16 = VCC PIN 7 = VEE PIN 8 = GND 3 X COMMON OUTPUT/ INPUT Select B A L L H H L L H H X ON Channels L H L H L H L H X X0 X1 X2 X3 X4 X5 X6 X7 NONE X = Don't Care Pinout: MC74HC4051A (Top View) VCC X2 X1 X0 X3 A B C 16 15 14 13 12 11 10 9 6 7 1 2 3 4 5 X4 X6 X X7 X5 8 Enable VEE GND FUNCTION TABLE - MC74HC4052A LOGIC DIAGRAM MC74HC4052A Double-Pole, 4-Position Plus Common Off Control Inputs Select 12 ANALOG INPUTS/OUTPUTS CHANNELSELECT INPUTS X0 14 X1 15 X2 11 X3 Y0 Y1 Y2 Y3 A B ENABLE X SWITCH 13 COMMON OUTPUTS/INPUTS 2 Y SWITCH 3 B A ON Channels L L L L H L L H H X L H L H X Y0 Y1 Y2 Y3 X 1 5 Enable X = Don't Care 4 6 NONE Y Pinout: MC74HC4052A (Top View) 10 9 X0 X1 X2 X3 PIN 16 = VCC PIN 7 = VEE PIN 8 = GND http://onsemi.com 2 VCC X2 X1 X X0 X3 A B 16 15 14 13 12 11 10 9 6 7 1 2 3 4 5 Y0 Y2 Y Y3 Y1 Enable VEE 8 GND MC74HC4051A, MC74HC4052A, MC74HC4053A FUNCTION TABLE - MC74HC4053A Control Inputs LOGIC DIAGRAM MC74HC4053A Triple Single-Pole, Double-Position Plus Common Off 12 X0 13 X1 14 X SWITCH 2 ANALOG INPUTS/OUTPUTS Y0 1 Y1 15 Y SWITCH 5 Z0 3 Z1 4 Z SWITCH Enable C L L L L L L L L H L L L L H H H H X X Y COMMON OUTPUTS/INPUTS Z Select B A L L H H L L H H X ON Channels Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 L H L H L H L H X Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 NONE X0 X1 X0 X1 X0 X1 X0 X1 X = Don't Care 11 A 10 B 9 C 6 ENABLE PIN 16 = VCC PIN 7 = VEE PIN 8 = GND CHANNELSELECT INPUTS Pinout: MC74HC4053A (Top View) VCC Y X X1 X0 A B C 16 15 14 13 12 11 10 9 6 7 NOTE: This device allows independent control of each switch. Channel-Select Input A controls the X-Switch, Input B controls the Y-Switch and Input C controls the Z-Switch 1 2 3 4 5 Y1 Y0 Z1 Z Z0 IIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III Enable VEE 8 GND MAXIMUM RATINGS* Symbol Parameter (Referenced to GND) (Referenced to VEE) Value Unit - 0.5 to + 7.0 - 0.5 to + 14.0 V VCC Positive DC Supply Voltage VEE Negative DC Supply Voltage (Referenced to GND) - 7.0 to + 5.0 V VIS Analog Input Voltage VEE - 0.5 to VCC + 0.5 V Vin Digital Input Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V DC Current, Into or Out of Any Pin 25 mA PD Power Dissipation in Still Air, 750 500 450 mW Tstg Storage Temperature Range - 65 to + 150 C TL Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package I Plastic DIP EIAJ/SOIC Package TSSOP Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. C 260 *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/C from 65 to 125C EIAJ/SOIC Package: - 7 mW/C from 65 to 125C TSSOP Package: - 6.1 mW/C from 65 to 125C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). http://onsemi.com 3 MC74HC4051A, MC74HC4052A, MC74HC4053A IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III II IIII IIIIIIIIIIIIIII III III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III III II IIII IIIIIIIIIIIIIII IIIII III RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 2.0 2.0 6.0 12.0 V Negative DC Supply Voltage, Output (Referenced to GND) - 6.0 GND V VIS Analog Input Voltage VEE VCC V Vin Digital Input Voltage (Referenced to GND) GND VCC V VIO* Static or Dynamic Voltage Across Switch 1.2 V - 55 + 125 C 0 0 0 0 1000 600 500 400 ns VCC Positive DC Supply Voltage VEE (Referenced to GND) (Referenced to VEE) TA Operating Temperature Range, All Package Types tr, tf Input Rise/Fall Time (Channel Select or Enable Inputs) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V *For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC CHARACTERISTICS -- Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted Symbol Parameter Condition Guaranteed Limit VCC V -55 to 25C 85C 125C Unit VIH Minimum High-Level Input Voltage, Channel-Select or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V VIL Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V Iin Maximum Input Leakage Current, Channel-Select or Enable Inputs Vin = VCC or GND, VEE = - 6.0 V 6.0 0.1 1.0 1.0 A ICC Maximum Quiescent Supply Current (per Package) Channel Select, Enable and VIS = VCC or GND; VEE = GND VIO = 0 V VEE = - 6.0 6.0 6.0 1 4 10 40 20 80 A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). http://onsemi.com 4 MC74HC4051A, MC74HC4052A, MC74HC4053A DC CHARACTERISTICS -- Analog Section Guaranteed Limit Symbol Ron 125C Unit VEE Vin = VIL or VIH; VIS = VCC to VEE; IS 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 - 4.5 - 6.0 190 120 100 240 150 125 280 170 140 Vin = VIL or VIH; VIS = VCC or VEE (Endpoints); IS 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 - 4.5 - 6.0 150 100 80 190 125 100 230 140 115 Parameter Condition Maximum "ON" Resistance 85C VCC -55 to 25C Ron Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Vin = VIL or VIH; VIS = 1/2 (VCC - VEE); IS 2.0 mA 4.5 4.5 6.0 0.0 - 4.5 - 6.0 30 12 10 35 15 12 40 18 14 Ioff Maximum Off-Channel Leakage Current, Any One Channel Vin = VIL or VIH; VIO = VCC - VEE; Switch Off (Figure 3) 6.0 - 6.0 0.1 0.5 1.0 Maximum Off-Channel HC4051A Vin = VIL or VIH; Leakage Current, HC4052A VIO = VCC - VEE; Common Channel HC4053A Switch Off (Figure 4) 6.0 6.0 6.0 - 6.0 - 6.0 - 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 Maximum On-Channel HC4051A Vin = VIL or VIH; Leakage Current, HC4052A Switch-to-Switch = Channel-to-Channel HC4053A VCC - VEE; (Figure 5) 6.0 6.0 6.0 - 6.0 - 6.0 - 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 Ion A A AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit VCC V -55 to 25C 85C 125C Unit Symbol Parameter tPLH, tPHL Maximum Propagation Delay, Channel-Select to Analog Output (Figure 9) 2.0 3.0 4.5 6.0 270 90 59 45 320 110 79 65 350 125 85 75 ns tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figure 10) 2.0 3.0 4.5 6.0 40 25 12 10 60 30 15 13 70 32 18 15 ns tPLZ, tPHZ Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 3.0 4.5 6.0 160 70 48 39 200 95 63 55 220 110 76 63 ns tPZL, tPZH Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 3.0 4.5 6.0 245 115 49 39 315 145 69 58 345 155 83 67 ns Cin Maximum Input Capacitance, Channel-Select or Enable Inputs 10 10 10 pF CI/O Maximum Capacitance Analog I/O 35 35 35 pF Common O/I: HC4051A HC4052A HC4053A 130 80 50 130 80 50 130 80 50 Feedthrough 1.0 1.0 1.0 (All Switches Off) NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D) Typical @ 25C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Figure 13)* HC4051A HC4052A HC4053A 45 80 45 pF * Used to determine the no-load dynamic power consumption: P D = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). http://onsemi.com 5 MC74HC4051A, MC74HC4052A, MC74HC4053A ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) Symbol BW -- -- Parameter Condition Maximum On-Channel Bandwidth or Minimum Mi i Frequency F Response R (Figure 6) fin = 1MHz Sine Wave; Adjust fin Voltage to Obt i 0dB Obtain 0dBm att VOS; IIncrease fin Frequency Until dB Meter Reads -3dB; RL = 50, CL = 10pF Off-Channel Feedthrough Isolation (Figure 7) Feedthrough Noise. Channel-Select Input to Common I/O (Figure 8) -- Crosstalk Between Any Two Switches (Figure 12) (Test does not apply to HC4051A) THD VCC V Total Harmonic Distortion (Figure 14) Limit* VEE V 25C `52 `53 80 80 80 95 95 95 120 120 120 2.25 4.50 6.00 -2.25 -4.50 -6.00 fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600, CL = 50pF 2.25 4.50 6.00 -2.25 -4.50 -6.00 -50 -50 -50 fin = 1.0MHz, RL = 50, CL = 10pF 2.25 4.50 6.00 -2.25 -4.50 -6.00 -40 -40 -40 Vin 1MHz Square Wave (tr = tf = 6ns); Adjust RL at Setup so that IS = 0A; Enable = GND RL = 600, CL = 50pF 2.25 4.50 6.00 -2.25 -4.50 -6.00 25 105 135 RL = 10k, CL = 10pF 2.25 4.50 6.00 -2.25 -4.50 -6.00 35 145 190 fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600, CL = 50pF 2.25 4.50 6.00 -2.25 -4.50 -6.00 -50 -50 -50 fin = 1.0MHz, RL = 50, CL = 10pF 2.25 4.50 6.00 -2.25 -4.50 -6.00 -60 -60 -60 fin = 1kHz, RL = 10k, CL = 50pF THD = THDmeasured - THDsource VIS = 4.0VPP sine wave VIS = 8.0VPP sine wave VIS = 11.0VPP sine wave Unit `51 MHz dB mVPP dB % 2.25 4.50 6.00 -2.25 -4.50 -6.00 0.10 0.08 0.05 *Limits not tested. Determined by design and verified by qualification. 180 250 200 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 300 125C 150 25C -55C 100 50 0 160 140 120 125C 100 80 25C 60 -55C 40 20 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 0 2.25 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1a. Typical On Resistance, VCC - VEE = 2.0 V Figure 1b. Typical On Resistance, VCC - VEE = 3.0 V http://onsemi.com 6 120 105 100 90 80 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) MC74HC4051A, MC74HC4052A, MC74HC4053A 125C 60 25C 40 -55C 20 0 75 125C 60 25C 45 -55C 30 15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 4.5 0 0.5 Figure 1c. Typical On Resistance, VCC - VEE = 4.5 V 3.0 3.5 4.0 4.5 5.0 5.5 6.0 60 70 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 2.0 2.5 Figure 1d. Typical On Resistance, VCC - VEE = 6.0 V 80 60 50 125C 40 30 25C 20 -55C 10 0 -4.5 1.0 1.5 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 50 125C 40 25C 30 -55C 20 10 0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 4.5 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 2.0 3.0 4.0 5.0 6.0 Figure 1f. Typical On Resistance, VCC - VEE = 12.0 V PLOTTER - 1.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1e. Typical On Resistance, VCC - VEE = 9.0 V PROGRAMMABLE POWER SUPPLY 0 MINI COMPUTER DC ANALYZER + VCC DEVICE UNDER TEST ANALOG IN COMMON OUT VEE GND Figure 2. On Resistance Test Set-Up http://onsemi.com 7 MC74HC4051A, MC74HC4052A, MC74HC4053A VCC VCC VCC 16 VEE OFF A VCC VEE VIH ANALOG I/O OFF VIH 6 7 8 VEE 6 7 8 VCC fin N/C COMMON O/I OFF VOS 16 0.1F ON VEE Figure 4. Maximum Off Channel Leakage Current, Common Channel, Test Set-Up VCC 16 A VCC COMMON O/I VEE Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up VCC OFF VCC COMMON O/I OFF NC VCC 16 dB METER ON RL CL* ANALOG I/O VIL 6 7 8 6 7 8 VEE VEE Figure 5. Maximum On Channel Leakage Current, Channel to Channel, Test Set-Up VCC VIS fin VCC dB METER OFF RL Figure 6. Maximum On Channel Bandwidth, Test Set-Up VOS 16 0.1F *Includes all probe and jig capacitance CL* 16 RL ANALOG I/O RL OFF/ON RL 6 7 8 VEE VIL or VIH VCC GND CHANNEL SELECT Vin 1 MHz tr = tf = 6 ns 6 7 8 VEE COMMON O/I ON/OFF RL CL* TEST POINT VCC 11 CHANNEL SELECT *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 7. Off Channel Feedthrough Isolation, Test Set-Up Figure 8. Feedthrough Noise, Channel Select to Common Out, Test Set-Up http://onsemi.com 8 MC74HC4051A, MC74HC4052A, MC74HC4053A VCC VCC 16 VCC CHANNEL SELECT 50% ANALOG I/O OFF/ON GND tPLH COMMON O/I ON/OFF CL* TEST POINT tPHL ANALOG OUT 6 7 8 50% CHANNEL SELECT *Includes all probe and jig capacitance Figure 9a. Propagation Delays, Channel Select to Analog Out Figure 9b. Propagation Delay, Test Set-Up Channel Select to Analog Out VCC 16 ANALOG I/O VCC ANALOG IN ON COMMON O/I 50% CL* tPLH tPHL ANALOG OUT TEST POINT GND 6 7 8 50% *Includes all probe and jig capacitance Figure 10a. Propagation Delays, Analog In to Analog Out tf tr 90% 50% 10% ENABLE tPZL ANALOG OUT tPLZ 50% tPZH ANALOG OUT Figure 10b. Propagation Delay, Test Set-Up Analog In to Analog Out 1 VCC 2 GND tPHZ 90% VCC VCC HIGH IMPEDANCE 10% POSITION 1 WHEN TESTING tPHZ AND tPZH POSITION 2 WHEN TESTING tPLZ AND tPZL 16 1 ANALOG I/O ON/OFF 2 CL* VOL ENABLE VOH 50% HIGH IMPEDANCE Figure 11a. Propagation Delays, Enable to Analog Out 1k 6 7 8 Figure 11b. Propagation Delay, Test Set-Up Enable to Analog Out http://onsemi.com 9 TEST POINT MC74HC4051A, MC74HC4052A, MC74HC4053A VCC VIS 16 RL fin A VCC 16 VOS ON ANALOG I/O 0.1F COMMON O/I ON/OFF OFF/ON NC OFF VEE RL RL CL* RL CL* 6 7 8 VEE VCC 6 7 8 11 CHANNEL SELECT *Includes all probe and jig capacitance Figure 12. Crosstalk Between Any Two Switches, Test Set-Up Figure 13. Power Dissipation Capacitance, Test Set-Up 0 VIS VCC -10 VOS 16 0.1F fin ON CL* TO DISTORTION METER -30 -40 dB RL -50 DEVICE -60 6 7 8 VEE FUNDAMENTAL FREQUENCY -20 SOURCE -70 -80 -90 *Includes all probe and jig capacitance -100 1.0 2.0 3.125 FREQUENCY (kHz) Figure 14a. Total Harmonic Distortion, Test Set-Up Figure 14b. Plot, Harmonic Distortion APPLICATIONS INFORMATION The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = +5V = logic high GND = 0V = logic low The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is ten volts. Therefore, using the configuration of Figure 15, a maximum analog signal of ten volts peak-to-peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VCC - GND = 2 to 6 volts VEE - GND = 0 to -6 volts VCC - VEE = 2 to 12 volts and VEE GND When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 16. These diodes should be able to absorb the maximum anticipated current surges during clipping. http://onsemi.com 10 MC74HC4051A, MC74HC4052A, MC74HC4053A VCC +5V +5V 16 ANALOG SIGNAL -5V ON 6 7 8 Dx +5V ANALOG SIGNAL VCC 16 Dx Dx VEE VEE 7 8 -5V VEE Figure 15. Application Example Figure 16. External Germanium or Schottky Clipping Diodes +5V +5V 16 ANALOG SIGNAL VEE ON/OFF 6 7 8 VEE Dx ON/OFF -5V TO EXTERNAL CMOS CIRCUITRY 0 to 5V DIGITAL SIGNALS 11 10 9 VCC +5V ANALOG SIGNAL +5V * R R 11 10 9 +5V +5V VEE VEE 16 ANALOG SIGNAL ON/OFF +5V ANALOG SIGNAL R VEE +5V 6 7 8 LSTTL/NMOS CIRCUITRY VEE * 2K R 10K a. Using Pull-Up Resistors 11 10 9 LSTTL/NMOS CIRCUITRY HCT BUFFER b. Using HCT Interface Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs A 11 13 LEVEL SHIFTER 14 B 10 15 LEVEL SHIFTER 12 C 9 1 LEVEL SHIFTER 5 ENABLE 6 2 LEVEL SHIFTER 4 3 Figure 18. Function Diagram, HC4051A http://onsemi.com 11 X0 X1 X2 X3 X4 X5 X6 X7 X MC74HC4051A, MC74HC4052A, MC74HC4053A A 10 12 LEVEL SHIFTER 14 B 9 15 LEVEL SHIFTER 11 13 ENABLE 6 1 LEVEL SHIFTER 5 2 4 3 X0 X1 X2 X3 X Y0 Y1 Y2 Y3 Y Figure 19. Function Diagram, HC4052A A 11 13 LEVEL SHIFTER 12 14 B 10 1 LEVEL SHIFTER 2 15 C 9 3 LEVEL SHIFTER 5 4 ENABLE 6 LEVEL SHIFTER Figure 20. Function Diagram, HC4053A http://onsemi.com 12 X1 X0 X Y1 Y0 Y Z1 Z0 Z MC74HC4051A, MC74HC4052A, MC74HC4053A ORDERING & SHIPPING INFORMATION Package Shipping MC74HC4051AN Device PDIP-16 500 Units / Unit Pak MC74HC4051AD SOIC-16 48 Units / Rail MC74HC4051ADR2 SOIC-16 2500 Units / Tape & Reel MC74HC4051ADT TSSOP-16 96 Units / Rail MC74HC4051ADTR2 TSSOP-16 2500 Units / Tape & Reel MC74HC4051ADW SOIC WIDE 48 Units / Rail MC74HC4051ADWR2 SOIC WIDE 1000 Units / Tape & Reel MC74HC4051AF SOEIAJ-16 See Note 1 MC74HC4051AFEL SOEIAJ-16 See Note 1 MC74HC4052AN PDIP-16 500 Units / Unit Pak MC74HC4052AD SOIC-16 48 Units / Rail MC74HC4052ADR2 SOIC-16 2500 Units / Tape & Reel MC74HC4052ADT TSSOP-16 96 Units / Rail MC74HC4052ADTR2 TSSOP-16 2500 Units / Tape & Reel MC74HC4052ADW SOIC WIDE 48 Units / Rail MC74HC4052ADWR2 SOIC WIDE 1000 Units / Tape & Reel MC74HC4052AF SOEIAJ-16 See Note 1 MC74HC4052AFEL SOEIAJ-16 See Note 1 MC74HC4053AN PDIP-16 500 Units / Unit Pak MC74HC4053AD SOIC-16 48 Units / Rail MC74HC4053ADR2 SOIC-16 2500 Units / Tape & Reel MC74HC4053ADT TSSOP-16 96 Units / Rail MC74HC4053ADTR2 TSSOP-16 2500 Units / Tape & Reel MC74HC4053ADW SOIC WIDE 48 Units / Rail MC74HC4053ADWR2 SOIC WIDE 1000 Units / Tape & Reel MC74HC4053AF SOEIAJ-16 See Note 1 MC74HC4053AFEL SOEIAJ-16 See Note 1 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. http://onsemi.com 13 MC74HC4051A, MC74HC4052A, MC74HC4053A PACKAGE DIMENSIONS PDIP-16 N SUFFIX CASE 648-08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A - 16 9 1 8 B F C DIM A B C D F G H J K L M S L S -T - SEATING PLANE K H D 16 PL 0.25 (0.010) M M J G T A M INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 6.85 0.250 0.270 3.69 4.44 0.145 0.175 0.39 0.53 0.015 0.021 1.02 1.77 0.040 0.070 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.38 0.008 0.015 2.80 3.30 0.110 0.130 7.50 7.74 0.295 0.305 0 10 0 10 0.51 1.01 0.020 0.040 SOIC-16 D SUFFIX CASE 751B-05 ISSUE J -A - 16 9 1 8 -B - NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. P 8 PL 0.25 (0.010) M B M G K F R X 45 C -T SEATING - PLANE D16PL 0.25 (0.010) J M M T B S A S http://onsemi.com 14 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.49 0.35 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 MC74HC4051A, MC74HC4052A, MC74HC4053A PACKAGE DIMENSIONS SOIC-16 WIDE DW SUFFIX CASE 751G-03 ISSUE B A D 9 1 8 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. h X 45 H E 0.25 8X M B M 16 B B 16X M T A 14X e S B S L A 0.25 DIM A A1 B C D E e H h L A1 SEATING PLANE C T MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0 7 TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K EEE CCC CCC EEE K1 2X L/2 16 9 J1 B -U- L SECTION N-N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A -V- M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N F DETAIL E -W- C 0.10 (0.004) -T- SEATING PLANE DETAIL E H D G http://onsemi.com 15 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 MC74HC4051A, MC74HC4052A, MC74HC4053A PACKAGE DIMENSIONS SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O 16 LE 9 Q1 M E HE 1 8 L DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 --0.031 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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