256-Channel ADPCM
3-74 February 26, 2001
Channel Configuration and Coding Control
Control
The 8-bit wide CFG bus determines the compression rate
and law for each channel. The function of each bit is listed
in Table 2. Note that the top 4 bits are only used in the du-
plex mode and specify the law and compression rate for en-
coding.
The input signal G726 is used to specify whether the G.726
or G.727 is in use; when high the core operates per the
G.726 standard, low indicates G.727.
Duplex (that is, the channels are split evenly between en-
code and decode) and flexible channel addressing modes
are selected via the static MODE input. When MODE is
high, the core operates in duplex mode and when MODE is
low the core operates in the flexible mode. In the latter
case, each channel can operate as either an encoding or a
decoding channel.
It should be noted that:
•The core should be configured before an encoding or
decoding operation is started.
•When core busy indicator BSY is HIGH, asserting the
control signal DSS is ignored.
•Other input control signals, namely, EDC, CHN, PCM,
G726 and EW, are latched on the clock rising edge
when DSS is HIGH and BSY is LOW.
•Input data S and ID are also latched on the clock rising
edge when DSS is HIGH and BSY is LOW.
•The output data is registered.
•The encoding status indicator ESI indicates the internal
encoding state of the core. When it goes to LOW, the
core has completed the predictor state update. When it
returns to HIGH, the encoding output is available.
•The decoding status indicator (DSI) indicates the
internal decoding state of the core. When it goes to
LOW, the core has completed the predictor state
update. When it returns to HIGH, the decoding output is
available.
•When an encoding or decoding operation is completed,
signal BSY returns to LOW and the core waits for DSS
to be asserted to start the next operation.
•Encoding and decoding can be performed in any order.
Output signals encode status indicator (ESI) and decode
status indicator (DSI) indicate the encoding and decoding
status, respectively. From the cycle when the codec picks
up the input data, ESI or DSI goes to ‘0’. In the cycle when
the encoding/decoding output is available, the correspond-
ing signal returns to ‘1’. Both the signals are set to ‘1’ after
reset and before the first input.
Table 2: Codec Configuration Control Word
CFG Description Control Choice
Bits Control Values 0 1
[7] Selects either A-law or µ-law for encoding in
the duplex mode
µ-law A-law
[6] Control whether even bit inversion is per-
formed for A-law/µ-law encoding operations
in duplex mode No bit inversion
Even bit inversion per-
formed for A-law
All bit inversion performed
for µ-law
Control Values 00 01 10 11
[5:4] Controls the number of bits in the ADPCM
output word when encoding in duplex mode
2 bits 3 bits 4 bits 5 bits
Control Values 0 1
[3] Selects either A-law or µ-law for decoding in
the duplex mode or encoding/decoding in the
flexible mode
µ-law A-law
[2] Controls whether even bit inversion/all bit in-
version is performed for A-law/µ-law decod-
ing operations in the duplex mode or
encoding/decoding in the flexible mode
No bit
inversion
Even bit inversion
performed for A-law
All bit inversion performed
for µ-law
Control Values 00 01 10 11
[1:0] Controls the number of bits in the ADPCM
output word when encoding in the duplex
mode or the number of bits in the ADPCM in-
put word and the ADPCM
output word in the flexible mode.
2 bits 3 bits 4 bits 5 bits